Paul Paterson / mbed-src-CanNucleoF0

mbed library sources, include can_api for nucleo-f091rc

Dependents:   CanNucleoF0_example

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c@645:13c87cbecd54, 2016-01-07 (annotated)

Committer:
ptpaterson
Date:
Thu Jan 07 05:49:05 2016 +0000
Revision:
645:13c87cbecd54
Parent:
499:d0e9408fd176 
corrected freeze on CAN_RECEIVE_IT

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 /* mbed Microcontroller Library
mbed_official 82:0b31dbcd4769 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 82:0b31dbcd4769 3 *
mbed_official 82:0b31dbcd4769 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 82:0b31dbcd4769 5 * you may not use this file except in compliance with the License.
mbed_official 82:0b31dbcd4769 6 * You may obtain a copy of the License at
mbed_official 82:0b31dbcd4769 7 *
mbed_official 82:0b31dbcd4769 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 82:0b31dbcd4769 9 *
mbed_official 82:0b31dbcd4769 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 82:0b31dbcd4769 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 82:0b31dbcd4769 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 82:0b31dbcd4769 13 * See the License for the specific language governing permissions and
mbed_official 82:0b31dbcd4769 14 * limitations under the License.
mbed_official 82:0b31dbcd4769 15 */
mbed_official 82:0b31dbcd4769 16 #include "sleep_api.h"
mbed_official 82:0b31dbcd4769 17 #include "cmsis.h"
mbed_official 82:0b31dbcd4769 18 #include "PeripheralPins.h"
mbed_official 82:0b31dbcd4769 19
mbed_official 82:0b31dbcd4769 20 //Normal wait mode
mbed_official 82:0b31dbcd4769 21 void sleep(void)
mbed_official 82:0b31dbcd4769 22 {
mbed_official 82:0b31dbcd4769 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
mbed_official 82:0b31dbcd4769 24
mbed_official 82:0b31dbcd4769 25 //Normal sleep mode for ARM core:
mbed_official 82:0b31dbcd4769 26 SCB->SCR = 0;
mbed_official 82:0b31dbcd4769 27 __WFI();
mbed_official 82:0b31dbcd4769 28 }
mbed_official 82:0b31dbcd4769 29
mbed_official 82:0b31dbcd4769 30 //Very low-power stop mode
mbed_official 82:0b31dbcd4769 31 void deepsleep(void)
mbed_official 82:0b31dbcd4769 32 {
mbed_official 499:d0e9408fd176 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
mbed_official 499:d0e9408fd176 34 uint8_t ADC_HSC = 0;
mbed_official 499:d0e9408fd176 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
mbed_official 499:d0e9408fd176 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
mbed_official 499:d0e9408fd176 37 ADC_HSC = 1;
mbed_official 499:d0e9408fd176 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
mbed_official 499:d0e9408fd176 39 }
mbed_official 499:d0e9408fd176 40 }
mbed_official 499:d0e9408fd176 41
mbed_official 363:12a245e5c745 42 #if ! defined(TARGET_KL43Z)
mbed_official 82:0b31dbcd4769 43 //Check if PLL/FLL is enabled:
mbed_official 82:0b31dbcd4769 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
mbed_official 363:12a245e5c745 45 #endif
mbed_official 363:12a245e5c745 46
mbed_official 82:0b31dbcd4769 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
mbed_official 82:0b31dbcd4769 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
mbed_official 82:0b31dbcd4769 49
mbed_official 82:0b31dbcd4769 50 //Deep sleep for ARM core:
mbed_official 82:0b31dbcd4769 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
mbed_official 82:0b31dbcd4769 52
mbed_official 82:0b31dbcd4769 53 __WFI();
mbed_official 82:0b31dbcd4769 54
mbed_official 363:12a245e5c745 55 #if ! defined(TARGET_KL43Z)
mbed_official 82:0b31dbcd4769 56 //Switch back to PLL as clock source if needed
mbed_official 82:0b31dbcd4769 57 //The interrupt that woke up the device will run at reduced speed
mbed_official 82:0b31dbcd4769 58 if (PLL_FLL_en) {
mbed_official 82:0b31dbcd4769 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
mbed_official 82:0b31dbcd4769 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
mbed_official 82:0b31dbcd4769 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
mbed_official 82:0b31dbcd4769 62 #endif
mbed_official 82:0b31dbcd4769 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
mbed_official 82:0b31dbcd4769 64 }
mbed_official 363:12a245e5c745 65 #endif
mbed_official 499:d0e9408fd176 66
mbed_official 499:d0e9408fd176 67 if (ADC_HSC) {
mbed_official 499:d0e9408fd176 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
mbed_official 499:d0e9408fd176 69 }
mbed_official 82:0b31dbcd4769 70 }