Diff: main.cpp

Revision:

2:e9d2346ea1bb

Parent:

1:b0e6c82af2ef

Child:

3:a643b6a454aa

diff -r b0e6c82af2ef -r e9d2346ea1bb main.cpp
--- a/main.cpp	Sat Sep 28 06:44:57 2013 +0000
+++ b/main.cpp	Wed Oct 23 23:17:55 2013 +0000
@@ -1,11 +1,14 @@
 // MBED driver for AD9850 digital synthesizer using hacked SPI interface
-// Liam Goudge Sept 2013
+// Original code by Liam Goudge Sept 2013
+// Modified for KL25Z by Mike Richards Oct 2013
 
 #include "mbed.h"
 
-SPI device (p5,p6,p7); // MOSI, MISO (not used), SCLK
-DigitalOut CS(p8); // Use pin 8 as a fake Chip select
-DigitalOut ADReset(p15); // Pin 15 is reset line for AD9850
+
+SPI device (PTD2, PTD3, PTD1); // Set the KL25Z SPI pins
+DigitalOut CS(PTD0); // Use pin P0_17 as a fake Chip select
+DigitalOut ADReset(PTA13); // Use Pin P0_7 as the reset line for AD9850
+
 
 Serial pc(USBTX, USBRX); // tx, rx for debug terminal
 
@@ -29,37 +32,39 @@
      
 void writeSPI(int frq, int phase)
 {           
-// Send the 40-bit packet. MBED only allows max 16-bit packets so we send 40-bits as 16, 16, 8
-    device.format(16,0); // 16-bits per packet, mode 0 (CPOL=0 CPHA=0)
+// Send the 40-bit packet. NB: KL25Z only supports 8-bit SPI so send five 8-bit packets
+    
+    device.format(8,0); // 8-bits per packet, mode 0 (CPOL=0 CPHA=0)
     device.frequency(1000000); //SPI clock set to 1MHz
 
-    wait_ms(5);
+    wait_ms(1);
 
     // First do chip select. Need to use a GPIO to fake the chip select since MBED doesn't allow to set positive logic CS signal
     CS=1; // assert chip select (a.k.a FQ_UD frequency update input to AD9850)
-    wait_ms(5);
+    wait_ms(1);
     CS=0;
         
-    device.write(frq>>16); // Write upper 16-bits first starting with bit 31
-    device.write(frq); // Now lower 16 bits starting with bit 15
-    
-    device.format(8,0); // Need to reset to 8-bit data since MBED only allows max 16-bit packets. For 40-bits we do 16, 16, 8
+    device.write(frq>>24); // Write upper 8-bits
+    device.write(frq>>16);
+    device.write(frq>>8);
+    device.write(frq); // Now the last 8 bits
     device.write(phase); // This is phase and factory settings byte
 
-    // Now pulse FQ_UD again to signal the end of the packet
+    // Now pulse FQ_UD again to load the word into the DDS
     CS=0;
-    wait_ms(5);
+    wait_ms(1);
     CS=1;
-    wait_ms(5);
+    wait_ms(1);
     CS=0;
 }
     
 
 int main()
 {
-    int targetFrq=0x147AE148; // This is desired sine wave frequency for the AD9850, here set to 10MHz
-    int increment=0x346DC6; // This is a 100KHz frequency increment
-
+    // This routine produces a continuous frequency sweep
+    int targetFrq=0x147AE148; // Frequency word = ([Desired freq in MHz] * 34.3597384)
+    int increment=0xD6B; //100Hz step
+    
     // Reset the AD9850. Active high logic. Minimum reset period 5 clock cycles (5/125MHz)
     ADReset=0;
     wait_ms(5);
@@ -70,18 +75,20 @@
     while(1)
     {
     
-    while (targetFrq<0x28F5C28F) // up to 20MHz
+    
+   
+   while (targetFrq<0x148bFFFF) // up to 10.001MHz
     {
         writeSPI(reverseBits(targetFrq),0); // Don't use phase so set to zero.
         targetFrq=targetFrq+increment;
-        //wait_ms(100);
+        //wait_ms(200);
         }
         
     while (targetFrq>0x147AE148) // down to 10MHz
     {
         writeSPI(reverseBits(targetFrq),0);
         targetFrq=targetFrq-increment;
-        //wait_ms(100);
+        //wait_ms(200);
         }  
     
     }