pl ack in tmtc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of COM_MNG_TMTC_SIMPLE_pl123 by shubham c

Committer:
pradeepvk2208
Date:
Sat Apr 02 04:17:20 2016 +0000
Revision:
140:4feeb1163bb6
Parent:
139:17353d6311ce
included ack for pl_tc_tm

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shreeshas95 1:a0055b3280c8 1 //without reset feature , with state checks.
shreeshas95 2:2caf2a9a13aa 2 InterruptIn IRQ(ADF_IRQ);
aniruddhv 52:0bd68655c651 3 //Ticker ticker;
ee12b079 9:e9eaada136c6 4
shreeshas95 1:a0055b3280c8 5 bool loop_on;
shreeshas95 1:a0055b3280c8 6 bool ADF_off;
shreeshas95 1:a0055b3280c8 7 bool buffer_state;
ee12b079 9:e9eaada136c6 8 bool finish_write_data;
shreeshas95 1:a0055b3280c8 9 uint8_t signal = 0x00;
shreeshas95 1:a0055b3280c8 10 unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x10,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00};
ee12b079 9:e9eaada136c6 11
shreeshas95 2:2caf2a9a13aa 12 //int initialise_card();
shreeshas95 2:2caf2a9a13aa 13 //int disk_initialize();
ee12b079 9:e9eaada136c6 14
shreeshas95 1:a0055b3280c8 15 #define bbram_write {\
shreeshas95 1:a0055b3280c8 16 SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 17 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 18 spi.write(0xB0);\
shreeshas95 1:a0055b3280c8 19 wait_us(300);\
shreeshas95 1:a0055b3280c8 20 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 21 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 22 for(int i=0;i<66;i++){\
shreeshas95 1:a0055b3280c8 23 spi.write(bbram_buffer[i]);\
shreeshas95 1:a0055b3280c8 24 }\
shreeshas95 1:a0055b3280c8 25 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 26 SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 27 }
shreeshas95 1:a0055b3280c8 28 //------------------------------------------------------------------------
shreeshas95 1:a0055b3280c8 29 // state checking functions
shreeshas95 1:a0055b3280c8 30 //bool assrt_phy_off( int, int, int);
shreeshas95 1:a0055b3280c8 31 //bool assrt_phy_on( int,int,int);
shreeshas95 1:a0055b3280c8 32 //bool assrt_phy_tx(int,int,int);
ee12b079 9:e9eaada136c6 33
shreeshas95 1:a0055b3280c8 34 #define START_ADDRESS 0x020;
shreeshas95 1:a0055b3280c8 35 #define MISO_PIN PTE3
shreeshas95 1:a0055b3280c8 36 /**************Defining Counter Limits**************/
shreeshas95 1:a0055b3280c8 37 #define THRS 20
shreeshas95 1:a0055b3280c8 38 #define STATE_ERR_THRS 20
shreeshas95 1:a0055b3280c8 39 #define PHY_OFF_EXEC_TIME 300
shreeshas95 1:a0055b3280c8 40 #define PHY_ON_EXEC_TIME 300
shreeshas95 1:a0055b3280c8 41 #define PHY_TX_EXEC_TIME 600
shreeshas95 1:a0055b3280c8 42 /******DEFINING COMMANDS*********/
shreeshas95 1:a0055b3280c8 43 #define CMD_HW_RESET 0xC8
shreeshas95 1:a0055b3280c8 44 #define CMD_PHY_ON 0xB1
shreeshas95 1:a0055b3280c8 45 #define CMD_PHY_OFF 0xB0
shreeshas95 1:a0055b3280c8 46 #define CMD_PHY_TX 0xB5
shreeshas95 1:a0055b3280c8 47 #define CMD_CONFIG_DEV 0xBB
ee12b079 9:e9eaada136c6 48
shreeshas95 1:a0055b3280c8 49 #define check_status {\
shreeshas95 1:a0055b3280c8 50 unsigned char stat=0;\
shreeshas95 1:a0055b3280c8 51 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 52 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 53 stat = spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 54 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 55 status = stat;\
shreeshas95 1:a0055b3280c8 56 }
ee12b079 9:e9eaada136c6 57
shreeshas95 1:a0055b3280c8 58 // all three arguments are int
shreeshas95 1:a0055b3280c8 59 #define assrt_phy_off(return_this) {\
shreeshas95 1:a0055b3280c8 60 int cmd_err_cnt = 0;\
shreeshas95 1:a0055b3280c8 61 int spi_err_cnt = 0;\
shreeshas95 1:a0055b3280c8 62 int state_err_cnt = 0;\
shreeshas95 1:a0055b3280c8 63 for(int i = 0 ; i < 40 ;i++){\
shreeshas95 1:a0055b3280c8 64 check_status;\
shreeshas95 1:a0055b3280c8 65 if(status == 0xB1){\
shreeshas95 1:a0055b3280c8 66 return_this = 0;\
shreeshas95 1:a0055b3280c8 67 break;\
shreeshas95 1:a0055b3280c8 68 }\
shreeshas95 1:a0055b3280c8 69 else if(cmd_err_cnt>THRS||spi_err_cnt>THRS){\
shreeshas95 1:a0055b3280c8 70 return_this = 1;\
shreeshas95 1:a0055b3280c8 71 break;\
shreeshas95 1:a0055b3280c8 72 }\
shreeshas95 1:a0055b3280c8 73 else if(state_err_cnt>STATE_ERR_THRS){\
shreeshas95 1:a0055b3280c8 74 return_this = 1;\
shreeshas95 1:a0055b3280c8 75 break;\
shreeshas95 1:a0055b3280c8 76 }\
shreeshas95 1:a0055b3280c8 77 else if( (status & 0xA0) == 0xA0 ){\
shreeshas95 1:a0055b3280c8 78 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 79 spi.write(CMD_PHY_OFF);\
shreeshas95 1:a0055b3280c8 80 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 81 wait_us(PHY_OFF_EXEC_TIME);\
shreeshas95 1:a0055b3280c8 82 state_err_cnt++;\
shreeshas95 1:a0055b3280c8 83 }\
shreeshas95 1:a0055b3280c8 84 else if(status&0x80==0x00){\
shreeshas95 1:a0055b3280c8 85 wait_ms(5);\
shreeshas95 1:a0055b3280c8 86 spi_err_cnt++;\
shreeshas95 1:a0055b3280c8 87 }\
shreeshas95 1:a0055b3280c8 88 else {\
shreeshas95 1:a0055b3280c8 89 wait_ms(1);\
shreeshas95 1:a0055b3280c8 90 cmd_err_cnt++;\
shreeshas95 1:a0055b3280c8 91 }\
shreeshas95 1:a0055b3280c8 92 }\
shreeshas95 1:a0055b3280c8 93 }
ee12b079 9:e9eaada136c6 94
ee12b079 9:e9eaada136c6 95
shreeshas95 1:a0055b3280c8 96 #define initial_adf_check {\
shreeshas95 1:a0055b3280c8 97 spi.write(CMD_PHY_OFF);\
shreeshas95 1:a0055b3280c8 98 int tempReturn = 0;\
shreeshas95 2:2caf2a9a13aa 99 bool flag = false;\
shreeshas95 1:a0055b3280c8 100 while( hw_reset_err_cnt < 2 ){\
shreeshas95 1:a0055b3280c8 101 assrt_phy_off( tempReturn);\
shreeshas95 1:a0055b3280c8 102 if( !tempReturn ){\
shreeshas95 1:a0055b3280c8 103 bbram_write;\
shreeshas95 1:a0055b3280c8 104 bbram_flag=1;\
shreeshas95 2:2caf2a9a13aa 105 flag = true;\
shreeshas95 1:a0055b3280c8 106 break;\
shreeshas95 1:a0055b3280c8 107 }\
shreeshas95 1:a0055b3280c8 108 else{\
shreeshas95 1:a0055b3280c8 109 hardware_reset(0);\
shreeshas95 1:a0055b3280c8 110 hw_reset_err_cnt++;\
aniruddhv 69:20f09a0c3fd2 111 /*gPC.puts("Resetting hardware\r\n");*/\
shreeshas95 1:a0055b3280c8 112 }\
shreeshas95 1:a0055b3280c8 113 }\
shreeshas95 2:2caf2a9a13aa 114 if( flag == false ){\
aniruddhv 69:20f09a0c3fd2 115 /*gPC.puts("Seems to be SPI problem\r\n");*/\
shreeshas95 2:2caf2a9a13aa 116 }\
shreeshas95 1:a0055b3280c8 117 assrt_phy_off(tempReturn);\
shreeshas95 1:a0055b3280c8 118 if(!bbram_flag){\
shreeshas95 1:a0055b3280c8 119 bcn_flag=1;\
shreeshas95 1:a0055b3280c8 120 }\
shreeshas95 1:a0055b3280c8 121 }
ee12b079 9:e9eaada136c6 122
shreeshas95 1:a0055b3280c8 123 unsigned char status =0;
shreeshas95 1:a0055b3280c8 124 unsigned int cmd_err_cnt=0;
shreeshas95 1:a0055b3280c8 125 unsigned int state_err_cnt=0;
shreeshas95 1:a0055b3280c8 126 unsigned int miso_err_cnt=0;
shreeshas95 1:a0055b3280c8 127 unsigned int hw_reset_err_cnt=0;
shreeshas95 1:a0055b3280c8 128 bool bcn_flag=0;
shreeshas95 1:a0055b3280c8 129 bool bbram_flag=0;
ee12b079 9:e9eaada136c6 130
shreeshas95 1:a0055b3280c8 131 bool hardware_reset(int bcn_call){
shreeshas95 1:a0055b3280c8 132 for(int i= 0; i < 20 ; i++){
shreeshas95 1:a0055b3280c8 133 gCS_ADF=0;
shreeshas95 1:a0055b3280c8 134 spi.write(CMD_HW_RESET);
shreeshas95 1:a0055b3280c8 135 gCS_ADF=1;
shreeshas95 1:a0055b3280c8 136 wait_ms(2);// Typically 1 ms
shreeshas95 1:a0055b3280c8 137 int count=0;
shreeshas95 1:a0055b3280c8 138 int temp_return = 0;
shreeshas95 1:a0055b3280c8 139 while(count<10 && miso_err_cnt<10){
shreeshas95 1:a0055b3280c8 140 if(MISO_PIN){
shreeshas95 1:a0055b3280c8 141 assrt_phy_off(temp_return);
shreeshas95 1:a0055b3280c8 142 if(!temp_return){
shreeshas95 1:a0055b3280c8 143 return 0;
shreeshas95 1:a0055b3280c8 144 }
shreeshas95 1:a0055b3280c8 145 count++;
shreeshas95 1:a0055b3280c8 146 }
shreeshas95 1:a0055b3280c8 147 else{
shreeshas95 1:a0055b3280c8 148 wait_us(50);
shreeshas95 1:a0055b3280c8 149 miso_err_cnt++;
shreeshas95 1:a0055b3280c8 150 }
shreeshas95 1:a0055b3280c8 151 }
shreeshas95 1:a0055b3280c8 152 }
shreeshas95 1:a0055b3280c8 153 return 1;
shreeshas95 1:a0055b3280c8 154 }
ee12b079 9:e9eaada136c6 155
shreeshas95 1:a0055b3280c8 156 //for reseting the transmission call assert function after b5 and b1. after b1 assert_phi_on and after b5 assert_phi_tx.
shreeshas95 1:a0055b3280c8 157 //----------------------------------------------------------------------------
ee12b079 9:e9eaada136c6 158
shreeshas95 1:a0055b3280c8 159 # define initiate {\
shreeshas95 1:a0055b3280c8 160 SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 161 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 162 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 163 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 164 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 165 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 166 spi.write(0x08);\
shreeshas95 1:a0055b3280c8 167 spi.write(0x14);\
shreeshas95 1:a0055b3280c8 168 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 169 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 170 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 171 spi.write(0x08);\
shreeshas95 1:a0055b3280c8 172 spi.write(0x15);\
shreeshas95 1:a0055b3280c8 173 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 174 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 175 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 176 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 177 spi.write(0x24);\
shreeshas95 1:a0055b3280c8 178 spi.write(0x20);\
shreeshas95 1:a0055b3280c8 179 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 180 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 181 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 182 spi.write(0x37);\
shreeshas95 1:a0055b3280c8 183 spi.write(0xE0);\
shreeshas95 1:a0055b3280c8 184 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 185 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 186 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 187 spi.write(0x36);\
shreeshas95 1:a0055b3280c8 188 spi.write(0x70);\
shreeshas95 1:a0055b3280c8 189 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 190 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 191 spi.write(0x09);\
shreeshas95 1:a0055b3280c8 192 spi.write(0x39);\
shreeshas95 1:a0055b3280c8 193 spi.write(0x10);\
shreeshas95 1:a0055b3280c8 194 gCS_ADF=1;\
ee12b079 9:e9eaada136c6 195 gCS_ADF=0;\
ee12b079 9:e9eaada136c6 196 spi.write(0xBB);\
ee12b079 9:e9eaada136c6 197 gCS_ADF=1;\
ee12b079 9:e9eaada136c6 198 gCS_ADF=0;\
ee12b079 9:e9eaada136c6 199 spi.write(0xFF);\
ee12b079 9:e9eaada136c6 200 spi.write(0xFF);\
ee12b079 9:e9eaada136c6 201 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 202 SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 203 }
ee12b079 9:e9eaada136c6 204
shreeshas95 1:a0055b3280c8 205 #define write_data {\
shreeshas95 1:a0055b3280c8 206 SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 207 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 208 spi.write(0x0B);\
shreeshas95 1:a0055b3280c8 209 spi.write(0x36);\
shreeshas95 1:a0055b3280c8 210 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 211 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 212 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 213 if(buffer_state){\
shreeshas95 1:a0055b3280c8 214 spi.write(0x18);\
shreeshas95 1:a0055b3280c8 215 spi.write(0x20);\
shreeshas95 1:a0055b3280c8 216 for(unsigned char i=0; i<112;i++){\
shreeshas95 1:a0055b3280c8 217 spi.write(buffer_112[i]);\
shreeshas95 1:a0055b3280c8 218 }\
shreeshas95 1:a0055b3280c8 219 }\
shreeshas95 1:a0055b3280c8 220 else{\
shreeshas95 1:a0055b3280c8 221 spi.write(0x18);\
shreeshas95 1:a0055b3280c8 222 spi.write(0x90);\
shreeshas95 1:a0055b3280c8 223 for(unsigned char i=0; i<112;i++){\
shreeshas95 1:a0055b3280c8 224 spi.write(buffer_112[i]);\
shreeshas95 1:a0055b3280c8 225 }\
shreeshas95 1:a0055b3280c8 226 }\
shreeshas95 1:a0055b3280c8 227 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 228 SPI_mutex.unlock();\
shreeshas95 1:a0055b3280c8 229 buffer_state = !buffer_state;\
shreeshas95 1:a0055b3280c8 230 if(last_buffer){\
ee12b079 9:e9eaada136c6 231 finish_write_data = true;\
aniruddhv 69:20f09a0c3fd2 232 /*gPC.puts("adf_off\r\n");*/\
shreeshas95 1:a0055b3280c8 233 }\
shreeshas95 1:a0055b3280c8 234 }
shreeshas95 1:a0055b3280c8 235
aniruddhv 52:0bd68655c651 236 /*
shreeshas95 1:a0055b3280c8 237 void check(){
shreeshas95 1:a0055b3280c8 238 if(IRQ){
shreeshas95 1:a0055b3280c8 239 gCOM_MNG_TMTC_THREAD->signal_set(signal);
shreeshas95 1:a0055b3280c8 240 }
aniruddhv 52:0bd68655c651 241 }*/
shreeshas95 1:a0055b3280c8 242
ee12b079 9:e9eaada136c6 243
shreeshas95 1:a0055b3280c8 244 #define send_data {\
ee12b079 88:b9beee1a7a3e 245 if(sent_tmfrom_SDcard){\
ee12b079 95:42d6747900cb 246 send_tm_from_SD_card_fun();\
shreeshas95 1:a0055b3280c8 247 }else{\
shreeshas95 1:a0055b3280c8 248 snd_tm.transmit_data(buffer_112,&last_buffer);\
shreeshas95 1:a0055b3280c8 249 }\
shreeshas95 1:a0055b3280c8 250 write_data;\
shreeshas95 1:a0055b3280c8 251 if(sent_tmfrom_SDcard){\
ee12b079 95:42d6747900cb 252 send_tm_from_SD_card_fun();\
shreeshas95 1:a0055b3280c8 253 }else{\
shreeshas95 1:a0055b3280c8 254 snd_tm.transmit_data(buffer_112,&last_buffer);\
shreeshas95 1:a0055b3280c8 255 }\
shreeshas95 1:a0055b3280c8 256 write_data;\
shreeshas95 1:a0055b3280c8 257 if(sent_tmfrom_SDcard){\
ee12b079 95:42d6747900cb 258 send_tm_from_SD_card_fun();\
shreeshas95 1:a0055b3280c8 259 }else{\
shreeshas95 1:a0055b3280c8 260 snd_tm.transmit_data(buffer_112,&last_buffer);\
shreeshas95 1:a0055b3280c8 261 }\
shreeshas95 1:a0055b3280c8 262 SPI_mutex.lock();\
shreeshas95 1:a0055b3280c8 263 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 264 spi.write(0xB1);\
shreeshas95 1:a0055b3280c8 265 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 266 wait_us(300);\
shreeshas95 1:a0055b3280c8 267 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 268 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 269 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 270 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 271 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 272 spi.write(0xB5);\
shreeshas95 1:a0055b3280c8 273 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 274 wait_us(300);\
shreeshas95 1:a0055b3280c8 275 gCS_ADF=0;\
shreeshas95 1:a0055b3280c8 276 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 277 spi.write(0xFF);\
shreeshas95 1:a0055b3280c8 278 gCS_ADF=1;\
shreeshas95 1:a0055b3280c8 279 SPI_mutex.unlock();\
aniruddhv 52:0bd68655c651 280 /*ticker.attach_us(&check,32000);*/\
shreeshas95 1:a0055b3280c8 281 }
ee12b079 9:e9eaada136c6 282
aniruddhv 52:0bd68655c651 283 #define configure_adf {\
aniruddhv 52:0bd68655c651 284 finish_write_data = false;\
aniruddhv 52:0bd68655c651 285 buffer_state = true;\
aniruddhv 52:0bd68655c651 286 last_buffer = false;\
aniruddhv 52:0bd68655c651 287 loop_on = true;\
aniruddhv 52:0bd68655c651 288 ADF_off = false;\
aniruddhv 52:0bd68655c651 289 initial_adf_check;\
aniruddhv 69:20f09a0c3fd2 290 /*gPC.puts("initial adf check\r\n");*/\
aniruddhv 52:0bd68655c651 291 initiate;\
aniruddhv 69:20f09a0c3fd2 292 /*gPC.puts("adf configured\r\n");*/\
ee12b079 96:4ca92f9775e0 293 /*gLEDR = !gLEDR;*/\
ee12b079 9:e9eaada136c6 294 }
ee12b079 9:e9eaada136c6 295
ee12b079 95:42d6747900cb 296 #define transmit_adf {\
aniruddhv 52:0bd68655c651 297 configure_adf;\
ee12b079 95:42d6747900cb 298 if(sent_tmfrom_SDcard)\
ee12b079 95:42d6747900cb 299 signal = COM_MNG_TMTC_SIGNAL_ADF_SD;\
ee12b079 95:42d6747900cb 300 else signal = COM_MNG_TMTC_SIGNAL_ADF_NSD;\
aniruddhv 52:0bd68655c651 301 send_data;\
aniruddhv 52:0bd68655c651 302 while(loop_on){\
aniruddhv 52:0bd68655c651 303 wait_ms(COM_TX_TICKER_LIMIT);\
aniruddhv 69:20f09a0c3fd2 304 if(IRQ || bypass_adf){\
aniruddhv 52:0bd68655c651 305 if(finish_write_data){\
aniruddhv 52:0bd68655c651 306 if(ADF_off){\
aniruddhv 52:0bd68655c651 307 SPI_mutex.lock();\
aniruddhv 52:0bd68655c651 308 gCS_ADF=0;\
aniruddhv 52:0bd68655c651 309 spi.write(0xB1);\
aniruddhv 52:0bd68655c651 310 gCS_ADF=1;\
aniruddhv 52:0bd68655c651 311 SPI_mutex.unlock();\
aniruddhv 52:0bd68655c651 312 loop_on = false;\
aniruddhv 52:0bd68655c651 313 }\
aniruddhv 52:0bd68655c651 314 else{\
aniruddhv 52:0bd68655c651 315 ADF_off = true;\
aniruddhv 52:0bd68655c651 316 }\
ee12b079 96:4ca92f9775e0 317 }else{\
ee12b079 132:d4a4461214ad 318 gLEDG = !gLEDG;\
aniruddhv 52:0bd68655c651 319 write_data;\
ee12b079 95:42d6747900cb 320 if(sent_tmfrom_SDcard)\
ee12b079 95:42d6747900cb 321 send_tm_from_SD_card_fun();\
ee12b079 95:42d6747900cb 322 else snd_tm.transmit_data(buffer_112,&last_buffer);\
aniruddhv 52:0bd68655c651 323 }\
aniruddhv 52:0bd68655c651 324 }\
aniruddhv 52:0bd68655c651 325 }\
aniruddhv 69:20f09a0c3fd2 326 /*gPC.puts("after while loop\r\n");*/\
ee12b079 88:b9beee1a7a3e 327 }
ee12b079 88:b9beee1a7a3e 328