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lpc17xx_emac.h
00001 /********************************************************************** 00002 * $Id$ lpc17xx_emac.h 2010-05-21 00003 *//** 00004 * @file lpc17xx_emac.h 00005 * @brief Contains all macro definitions and function prototypes 00006 * support for Ethernet MAC firmware library on LPC17xx 00007 * @version 2.0 00008 * @date 21. May. 2010 00009 * @author NXP MCU SW Application Team 00010 * 00011 * Copyright(C) 2010, NXP Semiconductor 00012 * All rights reserved. 00013 * 00014 *********************************************************************** 00015 * Software that is described herein is for illustrative purposes only 00016 * which provides customers with programming information regarding the 00017 * products. This software is supplied "AS IS" without any warranties. 00018 * NXP Semiconductors assumes no responsibility or liability for the 00019 * use of the software, conveys no license or title under any patent, 00020 * copyright, or mask work right to the product. NXP Semiconductors 00021 * reserves the right to make changes in the software without 00022 * notification. NXP Semiconductors also make no representation or 00023 * warranty that such application will be suitable for the specified 00024 * use without further testing or modification. 00025 **********************************************************************/ 00026 00027 /* Peripheral group ----------------------------------------------------------- */ 00028 /** @defgroup EMAC EMAC (Ethernet Media Access Controller) 00029 * @ingroup LPC1700CMSIS_FwLib_Drivers 00030 * @{ 00031 */ 00032 00033 #ifndef LPC17XX_EMAC_H_ 00034 #define LPC17XX_EMAC_H_ 00035 00036 /* Includes ------------------------------------------------------------------- */ 00037 #include "LPC17xx.h" 00038 #include "lpc_types.h" 00039 00040 00041 #ifdef __cplusplus 00042 extern "C" 00043 { 00044 #endif 00045 00046 #define MCB_LPC_1768 00047 //#define IAR_LPC_1768 00048 00049 /* Public Macros -------------------------------------------------------------- */ 00050 /** @defgroup EMAC_Public_Macros EMAC Public Macros 00051 * @{ 00052 */ 00053 00054 00055 /* EMAC PHY status type definitions */ 00056 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */ 00057 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */ 00058 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */ 00059 00060 /* EMAC PHY device Speed definitions */ 00061 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */ 00062 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */ 00063 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */ 00064 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */ 00065 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */ 00066 00067 /** 00068 * @} 00069 */ 00070 /* Private Macros ------------------------------------------------------------- */ 00071 /** @defgroup EMAC_Private_Macros EMAC Private Macros 00072 * @{ 00073 */ 00074 00075 00076 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */ 00077 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */ 00078 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */ 00079 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */ 00080 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */ 00081 00082 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 00083 /*********************************************************************//** 00084 * Macro defines for MAC Configuration Register 1 00085 **********************************************************************/ 00086 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */ 00087 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */ 00088 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */ 00089 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */ 00090 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */ 00091 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */ 00092 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */ 00093 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */ 00094 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */ 00095 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */ 00096 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */ 00097 00098 /*********************************************************************//** 00099 * Macro defines for MAC Configuration Register 2 00100 **********************************************************************/ 00101 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */ 00102 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */ 00103 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */ 00104 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */ 00105 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */ 00106 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */ 00107 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */ 00108 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */ 00109 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */ 00110 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */ 00111 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */ 00112 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */ 00113 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */ 00114 00115 /*********************************************************************//** 00116 * Macro defines for Back-to-Back Inter-Packet-Gap Register 00117 **********************************************************************/ 00118 /** Programmable field representing the nibble time offset of the minimum possible period 00119 * between the end of any transmitted packet to the beginning of the next */ 00120 #define EMAC_IPGT_BBIPG(n) (n&0x7F) 00121 /** Recommended value for Full Duplex of Programmable field representing the nibble time 00122 * offset of the minimum possible period between the end of any transmitted packet to the 00123 * beginning of the next */ 00124 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) 00125 /** Recommended value for Half Duplex of Programmable field representing the nibble time 00126 * offset of the minimum possible period between the end of any transmitted packet to the 00127 * beginning of the next */ 00128 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) 00129 00130 /*********************************************************************//** 00131 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register 00132 **********************************************************************/ 00133 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */ 00134 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) 00135 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */ 00136 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) 00137 /** Programmable field representing the optional carrierSense window referenced in 00138 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */ 00139 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) 00140 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */ 00141 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) 00142 00143 /*********************************************************************//** 00144 * Macro defines for Collision Window/Retry Register 00145 **********************************************************************/ 00146 /** Programmable field specifying the number of retransmission attempts following a collision before 00147 * aborting the packet due to excessive collisions */ 00148 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F) 00149 /** Programmable field representing the slot time or collision window during which collisions occur 00150 * in properly configured networks */ 00151 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8) 00152 /** Default value for Collision Window / Retry register */ 00153 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) 00154 00155 /*********************************************************************//** 00156 * Macro defines for Maximum Frame Register 00157 **********************************************************************/ 00158 /** Represents a maximum receive frame of 1536 octets */ 00159 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) 00160 00161 /*********************************************************************//** 00162 * Macro defines for PHY Support Register 00163 **********************************************************************/ 00164 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */ 00165 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */ 00166 00167 /*********************************************************************//** 00168 * Macro defines for Test Register 00169 **********************************************************************/ 00170 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */ 00171 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */ 00172 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */ 00173 00174 /*********************************************************************//** 00175 * Macro defines for MII Management Configuration Register 00176 **********************************************************************/ 00177 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */ 00178 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */ 00179 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */ 00180 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */ 00181 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */ 00182 00183 /*********************************************************************//** 00184 * Macro defines for MII Management Command Register 00185 **********************************************************************/ 00186 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */ 00187 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */ 00188 00189 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */ 00190 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */ 00191 00192 /*********************************************************************//** 00193 * Macro defines for MII Management Address Register 00194 **********************************************************************/ 00195 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */ 00196 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */ 00197 00198 /*********************************************************************//** 00199 * Macro defines for MII Management Write Data Register 00200 **********************************************************************/ 00201 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */ 00202 00203 /*********************************************************************//** 00204 * Macro defines for MII Management Read Data Register 00205 **********************************************************************/ 00206 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */ 00207 00208 /*********************************************************************//** 00209 * Macro defines for MII Management Indicators Register 00210 **********************************************************************/ 00211 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */ 00212 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */ 00213 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */ 00214 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */ 00215 00216 /* Station Address 0 Register */ 00217 /* Station Address 1 Register */ 00218 /* Station Address 2 Register */ 00219 00220 00221 /* Control register definitions --------------------------------------------------------------------------- */ 00222 /*********************************************************************//** 00223 * Macro defines for Command Register 00224 **********************************************************************/ 00225 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */ 00226 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */ 00227 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */ 00228 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */ 00229 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */ 00230 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */ 00231 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */ 00232 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */ 00233 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */ 00234 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */ 00235 00236 /*********************************************************************//** 00237 * Macro defines for Status Register 00238 **********************************************************************/ 00239 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */ 00240 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */ 00241 00242 /*********************************************************************//** 00243 * Macro defines for Transmit Status Vector 0 Register 00244 **********************************************************************/ 00245 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */ 00246 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */ 00247 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */ 00248 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */ 00249 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */ 00250 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */ 00251 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ 00252 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ 00253 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ 00254 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ 00255 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ 00256 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ 00257 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ 00258 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */ 00259 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */ 00260 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */ 00261 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */ 00262 00263 /*********************************************************************//** 00264 * Macro defines for Transmit Status Vector 1 Register 00265 **********************************************************************/ 00266 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */ 00267 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */ 00268 00269 /*********************************************************************//** 00270 * Macro defines for Receive Status Vector Register 00271 **********************************************************************/ 00272 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */ 00273 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */ 00274 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */ 00275 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */ 00276 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */ 00277 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */ 00278 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */ 00279 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */ 00280 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */ 00281 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */ 00282 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */ 00283 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */ 00284 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */ 00285 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */ 00286 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */ 00287 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */ 00288 00289 /*********************************************************************//** 00290 * Macro defines for Flow Control Counter Register 00291 **********************************************************************/ 00292 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */ 00293 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */ 00294 00295 /*********************************************************************//** 00296 * Macro defines for Flow Control Status Register 00297 **********************************************************************/ 00298 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */ 00299 00300 00301 /* Receive filter register definitions -------------------------------------------------------- */ 00302 /*********************************************************************//** 00303 * Macro defines for Receive Filter Control Register 00304 **********************************************************************/ 00305 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */ 00306 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */ 00307 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */ 00308 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */ 00309 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/ 00310 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */ 00311 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */ 00312 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */ 00313 00314 /*********************************************************************//** 00315 * Macro defines for Receive Filter WoL Status/Clear Registers 00316 **********************************************************************/ 00317 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */ 00318 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */ 00319 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */ 00320 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */ 00321 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */ 00322 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */ 00323 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */ 00324 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */ 00325 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */ 00326 00327 00328 /* Module control register definitions ---------------------------------------------------- */ 00329 /*********************************************************************//** 00330 * Macro defines for Interrupt Status/Enable/Clear/Set Registers 00331 **********************************************************************/ 00332 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */ 00333 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */ 00334 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */ 00335 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */ 00336 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */ 00337 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */ 00338 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */ 00339 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */ 00340 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */ 00341 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */ 00342 00343 /*********************************************************************//** 00344 * Macro defines for Power Down Register 00345 **********************************************************************/ 00346 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */ 00347 00348 /* Descriptor and status formats ---------------------------------------------------- */ 00349 /*********************************************************************//** 00350 * Macro defines for RX Descriptor Control Word 00351 **********************************************************************/ 00352 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */ 00353 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */ 00354 00355 /*********************************************************************//** 00356 * Macro defines for RX Status Hash CRC Word 00357 **********************************************************************/ 00358 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */ 00359 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */ 00360 00361 /*********************************************************************//** 00362 * Macro defines for RX Status Information Word 00363 **********************************************************************/ 00364 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */ 00365 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */ 00366 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */ 00367 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */ 00368 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */ 00369 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */ 00370 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */ 00371 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */ 00372 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */ 00373 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */ 00374 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */ 00375 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ 00376 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ 00377 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ 00378 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ 00379 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ 00380 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) 00381 00382 /*********************************************************************//** 00383 * Macro defines for TX Descriptor Control Word 00384 **********************************************************************/ 00385 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */ 00386 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */ 00387 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */ 00388 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */ 00389 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */ 00390 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */ 00391 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */ 00392 00393 /*********************************************************************//** 00394 * Macro defines for TX Status Information Word 00395 **********************************************************************/ 00396 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */ 00397 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ 00398 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ 00399 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ 00400 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ 00401 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ 00402 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ 00403 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ 00404 00405 #ifdef MCB_LPC_1768 00406 /* DP83848C PHY definition ------------------------------------------------------------ */ 00407 00408 /** PHY device reset time out definition */ 00409 #define EMAC_PHY_RESP_TOUT 0x100000UL 00410 00411 /* ENET Device Revision ID */ 00412 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ 00413 00414 /*********************************************************************//** 00415 * Macro defines for DP83848C PHY Registers 00416 **********************************************************************/ 00417 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ 00418 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ 00419 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ 00420 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ 00421 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ 00422 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ 00423 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ 00424 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ 00425 #define EMAC_PHY_REG_LPNPA 0x08 00426 00427 /*********************************************************************//** 00428 * Macro defines for PHY Extended Registers 00429 **********************************************************************/ 00430 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */ 00431 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */ 00432 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */ 00433 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */ 00434 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */ 00435 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */ 00436 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */ 00437 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */ 00438 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */ 00439 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */ 00440 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */ 00441 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */ 00442 00443 /*********************************************************************//** 00444 * Macro defines for PHY Basic Mode Control Register 00445 **********************************************************************/ 00446 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ 00447 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ 00448 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ 00449 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ 00450 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ 00451 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ 00452 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ 00453 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ 00454 00455 /*********************************************************************//** 00456 * Macro defines for PHY Basic Mode Status Status Register 00457 **********************************************************************/ 00458 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ 00459 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ 00460 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ 00461 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ 00462 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ 00463 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ 00464 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ 00465 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ 00466 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ 00467 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */ 00468 00469 /*********************************************************************//** 00470 * Macro defines for PHY Status Register 00471 **********************************************************************/ 00472 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */ 00473 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */ 00474 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */ 00475 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */ 00476 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */ 00477 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */ 00478 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */ 00479 00480 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ 00481 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ 00482 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ 00483 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ 00484 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ 00485 00486 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */ 00487 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */ 00488 00489 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) 00490 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) 00491 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ 00492 00493 #elif defined(IAR_LPC_1768) 00494 /* KSZ8721BL PHY definition ------------------------------------------------------------ */ 00495 /** PHY device reset time out definition */ 00496 #define EMAC_PHY_RESP_TOUT 0x100000UL 00497 00498 /* ENET Device Revision ID */ 00499 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ 00500 00501 /*********************************************************************//** 00502 * Macro defines for KSZ8721BL PHY Registers 00503 **********************************************************************/ 00504 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ 00505 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ 00506 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ 00507 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ 00508 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ 00509 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ 00510 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ 00511 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ 00512 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ 00513 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */ 00514 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */ 00515 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */ 00516 00517 /*********************************************************************//** 00518 * Macro defines for PHY Basic Mode Control Register 00519 **********************************************************************/ 00520 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ 00521 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ 00522 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ 00523 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ 00524 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ 00525 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ 00526 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ 00527 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ 00528 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */ 00529 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */ 00530 00531 /*********************************************************************//** 00532 * Macro defines for PHY Basic Mode Status Register 00533 **********************************************************************/ 00534 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ 00535 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ 00536 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ 00537 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ 00538 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ 00539 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ 00540 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ 00541 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ 00542 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ 00543 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ 00544 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */ 00545 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */ 00546 00547 /*********************************************************************//** 00548 * Macro defines for PHY Identifier 00549 **********************************************************************/ 00550 /* PHY Identifier 1 bitmap definitions */ 00551 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */ 00552 00553 /* PHY Identifier 2 bitmap definitions */ 00554 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */ 00555 00556 /*********************************************************************//** 00557 * Macro defines for Auto-Negotiation Advertisement 00558 **********************************************************************/ 00559 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */ 00560 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */ 00561 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */ 00562 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */ 00563 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */ 00564 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */ 00565 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */ 00566 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */ 00567 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */ 00568 00569 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ 00570 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ 00571 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ 00572 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ 00573 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ 00574 00575 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) 00576 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) 00577 00578 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */ 00579 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */ 00580 #endif 00581 00582 /** 00583 * @} 00584 */ 00585 00586 /** Ethernet block power/clock control bit*/ 00587 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) 00588 00589 #ifdef __cplusplus 00590 } 00591 #endif 00592 00593 #endif /* LPC17XX_EMAC_H_ */ 00594 00595 /** 00596 * @} 00597 */ 00598 00599 /* --------------------------------- End Of File ------------------------------ */
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