Pratyush Mallick / Mbed OS testing

this is testing

app/noos_mbed/drivers/adc/ad713x/ad713x.h@0:3afcd581558d, 2021-01-14 (annotated)

Committer:
pmallick
Date:
Thu Jan 14 18:54:16 2021 +0530
Revision:
0:3afcd581558d
this is testing

Who changed what in which revision?

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pmallick 0:3afcd581558d 1 /***************************************************************************//**
pmallick 0:3afcd581558d 2 * @file ad713x.h
pmallick 0:3afcd581558d 3 * @brief Header file for the ad713x Driver.
pmallick 0:3afcd581558d 4 * @author SPopa (stefan.popa@analog.com)
pmallick 0:3afcd581558d 5 * @author Andrei Drimbarean (andrei.drimbarean@analog.com)
pmallick 0:3afcd581558d 6 ********************************************************************************
pmallick 0:3afcd581558d 7 * Copyright 2020(c) Analog Devices, Inc.
pmallick 0:3afcd581558d 8 *
pmallick 0:3afcd581558d 9 * All rights reserved.
pmallick 0:3afcd581558d 10 *
pmallick 0:3afcd581558d 11 * Redistribution and use in source and binary forms, with or without
pmallick 0:3afcd581558d 12 * modification, are permitted provided that the following conditions are met:
pmallick 0:3afcd581558d 13 * - Redistributions of source code must retain the above copyright
pmallick 0:3afcd581558d 14 * notice, this list of conditions and the following disclaimer.
pmallick 0:3afcd581558d 15 * - Redistributions in binary form must reproduce the above copyright
pmallick 0:3afcd581558d 16 * notice, this list of conditions and the following disclaimer in
pmallick 0:3afcd581558d 17 * the documentation and/or other materials provided with the
pmallick 0:3afcd581558d 18 * distribution.
pmallick 0:3afcd581558d 19 * - Neither the name of Analog Devices, Inc. nor the names of its
pmallick 0:3afcd581558d 20 * contributors may be used to endorse or promote products derived
pmallick 0:3afcd581558d 21 * from this software without specific prior written permission.
pmallick 0:3afcd581558d 22 * - The use of this software may or may not infringe the patent rights
pmallick 0:3afcd581558d 23 * of one or more patent holders. This license does not release you
pmallick 0:3afcd581558d 24 * from the requirement that you obtain separate licenses from these
pmallick 0:3afcd581558d 25 * patent holders to use this software.
pmallick 0:3afcd581558d 26 * - Use of the software either in source or binary form, must be run
pmallick 0:3afcd581558d 27 * on or directly connected to an Analog Devices Inc. component.
pmallick 0:3afcd581558d 28 *
pmallick 0:3afcd581558d 29 * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
pmallick 0:3afcd581558d 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
pmallick 0:3afcd581558d 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
pmallick 0:3afcd581558d 32 * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
pmallick 0:3afcd581558d 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
pmallick 0:3afcd581558d 34 * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
pmallick 0:3afcd581558d 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
pmallick 0:3afcd581558d 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
pmallick 0:3afcd581558d 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
pmallick 0:3afcd581558d 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pmallick 0:3afcd581558d 39 *******************************************************************************/
pmallick 0:3afcd581558d 40
pmallick 0:3afcd581558d 41 #ifndef SRC_AD713X_H_
pmallick 0:3afcd581558d 42 #define SRC_AD713X_H_
pmallick 0:3afcd581558d 43
pmallick 0:3afcd581558d 44 /******************************************************************************/
pmallick 0:3afcd581558d 45 /***************************** Include Files **********************************/
pmallick 0:3afcd581558d 46 /******************************************************************************/
pmallick 0:3afcd581558d 47
pmallick 0:3afcd581558d 48 #include <stdbool.h>
pmallick 0:3afcd581558d 49 #include <stdio.h>
pmallick 0:3afcd581558d 50
pmallick 0:3afcd581558d 51 #include "platform_drivers.h"
pmallick 0:3afcd581558d 52
pmallick 0:3afcd581558d 53 /******************************************************************************/
pmallick 0:3afcd581558d 54 /********************** Macros and Constants Definitions **********************/
pmallick 0:3afcd581558d 55 /******************************************************************************/
pmallick 0:3afcd581558d 56 /*
pmallick 0:3afcd581558d 57 * AD713X registers definition
pmallick 0:3afcd581558d 58 */
pmallick 0:3afcd581558d 59 #define AD713X_REG_INTERFACE_CONFIG_A 0x00
pmallick 0:3afcd581558d 60 #define AD713X_REG_INTERFACE_CONFIG_B 0x01
pmallick 0:3afcd581558d 61 #define AD713X_REG_DEVICE_CONFIG 0x02
pmallick 0:3afcd581558d 62 #define AD713X_REG_CHIP_TYPE 0x03
pmallick 0:3afcd581558d 63 #define AD713X_REG_PRODUCT_ID_LSB 0x04
pmallick 0:3afcd581558d 64 #define AD713X_REG_PRODUCT_ID_MSB 0x05
pmallick 0:3afcd581558d 65 #define AD713X_REG_CHIP_GRADE 0x06
pmallick 0:3afcd581558d 66 #define AD713X_REG_CHIP_INDEX 0x07
pmallick 0:3afcd581558d 67 #define AD713X_REG_SCTATCH_PAD 0x0A
pmallick 0:3afcd581558d 68 #define AD713X_REG_SPI_REVISION 0x0B
pmallick 0:3afcd581558d 69 #define AD713X_REG_VENDOR_ID_LSB 0x0C
pmallick 0:3afcd581558d 70 #define AD713X_REG_VENDOR_ID_MSB 0x0D
pmallick 0:3afcd581558d 71 #define AD713X_REG_STREAM_MODE 0x0E
pmallick 0:3afcd581558d 72 #define AD713X_REG_TRANSFER_REGISTER 0x0F
pmallick 0:3afcd581558d 73 #define AD713X_REG_DEVICE_CONFIG1 0x10
pmallick 0:3afcd581558d 74 #define AD713X_REG_DATA_PACKET_CONFIG 0x11
pmallick 0:3afcd581558d 75 #define AD713X_REG_DIGITAL_INTERFACE_CONFIG 0x12
pmallick 0:3afcd581558d 76 #define AD713X_REG_POWER_DOWN_CONTROL 0x13
pmallick 0:3afcd581558d 77 #define AD713X_REG_AIN_RANGE_SELECT 0x14
pmallick 0:3afcd581558d 78 #define AD713X_REG_DEVICE_STATUS 0x15
pmallick 0:3afcd581558d 79 #define AD713X_REG_ODR_VAL_INT_LSB 0x16
pmallick 0:3afcd581558d 80 #define AD713X_REG_ODR_VAL_INT_MID 0x17
pmallick 0:3afcd581558d 81 #define AD713X_REG_ODR_VAL_INT_MSB 0x18
pmallick 0:3afcd581558d 82 #define AD713X_REG_ODR_VAL_FLT_LSB 0x19
pmallick 0:3afcd581558d 83 #define AD713X_REG_ODR_VAL_FLT_MID0 0x1A
pmallick 0:3afcd581558d 84 #define AD713X_REG_ODR_VAL_FLT_MID1 0x1B
pmallick 0:3afcd581558d 85 #define AD713X_REG_ODR_VAL_FLT_MSB 0x1C
pmallick 0:3afcd581558d 86 #define AD713X_REG_CHANNEL_ODR_SELECT 0x1D
pmallick 0:3afcd581558d 87 #define AD713X_REG_CHAN_DIG_FILTER_SEL 0x1E
pmallick 0:3afcd581558d 88 #define AD713X_REG_FIR_BW_SEL 0x1F
pmallick 0:3afcd581558d 89 #define AD713X_REG_GPIO_DIR_CTRL 0x20
pmallick 0:3afcd581558d 90 #define AD713X_REG_GPIO_DATA 0x21
pmallick 0:3afcd581558d 91 #define AD713X_REG_ERROR_PIN_SRC_CONTROL 0x22
pmallick 0:3afcd581558d 92 #define AD713X_REG_ERROR_PIN_CONTROL 0x23
pmallick 0:3afcd581558d 93 #define AD713X_REG_VCMBUF_CTRL 0x24
pmallick 0:3afcd581558d 94 #define AD713X_REG_DIAGNOSTIC_CONTROL 0x25
pmallick 0:3afcd581558d 95 #define AD713X_REG_MPC_CONFIG 0x26
pmallick 0:3afcd581558d 96 #define AD713X_REG_CH0_GAIN_LSB 0x27
pmallick 0:3afcd581558d 97 #define AD713X_REG_CH0_GAIN_MID 0x28
pmallick 0:3afcd581558d 98 #define AD713X_REG_CH0_GAIN_MSB 0x29
pmallick 0:3afcd581558d 99 #define AD713X_REG_CH0_OFFSET_LSB 0x2A
pmallick 0:3afcd581558d 100 #define AD713X_REG_CH0_OFFSET_MID 0x2B
pmallick 0:3afcd581558d 101 #define AD713X_REG_CH0_OFFSET_MSB 0x2C
pmallick 0:3afcd581558d 102 #define AD713X_REG_CH1_GAIN_LSB 0x2D
pmallick 0:3afcd581558d 103 #define AD713X_REG_CH1_GAIN_MID 0x2E
pmallick 0:3afcd581558d 104 #define AD713X_REG_CH1_GAIN_MSB 0x2F
pmallick 0:3afcd581558d 105 #define AD713X_REG_CH1_OFFSET_LSB 0x30
pmallick 0:3afcd581558d 106 #define AD713X_REG_CH1_OFFSET_MID 0x31
pmallick 0:3afcd581558d 107 #define AD713X_REG_CH1_OFFSET_MSB 0x32
pmallick 0:3afcd581558d 108 #define AD713X_REG_CH2_GAIN_LSB 0x33
pmallick 0:3afcd581558d 109 #define AD713X_REG_CH2_GAIN_MID 0x34
pmallick 0:3afcd581558d 110 #define AD713X_REG_CH2_GAIN_MSB 0x35
pmallick 0:3afcd581558d 111 #define AD713X_REG_CH2_OFFSET_LSB 0x36
pmallick 0:3afcd581558d 112 #define AD713X_REG_CH2_OFFSET_MID 0x37
pmallick 0:3afcd581558d 113 #define AD713X_REG_CH2_OFFSET_MSB 0x38
pmallick 0:3afcd581558d 114 #define AD713X_REG_CH3_GAIN_LSB 0x39
pmallick 0:3afcd581558d 115 #define AD713X_REG_CH3_GAIN_MID 0x3A
pmallick 0:3afcd581558d 116 #define AD713X_REG_CH3_GAIN_MSB 0x3B
pmallick 0:3afcd581558d 117 #define AD713X_REG_CH3_OFFSET_LSB 0x3C
pmallick 0:3afcd581558d 118 #define AD713X_REG_CH3_OFFSET_MID 0x3D
pmallick 0:3afcd581558d 119 #define AD713X_REG_CH3_OFFSET_MSB 0x3E
pmallick 0:3afcd581558d 120 #define AD713X_REG_MCLK_COUNTER 0x3F
pmallick 0:3afcd581558d 121 #define AD713X_REG_DIG_FILTER_OFUF 0x40
pmallick 0:3afcd581558d 122 #define AD713X_REG_DIG_FILTER_SETTLED 0x41
pmallick 0:3afcd581558d 123 #define AD713X_REG_INTERNAL_ERROR 0x42
pmallick 0:3afcd581558d 124 #define AD713X_REG_POWER_OV_ERROR_1 0x43
pmallick 0:3afcd581558d 125 #define AD713X_REG_POWER_UV_ERROR_1 0x44
pmallick 0:3afcd581558d 126 #define AD713X_REG_POWER_OV_ERROR_2 0x45
pmallick 0:3afcd581558d 127 #define AD713X_REG_POWER_UV_ERROR_2 0x46
pmallick 0:3afcd581558d 128 #define AD713X_REG_SPI_ERROR 0x47
pmallick 0:3afcd581558d 129 #define AD713X_REG_AIN_OR_ERROR 0x48
pmallick 0:3afcd581558d 130 #define AD713X_REG_AVDD5_VALUE 0x49
pmallick 0:3afcd581558d 131 #define AD713X_REG_DVDD5_VALUE 0x4A
pmallick 0:3afcd581558d 132 #define AD713X_REG_VREF_VALUE 0x4B
pmallick 0:3afcd581558d 133 #define AD713X_REG_LDOIN_VALUE 0x4C
pmallick 0:3afcd581558d 134 #define AD713X_REG_AVDD1V8_VALUE 0x4D
pmallick 0:3afcd581558d 135 #define AD713X_REG_DVDD1V8_VALUE 0x4E
pmallick 0:3afcd581558d 136 #define AD713X_REG_CLKVDD_VALUE 0x4F
pmallick 0:3afcd581558d 137 #define AD713X_REG_IOVDD_VALUE 0x50
pmallick 0:3afcd581558d 138 #define AD713X_REG_TEMPERATURE_DATA 0x51
pmallick 0:3afcd581558d 139
pmallick 0:3afcd581558d 140 /*
pmallick 0:3afcd581558d 141 * AD713X_REG_INTERFACE_CONFIG_A
pmallick 0:3afcd581558d 142 */
pmallick 0:3afcd581558d 143 #define AD713X_INT_CONFIG_A_SOFT_RESET_MSK BIT(7)
pmallick 0:3afcd581558d 144 #define AD713X_INT_CONFIG_A_ADDR_ASC_BIT_MSK BIT(5)
pmallick 0:3afcd581558d 145 #define AD713X_INT_CONFIG_A_SDO_ACTIVE_BIT_MSK BIT(4)
pmallick 0:3afcd581558d 146 #define AD713X_INT_CONFIG_A_SOFT_RESET_MIRR_MSK BIT(0)
pmallick 0:3afcd581558d 147 #define AD713X_INT_CONFIG_A_ADDR_ASC_MIRR_MSK BIT(2)
pmallick 0:3afcd581558d 148 #define AD713X_INT_CONFIG_A_SDO_ACTIVE_MIRR_MSK BIT(3)
pmallick 0:3afcd581558d 149
pmallick 0:3afcd581558d 150 /*
pmallick 0:3afcd581558d 151 * AD713X_REG_INTERFACE_CONFIG_B
pmallick 0:3afcd581558d 152 */
pmallick 0:3afcd581558d 153 #define AD713X_INT_CONFIG_B_SINGLE_INSTR_MSK BIT(7)
pmallick 0:3afcd581558d 154 #define AD713X_INT_CONFIG_B_M_S_RD_CTRL_MSK BIT(5)
pmallick 0:3afcd581558d 155 #define AD713X_INT_CONFIG_B_DIG_IF_RST_MSK BIT(1)
pmallick 0:3afcd581558d 156
pmallick 0:3afcd581558d 157 /*
pmallick 0:3afcd581558d 158 * AD713X_REG_DEVICE_CONFIG
pmallick 0:3afcd581558d 159 */
pmallick 0:3afcd581558d 160 #define AD713X_DEV_CONFIG_OP_IN_PROGRESS_MSK BIT(5)
pmallick 0:3afcd581558d 161 #define AD713X_DEV_CONFIG_NO_CHIP_ERR_MSK BIT(4)
pmallick 0:3afcd581558d 162 #define AD713X_DEV_CONFIG_PWR_MODE_MSK BIT(0)
pmallick 0:3afcd581558d 163
pmallick 0:3afcd581558d 164 /*
pmallick 0:3afcd581558d 165 * AD713X_REG_CHIP_TYPE
pmallick 0:3afcd581558d 166 */
pmallick 0:3afcd581558d 167 #define AD713X_CHIP_TYPE_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 168 #define AD713X_CHIP_TYPE_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 169
pmallick 0:3afcd581558d 170 /*
pmallick 0:3afcd581558d 171 * AD713X_REG_PRODUCT_ID_LSB
pmallick 0:3afcd581558d 172 */
pmallick 0:3afcd581558d 173 #define AD713X_PRODUCT_ID_LSB_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 174 #define AD713X_PRODUCT_ID_LSB_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 175
pmallick 0:3afcd581558d 176 /*
pmallick 0:3afcd581558d 177 * AD713X_REG_PRODUCT_ID_MSB
pmallick 0:3afcd581558d 178 */
pmallick 0:3afcd581558d 179 #define AD713X_PRODUCT_ID_MSB_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 180 #define AD713X_PRODUCT_ID_MSB_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 181
pmallick 0:3afcd581558d 182 /*
pmallick 0:3afcd581558d 183 * AD713X_REG_CHIP_GRADE
pmallick 0:3afcd581558d 184 */
pmallick 0:3afcd581558d 185 #define AD713X_CHIP_GRADE_PROD_GRADE_BITS_MSK GENMASK(7, 4)
pmallick 0:3afcd581558d 186 #define AD713X_CHIP_GRADE_PROD_GRADE_BITS_MODE(x) (((x) & 0x0F) << 4)
pmallick 0:3afcd581558d 187 #define AD713X_CHIP_GRADE_DEV_VERSION_BITS_MSK GENMASK(3, 0)
pmallick 0:3afcd581558d 188 #define AD713X_CHIP_GRADE_DEV_VERSION_BITS_MODE(x) (((x) & 0x0F) << 0)
pmallick 0:3afcd581558d 189
pmallick 0:3afcd581558d 190 /*
pmallick 0:3afcd581558d 191 * AD713X_REG_CHIP_INDEX
pmallick 0:3afcd581558d 192 */
pmallick 0:3afcd581558d 193 #define AD713X_SILICON_REV_ID_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 194 #define AD713X_SILICON_REV_ID_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 195
pmallick 0:3afcd581558d 196 /*
pmallick 0:3afcd581558d 197 * AD713X_REG_SCRATCH_PAD
pmallick 0:3afcd581558d 198 */
pmallick 0:3afcd581558d 199 #define AD713X_SCRATCH_PAD_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 200 #define AD713X_SCRATCH_PAD_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 201
pmallick 0:3afcd581558d 202 /*
pmallick 0:3afcd581558d 203 * AD713X_REG_SPI_REVISION
pmallick 0:3afcd581558d 204 */
pmallick 0:3afcd581558d 205 #define AD713X_SPI_REVISION_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 206 #define AD713X_SPI_REVISION_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 207
pmallick 0:3afcd581558d 208 /*
pmallick 0:3afcd581558d 209 * AD713X_REG_VENDOR_ID_LSB
pmallick 0:3afcd581558d 210 */
pmallick 0:3afcd581558d 211 #define AD713X_VENDOR_ID_LSB_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 212 #define AD713X_VENDOR_ID_LSB_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 213
pmallick 0:3afcd581558d 214 /*
pmallick 0:3afcd581558d 215 * AD713X_REG_VENDOR_ID_MSB
pmallick 0:3afcd581558d 216 */
pmallick 0:3afcd581558d 217 #define AD713X_VENDOR_ID_MSB_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 218 #define AD713X_VENDOR_ID_MSB_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 219
pmallick 0:3afcd581558d 220 /*
pmallick 0:3afcd581558d 221 * AD713X_REG_STREAM_MODE
pmallick 0:3afcd581558d 222 */
pmallick 0:3afcd581558d 223 #define AD713X_STREAM_MODE_BITS_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 224 #define AD713X_STREAM_MODE_BITS_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 225
pmallick 0:3afcd581558d 226 /*
pmallick 0:3afcd581558d 227 * AD713X_REG_TRANSFER_REGISTER
pmallick 0:3afcd581558d 228 */
pmallick 0:3afcd581558d 229 #define AD713X_TRANSFER_MASTER_SLAVE_TX_BIT_MSK BIT(0)
pmallick 0:3afcd581558d 230
pmallick 0:3afcd581558d 231 /*
pmallick 0:3afcd581558d 232 * AD713X_REG_DEVICE_CONFIG1
pmallick 0:3afcd581558d 233 */
pmallick 0:3afcd581558d 234 #define AD713X_DEV_CONFIG1_MPC_MAGPHA_EN_MSK BIT(6)
pmallick 0:3afcd581558d 235 #define AD713X_DEV_CONFIG1_MPC_MAG_EN_MSK BIT(5)
pmallick 0:3afcd581558d 236 #define AD713X_DEV_CONFIG1_AA_MODE_MSK BIT(4)
pmallick 0:3afcd581558d 237 #define AD713X_DEV_CONFIG1_SDO_PIN_SRC_SEL_MSK BIT(2)
pmallick 0:3afcd581558d 238 #define AD713X_DEV_CONFIG1_REF_GAIN_CORR_EN_MSK BIT(1)
pmallick 0:3afcd581558d 239 #define AD713X_DEV_CONFIG1_CLKOUT_EN_MSK BIT(0)
pmallick 0:3afcd581558d 240
pmallick 0:3afcd581558d 241 /*
pmallick 0:3afcd581558d 242 * AD713X_REG_DATA_PACKET_CONFIG
pmallick 0:3afcd581558d 243 */
pmallick 0:3afcd581558d 244 #define AD713X_DATA_PACKET_CONFIG_CRC_POLY_RST_MSK BIT(7)
pmallick 0:3afcd581558d 245 #define AD713X_DATA_PACKET_CONFIG_FRAME_MSK GENMASK(6, 4)
pmallick 0:3afcd581558d 246 #define AD713X_DATA_PACKET_CONFIG_FRAME_MODE(x) (((x) & 0x7) << 4)
pmallick 0:3afcd581558d 247 #define AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MSK GENMASK(3, 0)
pmallick 0:3afcd581558d 248 #define AD713X_DATA_PACKET_CONFIG_DCLK_FREQ_MODE(x) (((x) & 0xF) << 0)
pmallick 0:3afcd581558d 249
pmallick 0:3afcd581558d 250 /*
pmallick 0:3afcd581558d 251 * AD713X_REG_DIGITAL_INTERFACE_CONFIG
pmallick 0:3afcd581558d 252 */
pmallick 0:3afcd581558d 253 #define AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MSK GENMASK(7, 4)
pmallick 0:3afcd581558d 254 #define AD713X_DIG_INT_CONFIG_DAISY_CHAIN_NUM_MODE(x) (((x) & 0xF) << 4)
pmallick 0:3afcd581558d 255 #define AD713X_DIG_INT_CONFIG_AVG_SEL_MSK GENMASK(3, 2)
pmallick 0:3afcd581558d 256 #define AD713X_DIG_INT_CONFIG_AVG_SEL_MODE(x) (((x) & 0x3) << 2)
pmallick 0:3afcd581558d 257 #define AD713X_DIG_INT_CONFIG_FORMAT_MSK GENMASK(1, 0)
pmallick 0:3afcd581558d 258 #define AD713X_DIG_INT_CONFIG_FORMAT_MODE(x) (((x) & 0x3) << 0)
pmallick 0:3afcd581558d 259
pmallick 0:3afcd581558d 260 /*
pmallick 0:3afcd581558d 261 * AD713X_REG_POWER_DOWN_CONTROL
pmallick 0:3afcd581558d 262 */
pmallick 0:3afcd581558d 263 #define AD713X_PWRDN_CTRL_PWRDN_CH_MSK(ch) BIT(ch)
pmallick 0:3afcd581558d 264 #define AD713X_PWRDN_CTRL_PWRDN_AUXADC_MSK BIT(2)
pmallick 0:3afcd581558d 265 #define AD713X_PWRDN_CTRL_PWRDN_LDO_MSK BIT(1)
pmallick 0:3afcd581558d 266 #define AD713X_PWRDN_CTRL_PWRDN_SLEEP_MODE_EN_MSK BIT(0)
pmallick 0:3afcd581558d 267
pmallick 0:3afcd581558d 268 /*
pmallick 0:3afcd581558d 269 * AD713X_REG_AIN_RANGE_SELECT
pmallick 0:3afcd581558d 270 */
pmallick 0:3afcd581558d 271 #define AD713X_AIN_RANGE_SEL_CH_MSK(ch) BIT(ch)
pmallick 0:3afcd581558d 272
pmallick 0:3afcd581558d 273 /*
pmallick 0:3afcd581558d 274 * AD713X_REG_DEVICE_STATUS
pmallick 0:3afcd581558d 275 */
pmallick 0:3afcd581558d 276 #define AD713X_DEV_STAT_DCLKMODE_MSK BIT(5)
pmallick 0:3afcd581558d 277 #define AD713X_DEV_STAT_DCLKIO_MSK BIT(4)
pmallick 0:3afcd581558d 278 #define AD713X_DEV_STAT_MODE_MSK BIT(3)
pmallick 0:3afcd581558d 279 #define AD713X_DEV_STAT_CLKSEL_MSK BIT(2)
pmallick 0:3afcd581558d 280 #define AD713X_DEV_STAT_FUSE_ECC_MSK BIT(1)
pmallick 0:3afcd581558d 281 #define AD713X_DEV_STAT_PLL_LOCK_MSK BIT(0)
pmallick 0:3afcd581558d 282
pmallick 0:3afcd581558d 283 /*
pmallick 0:3afcd581558d 284 * AD713X_REG_ODR_VAL_INT_LSB
pmallick 0:3afcd581558d 285 */
pmallick 0:3afcd581558d 286 #define AD713X_ODR_VAL_INT_LSB_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 287 #define AD713X_ODR_VAL_INT_LSB_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 288
pmallick 0:3afcd581558d 289 /*
pmallick 0:3afcd581558d 290 * AD713X_REG_ODR_VAL_INT_MID
pmallick 0:3afcd581558d 291 */
pmallick 0:3afcd581558d 292 #define AD713X_ODR_VAL_INT_MID_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 293 #define AD713X_ODR_VAL_INT_MID_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 294
pmallick 0:3afcd581558d 295 /*
pmallick 0:3afcd581558d 296 * AD713X_REG_ODR_VAL_INT_MSB
pmallick 0:3afcd581558d 297 */
pmallick 0:3afcd581558d 298 #define AD713X_ODR_VAL_INT_MSB_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 299 #define AD713X_ODR_VAL_INT_MSB_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 300
pmallick 0:3afcd581558d 301 /*
pmallick 0:3afcd581558d 302 * AD713X_REG_ODR_VAL_FLT_LSB
pmallick 0:3afcd581558d 303 */
pmallick 0:3afcd581558d 304 #define AD713X_ODR_VAL_FLT_LSB_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 305 #define AD713X_ODR_VAL_FLT_LSB_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 306
pmallick 0:3afcd581558d 307 /*
pmallick 0:3afcd581558d 308 * AD713X_REG_ODR_VAL_FLT_MID0
pmallick 0:3afcd581558d 309 */
pmallick 0:3afcd581558d 310 #define AD713X_ODR_VAL_FLT_MID0_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 311 #define AD713X_ODR_VAL_FLT_MID0_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 312
pmallick 0:3afcd581558d 313 /*
pmallick 0:3afcd581558d 314 * AD713X_REG_ODR_VAL_FLT_MID1
pmallick 0:3afcd581558d 315 */
pmallick 0:3afcd581558d 316 #define AD713X_ODR_VAL_FLT_MID1_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 317 #define AD713X_ODR_VAL_FLT_MID1_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 318
pmallick 0:3afcd581558d 319 /*
pmallick 0:3afcd581558d 320 * AD713X_REG_ODR_VAL_FLT_MSB
pmallick 0:3afcd581558d 321 */
pmallick 0:3afcd581558d 322 #define AD713X_ODR_VAL_FLT_MSB_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 323 #define AD713X_ODR_VAL_FLT_MSB_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 324
pmallick 0:3afcd581558d 325 /*
pmallick 0:3afcd581558d 326 * AD713X_REG_CHANNEL_ODR_SELECT
pmallick 0:3afcd581558d 327 */
pmallick 0:3afcd581558d 328 #define AD713X_ODR_RATE_SEL_CH_MSK(ch) (GENMASK(1, 0) << (2 * ch))
pmallick 0:3afcd581558d 329 #define AD713X_ODR_RATE_SEL_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))
pmallick 0:3afcd581558d 330
pmallick 0:3afcd581558d 331 /*
pmallick 0:3afcd581558d 332 * AD713X_REG_CHAN_DIG_FILTER_SEL
pmallick 0:3afcd581558d 333 */
pmallick 0:3afcd581558d 334 #define AD713X_DIGFILTER_SEL_CH_MSK(ch) (GENMASK(1, 0) << (2 * ch))
pmallick 0:3afcd581558d 335 #define AD713X_DIGFILTER_SEL_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))
pmallick 0:3afcd581558d 336
pmallick 0:3afcd581558d 337 /*
pmallick 0:3afcd581558d 338 * AD713X_REG_FIR_BW_SEL
pmallick 0:3afcd581558d 339 */
pmallick 0:3afcd581558d 340 #define AD713X_FIR_BW_SEL_CH_MSK(ch) BIT(ch)
pmallick 0:3afcd581558d 341
pmallick 0:3afcd581558d 342 /*
pmallick 0:3afcd581558d 343 * AD713X_REG_GPIO_DIR_CTRL
pmallick 0:3afcd581558d 344 */
pmallick 0:3afcd581558d 345 #define AD713X_GPIO_IO_CTRL_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 346 #define AD713X_GPIO_IO_CTRL_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 347
pmallick 0:3afcd581558d 348 /*
pmallick 0:3afcd581558d 349 * AD713X_REG_GPIO_DATA
pmallick 0:3afcd581558d 350 */
pmallick 0:3afcd581558d 351 #define AD713X_GPIO_DATA_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 352 #define AD713X_GPIO_DATA_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 353
pmallick 0:3afcd581558d 354 /*
pmallick 0:3afcd581558d 355 * AD713X_REG_ERROR_PIN_SRC_CONTROL
pmallick 0:3afcd581558d 356 */
pmallick 0:3afcd581558d 357 #define AD713X_ERR_PIN_EN_OR_AIN_MSK BIT(5)
pmallick 0:3afcd581558d 358 #define AD713X_ERR_PIN_EN_INTERNAL_MSK BIT(4)
pmallick 0:3afcd581558d 359 #define AD713X_ERR_PIN_EN_SPI_MSK BIT(3)
pmallick 0:3afcd581558d 360 #define AD713X_ERR_PIN_EN_LDO_XOSC_MSK BIT(2)
pmallick 0:3afcd581558d 361 #define AD713X_ERR_PIN_EN_TEMP_MSK BIT(1)
pmallick 0:3afcd581558d 362 #define AD713X_ERR_PIN_EN_PWR_MSK BIT(0)
pmallick 0:3afcd581558d 363
pmallick 0:3afcd581558d 364 /*
pmallick 0:3afcd581558d 365 * AD713X_REG_ERROR_PIN_CONTROL
pmallick 0:3afcd581558d 366 */
pmallick 0:3afcd581558d 367 #define AD713X_ERR_PIN_IN_STATUS_MSK BIT(2)
pmallick 0:3afcd581558d 368 #define AD713X_ERR_PIN_IN_EN_MSK BIT(1)
pmallick 0:3afcd581558d 369 #define AD713X_ERR_PIN_OUT_EN_MSK BIT(0)
pmallick 0:3afcd581558d 370
pmallick 0:3afcd581558d 371 /*
pmallick 0:3afcd581558d 372 * AD713X_REG_VCMBUF_CTRL
pmallick 0:3afcd581558d 373 */
pmallick 0:3afcd581558d 374 #define AD713X_VCMBUF_CTRL_PWRDN_MSK BIT(6)
pmallick 0:3afcd581558d 375 #define AD713X_VCMBUF_CTRL_REF_DIV_SEL_MSK GENMASK(5, 1)
pmallick 0:3afcd581558d 376 #define AD713X_VCMBUF_CTRL_REF_DIV_SEL_MODE(x) (((x) & 0x1F) << 1)
pmallick 0:3afcd581558d 377 #define AD713X_VCMBUF_CTRL_REF_SEL_MSK BIT(0)
pmallick 0:3afcd581558d 378
pmallick 0:3afcd581558d 379 /*
pmallick 0:3afcd581558d 380 * AD713X_REG_DIAGNOSTIC_CONTROL
pmallick 0:3afcd581558d 381 */
pmallick 0:3afcd581558d 382 #define AD713X_DIAGCTRL_ERR_OR_AIN_EN_MSK BIT(5)
pmallick 0:3afcd581558d 383 #define AD713X_DIAGCTRL_ERR_PWR_MON_EN_MSK BIT(4)
pmallick 0:3afcd581558d 384 #define AD713X_DIAGCTRL_MCLK_CNT_EN_MSK BIT(3)
pmallick 0:3afcd581558d 385 #define AD713X_DIAGCTRL_ERR_SPI_CRC_EN_MSK BIT(2)
pmallick 0:3afcd581558d 386 #define AD713X_DIAGCTRL_ERR_MM_CRC_EN_MSK BIT(1)
pmallick 0:3afcd581558d 387 #define AD713X_DIAGCTRL_FUSE_CRC_CHECK_MSK BIT(0)
pmallick 0:3afcd581558d 388
pmallick 0:3afcd581558d 389 /*
pmallick 0:3afcd581558d 390 * AD713X_REG_MPC_CONFIG
pmallick 0:3afcd581558d 391 */
pmallick 0:3afcd581558d 392 #define AD713X_MPC_CLKDEL_EN_CH_MSK(ch) (GENMASK(1, 0) << (2 * ch))
pmallick 0:3afcd581558d 393 #define AD713X_MPC_CLKDEL_EN_CH_MODE(x, ch) (((x) & 0x3) << (2 * ch))
pmallick 0:3afcd581558d 394
pmallick 0:3afcd581558d 395 /*
pmallick 0:3afcd581558d 396 * AD713X_REG_CHx_GAIN_LSB
pmallick 0:3afcd581558d 397 */
pmallick 0:3afcd581558d 398 #define AD713X_CH_GAIN_LSB_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 399 #define AD713X_CH_GAIN_LSB_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 400
pmallick 0:3afcd581558d 401 /*
pmallick 0:3afcd581558d 402 * AD713X_REG_CHx_GAIN_MID
pmallick 0:3afcd581558d 403 */
pmallick 0:3afcd581558d 404 #define AD713X_CH_GAIN_MID_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 405 #define AD713X_CH_GAIN_MID_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 406
pmallick 0:3afcd581558d 407 /*
pmallick 0:3afcd581558d 408 * AD713X_REG_CHx_GAIN_MSB
pmallick 0:3afcd581558d 409 */
pmallick 0:3afcd581558d 410 #define AD713X_CH_GAIN_CAL_SEL_MSK BIT(4)
pmallick 0:3afcd581558d 411 #define AD713X_CH_GAIN_MSB_MSK GENMASK(3, 0)
pmallick 0:3afcd581558d 412 #define AD713X_CH_GAIN_MSB_MODE(x) (((x) & 0xF) << 0)
pmallick 0:3afcd581558d 413
pmallick 0:3afcd581558d 414 /*
pmallick 0:3afcd581558d 415 * AD713X_REG_CHx_OFFSET_LSB
pmallick 0:3afcd581558d 416 */
pmallick 0:3afcd581558d 417 #define AD713X_CH_OFFSET_LSB_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 418 #define AD713X_CH_OFFSET_LSB_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 419
pmallick 0:3afcd581558d 420 /*
pmallick 0:3afcd581558d 421 * AD713X_REG_CHx_OFFSET_MID
pmallick 0:3afcd581558d 422 */
pmallick 0:3afcd581558d 423 #define AD713X_CH_OFFSET_MID_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 424 #define AD713X_CH_OFFSET_MID_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 425
pmallick 0:3afcd581558d 426 /*
pmallick 0:3afcd581558d 427 * AD713X_REG_CHx_OFFSET_MSB
pmallick 0:3afcd581558d 428 */
pmallick 0:3afcd581558d 429 #define AD713X_CH_OFFSET_CAL_EN_MSK BIT(7)
pmallick 0:3afcd581558d 430 #define AD713X_CH_OFFSET_MSB_MSK GENMASK(6, 0)
pmallick 0:3afcd581558d 431 #define AD713X_CH_OFFSET_MSB_MODE(x) (((x) & 0x7F) << 0)
pmallick 0:3afcd581558d 432
pmallick 0:3afcd581558d 433 /*
pmallick 0:3afcd581558d 434 * AD713X_REG_MCLK_COUNTER
pmallick 0:3afcd581558d 435 */
pmallick 0:3afcd581558d 436 #define AD713X_MCLK_COUNT_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 437 #define AD713X_MCLK_COUNT_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 438
pmallick 0:3afcd581558d 439 /*
pmallick 0:3afcd581558d 440 * AD713X_REG_DIG_FILTER_OFUF
pmallick 0:3afcd581558d 441 */
pmallick 0:3afcd581558d 442 #define AD713X_DIGFILTER_ERR_OFUF_CH_MSK(ch) BIT(ch)
pmallick 0:3afcd581558d 443
pmallick 0:3afcd581558d 444 /*
pmallick 0:3afcd581558d 445 * AD713X_REG_DIG_FILTER_SETTLED
pmallick 0:3afcd581558d 446 */
pmallick 0:3afcd581558d 447 #define AD713X_DIGFILTER_CH_SETTLED_MSK(ch) BIT(ch)
pmallick 0:3afcd581558d 448
pmallick 0:3afcd581558d 449 /*
pmallick 0:3afcd581558d 450 * AD713X_REG_INTERNAL_ERROR
pmallick 0:3afcd581558d 451 */
pmallick 0:3afcd581558d 452 #define AD713X_INT_ERR_NO_CLOCK_MSK BIT(5)
pmallick 0:3afcd581558d 453 #define AD713X_INT_ERR_TEMP_MSK BIT(4)
pmallick 0:3afcd581558d 454 #define AD713X_INT_ERR_DCLK_MSK BIT(3)
pmallick 0:3afcd581558d 455 #define AD713X_INT_ERR_FUSE_CRC_MSK BIT(2)
pmallick 0:3afcd581558d 456 #define AD713X_INT_ERR_ASRC_MSK BIT(1)
pmallick 0:3afcd581558d 457 #define AD713X_INT_ERR_MM_CRC_MSK BIT(0)
pmallick 0:3afcd581558d 458
pmallick 0:3afcd581558d 459 /*
pmallick 0:3afcd581558d 460 * AD713X_REG_POWER_OV_ERROR_1
pmallick 0:3afcd581558d 461 */
pmallick 0:3afcd581558d 462 #define AD713X_POWER_ERR_OV_IOVDD_MSK BIT(3)
pmallick 0:3afcd581558d 463 #define AD713X_POWER_ERR_OV_CLKVDD_MSK BIT(2)
pmallick 0:3afcd581558d 464 #define AD713X_POWER_ERR_OV_DVDD1V8_MSK BIT(1)
pmallick 0:3afcd581558d 465 #define AD713X_POWER_ERR_OV_AVDD1V8_MSK BIT(0)
pmallick 0:3afcd581558d 466
pmallick 0:3afcd581558d 467 /*
pmallick 0:3afcd581558d 468 * AD713X_REG_POWER_UV_ERROR_1
pmallick 0:3afcd581558d 469 */
pmallick 0:3afcd581558d 470 #define AD713X_POWER_ERR_UV_IOVDD_MSK BIT(3)
pmallick 0:3afcd581558d 471 #define AD713X_POWER_ERR_UV_CLKVDD_MSK BIT(2)
pmallick 0:3afcd581558d 472 #define AD713X_POWER_ERR_UV_DVDD1V8_MSK BIT(1)
pmallick 0:3afcd581558d 473 #define AD713X_POWER_ERR_UV_AVDD1V8_MSK BIT(0)
pmallick 0:3afcd581558d 474
pmallick 0:3afcd581558d 475 /*
pmallick 0:3afcd581558d 476 * AD713X_REG_POWER_OV_ERROR_2
pmallick 0:3afcd581558d 477 */
pmallick 0:3afcd581558d 478 #define AD713X_POWER_ERR_OV_VREF_MSK BIT(3)
pmallick 0:3afcd581558d 479 #define AD713X_POWER_ERR_OV_LDOIN_MSK BIT(2)
pmallick 0:3afcd581558d 480 #define AD713X_POWER_ERR_OV_DVDD5_MSK BIT(1)
pmallick 0:3afcd581558d 481 #define AD713X_POWER_ERR_OV_AVDD5_MSK BIT(0)
pmallick 0:3afcd581558d 482
pmallick 0:3afcd581558d 483 /*
pmallick 0:3afcd581558d 484 * AD713X_REG_POWER_UV_ERROR_2
pmallick 0:3afcd581558d 485 */
pmallick 0:3afcd581558d 486 #define AD713X_POWER_ERR_UV_VREF_MSK BIT(3)
pmallick 0:3afcd581558d 487 #define AD713X_POWER_ERR_UV_LDOIN_MSK BIT(2)
pmallick 0:3afcd581558d 488 #define AD713X_POWER_ERR_UV_DVDD5_MSK BIT(1)
pmallick 0:3afcd581558d 489 #define AD713X_POWER_ERR_UV_AVDD5_MSK BIT(0)
pmallick 0:3afcd581558d 490
pmallick 0:3afcd581558d 491 /*
pmallick 0:3afcd581558d 492 * AD713X_REG_SPI_ERROR
pmallick 0:3afcd581558d 493 */
pmallick 0:3afcd581558d 494 #define AD713X_SPI_ERROR_CRC_MSK BIT(3)
pmallick 0:3afcd581558d 495 #define AD713X_SPI_ERROR_SCLK_CNT_MSK BIT(2)
pmallick 0:3afcd581558d 496 #define AD713X_SPI_ERROR_WRITE_MSK BIT(1)
pmallick 0:3afcd581558d 497 #define AD713X_SPI_ERROR_READ_MSK BIT(0)
pmallick 0:3afcd581558d 498
pmallick 0:3afcd581558d 499 /*
pmallick 0:3afcd581558d 500 * AD713X_REG_AIN_OR_ERROR
pmallick 0:3afcd581558d 501 */
pmallick 0:3afcd581558d 502 #define AD713X_ERR_OR_AIN_MSK(ch) BIT(ch)
pmallick 0:3afcd581558d 503
pmallick 0:3afcd581558d 504 /*
pmallick 0:3afcd581558d 505 * AD713X_REG_AVDD5_VALUE
pmallick 0:3afcd581558d 506 */
pmallick 0:3afcd581558d 507 #define AD713X_AVDD5_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 508 #define AD713X_AVDD5_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 509
pmallick 0:3afcd581558d 510 /*
pmallick 0:3afcd581558d 511 * AD713X_REG_DVDD5_VALUE
pmallick 0:3afcd581558d 512 */
pmallick 0:3afcd581558d 513 #define AD713X_DVDD5_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 514 #define AD713X_DVDD5_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 515
pmallick 0:3afcd581558d 516 /*
pmallick 0:3afcd581558d 517 * AD713X_REG_VREF_VALUE
pmallick 0:3afcd581558d 518 */
pmallick 0:3afcd581558d 519 #define AD713X_VREF_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 520 #define AD713X_VREF_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 521
pmallick 0:3afcd581558d 522 /*
pmallick 0:3afcd581558d 523 * AD713X_REG_LDOIN_VALUE
pmallick 0:3afcd581558d 524 */
pmallick 0:3afcd581558d 525 #define AD713X_LDOIN_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 526 #define AD713X_LDOIN_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 527
pmallick 0:3afcd581558d 528 /*
pmallick 0:3afcd581558d 529 * AD713X_REG_AVDD1V8_VALUE
pmallick 0:3afcd581558d 530 */
pmallick 0:3afcd581558d 531 #define AD713X_AVDD1V8_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 532 #define AD713X_AVDD1V8_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 533
pmallick 0:3afcd581558d 534 /*
pmallick 0:3afcd581558d 535 * AD713X_REG_DVDD1V8_VALUE
pmallick 0:3afcd581558d 536 */
pmallick 0:3afcd581558d 537 #define AD713X_DVDD1V8_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 538 #define AD713X_DVDD1V8_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 539
pmallick 0:3afcd581558d 540 /*
pmallick 0:3afcd581558d 541 * AD713X_REG_CLKVDD_VALUE
pmallick 0:3afcd581558d 542 */
pmallick 0:3afcd581558d 543 #define AD713X_CLKVDD_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 544 #define AD713X_CLKVDD_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 545
pmallick 0:3afcd581558d 546 /*
pmallick 0:3afcd581558d 547 * AD713X_REG_IOVDD_VALUE
pmallick 0:3afcd581558d 548 */
pmallick 0:3afcd581558d 549 #define AD713X_IOVDD_VALUE_PIN_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 550 #define AD713X_IOVDD_VALUE_PIN_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 551
pmallick 0:3afcd581558d 552 /*
pmallick 0:3afcd581558d 553 * AD713X_REG_TEMPERATURE_DATA
pmallick 0:3afcd581558d 554 */
pmallick 0:3afcd581558d 555 #define AD713X_TEMP_DATA_MSK GENMASK(7, 0)
pmallick 0:3afcd581558d 556 #define AD713X_TEMP_DATA_MODE(x) (((x) & 0xFF) << 0)
pmallick 0:3afcd581558d 557
pmallick 0:3afcd581558d 558 #define AD713X_REG_READ(x) ((1 << 7) | (x & 0x7F))
pmallick 0:3afcd581558d 559
pmallick 0:3afcd581558d 560 /******************************************************************************/
pmallick 0:3afcd581558d 561 /*************************** Types Declarations *******************************/
pmallick 0:3afcd581558d 562 /******************************************************************************/
pmallick 0:3afcd581558d 563
pmallick 0:3afcd581558d 564 /**
pmallick 0:3afcd581558d 565 * @enum ad713x_supported_dev_ids
pmallick 0:3afcd581558d 566 * @brief ID of devices supported by the driver
pmallick 0:3afcd581558d 567 */
pmallick 0:3afcd581558d 568 enum ad713x_supported_dev_ids {
pmallick 0:3afcd581558d 569 ID_AD7132,
pmallick 0:3afcd581558d 570 ID_AD7134,
pmallick 0:3afcd581558d 571 ID_AD7136
pmallick 0:3afcd581558d 572 };
pmallick 0:3afcd581558d 573
pmallick 0:3afcd581558d 574 /**
pmallick 0:3afcd581558d 575 * @enum ad713x_power_mode
pmallick 0:3afcd581558d 576 * @brief AD713x power modes
pmallick 0:3afcd581558d 577 */
pmallick 0:3afcd581558d 578 enum ad713x_power_mode {
pmallick 0:3afcd581558d 579 /** Low power mode option */
pmallick 0:3afcd581558d 580 LOW_POWER,
pmallick 0:3afcd581558d 581 /** Full power mode option */
pmallick 0:3afcd581558d 582 HIGH_POWER
pmallick 0:3afcd581558d 583 };
pmallick 0:3afcd581558d 584
pmallick 0:3afcd581558d 585 /**
pmallick 0:3afcd581558d 586 * @enum ad713x_adc_data_len
pmallick 0:3afcd581558d 587 * @brief AD713x possible number of bits per data sample
pmallick 0:3afcd581558d 588 */
pmallick 0:3afcd581558d 589 enum ad713x_adc_data_len {
pmallick 0:3afcd581558d 590 /** 16 bit data sample */
pmallick 0:3afcd581558d 591 ADC_16_BIT_DATA,
pmallick 0:3afcd581558d 592 /** 24 bit data sample */
pmallick 0:3afcd581558d 593 ADC_24_BIT_DATA,
pmallick 0:3afcd581558d 594 /** 32 bit data sample */
pmallick 0:3afcd581558d 595 ADC_32_BIT_DATA,
pmallick 0:3afcd581558d 596 /** To know when to stop when cycling between them */
pmallick 0:3afcd581558d 597 INVALID
pmallick 0:3afcd581558d 598 };
pmallick 0:3afcd581558d 599
pmallick 0:3afcd581558d 600 /**
pmallick 0:3afcd581558d 601 * @enum ad713x_crc_header
pmallick 0:3afcd581558d 602 * @brief AD713x possible data CRC header choices
pmallick 0:3afcd581558d 603 */
pmallick 0:3afcd581558d 604 enum ad713x_crc_header {
pmallick 0:3afcd581558d 605 /** Data sample comes with no CRC attached */
pmallick 0:3afcd581558d 606 NO_CRC,
pmallick 0:3afcd581558d 607 /** Data sample comes with 6-bit CRC attached */
pmallick 0:3afcd581558d 608 CRC_6,
pmallick 0:3afcd581558d 609 /** Data sample comes with 8-bit CRC attached */
pmallick 0:3afcd581558d 610 CRC_8
pmallick 0:3afcd581558d 611 };
pmallick 0:3afcd581558d 612
pmallick 0:3afcd581558d 613 /**
pmallick 0:3afcd581558d 614 * @enum ad713x_doutx_format
pmallick 0:3afcd581558d 615 * @brief AD713x list for possible output modes
pmallick 0:3afcd581558d 616 */
pmallick 0:3afcd581558d 617 enum ad713x_doutx_format {
pmallick 0:3afcd581558d 618 /** Single channel Daisy-chain mode */
pmallick 0:3afcd581558d 619 SINGLE_CH_DC,
pmallick 0:3afcd581558d 620 /** Dual channel Daisy-chain mode */
pmallick 0:3afcd581558d 621 DUAL_CH_DC,
pmallick 0:3afcd581558d 622 /** Quad-channel parallel output mode */
pmallick 0:3afcd581558d 623 QUAD_CH_PO,
pmallick 0:3afcd581558d 624 /** Channel average mode */
pmallick 0:3afcd581558d 625 CH_AVG_MODE
pmallick 0:3afcd581558d 626 };
pmallick 0:3afcd581558d 627
pmallick 0:3afcd581558d 628 /**
pmallick 0:3afcd581558d 629 * @enum ad713x_dig_filter_sel
pmallick 0:3afcd581558d 630 * @brief AD713x list of input filters.
pmallick 0:3afcd581558d 631 */
pmallick 0:3afcd581558d 632 enum ad713x_dig_filter_sel {
pmallick 0:3afcd581558d 633 /** Wideband filter (Finite impulse response) */
pmallick 0:3afcd581558d 634 FIR,
pmallick 0:3afcd581558d 635 /** Sinc6 filter */
pmallick 0:3afcd581558d 636 SINC6,
pmallick 0:3afcd581558d 637 /** Sinc3 filter */
pmallick 0:3afcd581558d 638 SINC3,
pmallick 0:3afcd581558d 639 /** Sinc3 filter with 50Hz and 60Hz rejection */
pmallick 0:3afcd581558d 640 SINC3_50_60_REJ
pmallick 0:3afcd581558d 641 };
pmallick 0:3afcd581558d 642
pmallick 0:3afcd581558d 643 /**
pmallick 0:3afcd581558d 644 * @enum ad713x_channels
pmallick 0:3afcd581558d 645 * @brief AD713x list of channels
pmallick 0:3afcd581558d 646 */
pmallick 0:3afcd581558d 647 enum ad713x_channels {
pmallick 0:3afcd581558d 648 /** Channel 0 */
pmallick 0:3afcd581558d 649 CH0,
pmallick 0:3afcd581558d 650 /** Channel 1 */
pmallick 0:3afcd581558d 651 CH1,
pmallick 0:3afcd581558d 652 /** Channel 2 */
pmallick 0:3afcd581558d 653 CH2,
pmallick 0:3afcd581558d 654 /** Channel 3 */
pmallick 0:3afcd581558d 655 CH3
pmallick 0:3afcd581558d 656 };
pmallick 0:3afcd581558d 657
pmallick 0:3afcd581558d 658 /**
pmallick 0:3afcd581558d 659 * @enum ad717x_mpc_clkdel
pmallick 0:3afcd581558d 660 * @brief AD713x list of clock delays
pmallick 0:3afcd581558d 661 */
pmallick 0:3afcd581558d 662 enum ad717x_mpc_clkdel {
pmallick 0:3afcd581558d 663 /** No delay */
pmallick 0:3afcd581558d 664 DELAY_NONE,
pmallick 0:3afcd581558d 665 /** One clock cycle delay */
pmallick 0:3afcd581558d 666 DELAY_1_CLOCKS,
pmallick 0:3afcd581558d 667 /** Two clock cycles delay */
pmallick 0:3afcd581558d 668 DELAY_2_CLOCKS
pmallick 0:3afcd581558d 669 };
pmallick 0:3afcd581558d 670
pmallick 0:3afcd581558d 671 /**
pmallick 0:3afcd581558d 672 * @struct ad713x_dev
pmallick 0:3afcd581558d 673 * @brief AD713x driver handler structure
pmallick 0:3afcd581558d 674 */
pmallick 0:3afcd581558d 675 struct ad713x_dev {
pmallick 0:3afcd581558d 676 /** SPI layer handler. */
pmallick 0:3afcd581558d 677 struct spi_desc *spi_desc;
pmallick 0:3afcd581558d 678 /** MODE GPIO handler. */
pmallick 0:3afcd581558d 679 struct gpio_desc *gpio_mode;
pmallick 0:3afcd581558d 680 /** DCLKMODE GPIO handler. */
pmallick 0:3afcd581558d 681 struct gpio_desc *gpio_dclkmode;
pmallick 0:3afcd581558d 682 /** DCLKIO GPIO handler. */
pmallick 0:3afcd581558d 683 struct gpio_desc *gpio_dclkio;
pmallick 0:3afcd581558d 684 /** RESET GPIO handler. */
pmallick 0:3afcd581558d 685 struct gpio_desc *gpio_resetn;
pmallick 0:3afcd581558d 686 /** PDN GPIO handler. */
pmallick 0:3afcd581558d 687 struct gpio_desc *gpio_pnd;
pmallick 0:3afcd581558d 688 /** ID of supported device. */
pmallick 0:3afcd581558d 689 enum ad713x_supported_dev_ids dev_id;
pmallick 0:3afcd581558d 690 /** Length of data in bits. */
pmallick 0:3afcd581558d 691 enum ad713x_adc_data_len adc_data_len;
pmallick 0:3afcd581558d 692 /** CRC option. */
pmallick 0:3afcd581558d 693 enum ad713x_crc_header crc_header;
pmallick 0:3afcd581558d 694 };
pmallick 0:3afcd581558d 695
pmallick 0:3afcd581558d 696 /**
pmallick 0:3afcd581558d 697 * @struct ad713x_init_param
pmallick 0:3afcd581558d 698 * @brief AD713x driver initialization structure
pmallick 0:3afcd581558d 699 */
pmallick 0:3afcd581558d 700 struct ad713x_init_param {
pmallick 0:3afcd581558d 701 /** SPI layer initialization structure. */
pmallick 0:3afcd581558d 702 struct spi_init_param spi_init_prm;
pmallick 0:3afcd581558d 703 /** MODE GPIO initialization structure. */
pmallick 0:3afcd581558d 704 struct gpio_init_param *gpio_mode;
pmallick 0:3afcd581558d 705 /** DCLKMODE GPIO initialization structure. */
pmallick 0:3afcd581558d 706 struct gpio_init_param *gpio_dclkmode;
pmallick 0:3afcd581558d 707 /** DCLKIO GPIO initialization structure. */
pmallick 0:3afcd581558d 708 struct gpio_init_param *gpio_dclkio;
pmallick 0:3afcd581558d 709 /** RESET GPIO initialization structure. */
pmallick 0:3afcd581558d 710 struct gpio_init_param *gpio_resetn;
pmallick 0:3afcd581558d 711 /** PDN GPIO initialization structure. */
pmallick 0:3afcd581558d 712 struct gpio_init_param *gpio_pnd;
pmallick 0:3afcd581558d 713 /** MODE GPIO starting value */
pmallick 0:3afcd581558d 714 bool mode_master_nslave;
pmallick 0:3afcd581558d 715 /** DCLKMODE GPIO starting value */
pmallick 0:3afcd581558d 716 bool dclkmode_free_ngated;
pmallick 0:3afcd581558d 717 /** DCLKIO GPIO starting value */
pmallick 0:3afcd581558d 718 bool dclkio_out_nin;
pmallick 0:3afcd581558d 719 /** PDN GPIO starting value */
pmallick 0:3afcd581558d 720 bool pnd;
pmallick 0:3afcd581558d 721 /** ID of supported device. */
pmallick 0:3afcd581558d 722 enum ad713x_supported_dev_ids dev_id;
pmallick 0:3afcd581558d 723 /** Length of data in bits. */
pmallick 0:3afcd581558d 724 enum ad713x_adc_data_len adc_data_len;
pmallick 0:3afcd581558d 725 /** CRC option. */
pmallick 0:3afcd581558d 726 enum ad713x_crc_header crc_header;
pmallick 0:3afcd581558d 727 enum ad713x_doutx_format format;
pmallick 0:3afcd581558d 728 /** Clock delay state. */
pmallick 0:3afcd581558d 729 bool clk_delay_en;
pmallick 0:3afcd581558d 730 /** SPI layer handler if the SPI bus is shared with another device. In this
pmallick 0:3afcd581558d 731 * case the SPI should not be initialized again. */
pmallick 0:3afcd581558d 732 struct spi_desc *spi_common_dev;
pmallick 0:3afcd581558d 733 };
pmallick 0:3afcd581558d 734
pmallick 0:3afcd581558d 735 /******************************************************************************/
pmallick 0:3afcd581558d 736 /************************ Functions Declarations ******************************/
pmallick 0:3afcd581558d 737 /******************************************************************************/
pmallick 0:3afcd581558d 738
pmallick 0:3afcd581558d 739 /** Read from device. */
pmallick 0:3afcd581558d 740 int32_t ad713x_spi_reg_read(struct ad713x_dev *dev, uint8_t reg_addr,
pmallick 0:3afcd581558d 741 uint8_t *reg_data);
pmallick 0:3afcd581558d 742
pmallick 0:3afcd581558d 743 /** Write to device. */
pmallick 0:3afcd581558d 744 int32_t ad713x_spi_reg_write(struct ad713x_dev *dev, uint8_t reg_addr,
pmallick 0:3afcd581558d 745 uint8_t reg_data);
pmallick 0:3afcd581558d 746
pmallick 0:3afcd581558d 747 /** SPI write to device using a mask. */
pmallick 0:3afcd581558d 748 int32_t ad713x_spi_write_mask(struct ad713x_dev *dev, uint8_t reg_addr,
pmallick 0:3afcd581558d 749 uint32_t mask, uint8_t data);
pmallick 0:3afcd581558d 750
pmallick 0:3afcd581558d 751 /** Device power mode control. */
pmallick 0:3afcd581558d 752 int32_t ad713x_set_power_mode(struct ad713x_dev *dev,
pmallick 0:3afcd581558d 753 enum ad713x_power_mode mode);
pmallick 0:3afcd581558d 754
pmallick 0:3afcd581558d 755 /** ADC conversion data output frame control. */
pmallick 0:3afcd581558d 756 int32_t ad713x_set_out_data_frame(struct ad713x_dev *dev,
pmallick 0:3afcd581558d 757 enum ad713x_adc_data_len adc_data_len,
pmallick 0:3afcd581558d 758 enum ad713x_crc_header crc_header);
pmallick 0:3afcd581558d 759
pmallick 0:3afcd581558d 760 /** DOUTx output format configuration. */
pmallick 0:3afcd581558d 761 int32_t ad713x_dout_format_config(struct ad713x_dev *dev,
pmallick 0:3afcd581558d 762 enum ad713x_doutx_format format);
pmallick 0:3afcd581558d 763
pmallick 0:3afcd581558d 764 /** Magnitude and phase matching calibration clock delay enable for all channels
pmallick 0:3afcd581558d 765 * at 2 clock delay. */
pmallick 0:3afcd581558d 766 int32_t ad713x_mag_phase_clk_delay(struct ad713x_dev *dev, bool clk_delay_en);
pmallick 0:3afcd581558d 767
pmallick 0:3afcd581558d 768 /** Digital filter type selection for each channel. */
pmallick 0:3afcd581558d 769 int32_t ad713x_dig_filter_sel_ch(struct ad713x_dev *dev,
pmallick 0:3afcd581558d 770 enum ad713x_dig_filter_sel filter, enum ad713x_channels ch);
pmallick 0:3afcd581558d 771
pmallick 0:3afcd581558d 772 /** Enable/Disable CLKOUT output. */
pmallick 0:3afcd581558d 773 int32_t ad713x_clkout_output_en(struct ad713x_dev *dev, bool enable);
pmallick 0:3afcd581558d 774
pmallick 0:3afcd581558d 775 /** Enable/Disable reference gain correction. */
pmallick 0:3afcd581558d 776 int32_t ad713x_ref_gain_correction_en(struct ad713x_dev *dev, bool enable);
pmallick 0:3afcd581558d 777
pmallick 0:3afcd581558d 778 /** Select the wideband filter bandwidth for a channel. */
pmallick 0:3afcd581558d 779 int32_t ad713x_wideband_bw_sel(struct ad713x_dev *dev,
pmallick 0:3afcd581558d 780 enum ad713x_channels ch, uint8_t wb_opt);
pmallick 0:3afcd581558d 781
pmallick 0:3afcd581558d 782 /** Initialize the device. */
pmallick 0:3afcd581558d 783 int32_t ad713x_init(struct ad713x_dev **device,
pmallick 0:3afcd581558d 784 struct ad713x_init_param *init_param);
pmallick 0:3afcd581558d 785
pmallick 0:3afcd581558d 786 /** Free the resources allocated by ad713x_init(). */
pmallick 0:3afcd581558d 787 int32_t ad713x_remove(struct ad713x_dev *dev);
pmallick 0:3afcd581558d 788
pmallick 0:3afcd581558d 789 #endif /* SRC_AD713X_H_ */