PHung Tung / SRC_STM32F7

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targets/cmsis/core_cmInstr.h@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

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phungductung 0:e87aa4c49e95 1 /**************************************************************************//**
phungductung 0:e87aa4c49e95 2 * @file core_cmInstr.h
phungductung 0:e87aa4c49e95 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
phungductung 0:e87aa4c49e95 4 * @version V4.10
phungductung 0:e87aa4c49e95 5 * @date 18. March 2015
phungductung 0:e87aa4c49e95 6 *
phungductung 0:e87aa4c49e95 7 * @note
phungductung 0:e87aa4c49e95 8 *
phungductung 0:e87aa4c49e95 9 ******************************************************************************/
phungductung 0:e87aa4c49e95 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
phungductung 0:e87aa4c49e95 11
phungductung 0:e87aa4c49e95 12 All rights reserved.
phungductung 0:e87aa4c49e95 13 Redistribution and use in source and binary forms, with or without
phungductung 0:e87aa4c49e95 14 modification, are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 15 - Redistributions of source code must retain the above copyright
phungductung 0:e87aa4c49e95 16 notice, this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 17 - Redistributions in binary form must reproduce the above copyright
phungductung 0:e87aa4c49e95 18 notice, this list of conditions and the following disclaimer in the
phungductung 0:e87aa4c49e95 19 documentation and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 20 - Neither the name of ARM nor the names of its contributors may be used
phungductung 0:e87aa4c49e95 21 to endorse or promote products derived from this software without
phungductung 0:e87aa4c49e95 22 specific prior written permission.
phungductung 0:e87aa4c49e95 23 *
phungductung 0:e87aa4c49e95 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
phungductung 0:e87aa4c49e95 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
phungductung 0:e87aa4c49e95 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
phungductung 0:e87aa4c49e95 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
phungductung 0:e87aa4c49e95 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
phungductung 0:e87aa4c49e95 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
phungductung 0:e87aa4c49e95 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
phungductung 0:e87aa4c49e95 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
phungductung 0:e87aa4c49e95 34 POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 35 ---------------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 36
phungductung 0:e87aa4c49e95 37
phungductung 0:e87aa4c49e95 38 #ifndef __CORE_CMINSTR_H
phungductung 0:e87aa4c49e95 39 #define __CORE_CMINSTR_H
phungductung 0:e87aa4c49e95 40
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 /* ########################## Core Instruction Access ######################### */
phungductung 0:e87aa4c49e95 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
phungductung 0:e87aa4c49e95 44 Access to dedicated instructions
phungductung 0:e87aa4c49e95 45 @{
phungductung 0:e87aa4c49e95 46 */
phungductung 0:e87aa4c49e95 47
phungductung 0:e87aa4c49e95 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
phungductung 0:e87aa4c49e95 49 /* ARM armcc specific functions */
phungductung 0:e87aa4c49e95 50
phungductung 0:e87aa4c49e95 51 #if (__ARMCC_VERSION < 400677)
phungductung 0:e87aa4c49e95 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
phungductung 0:e87aa4c49e95 53 #endif
phungductung 0:e87aa4c49e95 54
phungductung 0:e87aa4c49e95 55
phungductung 0:e87aa4c49e95 56 /** \brief No Operation
phungductung 0:e87aa4c49e95 57
phungductung 0:e87aa4c49e95 58 No Operation does nothing. This instruction can be used for code alignment purposes.
phungductung 0:e87aa4c49e95 59 */
phungductung 0:e87aa4c49e95 60 #define __NOP __nop
phungductung 0:e87aa4c49e95 61
phungductung 0:e87aa4c49e95 62
phungductung 0:e87aa4c49e95 63 /** \brief Wait For Interrupt
phungductung 0:e87aa4c49e95 64
phungductung 0:e87aa4c49e95 65 Wait For Interrupt is a hint instruction that suspends execution
phungductung 0:e87aa4c49e95 66 until one of a number of events occurs.
phungductung 0:e87aa4c49e95 67 */
phungductung 0:e87aa4c49e95 68 #define __WFI __wfi
phungductung 0:e87aa4c49e95 69
phungductung 0:e87aa4c49e95 70
phungductung 0:e87aa4c49e95 71 /** \brief Wait For Event
phungductung 0:e87aa4c49e95 72
phungductung 0:e87aa4c49e95 73 Wait For Event is a hint instruction that permits the processor to enter
phungductung 0:e87aa4c49e95 74 a low-power state until one of a number of events occurs.
phungductung 0:e87aa4c49e95 75 */
phungductung 0:e87aa4c49e95 76 #define __WFE __wfe
phungductung 0:e87aa4c49e95 77
phungductung 0:e87aa4c49e95 78
phungductung 0:e87aa4c49e95 79 /** \brief Send Event
phungductung 0:e87aa4c49e95 80
phungductung 0:e87aa4c49e95 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
phungductung 0:e87aa4c49e95 82 */
phungductung 0:e87aa4c49e95 83 #define __SEV __sev
phungductung 0:e87aa4c49e95 84
phungductung 0:e87aa4c49e95 85
phungductung 0:e87aa4c49e95 86 /** \brief Instruction Synchronization Barrier
phungductung 0:e87aa4c49e95 87
phungductung 0:e87aa4c49e95 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
phungductung 0:e87aa4c49e95 89 so that all instructions following the ISB are fetched from cache or
phungductung 0:e87aa4c49e95 90 memory, after the instruction has been completed.
phungductung 0:e87aa4c49e95 91 */
phungductung 0:e87aa4c49e95 92 #define __ISB() do {\
phungductung 0:e87aa4c49e95 93 __schedule_barrier();\
phungductung 0:e87aa4c49e95 94 __isb(0xF);\
phungductung 0:e87aa4c49e95 95 __schedule_barrier();\
phungductung 0:e87aa4c49e95 96 } while (0)
phungductung 0:e87aa4c49e95 97
phungductung 0:e87aa4c49e95 98 /** \brief Data Synchronization Barrier
phungductung 0:e87aa4c49e95 99
phungductung 0:e87aa4c49e95 100 This function acts as a special kind of Data Memory Barrier.
phungductung 0:e87aa4c49e95 101 It completes when all explicit memory accesses before this instruction complete.
phungductung 0:e87aa4c49e95 102 */
phungductung 0:e87aa4c49e95 103 #define __DSB() do {\
phungductung 0:e87aa4c49e95 104 __schedule_barrier();\
phungductung 0:e87aa4c49e95 105 __dsb(0xF);\
phungductung 0:e87aa4c49e95 106 __schedule_barrier();\
phungductung 0:e87aa4c49e95 107 } while (0)
phungductung 0:e87aa4c49e95 108
phungductung 0:e87aa4c49e95 109 /** \brief Data Memory Barrier
phungductung 0:e87aa4c49e95 110
phungductung 0:e87aa4c49e95 111 This function ensures the apparent order of the explicit memory operations before
phungductung 0:e87aa4c49e95 112 and after the instruction, without ensuring their completion.
phungductung 0:e87aa4c49e95 113 */
phungductung 0:e87aa4c49e95 114 #define __DMB() do {\
phungductung 0:e87aa4c49e95 115 __schedule_barrier();\
phungductung 0:e87aa4c49e95 116 __dmb(0xF);\
phungductung 0:e87aa4c49e95 117 __schedule_barrier();\
phungductung 0:e87aa4c49e95 118 } while (0)
phungductung 0:e87aa4c49e95 119
phungductung 0:e87aa4c49e95 120 /** \brief Reverse byte order (32 bit)
phungductung 0:e87aa4c49e95 121
phungductung 0:e87aa4c49e95 122 This function reverses the byte order in integer value.
phungductung 0:e87aa4c49e95 123
phungductung 0:e87aa4c49e95 124 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 125 \return Reversed value
phungductung 0:e87aa4c49e95 126 */
phungductung 0:e87aa4c49e95 127 #define __REV __rev
phungductung 0:e87aa4c49e95 128
phungductung 0:e87aa4c49e95 129
phungductung 0:e87aa4c49e95 130 /** \brief Reverse byte order (16 bit)
phungductung 0:e87aa4c49e95 131
phungductung 0:e87aa4c49e95 132 This function reverses the byte order in two unsigned short values.
phungductung 0:e87aa4c49e95 133
phungductung 0:e87aa4c49e95 134 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 135 \return Reversed value
phungductung 0:e87aa4c49e95 136 */
phungductung 0:e87aa4c49e95 137 #ifndef __NO_EMBEDDED_ASM
phungductung 0:e87aa4c49e95 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
phungductung 0:e87aa4c49e95 139 {
phungductung 0:e87aa4c49e95 140 rev16 r0, r0
phungductung 0:e87aa4c49e95 141 bx lr
phungductung 0:e87aa4c49e95 142 }
phungductung 0:e87aa4c49e95 143 #endif
phungductung 0:e87aa4c49e95 144
phungductung 0:e87aa4c49e95 145 /** \brief Reverse byte order in signed short value
phungductung 0:e87aa4c49e95 146
phungductung 0:e87aa4c49e95 147 This function reverses the byte order in a signed short value with sign extension to integer.
phungductung 0:e87aa4c49e95 148
phungductung 0:e87aa4c49e95 149 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 150 \return Reversed value
phungductung 0:e87aa4c49e95 151 */
phungductung 0:e87aa4c49e95 152 #ifndef __NO_EMBEDDED_ASM
phungductung 0:e87aa4c49e95 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
phungductung 0:e87aa4c49e95 154 {
phungductung 0:e87aa4c49e95 155 revsh r0, r0
phungductung 0:e87aa4c49e95 156 bx lr
phungductung 0:e87aa4c49e95 157 }
phungductung 0:e87aa4c49e95 158 #endif
phungductung 0:e87aa4c49e95 159
phungductung 0:e87aa4c49e95 160
phungductung 0:e87aa4c49e95 161 /** \brief Rotate Right in unsigned value (32 bit)
phungductung 0:e87aa4c49e95 162
phungductung 0:e87aa4c49e95 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
phungductung 0:e87aa4c49e95 164
phungductung 0:e87aa4c49e95 165 \param [in] value Value to rotate
phungductung 0:e87aa4c49e95 166 \param [in] value Number of Bits to rotate
phungductung 0:e87aa4c49e95 167 \return Rotated value
phungductung 0:e87aa4c49e95 168 */
phungductung 0:e87aa4c49e95 169 #define __ROR __ror
phungductung 0:e87aa4c49e95 170
phungductung 0:e87aa4c49e95 171
phungductung 0:e87aa4c49e95 172 /** \brief Breakpoint
phungductung 0:e87aa4c49e95 173
phungductung 0:e87aa4c49e95 174 This function causes the processor to enter Debug state.
phungductung 0:e87aa4c49e95 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
phungductung 0:e87aa4c49e95 176
phungductung 0:e87aa4c49e95 177 \param [in] value is ignored by the processor.
phungductung 0:e87aa4c49e95 178 If required, a debugger can use it to store additional information about the breakpoint.
phungductung 0:e87aa4c49e95 179 */
phungductung 0:e87aa4c49e95 180 #define __BKPT(value) __breakpoint(value)
phungductung 0:e87aa4c49e95 181
phungductung 0:e87aa4c49e95 182
phungductung 0:e87aa4c49e95 183 /** \brief Reverse bit order of value
phungductung 0:e87aa4c49e95 184
phungductung 0:e87aa4c49e95 185 This function reverses the bit order of the given value.
phungductung 0:e87aa4c49e95 186
phungductung 0:e87aa4c49e95 187 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 188 \return Reversed value
phungductung 0:e87aa4c49e95 189 */
phungductung 0:e87aa4c49e95 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
phungductung 0:e87aa4c49e95 191 #define __RBIT __rbit
phungductung 0:e87aa4c49e95 192 #else
phungductung 0:e87aa4c49e95 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
phungductung 0:e87aa4c49e95 194 {
phungductung 0:e87aa4c49e95 195 uint32_t result;
phungductung 0:e87aa4c49e95 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
phungductung 0:e87aa4c49e95 197
phungductung 0:e87aa4c49e95 198 result = value; // r will be reversed bits of v; first get LSB of v
phungductung 0:e87aa4c49e95 199 for (value >>= 1; value; value >>= 1)
phungductung 0:e87aa4c49e95 200 {
phungductung 0:e87aa4c49e95 201 result <<= 1;
phungductung 0:e87aa4c49e95 202 result |= value & 1;
phungductung 0:e87aa4c49e95 203 s--;
phungductung 0:e87aa4c49e95 204 }
phungductung 0:e87aa4c49e95 205 result <<= s; // shift when v's highest bits are zero
phungductung 0:e87aa4c49e95 206 return(result);
phungductung 0:e87aa4c49e95 207 }
phungductung 0:e87aa4c49e95 208 #endif
phungductung 0:e87aa4c49e95 209
phungductung 0:e87aa4c49e95 210
phungductung 0:e87aa4c49e95 211 /** \brief Count leading zeros
phungductung 0:e87aa4c49e95 212
phungductung 0:e87aa4c49e95 213 This function counts the number of leading zeros of a data value.
phungductung 0:e87aa4c49e95 214
phungductung 0:e87aa4c49e95 215 \param [in] value Value to count the leading zeros
phungductung 0:e87aa4c49e95 216 \return number of leading zeros in value
phungductung 0:e87aa4c49e95 217 */
phungductung 0:e87aa4c49e95 218 #define __CLZ __clz
phungductung 0:e87aa4c49e95 219
phungductung 0:e87aa4c49e95 220
phungductung 0:e87aa4c49e95 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
phungductung 0:e87aa4c49e95 222
phungductung 0:e87aa4c49e95 223 /** \brief LDR Exclusive (8 bit)
phungductung 0:e87aa4c49e95 224
phungductung 0:e87aa4c49e95 225 This function executes a exclusive LDR instruction for 8 bit value.
phungductung 0:e87aa4c49e95 226
phungductung 0:e87aa4c49e95 227 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 228 \return value of type uint8_t at (*ptr)
phungductung 0:e87aa4c49e95 229 */
phungductung 0:e87aa4c49e95 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
phungductung 0:e87aa4c49e95 231
phungductung 0:e87aa4c49e95 232
phungductung 0:e87aa4c49e95 233 /** \brief LDR Exclusive (16 bit)
phungductung 0:e87aa4c49e95 234
phungductung 0:e87aa4c49e95 235 This function executes a exclusive LDR instruction for 16 bit values.
phungductung 0:e87aa4c49e95 236
phungductung 0:e87aa4c49e95 237 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 238 \return value of type uint16_t at (*ptr)
phungductung 0:e87aa4c49e95 239 */
phungductung 0:e87aa4c49e95 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
phungductung 0:e87aa4c49e95 241
phungductung 0:e87aa4c49e95 242
phungductung 0:e87aa4c49e95 243 /** \brief LDR Exclusive (32 bit)
phungductung 0:e87aa4c49e95 244
phungductung 0:e87aa4c49e95 245 This function executes a exclusive LDR instruction for 32 bit values.
phungductung 0:e87aa4c49e95 246
phungductung 0:e87aa4c49e95 247 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 248 \return value of type uint32_t at (*ptr)
phungductung 0:e87aa4c49e95 249 */
phungductung 0:e87aa4c49e95 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
phungductung 0:e87aa4c49e95 251
phungductung 0:e87aa4c49e95 252
phungductung 0:e87aa4c49e95 253 /** \brief STR Exclusive (8 bit)
phungductung 0:e87aa4c49e95 254
phungductung 0:e87aa4c49e95 255 This function executes a exclusive STR instruction for 8 bit values.
phungductung 0:e87aa4c49e95 256
phungductung 0:e87aa4c49e95 257 \param [in] value Value to store
phungductung 0:e87aa4c49e95 258 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 259 \return 0 Function succeeded
phungductung 0:e87aa4c49e95 260 \return 1 Function failed
phungductung 0:e87aa4c49e95 261 */
phungductung 0:e87aa4c49e95 262 #define __STREXB(value, ptr) __strex(value, ptr)
phungductung 0:e87aa4c49e95 263
phungductung 0:e87aa4c49e95 264
phungductung 0:e87aa4c49e95 265 /** \brief STR Exclusive (16 bit)
phungductung 0:e87aa4c49e95 266
phungductung 0:e87aa4c49e95 267 This function executes a exclusive STR instruction for 16 bit values.
phungductung 0:e87aa4c49e95 268
phungductung 0:e87aa4c49e95 269 \param [in] value Value to store
phungductung 0:e87aa4c49e95 270 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 271 \return 0 Function succeeded
phungductung 0:e87aa4c49e95 272 \return 1 Function failed
phungductung 0:e87aa4c49e95 273 */
phungductung 0:e87aa4c49e95 274 #define __STREXH(value, ptr) __strex(value, ptr)
phungductung 0:e87aa4c49e95 275
phungductung 0:e87aa4c49e95 276
phungductung 0:e87aa4c49e95 277 /** \brief STR Exclusive (32 bit)
phungductung 0:e87aa4c49e95 278
phungductung 0:e87aa4c49e95 279 This function executes a exclusive STR instruction for 32 bit values.
phungductung 0:e87aa4c49e95 280
phungductung 0:e87aa4c49e95 281 \param [in] value Value to store
phungductung 0:e87aa4c49e95 282 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 283 \return 0 Function succeeded
phungductung 0:e87aa4c49e95 284 \return 1 Function failed
phungductung 0:e87aa4c49e95 285 */
phungductung 0:e87aa4c49e95 286 #define __STREXW(value, ptr) __strex(value, ptr)
phungductung 0:e87aa4c49e95 287
phungductung 0:e87aa4c49e95 288
phungductung 0:e87aa4c49e95 289 /** \brief Remove the exclusive lock
phungductung 0:e87aa4c49e95 290
phungductung 0:e87aa4c49e95 291 This function removes the exclusive lock which is created by LDREX.
phungductung 0:e87aa4c49e95 292
phungductung 0:e87aa4c49e95 293 */
phungductung 0:e87aa4c49e95 294 #define __CLREX __clrex
phungductung 0:e87aa4c49e95 295
phungductung 0:e87aa4c49e95 296
phungductung 0:e87aa4c49e95 297 /** \brief Signed Saturate
phungductung 0:e87aa4c49e95 298
phungductung 0:e87aa4c49e95 299 This function saturates a signed value.
phungductung 0:e87aa4c49e95 300
phungductung 0:e87aa4c49e95 301 \param [in] value Value to be saturated
phungductung 0:e87aa4c49e95 302 \param [in] sat Bit position to saturate to (1..32)
phungductung 0:e87aa4c49e95 303 \return Saturated value
phungductung 0:e87aa4c49e95 304 */
phungductung 0:e87aa4c49e95 305 #define __SSAT __ssat
phungductung 0:e87aa4c49e95 306
phungductung 0:e87aa4c49e95 307
phungductung 0:e87aa4c49e95 308 /** \brief Unsigned Saturate
phungductung 0:e87aa4c49e95 309
phungductung 0:e87aa4c49e95 310 This function saturates an unsigned value.
phungductung 0:e87aa4c49e95 311
phungductung 0:e87aa4c49e95 312 \param [in] value Value to be saturated
phungductung 0:e87aa4c49e95 313 \param [in] sat Bit position to saturate to (0..31)
phungductung 0:e87aa4c49e95 314 \return Saturated value
phungductung 0:e87aa4c49e95 315 */
phungductung 0:e87aa4c49e95 316 #define __USAT __usat
phungductung 0:e87aa4c49e95 317
phungductung 0:e87aa4c49e95 318
phungductung 0:e87aa4c49e95 319 /** \brief Rotate Right with Extend (32 bit)
phungductung 0:e87aa4c49e95 320
phungductung 0:e87aa4c49e95 321 This function moves each bit of a bitstring right by one bit.
phungductung 0:e87aa4c49e95 322 The carry input is shifted in at the left end of the bitstring.
phungductung 0:e87aa4c49e95 323
phungductung 0:e87aa4c49e95 324 \param [in] value Value to rotate
phungductung 0:e87aa4c49e95 325 \return Rotated value
phungductung 0:e87aa4c49e95 326 */
phungductung 0:e87aa4c49e95 327 #ifndef __NO_EMBEDDED_ASM
phungductung 0:e87aa4c49e95 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
phungductung 0:e87aa4c49e95 329 {
phungductung 0:e87aa4c49e95 330 rrx r0, r0
phungductung 0:e87aa4c49e95 331 bx lr
phungductung 0:e87aa4c49e95 332 }
phungductung 0:e87aa4c49e95 333 #endif
phungductung 0:e87aa4c49e95 334
phungductung 0:e87aa4c49e95 335
phungductung 0:e87aa4c49e95 336 /** \brief LDRT Unprivileged (8 bit)
phungductung 0:e87aa4c49e95 337
phungductung 0:e87aa4c49e95 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
phungductung 0:e87aa4c49e95 339
phungductung 0:e87aa4c49e95 340 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 341 \return value of type uint8_t at (*ptr)
phungductung 0:e87aa4c49e95 342 */
phungductung 0:e87aa4c49e95 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
phungductung 0:e87aa4c49e95 344
phungductung 0:e87aa4c49e95 345
phungductung 0:e87aa4c49e95 346 /** \brief LDRT Unprivileged (16 bit)
phungductung 0:e87aa4c49e95 347
phungductung 0:e87aa4c49e95 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
phungductung 0:e87aa4c49e95 349
phungductung 0:e87aa4c49e95 350 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 351 \return value of type uint16_t at (*ptr)
phungductung 0:e87aa4c49e95 352 */
phungductung 0:e87aa4c49e95 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
phungductung 0:e87aa4c49e95 354
phungductung 0:e87aa4c49e95 355
phungductung 0:e87aa4c49e95 356 /** \brief LDRT Unprivileged (32 bit)
phungductung 0:e87aa4c49e95 357
phungductung 0:e87aa4c49e95 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
phungductung 0:e87aa4c49e95 359
phungductung 0:e87aa4c49e95 360 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 361 \return value of type uint32_t at (*ptr)
phungductung 0:e87aa4c49e95 362 */
phungductung 0:e87aa4c49e95 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
phungductung 0:e87aa4c49e95 364
phungductung 0:e87aa4c49e95 365
phungductung 0:e87aa4c49e95 366 /** \brief STRT Unprivileged (8 bit)
phungductung 0:e87aa4c49e95 367
phungductung 0:e87aa4c49e95 368 This function executes a Unprivileged STRT instruction for 8 bit values.
phungductung 0:e87aa4c49e95 369
phungductung 0:e87aa4c49e95 370 \param [in] value Value to store
phungductung 0:e87aa4c49e95 371 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 372 */
phungductung 0:e87aa4c49e95 373 #define __STRBT(value, ptr) __strt(value, ptr)
phungductung 0:e87aa4c49e95 374
phungductung 0:e87aa4c49e95 375
phungductung 0:e87aa4c49e95 376 /** \brief STRT Unprivileged (16 bit)
phungductung 0:e87aa4c49e95 377
phungductung 0:e87aa4c49e95 378 This function executes a Unprivileged STRT instruction for 16 bit values.
phungductung 0:e87aa4c49e95 379
phungductung 0:e87aa4c49e95 380 \param [in] value Value to store
phungductung 0:e87aa4c49e95 381 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 382 */
phungductung 0:e87aa4c49e95 383 #define __STRHT(value, ptr) __strt(value, ptr)
phungductung 0:e87aa4c49e95 384
phungductung 0:e87aa4c49e95 385
phungductung 0:e87aa4c49e95 386 /** \brief STRT Unprivileged (32 bit)
phungductung 0:e87aa4c49e95 387
phungductung 0:e87aa4c49e95 388 This function executes a Unprivileged STRT instruction for 32 bit values.
phungductung 0:e87aa4c49e95 389
phungductung 0:e87aa4c49e95 390 \param [in] value Value to store
phungductung 0:e87aa4c49e95 391 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 392 */
phungductung 0:e87aa4c49e95 393 #define __STRT(value, ptr) __strt(value, ptr)
phungductung 0:e87aa4c49e95 394
phungductung 0:e87aa4c49e95 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
phungductung 0:e87aa4c49e95 396
phungductung 0:e87aa4c49e95 397
phungductung 0:e87aa4c49e95 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
phungductung 0:e87aa4c49e95 399 /* GNU gcc specific functions */
phungductung 0:e87aa4c49e95 400
phungductung 0:e87aa4c49e95 401 /* Define macros for porting to both thumb1 and thumb2.
phungductung 0:e87aa4c49e95 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
phungductung 0:e87aa4c49e95 403 * Otherwise, use general registers, specified by constrant "r" */
phungductung 0:e87aa4c49e95 404 #if defined (__thumb__) && !defined (__thumb2__)
phungductung 0:e87aa4c49e95 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
phungductung 0:e87aa4c49e95 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
phungductung 0:e87aa4c49e95 407 #else
phungductung 0:e87aa4c49e95 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
phungductung 0:e87aa4c49e95 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
phungductung 0:e87aa4c49e95 410 #endif
phungductung 0:e87aa4c49e95 411
phungductung 0:e87aa4c49e95 412 /** \brief No Operation
phungductung 0:e87aa4c49e95 413
phungductung 0:e87aa4c49e95 414 No Operation does nothing. This instruction can be used for code alignment purposes.
phungductung 0:e87aa4c49e95 415 */
phungductung 0:e87aa4c49e95 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
phungductung 0:e87aa4c49e95 417 {
phungductung 0:e87aa4c49e95 418 __ASM volatile ("nop");
phungductung 0:e87aa4c49e95 419 }
phungductung 0:e87aa4c49e95 420
phungductung 0:e87aa4c49e95 421
phungductung 0:e87aa4c49e95 422 /** \brief Wait For Interrupt
phungductung 0:e87aa4c49e95 423
phungductung 0:e87aa4c49e95 424 Wait For Interrupt is a hint instruction that suspends execution
phungductung 0:e87aa4c49e95 425 until one of a number of events occurs.
phungductung 0:e87aa4c49e95 426 */
phungductung 0:e87aa4c49e95 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
phungductung 0:e87aa4c49e95 428 {
phungductung 0:e87aa4c49e95 429 __ASM volatile ("wfi");
phungductung 0:e87aa4c49e95 430 }
phungductung 0:e87aa4c49e95 431
phungductung 0:e87aa4c49e95 432
phungductung 0:e87aa4c49e95 433 /** \brief Wait For Event
phungductung 0:e87aa4c49e95 434
phungductung 0:e87aa4c49e95 435 Wait For Event is a hint instruction that permits the processor to enter
phungductung 0:e87aa4c49e95 436 a low-power state until one of a number of events occurs.
phungductung 0:e87aa4c49e95 437 */
phungductung 0:e87aa4c49e95 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
phungductung 0:e87aa4c49e95 439 {
phungductung 0:e87aa4c49e95 440 __ASM volatile ("wfe");
phungductung 0:e87aa4c49e95 441 }
phungductung 0:e87aa4c49e95 442
phungductung 0:e87aa4c49e95 443
phungductung 0:e87aa4c49e95 444 /** \brief Send Event
phungductung 0:e87aa4c49e95 445
phungductung 0:e87aa4c49e95 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
phungductung 0:e87aa4c49e95 447 */
phungductung 0:e87aa4c49e95 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
phungductung 0:e87aa4c49e95 449 {
phungductung 0:e87aa4c49e95 450 __ASM volatile ("sev");
phungductung 0:e87aa4c49e95 451 }
phungductung 0:e87aa4c49e95 452
phungductung 0:e87aa4c49e95 453
phungductung 0:e87aa4c49e95 454 /** \brief Instruction Synchronization Barrier
phungductung 0:e87aa4c49e95 455
phungductung 0:e87aa4c49e95 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
phungductung 0:e87aa4c49e95 457 so that all instructions following the ISB are fetched from cache or
phungductung 0:e87aa4c49e95 458 memory, after the instruction has been completed.
phungductung 0:e87aa4c49e95 459 */
phungductung 0:e87aa4c49e95 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
phungductung 0:e87aa4c49e95 461 {
phungductung 0:e87aa4c49e95 462 __ASM volatile ("isb 0xF":::"memory");
phungductung 0:e87aa4c49e95 463 }
phungductung 0:e87aa4c49e95 464
phungductung 0:e87aa4c49e95 465
phungductung 0:e87aa4c49e95 466 /** \brief Data Synchronization Barrier
phungductung 0:e87aa4c49e95 467
phungductung 0:e87aa4c49e95 468 This function acts as a special kind of Data Memory Barrier.
phungductung 0:e87aa4c49e95 469 It completes when all explicit memory accesses before this instruction complete.
phungductung 0:e87aa4c49e95 470 */
phungductung 0:e87aa4c49e95 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
phungductung 0:e87aa4c49e95 472 {
phungductung 0:e87aa4c49e95 473 __ASM volatile ("dsb 0xF":::"memory");
phungductung 0:e87aa4c49e95 474 }
phungductung 0:e87aa4c49e95 475
phungductung 0:e87aa4c49e95 476
phungductung 0:e87aa4c49e95 477 /** \brief Data Memory Barrier
phungductung 0:e87aa4c49e95 478
phungductung 0:e87aa4c49e95 479 This function ensures the apparent order of the explicit memory operations before
phungductung 0:e87aa4c49e95 480 and after the instruction, without ensuring their completion.
phungductung 0:e87aa4c49e95 481 */
phungductung 0:e87aa4c49e95 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
phungductung 0:e87aa4c49e95 483 {
phungductung 0:e87aa4c49e95 484 __ASM volatile ("dmb 0xF":::"memory");
phungductung 0:e87aa4c49e95 485 }
phungductung 0:e87aa4c49e95 486
phungductung 0:e87aa4c49e95 487
phungductung 0:e87aa4c49e95 488 /** \brief Reverse byte order (32 bit)
phungductung 0:e87aa4c49e95 489
phungductung 0:e87aa4c49e95 490 This function reverses the byte order in integer value.
phungductung 0:e87aa4c49e95 491
phungductung 0:e87aa4c49e95 492 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 493 \return Reversed value
phungductung 0:e87aa4c49e95 494 */
phungductung 0:e87aa4c49e95 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
phungductung 0:e87aa4c49e95 496 {
phungductung 0:e87aa4c49e95 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
phungductung 0:e87aa4c49e95 498 return __builtin_bswap32(value);
phungductung 0:e87aa4c49e95 499 #else
phungductung 0:e87aa4c49e95 500 uint32_t result;
phungductung 0:e87aa4c49e95 501
phungductung 0:e87aa4c49e95 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
phungductung 0:e87aa4c49e95 503 return(result);
phungductung 0:e87aa4c49e95 504 #endif
phungductung 0:e87aa4c49e95 505 }
phungductung 0:e87aa4c49e95 506
phungductung 0:e87aa4c49e95 507
phungductung 0:e87aa4c49e95 508 /** \brief Reverse byte order (16 bit)
phungductung 0:e87aa4c49e95 509
phungductung 0:e87aa4c49e95 510 This function reverses the byte order in two unsigned short values.
phungductung 0:e87aa4c49e95 511
phungductung 0:e87aa4c49e95 512 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 513 \return Reversed value
phungductung 0:e87aa4c49e95 514 */
phungductung 0:e87aa4c49e95 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
phungductung 0:e87aa4c49e95 516 {
phungductung 0:e87aa4c49e95 517 uint32_t result;
phungductung 0:e87aa4c49e95 518
phungductung 0:e87aa4c49e95 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
phungductung 0:e87aa4c49e95 520 return(result);
phungductung 0:e87aa4c49e95 521 }
phungductung 0:e87aa4c49e95 522
phungductung 0:e87aa4c49e95 523
phungductung 0:e87aa4c49e95 524 /** \brief Reverse byte order in signed short value
phungductung 0:e87aa4c49e95 525
phungductung 0:e87aa4c49e95 526 This function reverses the byte order in a signed short value with sign extension to integer.
phungductung 0:e87aa4c49e95 527
phungductung 0:e87aa4c49e95 528 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 529 \return Reversed value
phungductung 0:e87aa4c49e95 530 */
phungductung 0:e87aa4c49e95 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
phungductung 0:e87aa4c49e95 532 {
phungductung 0:e87aa4c49e95 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
phungductung 0:e87aa4c49e95 534 return (short)__builtin_bswap16(value);
phungductung 0:e87aa4c49e95 535 #else
phungductung 0:e87aa4c49e95 536 uint32_t result;
phungductung 0:e87aa4c49e95 537
phungductung 0:e87aa4c49e95 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
phungductung 0:e87aa4c49e95 539 return(result);
phungductung 0:e87aa4c49e95 540 #endif
phungductung 0:e87aa4c49e95 541 }
phungductung 0:e87aa4c49e95 542
phungductung 0:e87aa4c49e95 543
phungductung 0:e87aa4c49e95 544 /** \brief Rotate Right in unsigned value (32 bit)
phungductung 0:e87aa4c49e95 545
phungductung 0:e87aa4c49e95 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
phungductung 0:e87aa4c49e95 547
phungductung 0:e87aa4c49e95 548 \param [in] value Value to rotate
phungductung 0:e87aa4c49e95 549 \param [in] value Number of Bits to rotate
phungductung 0:e87aa4c49e95 550 \return Rotated value
phungductung 0:e87aa4c49e95 551 */
phungductung 0:e87aa4c49e95 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
phungductung 0:e87aa4c49e95 553 {
phungductung 0:e87aa4c49e95 554 return (op1 >> op2) | (op1 << (32 - op2));
phungductung 0:e87aa4c49e95 555 }
phungductung 0:e87aa4c49e95 556
phungductung 0:e87aa4c49e95 557
phungductung 0:e87aa4c49e95 558 /** \brief Breakpoint
phungductung 0:e87aa4c49e95 559
phungductung 0:e87aa4c49e95 560 This function causes the processor to enter Debug state.
phungductung 0:e87aa4c49e95 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
phungductung 0:e87aa4c49e95 562
phungductung 0:e87aa4c49e95 563 \param [in] value is ignored by the processor.
phungductung 0:e87aa4c49e95 564 If required, a debugger can use it to store additional information about the breakpoint.
phungductung 0:e87aa4c49e95 565 */
phungductung 0:e87aa4c49e95 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
phungductung 0:e87aa4c49e95 567
phungductung 0:e87aa4c49e95 568
phungductung 0:e87aa4c49e95 569 /** \brief Reverse bit order of value
phungductung 0:e87aa4c49e95 570
phungductung 0:e87aa4c49e95 571 This function reverses the bit order of the given value.
phungductung 0:e87aa4c49e95 572
phungductung 0:e87aa4c49e95 573 \param [in] value Value to reverse
phungductung 0:e87aa4c49e95 574 \return Reversed value
phungductung 0:e87aa4c49e95 575 */
phungductung 0:e87aa4c49e95 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
phungductung 0:e87aa4c49e95 577 {
phungductung 0:e87aa4c49e95 578 uint32_t result;
phungductung 0:e87aa4c49e95 579
phungductung 0:e87aa4c49e95 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
phungductung 0:e87aa4c49e95 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
phungductung 0:e87aa4c49e95 582 #else
phungductung 0:e87aa4c49e95 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
phungductung 0:e87aa4c49e95 584
phungductung 0:e87aa4c49e95 585 result = value; // r will be reversed bits of v; first get LSB of v
phungductung 0:e87aa4c49e95 586 for (value >>= 1; value; value >>= 1)
phungductung 0:e87aa4c49e95 587 {
phungductung 0:e87aa4c49e95 588 result <<= 1;
phungductung 0:e87aa4c49e95 589 result |= value & 1;
phungductung 0:e87aa4c49e95 590 s--;
phungductung 0:e87aa4c49e95 591 }
phungductung 0:e87aa4c49e95 592 result <<= s; // shift when v's highest bits are zero
phungductung 0:e87aa4c49e95 593 #endif
phungductung 0:e87aa4c49e95 594 return(result);
phungductung 0:e87aa4c49e95 595 }
phungductung 0:e87aa4c49e95 596
phungductung 0:e87aa4c49e95 597
phungductung 0:e87aa4c49e95 598 /** \brief Count leading zeros
phungductung 0:e87aa4c49e95 599
phungductung 0:e87aa4c49e95 600 This function counts the number of leading zeros of a data value.
phungductung 0:e87aa4c49e95 601
phungductung 0:e87aa4c49e95 602 \param [in] value Value to count the leading zeros
phungductung 0:e87aa4c49e95 603 \return number of leading zeros in value
phungductung 0:e87aa4c49e95 604 */
phungductung 0:e87aa4c49e95 605 #define __CLZ __builtin_clz
phungductung 0:e87aa4c49e95 606
phungductung 0:e87aa4c49e95 607
phungductung 0:e87aa4c49e95 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
phungductung 0:e87aa4c49e95 609
phungductung 0:e87aa4c49e95 610 /** \brief LDR Exclusive (8 bit)
phungductung 0:e87aa4c49e95 611
phungductung 0:e87aa4c49e95 612 This function executes a exclusive LDR instruction for 8 bit value.
phungductung 0:e87aa4c49e95 613
phungductung 0:e87aa4c49e95 614 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 615 \return value of type uint8_t at (*ptr)
phungductung 0:e87aa4c49e95 616 */
phungductung 0:e87aa4c49e95 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
phungductung 0:e87aa4c49e95 618 {
phungductung 0:e87aa4c49e95 619 uint32_t result;
phungductung 0:e87aa4c49e95 620
phungductung 0:e87aa4c49e95 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
phungductung 0:e87aa4c49e95 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
phungductung 0:e87aa4c49e95 623 #else
phungductung 0:e87aa4c49e95 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
phungductung 0:e87aa4c49e95 625 accepted by assembler. So has to use following less efficient pattern.
phungductung 0:e87aa4c49e95 626 */
phungductung 0:e87aa4c49e95 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
phungductung 0:e87aa4c49e95 628 #endif
phungductung 0:e87aa4c49e95 629 return ((uint8_t) result); /* Add explicit type cast here */
phungductung 0:e87aa4c49e95 630 }
phungductung 0:e87aa4c49e95 631
phungductung 0:e87aa4c49e95 632
phungductung 0:e87aa4c49e95 633 /** \brief LDR Exclusive (16 bit)
phungductung 0:e87aa4c49e95 634
phungductung 0:e87aa4c49e95 635 This function executes a exclusive LDR instruction for 16 bit values.
phungductung 0:e87aa4c49e95 636
phungductung 0:e87aa4c49e95 637 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 638 \return value of type uint16_t at (*ptr)
phungductung 0:e87aa4c49e95 639 */
phungductung 0:e87aa4c49e95 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
phungductung 0:e87aa4c49e95 641 {
phungductung 0:e87aa4c49e95 642 uint32_t result;
phungductung 0:e87aa4c49e95 643
phungductung 0:e87aa4c49e95 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
phungductung 0:e87aa4c49e95 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
phungductung 0:e87aa4c49e95 646 #else
phungductung 0:e87aa4c49e95 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
phungductung 0:e87aa4c49e95 648 accepted by assembler. So has to use following less efficient pattern.
phungductung 0:e87aa4c49e95 649 */
phungductung 0:e87aa4c49e95 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
phungductung 0:e87aa4c49e95 651 #endif
phungductung 0:e87aa4c49e95 652 return ((uint16_t) result); /* Add explicit type cast here */
phungductung 0:e87aa4c49e95 653 }
phungductung 0:e87aa4c49e95 654
phungductung 0:e87aa4c49e95 655
phungductung 0:e87aa4c49e95 656 /** \brief LDR Exclusive (32 bit)
phungductung 0:e87aa4c49e95 657
phungductung 0:e87aa4c49e95 658 This function executes a exclusive LDR instruction for 32 bit values.
phungductung 0:e87aa4c49e95 659
phungductung 0:e87aa4c49e95 660 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 661 \return value of type uint32_t at (*ptr)
phungductung 0:e87aa4c49e95 662 */
phungductung 0:e87aa4c49e95 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
phungductung 0:e87aa4c49e95 664 {
phungductung 0:e87aa4c49e95 665 uint32_t result;
phungductung 0:e87aa4c49e95 666
phungductung 0:e87aa4c49e95 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
phungductung 0:e87aa4c49e95 668 return(result);
phungductung 0:e87aa4c49e95 669 }
phungductung 0:e87aa4c49e95 670
phungductung 0:e87aa4c49e95 671
phungductung 0:e87aa4c49e95 672 /** \brief STR Exclusive (8 bit)
phungductung 0:e87aa4c49e95 673
phungductung 0:e87aa4c49e95 674 This function executes a exclusive STR instruction for 8 bit values.
phungductung 0:e87aa4c49e95 675
phungductung 0:e87aa4c49e95 676 \param [in] value Value to store
phungductung 0:e87aa4c49e95 677 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 678 \return 0 Function succeeded
phungductung 0:e87aa4c49e95 679 \return 1 Function failed
phungductung 0:e87aa4c49e95 680 */
phungductung 0:e87aa4c49e95 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
phungductung 0:e87aa4c49e95 682 {
phungductung 0:e87aa4c49e95 683 uint32_t result;
phungductung 0:e87aa4c49e95 684
phungductung 0:e87aa4c49e95 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
phungductung 0:e87aa4c49e95 686 return(result);
phungductung 0:e87aa4c49e95 687 }
phungductung 0:e87aa4c49e95 688
phungductung 0:e87aa4c49e95 689
phungductung 0:e87aa4c49e95 690 /** \brief STR Exclusive (16 bit)
phungductung 0:e87aa4c49e95 691
phungductung 0:e87aa4c49e95 692 This function executes a exclusive STR instruction for 16 bit values.
phungductung 0:e87aa4c49e95 693
phungductung 0:e87aa4c49e95 694 \param [in] value Value to store
phungductung 0:e87aa4c49e95 695 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 696 \return 0 Function succeeded
phungductung 0:e87aa4c49e95 697 \return 1 Function failed
phungductung 0:e87aa4c49e95 698 */
phungductung 0:e87aa4c49e95 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
phungductung 0:e87aa4c49e95 700 {
phungductung 0:e87aa4c49e95 701 uint32_t result;
phungductung 0:e87aa4c49e95 702
phungductung 0:e87aa4c49e95 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
phungductung 0:e87aa4c49e95 704 return(result);
phungductung 0:e87aa4c49e95 705 }
phungductung 0:e87aa4c49e95 706
phungductung 0:e87aa4c49e95 707
phungductung 0:e87aa4c49e95 708 /** \brief STR Exclusive (32 bit)
phungductung 0:e87aa4c49e95 709
phungductung 0:e87aa4c49e95 710 This function executes a exclusive STR instruction for 32 bit values.
phungductung 0:e87aa4c49e95 711
phungductung 0:e87aa4c49e95 712 \param [in] value Value to store
phungductung 0:e87aa4c49e95 713 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 714 \return 0 Function succeeded
phungductung 0:e87aa4c49e95 715 \return 1 Function failed
phungductung 0:e87aa4c49e95 716 */
phungductung 0:e87aa4c49e95 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
phungductung 0:e87aa4c49e95 718 {
phungductung 0:e87aa4c49e95 719 uint32_t result;
phungductung 0:e87aa4c49e95 720
phungductung 0:e87aa4c49e95 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
phungductung 0:e87aa4c49e95 722 return(result);
phungductung 0:e87aa4c49e95 723 }
phungductung 0:e87aa4c49e95 724
phungductung 0:e87aa4c49e95 725
phungductung 0:e87aa4c49e95 726 /** \brief Remove the exclusive lock
phungductung 0:e87aa4c49e95 727
phungductung 0:e87aa4c49e95 728 This function removes the exclusive lock which is created by LDREX.
phungductung 0:e87aa4c49e95 729
phungductung 0:e87aa4c49e95 730 */
phungductung 0:e87aa4c49e95 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
phungductung 0:e87aa4c49e95 732 {
phungductung 0:e87aa4c49e95 733 __ASM volatile ("clrex" ::: "memory");
phungductung 0:e87aa4c49e95 734 }
phungductung 0:e87aa4c49e95 735
phungductung 0:e87aa4c49e95 736
phungductung 0:e87aa4c49e95 737 /** \brief Signed Saturate
phungductung 0:e87aa4c49e95 738
phungductung 0:e87aa4c49e95 739 This function saturates a signed value.
phungductung 0:e87aa4c49e95 740
phungductung 0:e87aa4c49e95 741 \param [in] value Value to be saturated
phungductung 0:e87aa4c49e95 742 \param [in] sat Bit position to saturate to (1..32)
phungductung 0:e87aa4c49e95 743 \return Saturated value
phungductung 0:e87aa4c49e95 744 */
phungductung 0:e87aa4c49e95 745 #define __SSAT(ARG1,ARG2) \
phungductung 0:e87aa4c49e95 746 ({ \
phungductung 0:e87aa4c49e95 747 uint32_t __RES, __ARG1 = (ARG1); \
phungductung 0:e87aa4c49e95 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
phungductung 0:e87aa4c49e95 749 __RES; \
phungductung 0:e87aa4c49e95 750 })
phungductung 0:e87aa4c49e95 751
phungductung 0:e87aa4c49e95 752
phungductung 0:e87aa4c49e95 753 /** \brief Unsigned Saturate
phungductung 0:e87aa4c49e95 754
phungductung 0:e87aa4c49e95 755 This function saturates an unsigned value.
phungductung 0:e87aa4c49e95 756
phungductung 0:e87aa4c49e95 757 \param [in] value Value to be saturated
phungductung 0:e87aa4c49e95 758 \param [in] sat Bit position to saturate to (0..31)
phungductung 0:e87aa4c49e95 759 \return Saturated value
phungductung 0:e87aa4c49e95 760 */
phungductung 0:e87aa4c49e95 761 #define __USAT(ARG1,ARG2) \
phungductung 0:e87aa4c49e95 762 ({ \
phungductung 0:e87aa4c49e95 763 uint32_t __RES, __ARG1 = (ARG1); \
phungductung 0:e87aa4c49e95 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
phungductung 0:e87aa4c49e95 765 __RES; \
phungductung 0:e87aa4c49e95 766 })
phungductung 0:e87aa4c49e95 767
phungductung 0:e87aa4c49e95 768
phungductung 0:e87aa4c49e95 769 /** \brief Rotate Right with Extend (32 bit)
phungductung 0:e87aa4c49e95 770
phungductung 0:e87aa4c49e95 771 This function moves each bit of a bitstring right by one bit.
phungductung 0:e87aa4c49e95 772 The carry input is shifted in at the left end of the bitstring.
phungductung 0:e87aa4c49e95 773
phungductung 0:e87aa4c49e95 774 \param [in] value Value to rotate
phungductung 0:e87aa4c49e95 775 \return Rotated value
phungductung 0:e87aa4c49e95 776 */
phungductung 0:e87aa4c49e95 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
phungductung 0:e87aa4c49e95 778 {
phungductung 0:e87aa4c49e95 779 uint32_t result;
phungductung 0:e87aa4c49e95 780
phungductung 0:e87aa4c49e95 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
phungductung 0:e87aa4c49e95 782 return(result);
phungductung 0:e87aa4c49e95 783 }
phungductung 0:e87aa4c49e95 784
phungductung 0:e87aa4c49e95 785
phungductung 0:e87aa4c49e95 786 /** \brief LDRT Unprivileged (8 bit)
phungductung 0:e87aa4c49e95 787
phungductung 0:e87aa4c49e95 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
phungductung 0:e87aa4c49e95 789
phungductung 0:e87aa4c49e95 790 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 791 \return value of type uint8_t at (*ptr)
phungductung 0:e87aa4c49e95 792 */
phungductung 0:e87aa4c49e95 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
phungductung 0:e87aa4c49e95 794 {
phungductung 0:e87aa4c49e95 795 uint32_t result;
phungductung 0:e87aa4c49e95 796
phungductung 0:e87aa4c49e95 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
phungductung 0:e87aa4c49e95 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
phungductung 0:e87aa4c49e95 799 #else
phungductung 0:e87aa4c49e95 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
phungductung 0:e87aa4c49e95 801 accepted by assembler. So has to use following less efficient pattern.
phungductung 0:e87aa4c49e95 802 */
phungductung 0:e87aa4c49e95 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
phungductung 0:e87aa4c49e95 804 #endif
phungductung 0:e87aa4c49e95 805 return ((uint8_t) result); /* Add explicit type cast here */
phungductung 0:e87aa4c49e95 806 }
phungductung 0:e87aa4c49e95 807
phungductung 0:e87aa4c49e95 808
phungductung 0:e87aa4c49e95 809 /** \brief LDRT Unprivileged (16 bit)
phungductung 0:e87aa4c49e95 810
phungductung 0:e87aa4c49e95 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
phungductung 0:e87aa4c49e95 812
phungductung 0:e87aa4c49e95 813 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 814 \return value of type uint16_t at (*ptr)
phungductung 0:e87aa4c49e95 815 */
phungductung 0:e87aa4c49e95 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
phungductung 0:e87aa4c49e95 817 {
phungductung 0:e87aa4c49e95 818 uint32_t result;
phungductung 0:e87aa4c49e95 819
phungductung 0:e87aa4c49e95 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
phungductung 0:e87aa4c49e95 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
phungductung 0:e87aa4c49e95 822 #else
phungductung 0:e87aa4c49e95 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
phungductung 0:e87aa4c49e95 824 accepted by assembler. So has to use following less efficient pattern.
phungductung 0:e87aa4c49e95 825 */
phungductung 0:e87aa4c49e95 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
phungductung 0:e87aa4c49e95 827 #endif
phungductung 0:e87aa4c49e95 828 return ((uint16_t) result); /* Add explicit type cast here */
phungductung 0:e87aa4c49e95 829 }
phungductung 0:e87aa4c49e95 830
phungductung 0:e87aa4c49e95 831
phungductung 0:e87aa4c49e95 832 /** \brief LDRT Unprivileged (32 bit)
phungductung 0:e87aa4c49e95 833
phungductung 0:e87aa4c49e95 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
phungductung 0:e87aa4c49e95 835
phungductung 0:e87aa4c49e95 836 \param [in] ptr Pointer to data
phungductung 0:e87aa4c49e95 837 \return value of type uint32_t at (*ptr)
phungductung 0:e87aa4c49e95 838 */
phungductung 0:e87aa4c49e95 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
phungductung 0:e87aa4c49e95 840 {
phungductung 0:e87aa4c49e95 841 uint32_t result;
phungductung 0:e87aa4c49e95 842
phungductung 0:e87aa4c49e95 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
phungductung 0:e87aa4c49e95 844 return(result);
phungductung 0:e87aa4c49e95 845 }
phungductung 0:e87aa4c49e95 846
phungductung 0:e87aa4c49e95 847
phungductung 0:e87aa4c49e95 848 /** \brief STRT Unprivileged (8 bit)
phungductung 0:e87aa4c49e95 849
phungductung 0:e87aa4c49e95 850 This function executes a Unprivileged STRT instruction for 8 bit values.
phungductung 0:e87aa4c49e95 851
phungductung 0:e87aa4c49e95 852 \param [in] value Value to store
phungductung 0:e87aa4c49e95 853 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 854 */
phungductung 0:e87aa4c49e95 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
phungductung 0:e87aa4c49e95 856 {
phungductung 0:e87aa4c49e95 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
phungductung 0:e87aa4c49e95 858 }
phungductung 0:e87aa4c49e95 859
phungductung 0:e87aa4c49e95 860
phungductung 0:e87aa4c49e95 861 /** \brief STRT Unprivileged (16 bit)
phungductung 0:e87aa4c49e95 862
phungductung 0:e87aa4c49e95 863 This function executes a Unprivileged STRT instruction for 16 bit values.
phungductung 0:e87aa4c49e95 864
phungductung 0:e87aa4c49e95 865 \param [in] value Value to store
phungductung 0:e87aa4c49e95 866 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 867 */
phungductung 0:e87aa4c49e95 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
phungductung 0:e87aa4c49e95 869 {
phungductung 0:e87aa4c49e95 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
phungductung 0:e87aa4c49e95 871 }
phungductung 0:e87aa4c49e95 872
phungductung 0:e87aa4c49e95 873
phungductung 0:e87aa4c49e95 874 /** \brief STRT Unprivileged (32 bit)
phungductung 0:e87aa4c49e95 875
phungductung 0:e87aa4c49e95 876 This function executes a Unprivileged STRT instruction for 32 bit values.
phungductung 0:e87aa4c49e95 877
phungductung 0:e87aa4c49e95 878 \param [in] value Value to store
phungductung 0:e87aa4c49e95 879 \param [in] ptr Pointer to location
phungductung 0:e87aa4c49e95 880 */
phungductung 0:e87aa4c49e95 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
phungductung 0:e87aa4c49e95 882 {
phungductung 0:e87aa4c49e95 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
phungductung 0:e87aa4c49e95 884 }
phungductung 0:e87aa4c49e95 885
phungductung 0:e87aa4c49e95 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
phungductung 0:e87aa4c49e95 887
phungductung 0:e87aa4c49e95 888
phungductung 0:e87aa4c49e95 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
phungductung 0:e87aa4c49e95 890 /* IAR iccarm specific functions */
phungductung 0:e87aa4c49e95 891 #include <cmsis_iar.h>
phungductung 0:e87aa4c49e95 892
phungductung 0:e87aa4c49e95 893
phungductung 0:e87aa4c49e95 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
phungductung 0:e87aa4c49e95 895 /* TI CCS specific functions */
phungductung 0:e87aa4c49e95 896 #include <cmsis_ccs.h>
phungductung 0:e87aa4c49e95 897
phungductung 0:e87aa4c49e95 898
phungductung 0:e87aa4c49e95 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
phungductung 0:e87aa4c49e95 900 /* TASKING carm specific functions */
phungductung 0:e87aa4c49e95 901 /*
phungductung 0:e87aa4c49e95 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
phungductung 0:e87aa4c49e95 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
phungductung 0:e87aa4c49e95 904 * Including the CMSIS ones.
phungductung 0:e87aa4c49e95 905 */
phungductung 0:e87aa4c49e95 906
phungductung 0:e87aa4c49e95 907
phungductung 0:e87aa4c49e95 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
phungductung 0:e87aa4c49e95 909 /* Cosmic specific functions */
phungductung 0:e87aa4c49e95 910 #include <cmsis_csm.h>
phungductung 0:e87aa4c49e95 911
phungductung 0:e87aa4c49e95 912 #endif
phungductung 0:e87aa4c49e95 913
phungductung 0:e87aa4c49e95 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
phungductung 0:e87aa4c49e95 915
phungductung 0:e87aa4c49e95 916 #endif /* __CORE_CMINSTR_H */