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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:51:46 2019 +0000
Revision:: 0:e87aa4c49e95

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User	Revision	Line number	New contents of line
phungductung	0:e87aa4c49e95	1	/**
phungductung	0:e87aa4c49e95	2	******************************************************************************
phungductung	0:e87aa4c49e95	3	* @file stm32f7xx_hal_qspi.c
phungductung	0:e87aa4c49e95	4	* @author MCD Application Team
phungductung	0:e87aa4c49e95	5	* @version V1.0.4
phungductung	0:e87aa4c49e95	6	* @date 09-December-2015
phungductung	0:e87aa4c49e95	7	* @brief QSPI HAL module driver.
phungductung	0:e87aa4c49e95	8	* This file provides firmware functions to manage the following
phungductung	0:e87aa4c49e95	9	* functionalities of the QuadSPI interface (QSPI).
phungductung	0:e87aa4c49e95	10	* + Initialization and de-initialization functions
phungductung	0:e87aa4c49e95	11	* + Indirect functional mode management
phungductung	0:e87aa4c49e95	12	* + Memory-mapped functional mode management
phungductung	0:e87aa4c49e95	13	* + Auto-polling functional mode management
phungductung	0:e87aa4c49e95	14	* + Interrupts and flags management
phungductung	0:e87aa4c49e95	15	* + DMA channel configuration for indirect functional mode
phungductung	0:e87aa4c49e95	16	* + Errors management and abort functionality
phungductung	0:e87aa4c49e95	17	*
phungductung	0:e87aa4c49e95	18	*
phungductung	0:e87aa4c49e95	19	@verbatim
phungductung	0:e87aa4c49e95	20	===============================================================================
phungductung	0:e87aa4c49e95	21	##### How to use this driver #####
phungductung	0:e87aa4c49e95	22	===============================================================================
phungductung	0:e87aa4c49e95	23	[..]
phungductung	0:e87aa4c49e95	24	* Initialization *
phungductung	0:e87aa4c49e95	25	======================
phungductung	0:e87aa4c49e95	26	[..]
phungductung	0:e87aa4c49e95	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
phungductung	0:e87aa4c49e95	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
phungductung	0:e87aa4c49e95	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
phungductung	0:e87aa4c49e95	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
phungductung	0:e87aa4c49e95	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
phungductung	0:e87aa4c49e95	32	(++) If interrupt mode is used, enable and configure QuadSPI global
phungductung	0:e87aa4c49e95	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
phungductung	0:e87aa4c49e95	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
phungductung	0:e87aa4c49e95	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
phungductung	0:e87aa4c49e95	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
phungductung	0:e87aa4c49e95	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
phungductung	0:e87aa4c49e95	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
phungductung	0:e87aa4c49e95	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
phungductung	0:e87aa4c49e95	40
phungductung	0:e87aa4c49e95	41	* Indirect functional mode *
phungductung	0:e87aa4c49e95	42	================================
phungductung	0:e87aa4c49e95	43	[..]
phungductung	0:e87aa4c49e95	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
phungductung	0:e87aa4c49e95	45	functions :
phungductung	0:e87aa4c49e95	46	(++) Instruction phase : the mode used and if present the instruction opcode.
phungductung	0:e87aa4c49e95	47	(++) Address phase : the mode used and if present the size and the address value.
phungductung	0:e87aa4c49e95	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
phungductung	0:e87aa4c49e95	49	bytes values.
phungductung	0:e87aa4c49e95	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
phungductung	0:e87aa4c49e95	51	(++) Data phase : the mode used and if present the number of bytes.
phungductung	0:e87aa4c49e95	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
phungductung	0:e87aa4c49e95	53	if activated.
phungductung	0:e87aa4c49e95	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
phungductung	0:e87aa4c49e95	55	(#) If no data is required for the command, it is sent directly to the memory :
phungductung	0:e87aa4c49e95	56	(++) In polling mode, the output of the function is done when the transfer is complete.
phungductung	0:e87aa4c49e95	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
phungductung	0:e87aa4c49e95	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
phungductung	0:e87aa4c49e95	59	HAL_QSPI_Transmit_IT() after the command configuration :
phungductung	0:e87aa4c49e95	60	(++) In polling mode, the output of the function is done when the transfer is complete.
phungductung	0:e87aa4c49e95	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
phungductung	0:e87aa4c49e95	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
phungductung	0:e87aa4c49e95	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
phungductung	0:e87aa4c49e95	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
phungductung	0:e87aa4c49e95	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
phungductung	0:e87aa4c49e95	66	HAL_QSPI_Receive_IT() after the command configuration :
phungductung	0:e87aa4c49e95	67	(++) In polling mode, the output of the function is done when the transfer is complete.
phungductung	0:e87aa4c49e95	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
phungductung	0:e87aa4c49e95	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
phungductung	0:e87aa4c49e95	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
phungductung	0:e87aa4c49e95	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
phungductung	0:e87aa4c49e95	72
phungductung	0:e87aa4c49e95	73	* Auto-polling functional mode *
phungductung	0:e87aa4c49e95	74	====================================
phungductung	0:e87aa4c49e95	75	[..]
phungductung	0:e87aa4c49e95	76	(#) Configure the command sequence and the auto-polling functional mode using the
phungductung	0:e87aa4c49e95	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
phungductung	0:e87aa4c49e95	78	(++) Instruction phase : the mode used and if present the instruction opcode.
phungductung	0:e87aa4c49e95	79	(++) Address phase : the mode used and if present the size and the address value.
phungductung	0:e87aa4c49e95	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
phungductung	0:e87aa4c49e95	81	bytes values.
phungductung	0:e87aa4c49e95	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
phungductung	0:e87aa4c49e95	83	(++) Data phase : the mode used.
phungductung	0:e87aa4c49e95	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
phungductung	0:e87aa4c49e95	85	if activated.
phungductung	0:e87aa4c49e95	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
phungductung	0:e87aa4c49e95	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
phungductung	0:e87aa4c49e95	88	the polling interval and the automatic stop activation.
phungductung	0:e87aa4c49e95	89	(#) After the configuration :
phungductung	0:e87aa4c49e95	90	(++) In polling mode, the output of the function is done when the status match is reached. The
phungductung	0:e87aa4c49e95	91	automatic stop is activated to avoid an infinite loop.
phungductung	0:e87aa4c49e95	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
phungductung	0:e87aa4c49e95	93
phungductung	0:e87aa4c49e95	94	* Memory-mapped functional mode *
phungductung	0:e87aa4c49e95	95	=====================================
phungductung	0:e87aa4c49e95	96	[..]
phungductung	0:e87aa4c49e95	97	(#) Configure the command sequence and the memory-mapped functional mode using the
phungductung	0:e87aa4c49e95	98	HAL_QSPI_MemoryMapped() functions :
phungductung	0:e87aa4c49e95	99	(++) Instruction phase : the mode used and if present the instruction opcode.
phungductung	0:e87aa4c49e95	100	(++) Address phase : the mode used and the size.
phungductung	0:e87aa4c49e95	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
phungductung	0:e87aa4c49e95	102	bytes values.
phungductung	0:e87aa4c49e95	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
phungductung	0:e87aa4c49e95	104	(++) Data phase : the mode used.
phungductung	0:e87aa4c49e95	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
phungductung	0:e87aa4c49e95	106	if activated.
phungductung	0:e87aa4c49e95	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
phungductung	0:e87aa4c49e95	108	(++) The timeout activation and the timeout period.
phungductung	0:e87aa4c49e95	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
phungductung	0:e87aa4c49e95	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
phungductung	0:e87aa4c49e95	111
phungductung	0:e87aa4c49e95	112	* Errors management and abort functionality *
phungductung	0:e87aa4c49e95	113	==================================================
phungductung	0:e87aa4c49e95	114	[..]
phungductung	0:e87aa4c49e95	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
phungductung	0:e87aa4c49e95	116	(#) HAL_QSPI_Abort() function aborts any on-going operation and flushes the fifo.
phungductung	0:e87aa4c49e95	117	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
phungductung	0:e87aa4c49e95	118
phungductung	0:e87aa4c49e95	119	* Workarounds linked to Silicon Limitation *
phungductung	0:e87aa4c49e95	120	====================================================
phungductung	0:e87aa4c49e95	121	[..]
phungductung	0:e87aa4c49e95	122	(#) Workarounds Implemented inside HAL Driver
phungductung	0:e87aa4c49e95	123	(++) Extra data written in the FIFO at the end of a read transfer
phungductung	0:e87aa4c49e95	124
phungductung	0:e87aa4c49e95	125	@endverbatim
phungductung	0:e87aa4c49e95	126	******************************************************************************
phungductung	0:e87aa4c49e95	127	* @attention
phungductung	0:e87aa4c49e95	128	*
phungductung	0:e87aa4c49e95	129	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung	0:e87aa4c49e95	130	*
phungductung	0:e87aa4c49e95	131	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:e87aa4c49e95	132	* are permitted provided that the following conditions are met:
phungductung	0:e87aa4c49e95	133	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:e87aa4c49e95	134	* this list of conditions and the following disclaimer.
phungductung	0:e87aa4c49e95	135	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:e87aa4c49e95	136	* this list of conditions and the following disclaimer in the documentation
phungductung	0:e87aa4c49e95	137	* and/or other materials provided with the distribution.
phungductung	0:e87aa4c49e95	138	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:e87aa4c49e95	139	* may be used to endorse or promote products derived from this software
phungductung	0:e87aa4c49e95	140	* without specific prior written permission.
phungductung	0:e87aa4c49e95	141	*
phungductung	0:e87aa4c49e95	142	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:e87aa4c49e95	143	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:e87aa4c49e95	144	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:e87aa4c49e95	145	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:e87aa4c49e95	146	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:e87aa4c49e95	147	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:e87aa4c49e95	148	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:e87aa4c49e95	149	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:e87aa4c49e95	150	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:e87aa4c49e95	151	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:e87aa4c49e95	152	*
phungductung	0:e87aa4c49e95	153	******************************************************************************
phungductung	0:e87aa4c49e95	154	*/
phungductung	0:e87aa4c49e95	155
phungductung	0:e87aa4c49e95	156	/* Includes ------------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	157	#include "stm32f7xx_hal.h"
phungductung	0:e87aa4c49e95	158
phungductung	0:e87aa4c49e95	159	/** @addtogroup STM32F7xx_HAL_Driver
phungductung	0:e87aa4c49e95	160	* @{
phungductung	0:e87aa4c49e95	161	*/
phungductung	0:e87aa4c49e95	162
phungductung	0:e87aa4c49e95	163	/** @defgroup QSPI QSPI
phungductung	0:e87aa4c49e95	164	* @brief HAL QSPI module driver
phungductung	0:e87aa4c49e95	165	* @{
phungductung	0:e87aa4c49e95	166	*/
phungductung	0:e87aa4c49e95	167	#ifdef HAL_QSPI_MODULE_ENABLED
phungductung	0:e87aa4c49e95	168
phungductung	0:e87aa4c49e95	169	/* Private typedef -----------------------------------------------------------*/
phungductung	0:e87aa4c49e95	170	/* Private define ------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	171	/** @addtogroup QSPI_Private_Constants
phungductung	0:e87aa4c49e95	172	* @{
phungductung	0:e87aa4c49e95	173	*/
phungductung	0:e87aa4c49e95	174	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /!<Indirect write mode/
phungductung	0:e87aa4c49e95	175	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
phungductung	0:e87aa4c49e95	176	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
phungductung	0:e87aa4c49e95	177	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
phungductung	0:e87aa4c49e95	178	/**
phungductung	0:e87aa4c49e95	179	* @}
phungductung	0:e87aa4c49e95	180	*/
phungductung	0:e87aa4c49e95	181
phungductung	0:e87aa4c49e95	182	/* Private macro -------------------------------------------------------------*/
phungductung	0:e87aa4c49e95	183	/** @addtogroup QSPI_Private_Macros QSPI Private Macros
phungductung	0:e87aa4c49e95	184	* @{
phungductung	0:e87aa4c49e95	185	*/
phungductung	0:e87aa4c49e95	186	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
phungductung	0:e87aa4c49e95	187	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
phungductung	0:e87aa4c49e95	188	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
phungductung	0:e87aa4c49e95	189	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
phungductung	0:e87aa4c49e95	190	/**
phungductung	0:e87aa4c49e95	191	* @}
phungductung	0:e87aa4c49e95	192	*/
phungductung	0:e87aa4c49e95	193
phungductung	0:e87aa4c49e95	194	/* Private variables ---------------------------------------------------------*/
phungductung	0:e87aa4c49e95	195	/* Private function prototypes -----------------------------------------------*/
phungductung	0:e87aa4c49e95	196	/** @addtogroup QSPI_Private_Functions QSPI Private Functions
phungductung	0:e87aa4c49e95	197	* @{
phungductung	0:e87aa4c49e95	198	*/
phungductung	0:e87aa4c49e95	199	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	200	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	201	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	202	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	203	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
phungductung	0:e87aa4c49e95	204	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout);
phungductung	0:e87aa4c49e95	205	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
phungductung	0:e87aa4c49e95	206	/**
phungductung	0:e87aa4c49e95	207	* @}
phungductung	0:e87aa4c49e95	208	*/
phungductung	0:e87aa4c49e95	209
phungductung	0:e87aa4c49e95	210	/* Exported functions ---------------------------------------------------------*/
phungductung	0:e87aa4c49e95	211
phungductung	0:e87aa4c49e95	212	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
phungductung	0:e87aa4c49e95	213	* @{
phungductung	0:e87aa4c49e95	214	*/
phungductung	0:e87aa4c49e95	215
phungductung	0:e87aa4c49e95	216	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
phungductung	0:e87aa4c49e95	217	* @brief Initialization and Configuration functions
phungductung	0:e87aa4c49e95	218	*
phungductung	0:e87aa4c49e95	219	@verbatim
phungductung	0:e87aa4c49e95	220	===============================================================================
phungductung	0:e87aa4c49e95	221	##### Initialization and Configuration functions #####
phungductung	0:e87aa4c49e95	222	===============================================================================
phungductung	0:e87aa4c49e95	223	[..]
phungductung	0:e87aa4c49e95	224	This subsection provides a set of functions allowing to :
phungductung	0:e87aa4c49e95	225	(+) Initialize the QuadSPI.
phungductung	0:e87aa4c49e95	226	(+) De-initialize the QuadSPI.
phungductung	0:e87aa4c49e95	227
phungductung	0:e87aa4c49e95	228	@endverbatim
phungductung	0:e87aa4c49e95	229	* @{
phungductung	0:e87aa4c49e95	230	*/
phungductung	0:e87aa4c49e95	231
phungductung	0:e87aa4c49e95	232	/**
phungductung	0:e87aa4c49e95	233	* @brief Initializes the QSPI mode according to the specified parameters
phungductung	0:e87aa4c49e95	234	* in the QSPI_InitTypeDef and creates the associated handle.
phungductung	0:e87aa4c49e95	235	* @param hqspi: qspi handle
phungductung	0:e87aa4c49e95	236	* @retval HAL status
phungductung	0:e87aa4c49e95	237	*/
phungductung	0:e87aa4c49e95	238	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	239	{
phungductung	0:e87aa4c49e95	240	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	241
phungductung	0:e87aa4c49e95	242	/* Check the QSPI handle allocation */
phungductung	0:e87aa4c49e95	243	if(hqspi == NULL)
phungductung	0:e87aa4c49e95	244	{
phungductung	0:e87aa4c49e95	245	return HAL_ERROR;
phungductung	0:e87aa4c49e95	246	}
phungductung	0:e87aa4c49e95	247
phungductung	0:e87aa4c49e95	248	/* Check the parameters */
phungductung	0:e87aa4c49e95	249	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
phungductung	0:e87aa4c49e95	250	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
phungductung	0:e87aa4c49e95	251	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
phungductung	0:e87aa4c49e95	252	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
phungductung	0:e87aa4c49e95	253	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
phungductung	0:e87aa4c49e95	254	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
phungductung	0:e87aa4c49e95	255	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
phungductung	0:e87aa4c49e95	256	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
phungductung	0:e87aa4c49e95	257
phungductung	0:e87aa4c49e95	258	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
phungductung	0:e87aa4c49e95	259	{
phungductung	0:e87aa4c49e95	260	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
phungductung	0:e87aa4c49e95	261	}
phungductung	0:e87aa4c49e95	262
phungductung	0:e87aa4c49e95	263	/* Process locked */
phungductung	0:e87aa4c49e95	264	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	265
phungductung	0:e87aa4c49e95	266	if(hqspi->State == HAL_QSPI_STATE_RESET)
phungductung	0:e87aa4c49e95	267	{
phungductung	0:e87aa4c49e95	268	/* Allocate lock resource and initialize it */
phungductung	0:e87aa4c49e95	269	hqspi->Lock = HAL_UNLOCKED;
phungductung	0:e87aa4c49e95	270
phungductung	0:e87aa4c49e95	271	/* Init the low level hardware : GPIO, CLOCK */
phungductung	0:e87aa4c49e95	272	HAL_QSPI_MspInit(hqspi);
phungductung	0:e87aa4c49e95	273
phungductung	0:e87aa4c49e95	274	/* Configure the default timeout for the QSPI memory access */
phungductung	0:e87aa4c49e95	275	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
phungductung	0:e87aa4c49e95	276	}
phungductung	0:e87aa4c49e95	277
phungductung	0:e87aa4c49e95	278	/* Configure QSPI FIFO Threshold */
phungductung	0:e87aa4c49e95	279	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
phungductung	0:e87aa4c49e95	280
phungductung	0:e87aa4c49e95	281	/* Wait till BUSY flag reset */
phungductung	0:e87aa4c49e95	282	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
phungductung	0:e87aa4c49e95	283
phungductung	0:e87aa4c49e95	284	if(status == HAL_OK)
phungductung	0:e87aa4c49e95	285	{
phungductung	0:e87aa4c49e95	286
phungductung	0:e87aa4c49e95	287	/* Configure QSPI Clock Prescaler and Sample Shift */
phungductung	0:e87aa4c49e95	288	MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)\| hqspi->Init.SampleShifting \| hqspi->Init.FlashID\| hqspi->Init.DualFlash ));
phungductung	0:e87aa4c49e95	289
phungductung	0:e87aa4c49e95	290	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
phungductung	0:e87aa4c49e95	291	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
phungductung	0:e87aa4c49e95	292	((hqspi->Init.FlashSize << 16) \| hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
phungductung	0:e87aa4c49e95	293
phungductung	0:e87aa4c49e95	294	/* Enable the QSPI peripheral */
phungductung	0:e87aa4c49e95	295	__HAL_QSPI_ENABLE(hqspi);
phungductung	0:e87aa4c49e95	296
phungductung	0:e87aa4c49e95	297	/* Set QSPI error code to none */
phungductung	0:e87aa4c49e95	298	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	299
phungductung	0:e87aa4c49e95	300	/* Initialize the QSPI state */
phungductung	0:e87aa4c49e95	301	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	302	}
phungductung	0:e87aa4c49e95	303
phungductung	0:e87aa4c49e95	304	/* Release Lock */
phungductung	0:e87aa4c49e95	305	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	306
phungductung	0:e87aa4c49e95	307	/* Return function status */
phungductung	0:e87aa4c49e95	308	return status;
phungductung	0:e87aa4c49e95	309	}
phungductung	0:e87aa4c49e95	310
phungductung	0:e87aa4c49e95	311	/**
phungductung	0:e87aa4c49e95	312	* @brief DeInitializes the QSPI peripheral
phungductung	0:e87aa4c49e95	313	* @param hqspi: qspi handle
phungductung	0:e87aa4c49e95	314	* @retval HAL status
phungductung	0:e87aa4c49e95	315	*/
phungductung	0:e87aa4c49e95	316	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	317	{
phungductung	0:e87aa4c49e95	318	/* Check the QSPI handle allocation */
phungductung	0:e87aa4c49e95	319	if(hqspi == NULL)
phungductung	0:e87aa4c49e95	320	{
phungductung	0:e87aa4c49e95	321	return HAL_ERROR;
phungductung	0:e87aa4c49e95	322	}
phungductung	0:e87aa4c49e95	323
phungductung	0:e87aa4c49e95	324	/* Process locked */
phungductung	0:e87aa4c49e95	325	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	326
phungductung	0:e87aa4c49e95	327	/* Disable the QSPI Peripheral Clock */
phungductung	0:e87aa4c49e95	328	__HAL_QSPI_DISABLE(hqspi);
phungductung	0:e87aa4c49e95	329
phungductung	0:e87aa4c49e95	330	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
phungductung	0:e87aa4c49e95	331	HAL_QSPI_MspDeInit(hqspi);
phungductung	0:e87aa4c49e95	332
phungductung	0:e87aa4c49e95	333	/* Set QSPI error code to none */
phungductung	0:e87aa4c49e95	334	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	335
phungductung	0:e87aa4c49e95	336	/* Initialize the QSPI state */
phungductung	0:e87aa4c49e95	337	hqspi->State = HAL_QSPI_STATE_RESET;
phungductung	0:e87aa4c49e95	338
phungductung	0:e87aa4c49e95	339	/* Release Lock */
phungductung	0:e87aa4c49e95	340	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	341
phungductung	0:e87aa4c49e95	342	return HAL_OK;
phungductung	0:e87aa4c49e95	343	}
phungductung	0:e87aa4c49e95	344
phungductung	0:e87aa4c49e95	345	/**
phungductung	0:e87aa4c49e95	346	* @brief QSPI MSP Init
phungductung	0:e87aa4c49e95	347	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	348	* @retval None
phungductung	0:e87aa4c49e95	349	*/
phungductung	0:e87aa4c49e95	350	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	351	{
phungductung	0:e87aa4c49e95	352	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	353	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	354
phungductung	0:e87aa4c49e95	355	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	356	the HAL_QSPI_MspInit can be implemented in the user file
phungductung	0:e87aa4c49e95	357	*/
phungductung	0:e87aa4c49e95	358	}
phungductung	0:e87aa4c49e95	359
phungductung	0:e87aa4c49e95	360	/**
phungductung	0:e87aa4c49e95	361	* @brief QSPI MSP DeInit
phungductung	0:e87aa4c49e95	362	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	363	* @retval None
phungductung	0:e87aa4c49e95	364	*/
phungductung	0:e87aa4c49e95	365	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	366	{
phungductung	0:e87aa4c49e95	367	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	368	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	369
phungductung	0:e87aa4c49e95	370	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	371	the HAL_QSPI_MspDeInit can be implemented in the user file
phungductung	0:e87aa4c49e95	372	*/
phungductung	0:e87aa4c49e95	373	}
phungductung	0:e87aa4c49e95	374
phungductung	0:e87aa4c49e95	375	/**
phungductung	0:e87aa4c49e95	376	* @}
phungductung	0:e87aa4c49e95	377	*/
phungductung	0:e87aa4c49e95	378
phungductung	0:e87aa4c49e95	379	/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
phungductung	0:e87aa4c49e95	380	* @brief QSPI Transmit/Receive functions
phungductung	0:e87aa4c49e95	381	*
phungductung	0:e87aa4c49e95	382	@verbatim
phungductung	0:e87aa4c49e95	383	===============================================================================
phungductung	0:e87aa4c49e95	384	##### IO operation functions #####
phungductung	0:e87aa4c49e95	385	===============================================================================
phungductung	0:e87aa4c49e95	386	[..]
phungductung	0:e87aa4c49e95	387	This subsection provides a set of functions allowing to :
phungductung	0:e87aa4c49e95	388	(+) Handle the interrupts.
phungductung	0:e87aa4c49e95	389	(+) Handle the command sequence.
phungductung	0:e87aa4c49e95	390	(+) Transmit data in blocking, interrupt or DMA mode.
phungductung	0:e87aa4c49e95	391	(+) Receive data in blocking, interrupt or DMA mode.
phungductung	0:e87aa4c49e95	392	(+) Manage the auto-polling functional mode.
phungductung	0:e87aa4c49e95	393	(+) Manage the memory-mapped functional mode.
phungductung	0:e87aa4c49e95	394
phungductung	0:e87aa4c49e95	395	@endverbatim
phungductung	0:e87aa4c49e95	396	* @{
phungductung	0:e87aa4c49e95	397	*/
phungductung	0:e87aa4c49e95	398
phungductung	0:e87aa4c49e95	399	/**
phungductung	0:e87aa4c49e95	400	* @brief This function handles QSPI interrupt request.
phungductung	0:e87aa4c49e95	401	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	402	* @retval None.
phungductung	0:e87aa4c49e95	403	*/
phungductung	0:e87aa4c49e95	404	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	405	{
phungductung	0:e87aa4c49e95	406	__IO uint32_t *data_reg;
phungductung	0:e87aa4c49e95	407	uint32_t flag = 0, itsource = 0;
phungductung	0:e87aa4c49e95	408
phungductung	0:e87aa4c49e95	409	/* QSPI FIFO Threshold interrupt occurred ----------------------------------*/
phungductung	0:e87aa4c49e95	410	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT);
phungductung	0:e87aa4c49e95	411	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_FT);
phungductung	0:e87aa4c49e95	412
phungductung	0:e87aa4c49e95	413	if((flag != RESET) && (itsource != RESET))
phungductung	0:e87aa4c49e95	414	{
phungductung	0:e87aa4c49e95	415	data_reg = &hqspi->Instance->DR;
phungductung	0:e87aa4c49e95	416
phungductung	0:e87aa4c49e95	417	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
phungductung	0:e87aa4c49e95	418	{
phungductung	0:e87aa4c49e95	419	/* Transmission process */
phungductung	0:e87aa4c49e95	420	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
phungductung	0:e87aa4c49e95	421	{
phungductung	0:e87aa4c49e95	422	if (hqspi->TxXferCount > 0)
phungductung	0:e87aa4c49e95	423	{
phungductung	0:e87aa4c49e95	424	/* Fill the FIFO until it is full */
phungductung	0:e87aa4c49e95	425	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
phungductung	0:e87aa4c49e95	426	hqspi->TxXferCount--;
phungductung	0:e87aa4c49e95	427	}
phungductung	0:e87aa4c49e95	428	else
phungductung	0:e87aa4c49e95	429	{
phungductung	0:e87aa4c49e95	430	/* No more data available for the transfer */
phungductung	0:e87aa4c49e95	431	break;
phungductung	0:e87aa4c49e95	432	}
phungductung	0:e87aa4c49e95	433	}
phungductung	0:e87aa4c49e95	434	}
phungductung	0:e87aa4c49e95	435	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
phungductung	0:e87aa4c49e95	436	{
phungductung	0:e87aa4c49e95	437	/* Receiving Process */
phungductung	0:e87aa4c49e95	438	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
phungductung	0:e87aa4c49e95	439	{
phungductung	0:e87aa4c49e95	440	if (hqspi->RxXferCount > 0)
phungductung	0:e87aa4c49e95	441	{
phungductung	0:e87aa4c49e95	442	/* Read the FIFO until it is empty */
phungductung	0:e87aa4c49e95	443	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
phungductung	0:e87aa4c49e95	444	hqspi->RxXferCount--;
phungductung	0:e87aa4c49e95	445	}
phungductung	0:e87aa4c49e95	446	else
phungductung	0:e87aa4c49e95	447	{
phungductung	0:e87aa4c49e95	448	/* All data have been received for the transfer */
phungductung	0:e87aa4c49e95	449	break;
phungductung	0:e87aa4c49e95	450	}
phungductung	0:e87aa4c49e95	451	}
phungductung	0:e87aa4c49e95	452	}
phungductung	0:e87aa4c49e95	453
phungductung	0:e87aa4c49e95	454	/* FIFO Threshold callback */
phungductung	0:e87aa4c49e95	455	HAL_QSPI_FifoThresholdCallback(hqspi);
phungductung	0:e87aa4c49e95	456	}
phungductung	0:e87aa4c49e95	457
phungductung	0:e87aa4c49e95	458	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
phungductung	0:e87aa4c49e95	459	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	460	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TC);
phungductung	0:e87aa4c49e95	461
phungductung	0:e87aa4c49e95	462	if((flag != RESET) && (itsource != RESET))
phungductung	0:e87aa4c49e95	463	{
phungductung	0:e87aa4c49e95	464	/* Clear interrupt */
phungductung	0:e87aa4c49e95	465	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	466
phungductung	0:e87aa4c49e95	467	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
phungductung	0:e87aa4c49e95	468	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
phungductung	0:e87aa4c49e95	469
phungductung	0:e87aa4c49e95	470	/* Transfer complete callback */
phungductung	0:e87aa4c49e95	471	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
phungductung	0:e87aa4c49e95	472	{
phungductung	0:e87aa4c49e95	473	/* Clear Busy bit */
phungductung	0:e87aa4c49e95	474	HAL_QSPI_Abort(hqspi);
phungductung	0:e87aa4c49e95	475
phungductung	0:e87aa4c49e95	476	/* TX Complete callback */
phungductung	0:e87aa4c49e95	477	HAL_QSPI_TxCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	478	}
phungductung	0:e87aa4c49e95	479	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
phungductung	0:e87aa4c49e95	480	{
phungductung	0:e87aa4c49e95	481	data_reg = &hqspi->Instance->DR;
phungductung	0:e87aa4c49e95	482	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
phungductung	0:e87aa4c49e95	483	{
phungductung	0:e87aa4c49e95	484	if (hqspi->RxXferCount > 0)
phungductung	0:e87aa4c49e95	485	{
phungductung	0:e87aa4c49e95	486	/* Read the last data received in the FIFO until it is empty */
phungductung	0:e87aa4c49e95	487	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
phungductung	0:e87aa4c49e95	488	hqspi->RxXferCount--;
phungductung	0:e87aa4c49e95	489	}
phungductung	0:e87aa4c49e95	490	else
phungductung	0:e87aa4c49e95	491	{
phungductung	0:e87aa4c49e95	492	/* All data have been received for the transfer */
phungductung	0:e87aa4c49e95	493	break;
phungductung	0:e87aa4c49e95	494	}
phungductung	0:e87aa4c49e95	495	}
phungductung	0:e87aa4c49e95	496
phungductung	0:e87aa4c49e95	497	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
phungductung	0:e87aa4c49e95	498	HAL_QSPI_Abort(hqspi);
phungductung	0:e87aa4c49e95	499
phungductung	0:e87aa4c49e95	500	/* RX Complete callback */
phungductung	0:e87aa4c49e95	501	HAL_QSPI_RxCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	502	}
phungductung	0:e87aa4c49e95	503	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
phungductung	0:e87aa4c49e95	504	{
phungductung	0:e87aa4c49e95	505	/* Command Complete callback */
phungductung	0:e87aa4c49e95	506	HAL_QSPI_CmdCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	507	}
phungductung	0:e87aa4c49e95	508
phungductung	0:e87aa4c49e95	509	/* Change state of QSPI */
phungductung	0:e87aa4c49e95	510	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	511	}
phungductung	0:e87aa4c49e95	512
phungductung	0:e87aa4c49e95	513	/* QSPI Status Match interrupt occurred ------------------------------------*/
phungductung	0:e87aa4c49e95	514	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_SM);
phungductung	0:e87aa4c49e95	515	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_SM);
phungductung	0:e87aa4c49e95	516
phungductung	0:e87aa4c49e95	517	if((flag != RESET) && (itsource != RESET))
phungductung	0:e87aa4c49e95	518	{
phungductung	0:e87aa4c49e95	519	/* Clear interrupt */
phungductung	0:e87aa4c49e95	520	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
phungductung	0:e87aa4c49e95	521
phungductung	0:e87aa4c49e95	522	/* Check if the automatic poll mode stop is activated */
phungductung	0:e87aa4c49e95	523	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
phungductung	0:e87aa4c49e95	524	{
phungductung	0:e87aa4c49e95	525	/* Disable the QSPI FIFO Threshold, Transfer Error and Status Match Interrupts */
phungductung	0:e87aa4c49e95	526	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TE);
phungductung	0:e87aa4c49e95	527
phungductung	0:e87aa4c49e95	528	/* Change state of QSPI */
phungductung	0:e87aa4c49e95	529	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	530	}
phungductung	0:e87aa4c49e95	531
phungductung	0:e87aa4c49e95	532	/* Status match callback */
phungductung	0:e87aa4c49e95	533	HAL_QSPI_StatusMatchCallback(hqspi);
phungductung	0:e87aa4c49e95	534	}
phungductung	0:e87aa4c49e95	535
phungductung	0:e87aa4c49e95	536	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
phungductung	0:e87aa4c49e95	537	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TE);
phungductung	0:e87aa4c49e95	538	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TE);
phungductung	0:e87aa4c49e95	539
phungductung	0:e87aa4c49e95	540	if((flag != RESET) && (itsource != RESET))
phungductung	0:e87aa4c49e95	541	{
phungductung	0:e87aa4c49e95	542	/* Clear interrupt */
phungductung	0:e87aa4c49e95	543	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE);
phungductung	0:e87aa4c49e95	544
phungductung	0:e87aa4c49e95	545	/* Disable all the QSPI Interrupts */
phungductung	0:e87aa4c49e95	546	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
phungductung	0:e87aa4c49e95	547
phungductung	0:e87aa4c49e95	548	/* Set error code */
phungductung	0:e87aa4c49e95	549	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
phungductung	0:e87aa4c49e95	550
phungductung	0:e87aa4c49e95	551	/* Change state of QSPI */
phungductung	0:e87aa4c49e95	552	hqspi->State = HAL_QSPI_STATE_ERROR;
phungductung	0:e87aa4c49e95	553
phungductung	0:e87aa4c49e95	554	/* Error callback */
phungductung	0:e87aa4c49e95	555	HAL_QSPI_ErrorCallback(hqspi);
phungductung	0:e87aa4c49e95	556	}
phungductung	0:e87aa4c49e95	557
phungductung	0:e87aa4c49e95	558	/* QSPI Time out interrupt occurred -----------------------------------------*/
phungductung	0:e87aa4c49e95	559	flag = __HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_TO);
phungductung	0:e87aa4c49e95	560	itsource = __HAL_QSPI_GET_IT_SOURCE(hqspi, QSPI_IT_TO);
phungductung	0:e87aa4c49e95	561
phungductung	0:e87aa4c49e95	562	if((flag != RESET) && (itsource != RESET))
phungductung	0:e87aa4c49e95	563	{
phungductung	0:e87aa4c49e95	564	/* Clear interrupt */
phungductung	0:e87aa4c49e95	565	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
phungductung	0:e87aa4c49e95	566
phungductung	0:e87aa4c49e95	567	/* Time out callback */
phungductung	0:e87aa4c49e95	568	HAL_QSPI_TimeOutCallback(hqspi);
phungductung	0:e87aa4c49e95	569	}
phungductung	0:e87aa4c49e95	570	}
phungductung	0:e87aa4c49e95	571
phungductung	0:e87aa4c49e95	572	/**
phungductung	0:e87aa4c49e95	573	* @brief Sets the command configuration.
phungductung	0:e87aa4c49e95	574	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	575	* @param cmd : structure that contains the command configuration information
phungductung	0:e87aa4c49e95	576	* @param Timeout : Time out duration
phungductung	0:e87aa4c49e95	577	* @note This function is used only in Indirect Read or Write Modes
phungductung	0:e87aa4c49e95	578	* @retval HAL status
phungductung	0:e87aa4c49e95	579	*/
phungductung	0:e87aa4c49e95	580	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
phungductung	0:e87aa4c49e95	581	{
phungductung	0:e87aa4c49e95	582	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	583
phungductung	0:e87aa4c49e95	584	/* Check the parameters */
phungductung	0:e87aa4c49e95	585	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
phungductung	0:e87aa4c49e95	586	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
phungductung	0:e87aa4c49e95	587	{
phungductung	0:e87aa4c49e95	588	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
phungductung	0:e87aa4c49e95	589	}
phungductung	0:e87aa4c49e95	590
phungductung	0:e87aa4c49e95	591	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
phungductung	0:e87aa4c49e95	592	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	593	{
phungductung	0:e87aa4c49e95	594	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
phungductung	0:e87aa4c49e95	595	}
phungductung	0:e87aa4c49e95	596
phungductung	0:e87aa4c49e95	597	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
phungductung	0:e87aa4c49e95	598	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	599	{
phungductung	0:e87aa4c49e95	600	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
phungductung	0:e87aa4c49e95	601	}
phungductung	0:e87aa4c49e95	602
phungductung	0:e87aa4c49e95	603	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
phungductung	0:e87aa4c49e95	604	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
phungductung	0:e87aa4c49e95	605
phungductung	0:e87aa4c49e95	606	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
phungductung	0:e87aa4c49e95	607	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
phungductung	0:e87aa4c49e95	608	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
phungductung	0:e87aa4c49e95	609
phungductung	0:e87aa4c49e95	610	/* Process locked */
phungductung	0:e87aa4c49e95	611	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	612
phungductung	0:e87aa4c49e95	613	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	614	{
phungductung	0:e87aa4c49e95	615	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	616
phungductung	0:e87aa4c49e95	617	/* Update QSPI state */
phungductung	0:e87aa4c49e95	618	hqspi->State = HAL_QSPI_STATE_BUSY;
phungductung	0:e87aa4c49e95	619
phungductung	0:e87aa4c49e95	620	/* Wait till BUSY flag reset */
phungductung	0:e87aa4c49e95	621	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
phungductung	0:e87aa4c49e95	622
phungductung	0:e87aa4c49e95	623	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	624	{
phungductung	0:e87aa4c49e95	625	/* Call the configuration function */
phungductung	0:e87aa4c49e95	626	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
phungductung	0:e87aa4c49e95	627
phungductung	0:e87aa4c49e95	628	if (cmd->DataMode == QSPI_DATA_NONE)
phungductung	0:e87aa4c49e95	629	{
phungductung	0:e87aa4c49e95	630	/* When there is no data phase, the transfer start as soon as the configuration is done
phungductung	0:e87aa4c49e95	631	so wait until TC flag is set to go back in idle state */
phungductung	0:e87aa4c49e95	632	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	633	{
phungductung	0:e87aa4c49e95	634	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	635	}
phungductung	0:e87aa4c49e95	636	else
phungductung	0:e87aa4c49e95	637	{
phungductung	0:e87aa4c49e95	638	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	639
phungductung	0:e87aa4c49e95	640	/* Update QSPI state */
phungductung	0:e87aa4c49e95	641	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	642	}
phungductung	0:e87aa4c49e95	643
phungductung	0:e87aa4c49e95	644	}
phungductung	0:e87aa4c49e95	645	else
phungductung	0:e87aa4c49e95	646	{
phungductung	0:e87aa4c49e95	647	/* Update QSPI state */
phungductung	0:e87aa4c49e95	648	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	649	}
phungductung	0:e87aa4c49e95	650	}
phungductung	0:e87aa4c49e95	651	}
phungductung	0:e87aa4c49e95	652	else
phungductung	0:e87aa4c49e95	653	{
phungductung	0:e87aa4c49e95	654	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	655	}
phungductung	0:e87aa4c49e95	656
phungductung	0:e87aa4c49e95	657	/* Process unlocked */
phungductung	0:e87aa4c49e95	658	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	659
phungductung	0:e87aa4c49e95	660	/* Return function status */
phungductung	0:e87aa4c49e95	661	return status;
phungductung	0:e87aa4c49e95	662	}
phungductung	0:e87aa4c49e95	663
phungductung	0:e87aa4c49e95	664	/**
phungductung	0:e87aa4c49e95	665	* @brief Sets the command configuration in interrupt mode.
phungductung	0:e87aa4c49e95	666	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	667	* @param cmd : structure that contains the command configuration information
phungductung	0:e87aa4c49e95	668	* @note This function is used only in Indirect Read or Write Modes
phungductung	0:e87aa4c49e95	669	* @retval HAL status
phungductung	0:e87aa4c49e95	670	*/
phungductung	0:e87aa4c49e95	671	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
phungductung	0:e87aa4c49e95	672	{
phungductung	0:e87aa4c49e95	673	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	674
phungductung	0:e87aa4c49e95	675	/* Check the parameters */
phungductung	0:e87aa4c49e95	676	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
phungductung	0:e87aa4c49e95	677	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
phungductung	0:e87aa4c49e95	678	{
phungductung	0:e87aa4c49e95	679	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
phungductung	0:e87aa4c49e95	680	}
phungductung	0:e87aa4c49e95	681
phungductung	0:e87aa4c49e95	682	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
phungductung	0:e87aa4c49e95	683	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	684	{
phungductung	0:e87aa4c49e95	685	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
phungductung	0:e87aa4c49e95	686	}
phungductung	0:e87aa4c49e95	687
phungductung	0:e87aa4c49e95	688	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
phungductung	0:e87aa4c49e95	689	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	690	{
phungductung	0:e87aa4c49e95	691	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
phungductung	0:e87aa4c49e95	692	}
phungductung	0:e87aa4c49e95	693
phungductung	0:e87aa4c49e95	694	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
phungductung	0:e87aa4c49e95	695	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
phungductung	0:e87aa4c49e95	696
phungductung	0:e87aa4c49e95	697	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
phungductung	0:e87aa4c49e95	698	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
phungductung	0:e87aa4c49e95	699	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
phungductung	0:e87aa4c49e95	700
phungductung	0:e87aa4c49e95	701	/* Process locked */
phungductung	0:e87aa4c49e95	702	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	703
phungductung	0:e87aa4c49e95	704	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	705	{
phungductung	0:e87aa4c49e95	706	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	707
phungductung	0:e87aa4c49e95	708	/* Update QSPI state */
phungductung	0:e87aa4c49e95	709	hqspi->State = HAL_QSPI_STATE_BUSY;
phungductung	0:e87aa4c49e95	710
phungductung	0:e87aa4c49e95	711	/* Wait till BUSY flag reset */
phungductung	0:e87aa4c49e95	712	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
phungductung	0:e87aa4c49e95	713
phungductung	0:e87aa4c49e95	714	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	715	{
phungductung	0:e87aa4c49e95	716	if (cmd->DataMode == QSPI_DATA_NONE)
phungductung	0:e87aa4c49e95	717	{
phungductung	0:e87aa4c49e95	718	/* When there is no data phase, the transfer start as soon as the configuration is done
phungductung	0:e87aa4c49e95	719	so activate TC and TE interrupts */
phungductung	0:e87aa4c49e95	720	/* Enable the QSPI Transfer Error Interrupt */
phungductung	0:e87aa4c49e95	721	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
phungductung	0:e87aa4c49e95	722	}
phungductung	0:e87aa4c49e95	723
phungductung	0:e87aa4c49e95	724	/* Call the configuration function */
phungductung	0:e87aa4c49e95	725	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
phungductung	0:e87aa4c49e95	726
phungductung	0:e87aa4c49e95	727	if (cmd->DataMode != QSPI_DATA_NONE)
phungductung	0:e87aa4c49e95	728	{
phungductung	0:e87aa4c49e95	729	/* Update QSPI state */
phungductung	0:e87aa4c49e95	730	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	731	}
phungductung	0:e87aa4c49e95	732	}
phungductung	0:e87aa4c49e95	733	}
phungductung	0:e87aa4c49e95	734	else
phungductung	0:e87aa4c49e95	735	{
phungductung	0:e87aa4c49e95	736	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	737	}
phungductung	0:e87aa4c49e95	738
phungductung	0:e87aa4c49e95	739	/* Process unlocked */
phungductung	0:e87aa4c49e95	740	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	741
phungductung	0:e87aa4c49e95	742	/* Return function status */
phungductung	0:e87aa4c49e95	743	return status;
phungductung	0:e87aa4c49e95	744	}
phungductung	0:e87aa4c49e95	745
phungductung	0:e87aa4c49e95	746	/**
phungductung	0:e87aa4c49e95	747	* @brief Transmit an amount of data in blocking mode.
phungductung	0:e87aa4c49e95	748	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	749	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	750	* @param Timeout : Time out duration
phungductung	0:e87aa4c49e95	751	* @note This function is used only in Indirect Write Mode
phungductung	0:e87aa4c49e95	752	* @retval HAL status
phungductung	0:e87aa4c49e95	753	*/
phungductung	0:e87aa4c49e95	754	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
phungductung	0:e87aa4c49e95	755	{
phungductung	0:e87aa4c49e95	756	HAL_StatusTypeDef status = HAL_OK;
phungductung	0:e87aa4c49e95	757	__IO uint32_t *data_reg = &hqspi->Instance->DR;
phungductung	0:e87aa4c49e95	758
phungductung	0:e87aa4c49e95	759	/* Process locked */
phungductung	0:e87aa4c49e95	760	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	761
phungductung	0:e87aa4c49e95	762	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	763	{
phungductung	0:e87aa4c49e95	764	if(pData != NULL )
phungductung	0:e87aa4c49e95	765	{
phungductung	0:e87aa4c49e95	766	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	767
phungductung	0:e87aa4c49e95	768	/* Update state */
phungductung	0:e87aa4c49e95	769	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
phungductung	0:e87aa4c49e95	770
phungductung	0:e87aa4c49e95	771	/* Configure counters and size of the handle */
phungductung	0:e87aa4c49e95	772	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	773	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	774	hqspi->pTxBuffPtr = pData;
phungductung	0:e87aa4c49e95	775
phungductung	0:e87aa4c49e95	776	/* Configure QSPI: CCR register with functional as indirect write */
phungductung	0:e87aa4c49e95	777	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
phungductung	0:e87aa4c49e95	778
phungductung	0:e87aa4c49e95	779	while(hqspi->TxXferCount > 0)
phungductung	0:e87aa4c49e95	780	{
phungductung	0:e87aa4c49e95	781	/* Wait until FT flag is set to send data */
phungductung	0:e87aa4c49e95	782	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	783	{
phungductung	0:e87aa4c49e95	784	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	785	break;
phungductung	0:e87aa4c49e95	786	}
phungductung	0:e87aa4c49e95	787
phungductung	0:e87aa4c49e95	788	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
phungductung	0:e87aa4c49e95	789	hqspi->TxXferCount--;
phungductung	0:e87aa4c49e95	790	}
phungductung	0:e87aa4c49e95	791
phungductung	0:e87aa4c49e95	792	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	793	{
phungductung	0:e87aa4c49e95	794	/* Wait until TC flag is set to go back in idle state */
phungductung	0:e87aa4c49e95	795	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	796	{
phungductung	0:e87aa4c49e95	797	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	798	}
phungductung	0:e87aa4c49e95	799	else
phungductung	0:e87aa4c49e95	800	{
phungductung	0:e87aa4c49e95	801	/* Clear Transfer Complete bit */
phungductung	0:e87aa4c49e95	802	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	803
phungductung	0:e87aa4c49e95	804	/* Clear Busy bit */
phungductung	0:e87aa4c49e95	805	status = HAL_QSPI_Abort(hqspi);
phungductung	0:e87aa4c49e95	806	}
phungductung	0:e87aa4c49e95	807	}
phungductung	0:e87aa4c49e95	808
phungductung	0:e87aa4c49e95	809	/* Update QSPI state */
phungductung	0:e87aa4c49e95	810	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	811	}
phungductung	0:e87aa4c49e95	812	else
phungductung	0:e87aa4c49e95	813	{
phungductung	0:e87aa4c49e95	814	status = HAL_ERROR;
phungductung	0:e87aa4c49e95	815	}
phungductung	0:e87aa4c49e95	816	}
phungductung	0:e87aa4c49e95	817	else
phungductung	0:e87aa4c49e95	818	{
phungductung	0:e87aa4c49e95	819	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	820	}
phungductung	0:e87aa4c49e95	821
phungductung	0:e87aa4c49e95	822	/* Process unlocked */
phungductung	0:e87aa4c49e95	823	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	824
phungductung	0:e87aa4c49e95	825	return status;
phungductung	0:e87aa4c49e95	826	}
phungductung	0:e87aa4c49e95	827
phungductung	0:e87aa4c49e95	828
phungductung	0:e87aa4c49e95	829	/**
phungductung	0:e87aa4c49e95	830	* @brief Receive an amount of data in blocking mode
phungductung	0:e87aa4c49e95	831	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	832	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	833	* @param Timeout : Time out duration
phungductung	0:e87aa4c49e95	834	* @note This function is used only in Indirect Read Mode
phungductung	0:e87aa4c49e95	835	* @retval HAL status
phungductung	0:e87aa4c49e95	836	*/
phungductung	0:e87aa4c49e95	837	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
phungductung	0:e87aa4c49e95	838	{
phungductung	0:e87aa4c49e95	839	HAL_StatusTypeDef status = HAL_OK;
phungductung	0:e87aa4c49e95	840	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
phungductung	0:e87aa4c49e95	841	__IO uint32_t *data_reg = &hqspi->Instance->DR;
phungductung	0:e87aa4c49e95	842
phungductung	0:e87aa4c49e95	843	/* Process locked */
phungductung	0:e87aa4c49e95	844	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	845
phungductung	0:e87aa4c49e95	846	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	847	{
phungductung	0:e87aa4c49e95	848	if(pData != NULL )
phungductung	0:e87aa4c49e95	849	{
phungductung	0:e87aa4c49e95	850	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	851
phungductung	0:e87aa4c49e95	852	/* Update state */
phungductung	0:e87aa4c49e95	853	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
phungductung	0:e87aa4c49e95	854
phungductung	0:e87aa4c49e95	855	/* Configure counters and size of the handle */
phungductung	0:e87aa4c49e95	856	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	857	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	858	hqspi->pRxBuffPtr = pData;
phungductung	0:e87aa4c49e95	859
phungductung	0:e87aa4c49e95	860	/* Configure QSPI: CCR register with functional as indirect read */
phungductung	0:e87aa4c49e95	861	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
phungductung	0:e87aa4c49e95	862
phungductung	0:e87aa4c49e95	863	/* Start the transfer by re-writing the address in AR register */
phungductung	0:e87aa4c49e95	864	WRITE_REG(hqspi->Instance->AR, addr_reg);
phungductung	0:e87aa4c49e95	865
phungductung	0:e87aa4c49e95	866	while(hqspi->RxXferCount > 0)
phungductung	0:e87aa4c49e95	867	{
phungductung	0:e87aa4c49e95	868	/* Wait until FT or TC flag is set to read received data */
phungductung	0:e87aa4c49e95	869	if(QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	870	{
phungductung	0:e87aa4c49e95	871	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	872	break;
phungductung	0:e87aa4c49e95	873	}
phungductung	0:e87aa4c49e95	874
phungductung	0:e87aa4c49e95	875	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
phungductung	0:e87aa4c49e95	876	hqspi->RxXferCount--;
phungductung	0:e87aa4c49e95	877	}
phungductung	0:e87aa4c49e95	878
phungductung	0:e87aa4c49e95	879	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	880	{
phungductung	0:e87aa4c49e95	881	/* Wait until TC flag is set to go back in idle state */
phungductung	0:e87aa4c49e95	882	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	883	{
phungductung	0:e87aa4c49e95	884	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	885	}
phungductung	0:e87aa4c49e95	886	else
phungductung	0:e87aa4c49e95	887	{
phungductung	0:e87aa4c49e95	888	/* Clear Transfer Complete bit */
phungductung	0:e87aa4c49e95	889	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	890
phungductung	0:e87aa4c49e95	891	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
phungductung	0:e87aa4c49e95	892	status = HAL_QSPI_Abort(hqspi);
phungductung	0:e87aa4c49e95	893	}
phungductung	0:e87aa4c49e95	894	}
phungductung	0:e87aa4c49e95	895
phungductung	0:e87aa4c49e95	896	/* Update QSPI state */
phungductung	0:e87aa4c49e95	897	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	898	}
phungductung	0:e87aa4c49e95	899	else
phungductung	0:e87aa4c49e95	900	{
phungductung	0:e87aa4c49e95	901	status = HAL_ERROR;
phungductung	0:e87aa4c49e95	902	}
phungductung	0:e87aa4c49e95	903	}
phungductung	0:e87aa4c49e95	904	else
phungductung	0:e87aa4c49e95	905	{
phungductung	0:e87aa4c49e95	906	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	907	}
phungductung	0:e87aa4c49e95	908
phungductung	0:e87aa4c49e95	909	/* Process unlocked */
phungductung	0:e87aa4c49e95	910	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	911
phungductung	0:e87aa4c49e95	912	return status;
phungductung	0:e87aa4c49e95	913	}
phungductung	0:e87aa4c49e95	914
phungductung	0:e87aa4c49e95	915	/**
phungductung	0:e87aa4c49e95	916	* @brief Send an amount of data in interrupt mode
phungductung	0:e87aa4c49e95	917	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	918	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	919	* @note This function is used only in Indirect Write Mode
phungductung	0:e87aa4c49e95	920	* @retval HAL status
phungductung	0:e87aa4c49e95	921	*/
phungductung	0:e87aa4c49e95	922	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
phungductung	0:e87aa4c49e95	923	{
phungductung	0:e87aa4c49e95	924	HAL_StatusTypeDef status = HAL_OK;
phungductung	0:e87aa4c49e95	925
phungductung	0:e87aa4c49e95	926	/* Process locked */
phungductung	0:e87aa4c49e95	927	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	928
phungductung	0:e87aa4c49e95	929	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	930	{
phungductung	0:e87aa4c49e95	931	if(pData != NULL )
phungductung	0:e87aa4c49e95	932	{
phungductung	0:e87aa4c49e95	933	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	934
phungductung	0:e87aa4c49e95	935	/* Update state */
phungductung	0:e87aa4c49e95	936	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
phungductung	0:e87aa4c49e95	937
phungductung	0:e87aa4c49e95	938	/* Configure counters and size of the handle */
phungductung	0:e87aa4c49e95	939	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	940	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	941	hqspi->pTxBuffPtr = pData;
phungductung	0:e87aa4c49e95	942
phungductung	0:e87aa4c49e95	943	/* Configure QSPI: CCR register with functional as indirect write */
phungductung	0:e87aa4c49e95	944	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
phungductung	0:e87aa4c49e95	945
phungductung	0:e87aa4c49e95	946	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
phungductung	0:e87aa4c49e95	947	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
phungductung	0:e87aa4c49e95	948
phungductung	0:e87aa4c49e95	949	}
phungductung	0:e87aa4c49e95	950	else
phungductung	0:e87aa4c49e95	951	{
phungductung	0:e87aa4c49e95	952	status = HAL_ERROR;
phungductung	0:e87aa4c49e95	953	}
phungductung	0:e87aa4c49e95	954	}
phungductung	0:e87aa4c49e95	955	else
phungductung	0:e87aa4c49e95	956	{
phungductung	0:e87aa4c49e95	957	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	958	}
phungductung	0:e87aa4c49e95	959
phungductung	0:e87aa4c49e95	960	/* Process unlocked */
phungductung	0:e87aa4c49e95	961	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	962
phungductung	0:e87aa4c49e95	963	return status;
phungductung	0:e87aa4c49e95	964	}
phungductung	0:e87aa4c49e95	965
phungductung	0:e87aa4c49e95	966	/**
phungductung	0:e87aa4c49e95	967	* @brief Receive an amount of data in no-blocking mode with Interrupt
phungductung	0:e87aa4c49e95	968	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	969	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	970	* @note This function is used only in Indirect Read Mode
phungductung	0:e87aa4c49e95	971	* @retval HAL status
phungductung	0:e87aa4c49e95	972	*/
phungductung	0:e87aa4c49e95	973	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
phungductung	0:e87aa4c49e95	974	{
phungductung	0:e87aa4c49e95	975	HAL_StatusTypeDef status = HAL_OK;
phungductung	0:e87aa4c49e95	976	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
phungductung	0:e87aa4c49e95	977
phungductung	0:e87aa4c49e95	978	/* Process locked */
phungductung	0:e87aa4c49e95	979	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	980
phungductung	0:e87aa4c49e95	981	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	982	{
phungductung	0:e87aa4c49e95	983	if(pData != NULL )
phungductung	0:e87aa4c49e95	984	{
phungductung	0:e87aa4c49e95	985	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	986
phungductung	0:e87aa4c49e95	987	/* Update state */
phungductung	0:e87aa4c49e95	988	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
phungductung	0:e87aa4c49e95	989
phungductung	0:e87aa4c49e95	990	/* Configure counters and size of the handle */
phungductung	0:e87aa4c49e95	991	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	992	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	993	hqspi->pRxBuffPtr = pData;
phungductung	0:e87aa4c49e95	994
phungductung	0:e87aa4c49e95	995	/* Configure QSPI: CCR register with functional as indirect read */
phungductung	0:e87aa4c49e95	996	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
phungductung	0:e87aa4c49e95	997
phungductung	0:e87aa4c49e95	998	/* Start the transfer by re-writing the address in AR register */
phungductung	0:e87aa4c49e95	999	WRITE_REG(hqspi->Instance->AR, addr_reg);
phungductung	0:e87aa4c49e95	1000
phungductung	0:e87aa4c49e95	1001	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
phungductung	0:e87aa4c49e95	1002	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
phungductung	0:e87aa4c49e95	1003	}
phungductung	0:e87aa4c49e95	1004	else
phungductung	0:e87aa4c49e95	1005	{
phungductung	0:e87aa4c49e95	1006	status = HAL_ERROR;
phungductung	0:e87aa4c49e95	1007	}
phungductung	0:e87aa4c49e95	1008	}
phungductung	0:e87aa4c49e95	1009	else
phungductung	0:e87aa4c49e95	1010	{
phungductung	0:e87aa4c49e95	1011	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	1012	}
phungductung	0:e87aa4c49e95	1013
phungductung	0:e87aa4c49e95	1014	/* Process unlocked */
phungductung	0:e87aa4c49e95	1015	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	1016
phungductung	0:e87aa4c49e95	1017	return status;
phungductung	0:e87aa4c49e95	1018	}
phungductung	0:e87aa4c49e95	1019
phungductung	0:e87aa4c49e95	1020	/**
phungductung	0:e87aa4c49e95	1021	* @brief Sends an amount of data in non blocking mode with DMA.
phungductung	0:e87aa4c49e95	1022	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1023	* @param pData: pointer to data buffer
phungductung	0:e87aa4c49e95	1024	* @note This function is used only in Indirect Write Mode
phungductung	0:e87aa4c49e95	1025	* @retval HAL status
phungductung	0:e87aa4c49e95	1026	*/
phungductung	0:e87aa4c49e95	1027	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
phungductung	0:e87aa4c49e95	1028	{
phungductung	0:e87aa4c49e95	1029	HAL_StatusTypeDef status = HAL_OK;
phungductung	0:e87aa4c49e95	1030	uint32_t *tmp;
phungductung	0:e87aa4c49e95	1031
phungductung	0:e87aa4c49e95	1032	/* Process locked */
phungductung	0:e87aa4c49e95	1033	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	1034
phungductung	0:e87aa4c49e95	1035	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	1036	{
phungductung	0:e87aa4c49e95	1037	if(pData != NULL )
phungductung	0:e87aa4c49e95	1038	{
phungductung	0:e87aa4c49e95	1039	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1040
phungductung	0:e87aa4c49e95	1041	/* Update state */
phungductung	0:e87aa4c49e95	1042	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
phungductung	0:e87aa4c49e95	1043
phungductung	0:e87aa4c49e95	1044	/* Configure counters and size of the handle */
phungductung	0:e87aa4c49e95	1045	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	1046	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	1047	hqspi->pTxBuffPtr = pData;
phungductung	0:e87aa4c49e95	1048
phungductung	0:e87aa4c49e95	1049	/* Configure QSPI: CCR register with functional mode as indirect write */
phungductung	0:e87aa4c49e95	1050	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
phungductung	0:e87aa4c49e95	1051
phungductung	0:e87aa4c49e95	1052	/* Set the QSPI DMA transfer complete callback */
phungductung	0:e87aa4c49e95	1053	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
phungductung	0:e87aa4c49e95	1054
phungductung	0:e87aa4c49e95	1055	/* Set the QSPI DMA Half transfer complete callback */
phungductung	0:e87aa4c49e95	1056	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
phungductung	0:e87aa4c49e95	1057
phungductung	0:e87aa4c49e95	1058	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1059	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
phungductung	0:e87aa4c49e95	1060
phungductung	0:e87aa4c49e95	1061	/* Configure the direction of the DMA */
phungductung	0:e87aa4c49e95	1062	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
phungductung	0:e87aa4c49e95	1063	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
phungductung	0:e87aa4c49e95	1064
phungductung	0:e87aa4c49e95	1065	/* Enable the QSPI transmit DMA Channel */
phungductung	0:e87aa4c49e95	1066	tmp = (uint32_t*)&pData;
phungductung	0:e87aa4c49e95	1067	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
phungductung	0:e87aa4c49e95	1068
phungductung	0:e87aa4c49e95	1069	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
phungductung	0:e87aa4c49e95	1070	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
phungductung	0:e87aa4c49e95	1071	}
phungductung	0:e87aa4c49e95	1072	else
phungductung	0:e87aa4c49e95	1073	{
phungductung	0:e87aa4c49e95	1074	status = HAL_OK;
phungductung	0:e87aa4c49e95	1075	}
phungductung	0:e87aa4c49e95	1076	}
phungductung	0:e87aa4c49e95	1077	else
phungductung	0:e87aa4c49e95	1078	{
phungductung	0:e87aa4c49e95	1079	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	1080	}
phungductung	0:e87aa4c49e95	1081
phungductung	0:e87aa4c49e95	1082	/* Process unlocked */
phungductung	0:e87aa4c49e95	1083	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	1084
phungductung	0:e87aa4c49e95	1085	return status;
phungductung	0:e87aa4c49e95	1086	}
phungductung	0:e87aa4c49e95	1087
phungductung	0:e87aa4c49e95	1088	/**
phungductung	0:e87aa4c49e95	1089	* @brief Receives an amount of data in non blocking mode with DMA.
phungductung	0:e87aa4c49e95	1090	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1091	* @param pData: pointer to data buffer.
phungductung	0:e87aa4c49e95	1092	* @note This function is used only in Indirect Read Mode
phungductung	0:e87aa4c49e95	1093	* @retval HAL status
phungductung	0:e87aa4c49e95	1094	*/
phungductung	0:e87aa4c49e95	1095	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
phungductung	0:e87aa4c49e95	1096	{
phungductung	0:e87aa4c49e95	1097	HAL_StatusTypeDef status = HAL_OK;
phungductung	0:e87aa4c49e95	1098	uint32_t *tmp;
phungductung	0:e87aa4c49e95	1099	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
phungductung	0:e87aa4c49e95	1100
phungductung	0:e87aa4c49e95	1101	/* Process locked */
phungductung	0:e87aa4c49e95	1102	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	1103
phungductung	0:e87aa4c49e95	1104	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	1105	{
phungductung	0:e87aa4c49e95	1106	if(pData != NULL )
phungductung	0:e87aa4c49e95	1107	{
phungductung	0:e87aa4c49e95	1108	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1109
phungductung	0:e87aa4c49e95	1110	/* Update state */
phungductung	0:e87aa4c49e95	1111	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
phungductung	0:e87aa4c49e95	1112
phungductung	0:e87aa4c49e95	1113	/* Configure counters and size of the handle */
phungductung	0:e87aa4c49e95	1114	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	1115	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
phungductung	0:e87aa4c49e95	1116	hqspi->pRxBuffPtr = pData;
phungductung	0:e87aa4c49e95	1117
phungductung	0:e87aa4c49e95	1118	/* Set the QSPI DMA transfer complete callback */
phungductung	0:e87aa4c49e95	1119	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
phungductung	0:e87aa4c49e95	1120
phungductung	0:e87aa4c49e95	1121	/* Set the QSPI DMA Half transfer complete callback */
phungductung	0:e87aa4c49e95	1122	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
phungductung	0:e87aa4c49e95	1123
phungductung	0:e87aa4c49e95	1124	/* Set the DMA error callback */
phungductung	0:e87aa4c49e95	1125	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
phungductung	0:e87aa4c49e95	1126
phungductung	0:e87aa4c49e95	1127	/* Configure the direction of the DMA */
phungductung	0:e87aa4c49e95	1128	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
phungductung	0:e87aa4c49e95	1129	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
phungductung	0:e87aa4c49e95	1130
phungductung	0:e87aa4c49e95	1131	/* Enable the DMA Channel */
phungductung	0:e87aa4c49e95	1132	tmp = (uint32_t*)&pData;
phungductung	0:e87aa4c49e95	1133	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
phungductung	0:e87aa4c49e95	1134
phungductung	0:e87aa4c49e95	1135	/* Configure QSPI: CCR register with functional as indirect read */
phungductung	0:e87aa4c49e95	1136	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
phungductung	0:e87aa4c49e95	1137
phungductung	0:e87aa4c49e95	1138	/* Start the transfer by re-writing the address in AR register */
phungductung	0:e87aa4c49e95	1139	WRITE_REG(hqspi->Instance->AR, addr_reg);
phungductung	0:e87aa4c49e95	1140
phungductung	0:e87aa4c49e95	1141	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
phungductung	0:e87aa4c49e95	1142	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
phungductung	0:e87aa4c49e95	1143	}
phungductung	0:e87aa4c49e95	1144	else
phungductung	0:e87aa4c49e95	1145	{
phungductung	0:e87aa4c49e95	1146	status = HAL_ERROR;
phungductung	0:e87aa4c49e95	1147	}
phungductung	0:e87aa4c49e95	1148	}
phungductung	0:e87aa4c49e95	1149	else
phungductung	0:e87aa4c49e95	1150	{
phungductung	0:e87aa4c49e95	1151	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	1152	}
phungductung	0:e87aa4c49e95	1153
phungductung	0:e87aa4c49e95	1154	/* Process unlocked */
phungductung	0:e87aa4c49e95	1155	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	1156
phungductung	0:e87aa4c49e95	1157	return status;
phungductung	0:e87aa4c49e95	1158	}
phungductung	0:e87aa4c49e95	1159
phungductung	0:e87aa4c49e95	1160	/**
phungductung	0:e87aa4c49e95	1161	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
phungductung	0:e87aa4c49e95	1162	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1163	* @param cmd: structure that contains the command configuration information.
phungductung	0:e87aa4c49e95	1164	* @param cfg: structure that contains the polling configuration information.
phungductung	0:e87aa4c49e95	1165	* @param Timeout : Time out duration
phungductung	0:e87aa4c49e95	1166	* @note This function is used only in Automatic Polling Mode
phungductung	0:e87aa4c49e95	1167	* @retval HAL status
phungductung	0:e87aa4c49e95	1168	*/
phungductung	0:e87aa4c49e95	1169	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
phungductung	0:e87aa4c49e95	1170	{
phungductung	0:e87aa4c49e95	1171	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	1172
phungductung	0:e87aa4c49e95	1173	/* Check the parameters */
phungductung	0:e87aa4c49e95	1174	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
phungductung	0:e87aa4c49e95	1175	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
phungductung	0:e87aa4c49e95	1176	{
phungductung	0:e87aa4c49e95	1177	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
phungductung	0:e87aa4c49e95	1178	}
phungductung	0:e87aa4c49e95	1179
phungductung	0:e87aa4c49e95	1180	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
phungductung	0:e87aa4c49e95	1181	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1182	{
phungductung	0:e87aa4c49e95	1183	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
phungductung	0:e87aa4c49e95	1184	}
phungductung	0:e87aa4c49e95	1185
phungductung	0:e87aa4c49e95	1186	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
phungductung	0:e87aa4c49e95	1187	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	1188	{
phungductung	0:e87aa4c49e95	1189	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
phungductung	0:e87aa4c49e95	1190	}
phungductung	0:e87aa4c49e95	1191
phungductung	0:e87aa4c49e95	1192	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
phungductung	0:e87aa4c49e95	1193	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
phungductung	0:e87aa4c49e95	1194
phungductung	0:e87aa4c49e95	1195	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
phungductung	0:e87aa4c49e95	1196	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
phungductung	0:e87aa4c49e95	1197	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
phungductung	0:e87aa4c49e95	1198
phungductung	0:e87aa4c49e95	1199	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
phungductung	0:e87aa4c49e95	1200	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
phungductung	0:e87aa4c49e95	1201	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
phungductung	0:e87aa4c49e95	1202
phungductung	0:e87aa4c49e95	1203	/* Process locked */
phungductung	0:e87aa4c49e95	1204	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	1205
phungductung	0:e87aa4c49e95	1206	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	1207	{
phungductung	0:e87aa4c49e95	1208
phungductung	0:e87aa4c49e95	1209	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1210
phungductung	0:e87aa4c49e95	1211	/* Update state */
phungductung	0:e87aa4c49e95	1212	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
phungductung	0:e87aa4c49e95	1213
phungductung	0:e87aa4c49e95	1214	/* Wait till BUSY flag reset */
phungductung	0:e87aa4c49e95	1215	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, Timeout);
phungductung	0:e87aa4c49e95	1216
phungductung	0:e87aa4c49e95	1217	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	1218	{
phungductung	0:e87aa4c49e95	1219	/* Configure QSPI: PSMAR register with the status match value */
phungductung	0:e87aa4c49e95	1220	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
phungductung	0:e87aa4c49e95	1221
phungductung	0:e87aa4c49e95	1222	/* Configure QSPI: PSMKR register with the status mask value */
phungductung	0:e87aa4c49e95	1223	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
phungductung	0:e87aa4c49e95	1224
phungductung	0:e87aa4c49e95	1225	/* Configure QSPI: PIR register with the interval value */
phungductung	0:e87aa4c49e95	1226	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
phungductung	0:e87aa4c49e95	1227
phungductung	0:e87aa4c49e95	1228	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
phungductung	0:e87aa4c49e95	1229	(otherwise there will be an infinite loop in blocking mode) */
phungductung	0:e87aa4c49e95	1230	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
phungductung	0:e87aa4c49e95	1231	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
phungductung	0:e87aa4c49e95	1232
phungductung	0:e87aa4c49e95	1233	/* Call the configuration function */
phungductung	0:e87aa4c49e95	1234	cmd->NbData = cfg->StatusBytesSize;
phungductung	0:e87aa4c49e95	1235	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
phungductung	0:e87aa4c49e95	1236
phungductung	0:e87aa4c49e95	1237	/* Wait until SM flag is set to go back in idle state */
phungductung	0:e87aa4c49e95	1238	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	1239	{
phungductung	0:e87aa4c49e95	1240	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	1241	}
phungductung	0:e87aa4c49e95	1242	else
phungductung	0:e87aa4c49e95	1243	{
phungductung	0:e87aa4c49e95	1244	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
phungductung	0:e87aa4c49e95	1245
phungductung	0:e87aa4c49e95	1246	/* Update state */
phungductung	0:e87aa4c49e95	1247	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	1248	}
phungductung	0:e87aa4c49e95	1249	}
phungductung	0:e87aa4c49e95	1250	}
phungductung	0:e87aa4c49e95	1251	else
phungductung	0:e87aa4c49e95	1252	{
phungductung	0:e87aa4c49e95	1253	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	1254	}
phungductung	0:e87aa4c49e95	1255	/* Process unlocked */
phungductung	0:e87aa4c49e95	1256	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	1257
phungductung	0:e87aa4c49e95	1258	/* Return function status */
phungductung	0:e87aa4c49e95	1259	return status;
phungductung	0:e87aa4c49e95	1260	}
phungductung	0:e87aa4c49e95	1261
phungductung	0:e87aa4c49e95	1262	/**
phungductung	0:e87aa4c49e95	1263	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
phungductung	0:e87aa4c49e95	1264	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1265	* @param cmd: structure that contains the command configuration information.
phungductung	0:e87aa4c49e95	1266	* @param cfg: structure that contains the polling configuration information.
phungductung	0:e87aa4c49e95	1267	* @note This function is used only in Automatic Polling Mode
phungductung	0:e87aa4c49e95	1268	* @retval HAL status
phungductung	0:e87aa4c49e95	1269	*/
phungductung	0:e87aa4c49e95	1270	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
phungductung	0:e87aa4c49e95	1271	{
phungductung	0:e87aa4c49e95	1272	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	1273
phungductung	0:e87aa4c49e95	1274	/* Check the parameters */
phungductung	0:e87aa4c49e95	1275	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
phungductung	0:e87aa4c49e95	1276	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
phungductung	0:e87aa4c49e95	1277	{
phungductung	0:e87aa4c49e95	1278	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
phungductung	0:e87aa4c49e95	1279	}
phungductung	0:e87aa4c49e95	1280
phungductung	0:e87aa4c49e95	1281	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
phungductung	0:e87aa4c49e95	1282	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1283	{
phungductung	0:e87aa4c49e95	1284	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
phungductung	0:e87aa4c49e95	1285	}
phungductung	0:e87aa4c49e95	1286
phungductung	0:e87aa4c49e95	1287	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
phungductung	0:e87aa4c49e95	1288	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	1289	{
phungductung	0:e87aa4c49e95	1290	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
phungductung	0:e87aa4c49e95	1291	}
phungductung	0:e87aa4c49e95	1292
phungductung	0:e87aa4c49e95	1293	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
phungductung	0:e87aa4c49e95	1294	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
phungductung	0:e87aa4c49e95	1295
phungductung	0:e87aa4c49e95	1296	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
phungductung	0:e87aa4c49e95	1297	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
phungductung	0:e87aa4c49e95	1298	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
phungductung	0:e87aa4c49e95	1299
phungductung	0:e87aa4c49e95	1300	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
phungductung	0:e87aa4c49e95	1301	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
phungductung	0:e87aa4c49e95	1302	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
phungductung	0:e87aa4c49e95	1303	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
phungductung	0:e87aa4c49e95	1304
phungductung	0:e87aa4c49e95	1305	/* Process locked */
phungductung	0:e87aa4c49e95	1306	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	1307
phungductung	0:e87aa4c49e95	1308	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	1309	{
phungductung	0:e87aa4c49e95	1310	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1311
phungductung	0:e87aa4c49e95	1312	/* Update state */
phungductung	0:e87aa4c49e95	1313	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
phungductung	0:e87aa4c49e95	1314
phungductung	0:e87aa4c49e95	1315	/* Wait till BUSY flag reset */
phungductung	0:e87aa4c49e95	1316	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
phungductung	0:e87aa4c49e95	1317
phungductung	0:e87aa4c49e95	1318	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	1319	{
phungductung	0:e87aa4c49e95	1320	/* Configure QSPI: PSMAR register with the status match value */
phungductung	0:e87aa4c49e95	1321	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
phungductung	0:e87aa4c49e95	1322
phungductung	0:e87aa4c49e95	1323	/* Configure QSPI: PSMKR register with the status mask value */
phungductung	0:e87aa4c49e95	1324	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
phungductung	0:e87aa4c49e95	1325
phungductung	0:e87aa4c49e95	1326	/* Configure QSPI: PIR register with the interval value */
phungductung	0:e87aa4c49e95	1327	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
phungductung	0:e87aa4c49e95	1328
phungductung	0:e87aa4c49e95	1329	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
phungductung	0:e87aa4c49e95	1330	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
phungductung	0:e87aa4c49e95	1331	(cfg->MatchMode \| cfg->AutomaticStop));
phungductung	0:e87aa4c49e95	1332
phungductung	0:e87aa4c49e95	1333	/* Clear interrupt */
phungductung	0:e87aa4c49e95	1334	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
phungductung	0:e87aa4c49e95	1335
phungductung	0:e87aa4c49e95	1336	/* Enable the QSPI Transfer Error and status match Interrupt */
phungductung	0:e87aa4c49e95	1337	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
phungductung	0:e87aa4c49e95	1338
phungductung	0:e87aa4c49e95	1339	/* Call the configuration function */
phungductung	0:e87aa4c49e95	1340	cmd->NbData = cfg->StatusBytesSize;
phungductung	0:e87aa4c49e95	1341	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
phungductung	0:e87aa4c49e95	1342	}
phungductung	0:e87aa4c49e95	1343	}
phungductung	0:e87aa4c49e95	1344	else
phungductung	0:e87aa4c49e95	1345	{
phungductung	0:e87aa4c49e95	1346	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	1347	}
phungductung	0:e87aa4c49e95	1348
phungductung	0:e87aa4c49e95	1349	/* Process unlocked */
phungductung	0:e87aa4c49e95	1350	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	1351
phungductung	0:e87aa4c49e95	1352	/* Return function status */
phungductung	0:e87aa4c49e95	1353	return status;
phungductung	0:e87aa4c49e95	1354	}
phungductung	0:e87aa4c49e95	1355
phungductung	0:e87aa4c49e95	1356	/**
phungductung	0:e87aa4c49e95	1357	* @brief Configure the Memory Mapped mode.
phungductung	0:e87aa4c49e95	1358	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1359	* @param cmd: structure that contains the command configuration information.
phungductung	0:e87aa4c49e95	1360	* @param cfg: structure that contains the memory mapped configuration information.
phungductung	0:e87aa4c49e95	1361	* @note This function is used only in Memory mapped Mode
phungductung	0:e87aa4c49e95	1362	* @retval HAL status
phungductung	0:e87aa4c49e95	1363	*/
phungductung	0:e87aa4c49e95	1364	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
phungductung	0:e87aa4c49e95	1365	{
phungductung	0:e87aa4c49e95	1366	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	1367
phungductung	0:e87aa4c49e95	1368	/* Check the parameters */
phungductung	0:e87aa4c49e95	1369	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
phungductung	0:e87aa4c49e95	1370	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
phungductung	0:e87aa4c49e95	1371	{
phungductung	0:e87aa4c49e95	1372	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
phungductung	0:e87aa4c49e95	1373	}
phungductung	0:e87aa4c49e95	1374
phungductung	0:e87aa4c49e95	1375	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
phungductung	0:e87aa4c49e95	1376	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1377	{
phungductung	0:e87aa4c49e95	1378	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
phungductung	0:e87aa4c49e95	1379	}
phungductung	0:e87aa4c49e95	1380
phungductung	0:e87aa4c49e95	1381	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
phungductung	0:e87aa4c49e95	1382	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	1383	{
phungductung	0:e87aa4c49e95	1384	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
phungductung	0:e87aa4c49e95	1385	}
phungductung	0:e87aa4c49e95	1386
phungductung	0:e87aa4c49e95	1387	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
phungductung	0:e87aa4c49e95	1388	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
phungductung	0:e87aa4c49e95	1389
phungductung	0:e87aa4c49e95	1390	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
phungductung	0:e87aa4c49e95	1391	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
phungductung	0:e87aa4c49e95	1392	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
phungductung	0:e87aa4c49e95	1393
phungductung	0:e87aa4c49e95	1394	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
phungductung	0:e87aa4c49e95	1395
phungductung	0:e87aa4c49e95	1396	/* Process locked */
phungductung	0:e87aa4c49e95	1397	__HAL_LOCK(hqspi);
phungductung	0:e87aa4c49e95	1398
phungductung	0:e87aa4c49e95	1399	if(hqspi->State == HAL_QSPI_STATE_READY)
phungductung	0:e87aa4c49e95	1400	{
phungductung	0:e87aa4c49e95	1401	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
phungductung	0:e87aa4c49e95	1402
phungductung	0:e87aa4c49e95	1403	/* Update state */
phungductung	0:e87aa4c49e95	1404	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
phungductung	0:e87aa4c49e95	1405
phungductung	0:e87aa4c49e95	1406	/* Wait till BUSY flag reset */
phungductung	0:e87aa4c49e95	1407	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
phungductung	0:e87aa4c49e95	1408
phungductung	0:e87aa4c49e95	1409	if (status == HAL_OK)
phungductung	0:e87aa4c49e95	1410	{
phungductung	0:e87aa4c49e95	1411	/* Configure QSPI: CR register with time out counter enable */
phungductung	0:e87aa4c49e95	1412	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
phungductung	0:e87aa4c49e95	1413
phungductung	0:e87aa4c49e95	1414	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
phungductung	0:e87aa4c49e95	1415	{
phungductung	0:e87aa4c49e95	1416	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
phungductung	0:e87aa4c49e95	1417
phungductung	0:e87aa4c49e95	1418	/* Configure QSPI: LPTR register with the low-power time out value */
phungductung	0:e87aa4c49e95	1419	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
phungductung	0:e87aa4c49e95	1420
phungductung	0:e87aa4c49e95	1421	/* Enable the QSPI TimeOut Interrupt */
phungductung	0:e87aa4c49e95	1422	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
phungductung	0:e87aa4c49e95	1423	}
phungductung	0:e87aa4c49e95	1424
phungductung	0:e87aa4c49e95	1425	/* Call the configuration function */
phungductung	0:e87aa4c49e95	1426	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
phungductung	0:e87aa4c49e95	1427
phungductung	0:e87aa4c49e95	1428	}
phungductung	0:e87aa4c49e95	1429	}
phungductung	0:e87aa4c49e95	1430	else
phungductung	0:e87aa4c49e95	1431	{
phungductung	0:e87aa4c49e95	1432	status = HAL_BUSY;
phungductung	0:e87aa4c49e95	1433
phungductung	0:e87aa4c49e95	1434	}
phungductung	0:e87aa4c49e95	1435
phungductung	0:e87aa4c49e95	1436	/* Process unlocked */
phungductung	0:e87aa4c49e95	1437	__HAL_UNLOCK(hqspi);
phungductung	0:e87aa4c49e95	1438
phungductung	0:e87aa4c49e95	1439	/* Return function status */
phungductung	0:e87aa4c49e95	1440	return status;
phungductung	0:e87aa4c49e95	1441	}
phungductung	0:e87aa4c49e95	1442
phungductung	0:e87aa4c49e95	1443	/**
phungductung	0:e87aa4c49e95	1444	* @brief Transfer Error callbacks
phungductung	0:e87aa4c49e95	1445	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1446	* @retval None
phungductung	0:e87aa4c49e95	1447	*/
phungductung	0:e87aa4c49e95	1448	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1449	{
phungductung	0:e87aa4c49e95	1450	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1451	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1452
phungductung	0:e87aa4c49e95	1453	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1454	the HAL_QSPI_ErrorCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1455	*/
phungductung	0:e87aa4c49e95	1456	}
phungductung	0:e87aa4c49e95	1457
phungductung	0:e87aa4c49e95	1458	/**
phungductung	0:e87aa4c49e95	1459	* @brief Command completed callbacks.
phungductung	0:e87aa4c49e95	1460	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1461	* @retval None
phungductung	0:e87aa4c49e95	1462	*/
phungductung	0:e87aa4c49e95	1463	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1464	{
phungductung	0:e87aa4c49e95	1465	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1466	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1467
phungductung	0:e87aa4c49e95	1468	/* NOTE: This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1469	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1470	*/
phungductung	0:e87aa4c49e95	1471	}
phungductung	0:e87aa4c49e95	1472
phungductung	0:e87aa4c49e95	1473	/**
phungductung	0:e87aa4c49e95	1474	* @brief Rx Transfer completed callbacks.
phungductung	0:e87aa4c49e95	1475	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1476	* @retval None
phungductung	0:e87aa4c49e95	1477	*/
phungductung	0:e87aa4c49e95	1478	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1479	{
phungductung	0:e87aa4c49e95	1480	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1481	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1482
phungductung	0:e87aa4c49e95	1483	/* NOTE: This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1484	the HAL_QSPI_RxCpltCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1485	*/
phungductung	0:e87aa4c49e95	1486	}
phungductung	0:e87aa4c49e95	1487
phungductung	0:e87aa4c49e95	1488	/**
phungductung	0:e87aa4c49e95	1489	* @brief Tx Transfer completed callbacks.
phungductung	0:e87aa4c49e95	1490	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1491	* @retval None
phungductung	0:e87aa4c49e95	1492	*/
phungductung	0:e87aa4c49e95	1493	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1494	{
phungductung	0:e87aa4c49e95	1495	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1496	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1497
phungductung	0:e87aa4c49e95	1498	/* NOTE: This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1499	the HAL_QSPI_TxCpltCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1500	*/
phungductung	0:e87aa4c49e95	1501	}
phungductung	0:e87aa4c49e95	1502
phungductung	0:e87aa4c49e95	1503	/**
phungductung	0:e87aa4c49e95	1504	* @brief Rx Half Transfer completed callbacks.
phungductung	0:e87aa4c49e95	1505	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1506	* @retval None
phungductung	0:e87aa4c49e95	1507	*/
phungductung	0:e87aa4c49e95	1508	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1509	{
phungductung	0:e87aa4c49e95	1510	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1511	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1512
phungductung	0:e87aa4c49e95	1513	/* NOTE: This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1514	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1515	*/
phungductung	0:e87aa4c49e95	1516	}
phungductung	0:e87aa4c49e95	1517
phungductung	0:e87aa4c49e95	1518	/**
phungductung	0:e87aa4c49e95	1519	* @brief Tx Half Transfer completed callbacks.
phungductung	0:e87aa4c49e95	1520	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1521	* @retval None
phungductung	0:e87aa4c49e95	1522	*/
phungductung	0:e87aa4c49e95	1523	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1524	{
phungductung	0:e87aa4c49e95	1525	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1526	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1527
phungductung	0:e87aa4c49e95	1528	/* NOTE: This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1529	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1530	*/
phungductung	0:e87aa4c49e95	1531	}
phungductung	0:e87aa4c49e95	1532
phungductung	0:e87aa4c49e95	1533	/**
phungductung	0:e87aa4c49e95	1534	* @brief FIFO Threshold callbacks
phungductung	0:e87aa4c49e95	1535	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1536	* @retval None
phungductung	0:e87aa4c49e95	1537	*/
phungductung	0:e87aa4c49e95	1538	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1539	{
phungductung	0:e87aa4c49e95	1540	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1541	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1542
phungductung	0:e87aa4c49e95	1543	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1544	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1545	*/
phungductung	0:e87aa4c49e95	1546	}
phungductung	0:e87aa4c49e95	1547
phungductung	0:e87aa4c49e95	1548	/**
phungductung	0:e87aa4c49e95	1549	* @brief Status Match callbacks
phungductung	0:e87aa4c49e95	1550	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1551	* @retval None
phungductung	0:e87aa4c49e95	1552	*/
phungductung	0:e87aa4c49e95	1553	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1554	{
phungductung	0:e87aa4c49e95	1555	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1556	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1557
phungductung	0:e87aa4c49e95	1558	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1559	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1560	*/
phungductung	0:e87aa4c49e95	1561	}
phungductung	0:e87aa4c49e95	1562
phungductung	0:e87aa4c49e95	1563	/**
phungductung	0:e87aa4c49e95	1564	* @brief Timeout callbacks
phungductung	0:e87aa4c49e95	1565	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1566	* @retval None
phungductung	0:e87aa4c49e95	1567	*/
phungductung	0:e87aa4c49e95	1568	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1569	{
phungductung	0:e87aa4c49e95	1570	/* Prevent unused argument(s) compilation warning */
phungductung	0:e87aa4c49e95	1571	UNUSED(hqspi);
phungductung	0:e87aa4c49e95	1572
phungductung	0:e87aa4c49e95	1573	/* NOTE : This function Should not be modified, when the callback is needed,
phungductung	0:e87aa4c49e95	1574	the HAL_QSPI_TimeOutCallback could be implemented in the user file
phungductung	0:e87aa4c49e95	1575	*/
phungductung	0:e87aa4c49e95	1576	}
phungductung	0:e87aa4c49e95	1577
phungductung	0:e87aa4c49e95	1578	/**
phungductung	0:e87aa4c49e95	1579	* @}
phungductung	0:e87aa4c49e95	1580	*/
phungductung	0:e87aa4c49e95	1581
phungductung	0:e87aa4c49e95	1582	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
phungductung	0:e87aa4c49e95	1583	* @brief QSPI control and State functions
phungductung	0:e87aa4c49e95	1584	*
phungductung	0:e87aa4c49e95	1585	@verbatim
phungductung	0:e87aa4c49e95	1586	===============================================================================
phungductung	0:e87aa4c49e95	1587	##### Peripheral Control and State functions #####
phungductung	0:e87aa4c49e95	1588	===============================================================================
phungductung	0:e87aa4c49e95	1589	[..]
phungductung	0:e87aa4c49e95	1590	This subsection provides a set of functions allowing to :
phungductung	0:e87aa4c49e95	1591	(+) Check in run-time the state of the driver.
phungductung	0:e87aa4c49e95	1592	(+) Check the error code set during last operation.
phungductung	0:e87aa4c49e95	1593	(+) Abort any operation.
phungductung	0:e87aa4c49e95	1594	.....
phungductung	0:e87aa4c49e95	1595	@endverbatim
phungductung	0:e87aa4c49e95	1596	* @{
phungductung	0:e87aa4c49e95	1597	*/
phungductung	0:e87aa4c49e95	1598
phungductung	0:e87aa4c49e95	1599	/**
phungductung	0:e87aa4c49e95	1600	* @brief Return the QSPI state.
phungductung	0:e87aa4c49e95	1601	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1602	* @retval HAL state
phungductung	0:e87aa4c49e95	1603	*/
phungductung	0:e87aa4c49e95	1604	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1605	{
phungductung	0:e87aa4c49e95	1606	return hqspi->State;
phungductung	0:e87aa4c49e95	1607	}
phungductung	0:e87aa4c49e95	1608
phungductung	0:e87aa4c49e95	1609	/**
phungductung	0:e87aa4c49e95	1610	* @brief Return the QSPI error code
phungductung	0:e87aa4c49e95	1611	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1612	* @retval QSPI Error Code
phungductung	0:e87aa4c49e95	1613	*/
phungductung	0:e87aa4c49e95	1614	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1615	{
phungductung	0:e87aa4c49e95	1616	return hqspi->ErrorCode;
phungductung	0:e87aa4c49e95	1617	}
phungductung	0:e87aa4c49e95	1618
phungductung	0:e87aa4c49e95	1619	/**
phungductung	0:e87aa4c49e95	1620	* @brief Abort the current transmission
phungductung	0:e87aa4c49e95	1621	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1622	* @retval HAL status
phungductung	0:e87aa4c49e95	1623	*/
phungductung	0:e87aa4c49e95	1624	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
phungductung	0:e87aa4c49e95	1625	{
phungductung	0:e87aa4c49e95	1626	HAL_StatusTypeDef status = HAL_ERROR;
phungductung	0:e87aa4c49e95	1627
phungductung	0:e87aa4c49e95	1628	/* Configure QSPI: CR register with Abort request */
phungductung	0:e87aa4c49e95	1629	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
phungductung	0:e87aa4c49e95	1630
phungductung	0:e87aa4c49e95	1631	/* Wait until TC flag is set to go back in idle state */
phungductung	0:e87aa4c49e95	1632	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	1633	{
phungductung	0:e87aa4c49e95	1634	status = HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	1635	}
phungductung	0:e87aa4c49e95	1636	else
phungductung	0:e87aa4c49e95	1637	{
phungductung	0:e87aa4c49e95	1638	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	1639
phungductung	0:e87aa4c49e95	1640	/* Wait until BUSY flag is reset */
phungductung	0:e87aa4c49e95	1641	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout);
phungductung	0:e87aa4c49e95	1642
phungductung	0:e87aa4c49e95	1643	/* Update state */
phungductung	0:e87aa4c49e95	1644	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	1645	}
phungductung	0:e87aa4c49e95	1646
phungductung	0:e87aa4c49e95	1647	return status;
phungductung	0:e87aa4c49e95	1648	}
phungductung	0:e87aa4c49e95	1649
phungductung	0:e87aa4c49e95	1650	/** @brief Set QSPI timeout
phungductung	0:e87aa4c49e95	1651	* @param hqspi: QSPI handle.
phungductung	0:e87aa4c49e95	1652	* @param Timeout: Timeout for the QSPI memory access.
phungductung	0:e87aa4c49e95	1653	* @retval None
phungductung	0:e87aa4c49e95	1654	*/
phungductung	0:e87aa4c49e95	1655	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
phungductung	0:e87aa4c49e95	1656	{
phungductung	0:e87aa4c49e95	1657	hqspi->Timeout = Timeout;
phungductung	0:e87aa4c49e95	1658	}
phungductung	0:e87aa4c49e95	1659
phungductung	0:e87aa4c49e95	1660	/**
phungductung	0:e87aa4c49e95	1661	* @}
phungductung	0:e87aa4c49e95	1662	*/
phungductung	0:e87aa4c49e95	1663
phungductung	0:e87aa4c49e95	1664	/* Private functions ---------------------------------------------------------*/
phungductung	0:e87aa4c49e95	1665
phungductung	0:e87aa4c49e95	1666	/**
phungductung	0:e87aa4c49e95	1667	* @brief DMA QSPI receive process complete callback.
phungductung	0:e87aa4c49e95	1668	* @param hdma: DMA handle
phungductung	0:e87aa4c49e95	1669	* @retval None
phungductung	0:e87aa4c49e95	1670	*/
phungductung	0:e87aa4c49e95	1671	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1672	{
phungductung	0:e87aa4c49e95	1673	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	1674	hqspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	1675
phungductung	0:e87aa4c49e95	1676	/* Wait for QSPI TC Flag */
phungductung	0:e87aa4c49e95	1677	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	1678	{
phungductung	0:e87aa4c49e95	1679	/* Time out Occurred */
phungductung	0:e87aa4c49e95	1680	HAL_QSPI_ErrorCallback(hqspi);
phungductung	0:e87aa4c49e95	1681	}
phungductung	0:e87aa4c49e95	1682	else
phungductung	0:e87aa4c49e95	1683	{
phungductung	0:e87aa4c49e95	1684	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
phungductung	0:e87aa4c49e95	1685	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
phungductung	0:e87aa4c49e95	1686
phungductung	0:e87aa4c49e95	1687	/* Disable the DMA channel */
phungductung	0:e87aa4c49e95	1688	HAL_DMA_Abort(hdma);
phungductung	0:e87aa4c49e95	1689
phungductung	0:e87aa4c49e95	1690	/* Clear Transfer Complete bit */
phungductung	0:e87aa4c49e95	1691	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	1692
phungductung	0:e87aa4c49e95	1693	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
phungductung	0:e87aa4c49e95	1694	HAL_QSPI_Abort(hqspi);
phungductung	0:e87aa4c49e95	1695
phungductung	0:e87aa4c49e95	1696	/* Update state */
phungductung	0:e87aa4c49e95	1697	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	1698
phungductung	0:e87aa4c49e95	1699	HAL_QSPI_RxCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	1700	}
phungductung	0:e87aa4c49e95	1701	}
phungductung	0:e87aa4c49e95	1702
phungductung	0:e87aa4c49e95	1703	/**
phungductung	0:e87aa4c49e95	1704	* @brief DMA QSPI transmit process complete callback.
phungductung	0:e87aa4c49e95	1705	* @param hdma: DMA handle
phungductung	0:e87aa4c49e95	1706	* @retval None
phungductung	0:e87aa4c49e95	1707	*/
phungductung	0:e87aa4c49e95	1708	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1709	{
phungductung	0:e87aa4c49e95	1710	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	1711	hqspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	1712
phungductung	0:e87aa4c49e95	1713	/* Wait for QSPI TC Flag */
phungductung	0:e87aa4c49e95	1714	if(QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, hqspi->Timeout) != HAL_OK)
phungductung	0:e87aa4c49e95	1715	{
phungductung	0:e87aa4c49e95	1716	/* Time out Occurred */
phungductung	0:e87aa4c49e95	1717	HAL_QSPI_ErrorCallback(hqspi);
phungductung	0:e87aa4c49e95	1718	}
phungductung	0:e87aa4c49e95	1719	else
phungductung	0:e87aa4c49e95	1720	{
phungductung	0:e87aa4c49e95	1721	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
phungductung	0:e87aa4c49e95	1722	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
phungductung	0:e87aa4c49e95	1723
phungductung	0:e87aa4c49e95	1724	/* Disable the DMA channel */
phungductung	0:e87aa4c49e95	1725	HAL_DMA_Abort(hdma);
phungductung	0:e87aa4c49e95	1726
phungductung	0:e87aa4c49e95	1727	/* Clear Transfer Complete bit */
phungductung	0:e87aa4c49e95	1728	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
phungductung	0:e87aa4c49e95	1729
phungductung	0:e87aa4c49e95	1730	/* Clear Busy bit */
phungductung	0:e87aa4c49e95	1731	HAL_QSPI_Abort(hqspi);
phungductung	0:e87aa4c49e95	1732
phungductung	0:e87aa4c49e95	1733	/* Update state */
phungductung	0:e87aa4c49e95	1734	hqspi->State = HAL_QSPI_STATE_READY;
phungductung	0:e87aa4c49e95	1735
phungductung	0:e87aa4c49e95	1736	HAL_QSPI_TxCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	1737	}
phungductung	0:e87aa4c49e95	1738	}
phungductung	0:e87aa4c49e95	1739
phungductung	0:e87aa4c49e95	1740	/**
phungductung	0:e87aa4c49e95	1741	* @brief DMA QSPI receive process half complete callback
phungductung	0:e87aa4c49e95	1742	* @param hdma : DMA handle
phungductung	0:e87aa4c49e95	1743	* @retval None
phungductung	0:e87aa4c49e95	1744	*/
phungductung	0:e87aa4c49e95	1745	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1746	{
phungductung	0:e87aa4c49e95	1747	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
phungductung	0:e87aa4c49e95	1748
phungductung	0:e87aa4c49e95	1749	HAL_QSPI_RxHalfCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	1750	}
phungductung	0:e87aa4c49e95	1751
phungductung	0:e87aa4c49e95	1752	/**
phungductung	0:e87aa4c49e95	1753	* @brief DMA QSPI transmit process half complete callback
phungductung	0:e87aa4c49e95	1754	* @param hdma : DMA handle
phungductung	0:e87aa4c49e95	1755	* @retval None
phungductung	0:e87aa4c49e95	1756	*/
phungductung	0:e87aa4c49e95	1757	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1758	{
phungductung	0:e87aa4c49e95	1759	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
phungductung	0:e87aa4c49e95	1760
phungductung	0:e87aa4c49e95	1761	HAL_QSPI_TxHalfCpltCallback(hqspi);
phungductung	0:e87aa4c49e95	1762	}
phungductung	0:e87aa4c49e95	1763
phungductung	0:e87aa4c49e95	1764	/**
phungductung	0:e87aa4c49e95	1765	* @brief DMA QSPI communication error callback.
phungductung	0:e87aa4c49e95	1766	* @param hdma: DMA handle
phungductung	0:e87aa4c49e95	1767	* @retval None
phungductung	0:e87aa4c49e95	1768	*/
phungductung	0:e87aa4c49e95	1769	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
phungductung	0:e87aa4c49e95	1770	{
phungductung	0:e87aa4c49e95	1771	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:e87aa4c49e95	1772
phungductung	0:e87aa4c49e95	1773	hqspi->RxXferCount = 0;
phungductung	0:e87aa4c49e95	1774	hqspi->TxXferCount = 0;
phungductung	0:e87aa4c49e95	1775	hqspi->State = HAL_QSPI_STATE_ERROR;
phungductung	0:e87aa4c49e95	1776	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
phungductung	0:e87aa4c49e95	1777
phungductung	0:e87aa4c49e95	1778	HAL_QSPI_ErrorCallback(hqspi);
phungductung	0:e87aa4c49e95	1779	}
phungductung	0:e87aa4c49e95	1780
phungductung	0:e87aa4c49e95	1781	/**
phungductung	0:e87aa4c49e95	1782	* @brief This function wait a flag state until time out.
phungductung	0:e87aa4c49e95	1783	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1784	* @param Flag: Flag checked
phungductung	0:e87aa4c49e95	1785	* @param State: Value of the flag expected
phungductung	0:e87aa4c49e95	1786	* @param Timeout: Duration of the time out
phungductung	0:e87aa4c49e95	1787	* @retval HAL status
phungductung	0:e87aa4c49e95	1788	*/
phungductung	0:e87aa4c49e95	1789	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
phungductung	0:e87aa4c49e95	1790	FlagStatus State, uint32_t Timeout)
phungductung	0:e87aa4c49e95	1791	{
phungductung	0:e87aa4c49e95	1792	uint32_t tickstart = HAL_GetTick();
phungductung	0:e87aa4c49e95	1793
phungductung	0:e87aa4c49e95	1794	/* Wait until flag is in expected state */
phungductung	0:e87aa4c49e95	1795	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
phungductung	0:e87aa4c49e95	1796	{
phungductung	0:e87aa4c49e95	1797	/* Check for the Timeout */
phungductung	0:e87aa4c49e95	1798	if (Timeout != HAL_MAX_DELAY)
phungductung	0:e87aa4c49e95	1799	{
phungductung	0:e87aa4c49e95	1800	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
phungductung	0:e87aa4c49e95	1801	{
phungductung	0:e87aa4c49e95	1802	hqspi->State = HAL_QSPI_STATE_ERROR;
phungductung	0:e87aa4c49e95	1803	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
phungductung	0:e87aa4c49e95	1804
phungductung	0:e87aa4c49e95	1805	return HAL_TIMEOUT;
phungductung	0:e87aa4c49e95	1806	}
phungductung	0:e87aa4c49e95	1807	}
phungductung	0:e87aa4c49e95	1808	}
phungductung	0:e87aa4c49e95	1809	return HAL_OK;
phungductung	0:e87aa4c49e95	1810	}
phungductung	0:e87aa4c49e95	1811
phungductung	0:e87aa4c49e95	1812	/**
phungductung	0:e87aa4c49e95	1813	* @brief This function configures the communication registers
phungductung	0:e87aa4c49e95	1814	* @param hqspi: QSPI handle
phungductung	0:e87aa4c49e95	1815	* @param cmd: structure that contains the command configuration information
phungductung	0:e87aa4c49e95	1816	* @param FunctionalMode: functional mode to configured
phungductung	0:e87aa4c49e95	1817	* This parameter can be one of the following values:
phungductung	0:e87aa4c49e95	1818	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
phungductung	0:e87aa4c49e95	1819	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
phungductung	0:e87aa4c49e95	1820	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
phungductung	0:e87aa4c49e95	1821	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
phungductung	0:e87aa4c49e95	1822	* @retval None
phungductung	0:e87aa4c49e95	1823	*/
phungductung	0:e87aa4c49e95	1824	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
phungductung	0:e87aa4c49e95	1825	{
phungductung	0:e87aa4c49e95	1826	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
phungductung	0:e87aa4c49e95	1827
phungductung	0:e87aa4c49e95	1828	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
phungductung	0:e87aa4c49e95	1829	{
phungductung	0:e87aa4c49e95	1830	/* Configure QSPI: DLR register with the number of data to read or write */
phungductung	0:e87aa4c49e95	1831	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
phungductung	0:e87aa4c49e95	1832	}
phungductung	0:e87aa4c49e95	1833
phungductung	0:e87aa4c49e95	1834	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
phungductung	0:e87aa4c49e95	1835	{
phungductung	0:e87aa4c49e95	1836	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	1837	{
phungductung	0:e87aa4c49e95	1838	/* Configure QSPI: ABR register with alternate bytes value */
phungductung	0:e87aa4c49e95	1839	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
phungductung	0:e87aa4c49e95	1840
phungductung	0:e87aa4c49e95	1841	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1842	{
phungductung	0:e87aa4c49e95	1843	/---- Command with instruction, address and alternate bytes ----/
phungductung	0:e87aa4c49e95	1844	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1845	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1846	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
phungductung	0:e87aa4c49e95	1847	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
phungductung	0:e87aa4c49e95	1848	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
phungductung	0:e87aa4c49e95	1849
phungductung	0:e87aa4c49e95	1850	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
phungductung	0:e87aa4c49e95	1851	{
phungductung	0:e87aa4c49e95	1852	/* Configure QSPI: AR register with address value */
phungductung	0:e87aa4c49e95	1853	WRITE_REG(hqspi->Instance->AR, cmd->Address);
phungductung	0:e87aa4c49e95	1854	}
phungductung	0:e87aa4c49e95	1855	}
phungductung	0:e87aa4c49e95	1856	else
phungductung	0:e87aa4c49e95	1857	{
phungductung	0:e87aa4c49e95	1858	/---- Command with instruction and alternate bytes ----/
phungductung	0:e87aa4c49e95	1859	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1860	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1861	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
phungductung	0:e87aa4c49e95	1862	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
phungductung	0:e87aa4c49e95	1863	cmd->Instruction \| FunctionalMode));
phungductung	0:e87aa4c49e95	1864	}
phungductung	0:e87aa4c49e95	1865	}
phungductung	0:e87aa4c49e95	1866	else
phungductung	0:e87aa4c49e95	1867	{
phungductung	0:e87aa4c49e95	1868	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1869	{
phungductung	0:e87aa4c49e95	1870	/---- Command with instruction and address ----/
phungductung	0:e87aa4c49e95	1871	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1872	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1873	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
phungductung	0:e87aa4c49e95	1874	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
phungductung	0:e87aa4c49e95	1875	cmd->Instruction \| FunctionalMode));
phungductung	0:e87aa4c49e95	1876
phungductung	0:e87aa4c49e95	1877	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
phungductung	0:e87aa4c49e95	1878	{
phungductung	0:e87aa4c49e95	1879	/* Configure QSPI: AR register with address value */
phungductung	0:e87aa4c49e95	1880	WRITE_REG(hqspi->Instance->AR, cmd->Address);
phungductung	0:e87aa4c49e95	1881	}
phungductung	0:e87aa4c49e95	1882	}
phungductung	0:e87aa4c49e95	1883	else
phungductung	0:e87aa4c49e95	1884	{
phungductung	0:e87aa4c49e95	1885	/---- Command with only instruction ----/
phungductung	0:e87aa4c49e95	1886	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1887	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1888	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
phungductung	0:e87aa4c49e95	1889	cmd->AddressMode \| cmd->InstructionMode \| cmd->Instruction \|
phungductung	0:e87aa4c49e95	1890	FunctionalMode));
phungductung	0:e87aa4c49e95	1891	}
phungductung	0:e87aa4c49e95	1892	}
phungductung	0:e87aa4c49e95	1893	}
phungductung	0:e87aa4c49e95	1894	else
phungductung	0:e87aa4c49e95	1895	{
phungductung	0:e87aa4c49e95	1896	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
phungductung	0:e87aa4c49e95	1897	{
phungductung	0:e87aa4c49e95	1898	/* Configure QSPI: ABR register with alternate bytes value */
phungductung	0:e87aa4c49e95	1899	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
phungductung	0:e87aa4c49e95	1900
phungductung	0:e87aa4c49e95	1901	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1902	{
phungductung	0:e87aa4c49e95	1903	/---- Command with address and alternate bytes ----/
phungductung	0:e87aa4c49e95	1904	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1905	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1906	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
phungductung	0:e87aa4c49e95	1907	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
phungductung	0:e87aa4c49e95	1908	cmd->InstructionMode \| FunctionalMode));
phungductung	0:e87aa4c49e95	1909
phungductung	0:e87aa4c49e95	1910	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
phungductung	0:e87aa4c49e95	1911	{
phungductung	0:e87aa4c49e95	1912	/* Configure QSPI: AR register with address value */
phungductung	0:e87aa4c49e95	1913	WRITE_REG(hqspi->Instance->AR, cmd->Address);
phungductung	0:e87aa4c49e95	1914	}
phungductung	0:e87aa4c49e95	1915	}
phungductung	0:e87aa4c49e95	1916	else
phungductung	0:e87aa4c49e95	1917	{
phungductung	0:e87aa4c49e95	1918	/---- Command with only alternate bytes ----/
phungductung	0:e87aa4c49e95	1919	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1920	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1921	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
phungductung	0:e87aa4c49e95	1922	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
phungductung	0:e87aa4c49e95	1923	FunctionalMode));
phungductung	0:e87aa4c49e95	1924	}
phungductung	0:e87aa4c49e95	1925	}
phungductung	0:e87aa4c49e95	1926	else
phungductung	0:e87aa4c49e95	1927	{
phungductung	0:e87aa4c49e95	1928	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
phungductung	0:e87aa4c49e95	1929	{
phungductung	0:e87aa4c49e95	1930	/---- Command with only address ----/
phungductung	0:e87aa4c49e95	1931	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1932	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1933	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
phungductung	0:e87aa4c49e95	1934	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
phungductung	0:e87aa4c49e95	1935	FunctionalMode));
phungductung	0:e87aa4c49e95	1936
phungductung	0:e87aa4c49e95	1937	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
phungductung	0:e87aa4c49e95	1938	{
phungductung	0:e87aa4c49e95	1939	/* Configure QSPI: AR register with address value */
phungductung	0:e87aa4c49e95	1940	WRITE_REG(hqspi->Instance->AR, cmd->Address);
phungductung	0:e87aa4c49e95	1941	}
phungductung	0:e87aa4c49e95	1942	}
phungductung	0:e87aa4c49e95	1943	else
phungductung	0:e87aa4c49e95	1944	{
phungductung	0:e87aa4c49e95	1945	/---- Command with only data phase ----/
phungductung	0:e87aa4c49e95	1946	if (cmd->DataMode != QSPI_DATA_NONE)
phungductung	0:e87aa4c49e95	1947	{
phungductung	0:e87aa4c49e95	1948	/* Configure QSPI: CCR register with all communications parameters */
phungductung	0:e87aa4c49e95	1949	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
phungductung	0:e87aa4c49e95	1950	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
phungductung	0:e87aa4c49e95	1951	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
phungductung	0:e87aa4c49e95	1952	}
phungductung	0:e87aa4c49e95	1953	}
phungductung	0:e87aa4c49e95	1954	}
phungductung	0:e87aa4c49e95	1955	}
phungductung	0:e87aa4c49e95	1956	}
phungductung	0:e87aa4c49e95	1957	/**
phungductung	0:e87aa4c49e95	1958	* @}
phungductung	0:e87aa4c49e95	1959	*/
phungductung	0:e87aa4c49e95	1960
phungductung	0:e87aa4c49e95	1961	#endif /* HAL_QSPI_MODULE_ENABLED */
phungductung	0:e87aa4c49e95	1962	/**
phungductung	0:e87aa4c49e95	1963	* @}
phungductung	0:e87aa4c49e95	1964	*/
phungductung	0:e87aa4c49e95	1965
phungductung	0:e87aa4c49e95	1966	/**
phungductung	0:e87aa4c49e95	1967	* @}
phungductung	0:e87aa4c49e95	1968	*/
phungductung	0:e87aa4c49e95	1969
phungductung	0:e87aa4c49e95	1970	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Jun 2019
Imports:	8
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c@0:e87aa4c49e95, 2019-06-04 (annotated)

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