PHung Tung / SRC_STM32F7

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c@0:e87aa4c49e95, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:51:46 2019 +0000
Revision:
0:e87aa4c49e95
libray

Who changed what in which revision?

UserRevisionLine numberNew contents of line
phungductung 0:e87aa4c49e95 1 /**
phungductung 0:e87aa4c49e95 2 ******************************************************************************
phungductung 0:e87aa4c49e95 3 * @file stm32f7xx_hal_nand.c
phungductung 0:e87aa4c49e95 4 * @author MCD Application Team
phungductung 0:e87aa4c49e95 5 * @version V1.0.4
phungductung 0:e87aa4c49e95 6 * @date 09-December-2015
phungductung 0:e87aa4c49e95 7 * @brief NAND HAL module driver.
phungductung 0:e87aa4c49e95 8 * This file provides a generic firmware to drive NAND memories mounted
phungductung 0:e87aa4c49e95 9 * as external device.
phungductung 0:e87aa4c49e95 10 *
phungductung 0:e87aa4c49e95 11 @verbatim
phungductung 0:e87aa4c49e95 12 ==============================================================================
phungductung 0:e87aa4c49e95 13 ##### How to use this driver #####
phungductung 0:e87aa4c49e95 14 ==============================================================================
phungductung 0:e87aa4c49e95 15 [..]
phungductung 0:e87aa4c49e95 16 This driver is a generic layered driver which contains a set of APIs used to
phungductung 0:e87aa4c49e95 17 control NAND flash memories. It uses the FMC/FSMC layer functions to interface
phungductung 0:e87aa4c49e95 18 with NAND devices. This driver is used as follows:
phungductung 0:e87aa4c49e95 19
phungductung 0:e87aa4c49e95 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
phungductung 0:e87aa4c49e95 21 with control and timing parameters for both common and attribute spaces.
phungductung 0:e87aa4c49e95 22
phungductung 0:e87aa4c49e95 23 (+) Read NAND flash memory maker and device IDs using the function
phungductung 0:e87aa4c49e95 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
phungductung 0:e87aa4c49e95 25 structure declared by the function caller.
phungductung 0:e87aa4c49e95 26
phungductung 0:e87aa4c49e95 27 (+) Access NAND flash memory by read/write operations using the functions
phungductung 0:e87aa4c49e95 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
phungductung 0:e87aa4c49e95 29 to read/write page(s)/spare area(s). These functions use specific device
phungductung 0:e87aa4c49e95 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
phungductung 0:e87aa4c49e95 31 structure. The read/write address information is contained by the Nand_Address_Typedef
phungductung 0:e87aa4c49e95 32 structure passed as parameter.
phungductung 0:e87aa4c49e95 33
phungductung 0:e87aa4c49e95 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
phungductung 0:e87aa4c49e95 35
phungductung 0:e87aa4c49e95 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
phungductung 0:e87aa4c49e95 37 The erase block address information is contained in the Nand_Address_Typedef
phungductung 0:e87aa4c49e95 38 structure passed as parameter.
phungductung 0:e87aa4c49e95 39
phungductung 0:e87aa4c49e95 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
phungductung 0:e87aa4c49e95 41
phungductung 0:e87aa4c49e95 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
phungductung 0:e87aa4c49e95 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
phungductung 0:e87aa4c49e95 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
phungductung 0:e87aa4c49e95 45
phungductung 0:e87aa4c49e95 46 (+) You can monitor the NAND device HAL state by calling the function
phungductung 0:e87aa4c49e95 47 HAL_NAND_GetState()
phungductung 0:e87aa4c49e95 48
phungductung 0:e87aa4c49e95 49 [..]
phungductung 0:e87aa4c49e95 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
phungductung 0:e87aa4c49e95 51 If a NAND flash device contains different operations and/or implementations,
phungductung 0:e87aa4c49e95 52 it should be implemented separately.
phungductung 0:e87aa4c49e95 53
phungductung 0:e87aa4c49e95 54 @endverbatim
phungductung 0:e87aa4c49e95 55 ******************************************************************************
phungductung 0:e87aa4c49e95 56 * @attention
phungductung 0:e87aa4c49e95 57 *
phungductung 0:e87aa4c49e95 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:e87aa4c49e95 59 *
phungductung 0:e87aa4c49e95 60 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:e87aa4c49e95 61 * are permitted provided that the following conditions are met:
phungductung 0:e87aa4c49e95 62 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:e87aa4c49e95 63 * this list of conditions and the following disclaimer.
phungductung 0:e87aa4c49e95 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:e87aa4c49e95 65 * this list of conditions and the following disclaimer in the documentation
phungductung 0:e87aa4c49e95 66 * and/or other materials provided with the distribution.
phungductung 0:e87aa4c49e95 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:e87aa4c49e95 68 * may be used to endorse or promote products derived from this software
phungductung 0:e87aa4c49e95 69 * without specific prior written permission.
phungductung 0:e87aa4c49e95 70 *
phungductung 0:e87aa4c49e95 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:e87aa4c49e95 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:e87aa4c49e95 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:e87aa4c49e95 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:e87aa4c49e95 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:e87aa4c49e95 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:e87aa4c49e95 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:e87aa4c49e95 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:e87aa4c49e95 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:e87aa4c49e95 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:e87aa4c49e95 81 *
phungductung 0:e87aa4c49e95 82 ******************************************************************************
phungductung 0:e87aa4c49e95 83 */
phungductung 0:e87aa4c49e95 84
phungductung 0:e87aa4c49e95 85 /* Includes ------------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 86 #include "stm32f7xx_hal.h"
phungductung 0:e87aa4c49e95 87
phungductung 0:e87aa4c49e95 88 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:e87aa4c49e95 89 * @{
phungductung 0:e87aa4c49e95 90 */
phungductung 0:e87aa4c49e95 91
phungductung 0:e87aa4c49e95 92
phungductung 0:e87aa4c49e95 93 #ifdef HAL_NAND_MODULE_ENABLED
phungductung 0:e87aa4c49e95 94
phungductung 0:e87aa4c49e95 95 /** @defgroup NAND NAND
phungductung 0:e87aa4c49e95 96 * @brief NAND HAL module driver
phungductung 0:e87aa4c49e95 97 * @{
phungductung 0:e87aa4c49e95 98 */
phungductung 0:e87aa4c49e95 99
phungductung 0:e87aa4c49e95 100 /* Private typedef -----------------------------------------------------------*/
phungductung 0:e87aa4c49e95 101 /* Private Constants ------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 102 /* Private macro -------------------------------------------------------------*/
phungductung 0:e87aa4c49e95 103 /* Private variables ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 104 /* Private function prototypes -----------------------------------------------*/
phungductung 0:e87aa4c49e95 105 /* Exported functions ---------------------------------------------------------*/
phungductung 0:e87aa4c49e95 106
phungductung 0:e87aa4c49e95 107 /** @defgroup NAND_Exported_Functions NAND Exported Functions
phungductung 0:e87aa4c49e95 108 * @{
phungductung 0:e87aa4c49e95 109 */
phungductung 0:e87aa4c49e95 110
phungductung 0:e87aa4c49e95 111 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung 0:e87aa4c49e95 112 * @brief Initialization and Configuration functions
phungductung 0:e87aa4c49e95 113 *
phungductung 0:e87aa4c49e95 114 @verbatim
phungductung 0:e87aa4c49e95 115 ==============================================================================
phungductung 0:e87aa4c49e95 116 ##### NAND Initialization and de-initialization functions #####
phungductung 0:e87aa4c49e95 117 ==============================================================================
phungductung 0:e87aa4c49e95 118 [..]
phungductung 0:e87aa4c49e95 119 This section provides functions allowing to initialize/de-initialize
phungductung 0:e87aa4c49e95 120 the NAND memory
phungductung 0:e87aa4c49e95 121
phungductung 0:e87aa4c49e95 122 @endverbatim
phungductung 0:e87aa4c49e95 123 * @{
phungductung 0:e87aa4c49e95 124 */
phungductung 0:e87aa4c49e95 125
phungductung 0:e87aa4c49e95 126 /**
phungductung 0:e87aa4c49e95 127 * @brief Perform NAND memory Initialization sequence
phungductung 0:e87aa4c49e95 128 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 129 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 130 * @param ComSpace_Timing: pointer to Common space timing structure
phungductung 0:e87aa4c49e95 131 * @param AttSpace_Timing: pointer to Attribute space timing structure
phungductung 0:e87aa4c49e95 132 * @retval HAL status
phungductung 0:e87aa4c49e95 133 */
phungductung 0:e87aa4c49e95 134 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
phungductung 0:e87aa4c49e95 135 {
phungductung 0:e87aa4c49e95 136 /* Check the NAND handle state */
phungductung 0:e87aa4c49e95 137 if(hnand == NULL)
phungductung 0:e87aa4c49e95 138 {
phungductung 0:e87aa4c49e95 139 return HAL_ERROR;
phungductung 0:e87aa4c49e95 140 }
phungductung 0:e87aa4c49e95 141
phungductung 0:e87aa4c49e95 142 if(hnand->State == HAL_NAND_STATE_RESET)
phungductung 0:e87aa4c49e95 143 {
phungductung 0:e87aa4c49e95 144 /* Allocate lock resource and initialize it */
phungductung 0:e87aa4c49e95 145 hnand->Lock = HAL_UNLOCKED;
phungductung 0:e87aa4c49e95 146 /* Initialize the low level hardware (MSP) */
phungductung 0:e87aa4c49e95 147 HAL_NAND_MspInit(hnand);
phungductung 0:e87aa4c49e95 148 }
phungductung 0:e87aa4c49e95 149
phungductung 0:e87aa4c49e95 150 /* Initialize NAND control Interface */
phungductung 0:e87aa4c49e95 151 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
phungductung 0:e87aa4c49e95 152
phungductung 0:e87aa4c49e95 153 /* Initialize NAND common space timing Interface */
phungductung 0:e87aa4c49e95 154 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
phungductung 0:e87aa4c49e95 155
phungductung 0:e87aa4c49e95 156 /* Initialize NAND attribute space timing Interface */
phungductung 0:e87aa4c49e95 157 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
phungductung 0:e87aa4c49e95 158
phungductung 0:e87aa4c49e95 159 /* Enable the NAND device */
phungductung 0:e87aa4c49e95 160 __FMC_NAND_ENABLE(hnand->Instance);
phungductung 0:e87aa4c49e95 161
phungductung 0:e87aa4c49e95 162 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 163 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 164
phungductung 0:e87aa4c49e95 165 return HAL_OK;
phungductung 0:e87aa4c49e95 166 }
phungductung 0:e87aa4c49e95 167
phungductung 0:e87aa4c49e95 168 /**
phungductung 0:e87aa4c49e95 169 * @brief Perform NAND memory De-Initialization sequence
phungductung 0:e87aa4c49e95 170 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 171 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 172 * @retval HAL status
phungductung 0:e87aa4c49e95 173 */
phungductung 0:e87aa4c49e95 174 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 175 {
phungductung 0:e87aa4c49e95 176 /* Initialize the low level hardware (MSP) */
phungductung 0:e87aa4c49e95 177 HAL_NAND_MspDeInit(hnand);
phungductung 0:e87aa4c49e95 178
phungductung 0:e87aa4c49e95 179 /* Configure the NAND registers with their reset values */
phungductung 0:e87aa4c49e95 180 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
phungductung 0:e87aa4c49e95 181
phungductung 0:e87aa4c49e95 182 /* Reset the NAND controller state */
phungductung 0:e87aa4c49e95 183 hnand->State = HAL_NAND_STATE_RESET;
phungductung 0:e87aa4c49e95 184
phungductung 0:e87aa4c49e95 185 /* Release Lock */
phungductung 0:e87aa4c49e95 186 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 187
phungductung 0:e87aa4c49e95 188 return HAL_OK;
phungductung 0:e87aa4c49e95 189 }
phungductung 0:e87aa4c49e95 190
phungductung 0:e87aa4c49e95 191 /**
phungductung 0:e87aa4c49e95 192 * @brief NAND MSP Init
phungductung 0:e87aa4c49e95 193 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 194 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 195 * @retval None
phungductung 0:e87aa4c49e95 196 */
phungductung 0:e87aa4c49e95 197 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 198 {
phungductung 0:e87aa4c49e95 199 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 200 UNUSED(hnand);
phungductung 0:e87aa4c49e95 201
phungductung 0:e87aa4c49e95 202 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 203 the HAL_NAND_MspInit could be implemented in the user file
phungductung 0:e87aa4c49e95 204 */
phungductung 0:e87aa4c49e95 205 }
phungductung 0:e87aa4c49e95 206
phungductung 0:e87aa4c49e95 207 /**
phungductung 0:e87aa4c49e95 208 * @brief NAND MSP DeInit
phungductung 0:e87aa4c49e95 209 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 210 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 211 * @retval None
phungductung 0:e87aa4c49e95 212 */
phungductung 0:e87aa4c49e95 213 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 214 {
phungductung 0:e87aa4c49e95 215 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 216 UNUSED(hnand);
phungductung 0:e87aa4c49e95 217
phungductung 0:e87aa4c49e95 218 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 219 the HAL_NAND_MspDeInit could be implemented in the user file
phungductung 0:e87aa4c49e95 220 */
phungductung 0:e87aa4c49e95 221 }
phungductung 0:e87aa4c49e95 222
phungductung 0:e87aa4c49e95 223
phungductung 0:e87aa4c49e95 224 /**
phungductung 0:e87aa4c49e95 225 * @brief This function handles NAND device interrupt request.
phungductung 0:e87aa4c49e95 226 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 227 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 228 * @retval HAL status
phungductung 0:e87aa4c49e95 229 */
phungductung 0:e87aa4c49e95 230 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 231 {
phungductung 0:e87aa4c49e95 232 /* Check NAND interrupt Rising edge flag */
phungductung 0:e87aa4c49e95 233 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
phungductung 0:e87aa4c49e95 234 {
phungductung 0:e87aa4c49e95 235 /* NAND interrupt callback*/
phungductung 0:e87aa4c49e95 236 HAL_NAND_ITCallback(hnand);
phungductung 0:e87aa4c49e95 237
phungductung 0:e87aa4c49e95 238 /* Clear NAND interrupt Rising edge pending bit */
phungductung 0:e87aa4c49e95 239 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
phungductung 0:e87aa4c49e95 240 }
phungductung 0:e87aa4c49e95 241
phungductung 0:e87aa4c49e95 242 /* Check NAND interrupt Level flag */
phungductung 0:e87aa4c49e95 243 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
phungductung 0:e87aa4c49e95 244 {
phungductung 0:e87aa4c49e95 245 /* NAND interrupt callback*/
phungductung 0:e87aa4c49e95 246 HAL_NAND_ITCallback(hnand);
phungductung 0:e87aa4c49e95 247
phungductung 0:e87aa4c49e95 248 /* Clear NAND interrupt Level pending bit */
phungductung 0:e87aa4c49e95 249 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
phungductung 0:e87aa4c49e95 250 }
phungductung 0:e87aa4c49e95 251
phungductung 0:e87aa4c49e95 252 /* Check NAND interrupt Falling edge flag */
phungductung 0:e87aa4c49e95 253 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
phungductung 0:e87aa4c49e95 254 {
phungductung 0:e87aa4c49e95 255 /* NAND interrupt callback*/
phungductung 0:e87aa4c49e95 256 HAL_NAND_ITCallback(hnand);
phungductung 0:e87aa4c49e95 257
phungductung 0:e87aa4c49e95 258 /* Clear NAND interrupt Falling edge pending bit */
phungductung 0:e87aa4c49e95 259 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
phungductung 0:e87aa4c49e95 260 }
phungductung 0:e87aa4c49e95 261
phungductung 0:e87aa4c49e95 262 /* Check NAND interrupt FIFO empty flag */
phungductung 0:e87aa4c49e95 263 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
phungductung 0:e87aa4c49e95 264 {
phungductung 0:e87aa4c49e95 265 /* NAND interrupt callback*/
phungductung 0:e87aa4c49e95 266 HAL_NAND_ITCallback(hnand);
phungductung 0:e87aa4c49e95 267
phungductung 0:e87aa4c49e95 268 /* Clear NAND interrupt FIFO empty pending bit */
phungductung 0:e87aa4c49e95 269 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
phungductung 0:e87aa4c49e95 270 }
phungductung 0:e87aa4c49e95 271
phungductung 0:e87aa4c49e95 272 }
phungductung 0:e87aa4c49e95 273
phungductung 0:e87aa4c49e95 274 /**
phungductung 0:e87aa4c49e95 275 * @brief NAND interrupt feature callback
phungductung 0:e87aa4c49e95 276 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 277 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 278 * @retval None
phungductung 0:e87aa4c49e95 279 */
phungductung 0:e87aa4c49e95 280 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 281 {
phungductung 0:e87aa4c49e95 282 /* Prevent unused argument(s) compilation warning */
phungductung 0:e87aa4c49e95 283 UNUSED(hnand);
phungductung 0:e87aa4c49e95 284
phungductung 0:e87aa4c49e95 285 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:e87aa4c49e95 286 the HAL_NAND_ITCallback could be implemented in the user file
phungductung 0:e87aa4c49e95 287 */
phungductung 0:e87aa4c49e95 288 }
phungductung 0:e87aa4c49e95 289
phungductung 0:e87aa4c49e95 290 /**
phungductung 0:e87aa4c49e95 291 * @}
phungductung 0:e87aa4c49e95 292 */
phungductung 0:e87aa4c49e95 293
phungductung 0:e87aa4c49e95 294 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
phungductung 0:e87aa4c49e95 295 * @brief Input Output and memory control functions
phungductung 0:e87aa4c49e95 296 *
phungductung 0:e87aa4c49e95 297 @verbatim
phungductung 0:e87aa4c49e95 298 ==============================================================================
phungductung 0:e87aa4c49e95 299 ##### NAND Input and Output functions #####
phungductung 0:e87aa4c49e95 300 ==============================================================================
phungductung 0:e87aa4c49e95 301 [..]
phungductung 0:e87aa4c49e95 302 This section provides functions allowing to use and control the NAND
phungductung 0:e87aa4c49e95 303 memory
phungductung 0:e87aa4c49e95 304
phungductung 0:e87aa4c49e95 305 @endverbatim
phungductung 0:e87aa4c49e95 306 * @{
phungductung 0:e87aa4c49e95 307 */
phungductung 0:e87aa4c49e95 308
phungductung 0:e87aa4c49e95 309 /**
phungductung 0:e87aa4c49e95 310 * @brief Read the NAND memory electronic signature
phungductung 0:e87aa4c49e95 311 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 312 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 313 * @param pNAND_ID: NAND ID structure
phungductung 0:e87aa4c49e95 314 * @retval HAL status
phungductung 0:e87aa4c49e95 315 */
phungductung 0:e87aa4c49e95 316 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
phungductung 0:e87aa4c49e95 317 {
phungductung 0:e87aa4c49e95 318 __IO uint32_t data = 0;
phungductung 0:e87aa4c49e95 319 uint32_t deviceAddress = 0;
phungductung 0:e87aa4c49e95 320
phungductung 0:e87aa4c49e95 321 /* Process Locked */
phungductung 0:e87aa4c49e95 322 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 323
phungductung 0:e87aa4c49e95 324 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 325 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 326 {
phungductung 0:e87aa4c49e95 327 return HAL_BUSY;
phungductung 0:e87aa4c49e95 328 }
phungductung 0:e87aa4c49e95 329
phungductung 0:e87aa4c49e95 330 /* Identify the device address */
phungductung 0:e87aa4c49e95 331 deviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 332
phungductung 0:e87aa4c49e95 333 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 334 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 335
phungductung 0:e87aa4c49e95 336 /* Send Read ID command sequence */
phungductung 0:e87aa4c49e95 337 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
phungductung 0:e87aa4c49e95 338 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:e87aa4c49e95 339
phungductung 0:e87aa4c49e95 340 /* Read the electronic signature from NAND flash */
phungductung 0:e87aa4c49e95 341 data = *(__IO uint32_t *)deviceAddress;
phungductung 0:e87aa4c49e95 342
phungductung 0:e87aa4c49e95 343 /* Return the data read */
phungductung 0:e87aa4c49e95 344 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
phungductung 0:e87aa4c49e95 345 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
phungductung 0:e87aa4c49e95 346 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
phungductung 0:e87aa4c49e95 347 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
phungductung 0:e87aa4c49e95 348
phungductung 0:e87aa4c49e95 349 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 350 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 351
phungductung 0:e87aa4c49e95 352 /* Process unlocked */
phungductung 0:e87aa4c49e95 353 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 354
phungductung 0:e87aa4c49e95 355 return HAL_OK;
phungductung 0:e87aa4c49e95 356 }
phungductung 0:e87aa4c49e95 357
phungductung 0:e87aa4c49e95 358 /**
phungductung 0:e87aa4c49e95 359 * @brief NAND memory reset
phungductung 0:e87aa4c49e95 360 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 361 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 362 * @retval HAL status
phungductung 0:e87aa4c49e95 363 */
phungductung 0:e87aa4c49e95 364 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 365 {
phungductung 0:e87aa4c49e95 366 uint32_t deviceAddress = 0;
phungductung 0:e87aa4c49e95 367
phungductung 0:e87aa4c49e95 368 /* Process Locked */
phungductung 0:e87aa4c49e95 369 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 370
phungductung 0:e87aa4c49e95 371 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 372 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 373 {
phungductung 0:e87aa4c49e95 374 return HAL_BUSY;
phungductung 0:e87aa4c49e95 375 }
phungductung 0:e87aa4c49e95 376
phungductung 0:e87aa4c49e95 377 /* Identify the device address */
phungductung 0:e87aa4c49e95 378 deviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 379
phungductung 0:e87aa4c49e95 380 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 381 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 382
phungductung 0:e87aa4c49e95 383 /* Send NAND reset command */
phungductung 0:e87aa4c49e95 384 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
phungductung 0:e87aa4c49e95 385
phungductung 0:e87aa4c49e95 386
phungductung 0:e87aa4c49e95 387 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 388 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 389
phungductung 0:e87aa4c49e95 390 /* Process unlocked */
phungductung 0:e87aa4c49e95 391 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 392
phungductung 0:e87aa4c49e95 393 return HAL_OK;
phungductung 0:e87aa4c49e95 394
phungductung 0:e87aa4c49e95 395 }
phungductung 0:e87aa4c49e95 396
phungductung 0:e87aa4c49e95 397 /**
phungductung 0:e87aa4c49e95 398 * @brief Read Page(s) from NAND memory block
phungductung 0:e87aa4c49e95 399 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 400 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 401 * @param pAddress : pointer to NAND address structure
phungductung 0:e87aa4c49e95 402 * @param pBuffer : pointer to destination read buffer
phungductung 0:e87aa4c49e95 403 * @param NumPageToRead : number of pages to read from block
phungductung 0:e87aa4c49e95 404 * @retval HAL status
phungductung 0:e87aa4c49e95 405 */
phungductung 0:e87aa4c49e95 406 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
phungductung 0:e87aa4c49e95 407 {
phungductung 0:e87aa4c49e95 408 __IO uint32_t index = 0;
phungductung 0:e87aa4c49e95 409 uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
phungductung 0:e87aa4c49e95 410
phungductung 0:e87aa4c49e95 411 /* Process Locked */
phungductung 0:e87aa4c49e95 412 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 413
phungductung 0:e87aa4c49e95 414 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 415 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 416 {
phungductung 0:e87aa4c49e95 417 return HAL_BUSY;
phungductung 0:e87aa4c49e95 418 }
phungductung 0:e87aa4c49e95 419
phungductung 0:e87aa4c49e95 420 /* Identify the device address */
phungductung 0:e87aa4c49e95 421 deviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 422
phungductung 0:e87aa4c49e95 423 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 424 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 425
phungductung 0:e87aa4c49e95 426 /* NAND raw address calculation */
phungductung 0:e87aa4c49e95 427 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:e87aa4c49e95 428
phungductung 0:e87aa4c49e95 429 /* Page(s) read loop */
phungductung 0:e87aa4c49e95 430 while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
phungductung 0:e87aa4c49e95 431 {
phungductung 0:e87aa4c49e95 432 /* update the buffer size */
phungductung 0:e87aa4c49e95 433 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
phungductung 0:e87aa4c49e95 434
phungductung 0:e87aa4c49e95 435 /* Send read page command sequence */
phungductung 0:e87aa4c49e95 436 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
phungductung 0:e87aa4c49e95 437
phungductung 0:e87aa4c49e95 438 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:e87aa4c49e95 439 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 440 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 441 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 442
phungductung 0:e87aa4c49e95 443 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:e87aa4c49e95 444 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:e87aa4c49e95 445 {
phungductung 0:e87aa4c49e95 446 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 447 }
phungductung 0:e87aa4c49e95 448
phungductung 0:e87aa4c49e95 449 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
phungductung 0:e87aa4c49e95 450
phungductung 0:e87aa4c49e95 451 /* Get Data into Buffer */
phungductung 0:e87aa4c49e95 452 for(index = 0; index < size; index++)
phungductung 0:e87aa4c49e95 453 {
phungductung 0:e87aa4c49e95 454 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
phungductung 0:e87aa4c49e95 455 }
phungductung 0:e87aa4c49e95 456
phungductung 0:e87aa4c49e95 457 /* Increment read pages number */
phungductung 0:e87aa4c49e95 458 numPagesRead++;
phungductung 0:e87aa4c49e95 459
phungductung 0:e87aa4c49e95 460 /* Decrement pages to read */
phungductung 0:e87aa4c49e95 461 NumPageToRead--;
phungductung 0:e87aa4c49e95 462
phungductung 0:e87aa4c49e95 463 /* Increment the NAND address */
phungductung 0:e87aa4c49e95 464 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
phungductung 0:e87aa4c49e95 465
phungductung 0:e87aa4c49e95 466 }
phungductung 0:e87aa4c49e95 467
phungductung 0:e87aa4c49e95 468 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 469 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 470
phungductung 0:e87aa4c49e95 471 /* Process unlocked */
phungductung 0:e87aa4c49e95 472 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 473
phungductung 0:e87aa4c49e95 474 return HAL_OK;
phungductung 0:e87aa4c49e95 475
phungductung 0:e87aa4c49e95 476 }
phungductung 0:e87aa4c49e95 477
phungductung 0:e87aa4c49e95 478 /**
phungductung 0:e87aa4c49e95 479 * @brief Write Page(s) to NAND memory block
phungductung 0:e87aa4c49e95 480 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 481 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 482 * @param pAddress : pointer to NAND address structure
phungductung 0:e87aa4c49e95 483 * @param pBuffer : pointer to source buffer to write
phungductung 0:e87aa4c49e95 484 * @param NumPageToWrite : number of pages to write to block
phungductung 0:e87aa4c49e95 485 * @retval HAL status
phungductung 0:e87aa4c49e95 486 */
phungductung 0:e87aa4c49e95 487 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
phungductung 0:e87aa4c49e95 488 {
phungductung 0:e87aa4c49e95 489 __IO uint32_t index = 0;
phungductung 0:e87aa4c49e95 490 uint32_t tickstart = 0;
phungductung 0:e87aa4c49e95 491 uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
phungductung 0:e87aa4c49e95 492
phungductung 0:e87aa4c49e95 493 /* Process Locked */
phungductung 0:e87aa4c49e95 494 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 495
phungductung 0:e87aa4c49e95 496 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 497 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 498 {
phungductung 0:e87aa4c49e95 499 return HAL_BUSY;
phungductung 0:e87aa4c49e95 500 }
phungductung 0:e87aa4c49e95 501
phungductung 0:e87aa4c49e95 502 /* Identify the device address */
phungductung 0:e87aa4c49e95 503 deviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 504
phungductung 0:e87aa4c49e95 505 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 506 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 507
phungductung 0:e87aa4c49e95 508 /* NAND raw address calculation */
phungductung 0:e87aa4c49e95 509 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:e87aa4c49e95 510
phungductung 0:e87aa4c49e95 511 /* Page(s) write loop */
phungductung 0:e87aa4c49e95 512 while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
phungductung 0:e87aa4c49e95 513 {
phungductung 0:e87aa4c49e95 514 /* update the buffer size */
phungductung 0:e87aa4c49e95 515 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
phungductung 0:e87aa4c49e95 516
phungductung 0:e87aa4c49e95 517 /* Send write page command sequence */
phungductung 0:e87aa4c49e95 518 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
phungductung 0:e87aa4c49e95 519 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
phungductung 0:e87aa4c49e95 520
phungductung 0:e87aa4c49e95 521 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:e87aa4c49e95 522 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 523 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 524 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 525 __DSB();
phungductung 0:e87aa4c49e95 526
phungductung 0:e87aa4c49e95 527 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:e87aa4c49e95 528 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:e87aa4c49e95 529 {
phungductung 0:e87aa4c49e95 530 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 531 __DSB();
phungductung 0:e87aa4c49e95 532 }
phungductung 0:e87aa4c49e95 533
phungductung 0:e87aa4c49e95 534 /* Write data to memory */
phungductung 0:e87aa4c49e95 535 for(index = 0; index < size; index++)
phungductung 0:e87aa4c49e95 536 {
phungductung 0:e87aa4c49e95 537 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
phungductung 0:e87aa4c49e95 538 __DSB();
phungductung 0:e87aa4c49e95 539 }
phungductung 0:e87aa4c49e95 540
phungductung 0:e87aa4c49e95 541 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
phungductung 0:e87aa4c49e95 542
phungductung 0:e87aa4c49e95 543 /* Read status until NAND is ready */
phungductung 0:e87aa4c49e95 544 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
phungductung 0:e87aa4c49e95 545 {
phungductung 0:e87aa4c49e95 546 /* Get tick */
phungductung 0:e87aa4c49e95 547 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 548
phungductung 0:e87aa4c49e95 549 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
phungductung 0:e87aa4c49e95 550 {
phungductung 0:e87aa4c49e95 551 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 552 }
phungductung 0:e87aa4c49e95 553 }
phungductung 0:e87aa4c49e95 554
phungductung 0:e87aa4c49e95 555 /* Increment written pages number */
phungductung 0:e87aa4c49e95 556 numPagesWritten++;
phungductung 0:e87aa4c49e95 557
phungductung 0:e87aa4c49e95 558 /* Decrement pages to write */
phungductung 0:e87aa4c49e95 559 NumPageToWrite--;
phungductung 0:e87aa4c49e95 560
phungductung 0:e87aa4c49e95 561 /* Increment the NAND address */
phungductung 0:e87aa4c49e95 562 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
phungductung 0:e87aa4c49e95 563 }
phungductung 0:e87aa4c49e95 564
phungductung 0:e87aa4c49e95 565 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 566 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 567
phungductung 0:e87aa4c49e95 568 /* Process unlocked */
phungductung 0:e87aa4c49e95 569 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 570
phungductung 0:e87aa4c49e95 571 return HAL_OK;
phungductung 0:e87aa4c49e95 572 }
phungductung 0:e87aa4c49e95 573
phungductung 0:e87aa4c49e95 574 /**
phungductung 0:e87aa4c49e95 575 * @brief Read Spare area(s) from NAND memory
phungductung 0:e87aa4c49e95 576 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 577 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 578 * @param pAddress : pointer to NAND address structure
phungductung 0:e87aa4c49e95 579 * @param pBuffer: pointer to source buffer to write
phungductung 0:e87aa4c49e95 580 * @param NumSpareAreaToRead: Number of spare area to read
phungductung 0:e87aa4c49e95 581 * @retval HAL status
phungductung 0:e87aa4c49e95 582 */
phungductung 0:e87aa4c49e95 583 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
phungductung 0:e87aa4c49e95 584 {
phungductung 0:e87aa4c49e95 585 __IO uint32_t index = 0;
phungductung 0:e87aa4c49e95 586 uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
phungductung 0:e87aa4c49e95 587
phungductung 0:e87aa4c49e95 588 /* Process Locked */
phungductung 0:e87aa4c49e95 589 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 590
phungductung 0:e87aa4c49e95 591 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 592 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 593 {
phungductung 0:e87aa4c49e95 594 return HAL_BUSY;
phungductung 0:e87aa4c49e95 595 }
phungductung 0:e87aa4c49e95 596
phungductung 0:e87aa4c49e95 597 /* Identify the device address */
phungductung 0:e87aa4c49e95 598 deviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 599
phungductung 0:e87aa4c49e95 600 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 601 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 602
phungductung 0:e87aa4c49e95 603 /* NAND raw address calculation */
phungductung 0:e87aa4c49e95 604 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:e87aa4c49e95 605
phungductung 0:e87aa4c49e95 606 /* Spare area(s) read loop */
phungductung 0:e87aa4c49e95 607 while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
phungductung 0:e87aa4c49e95 608 {
phungductung 0:e87aa4c49e95 609
phungductung 0:e87aa4c49e95 610 /* update the buffer size */
phungductung 0:e87aa4c49e95 611 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
phungductung 0:e87aa4c49e95 612
phungductung 0:e87aa4c49e95 613 /* Send read spare area command sequence */
phungductung 0:e87aa4c49e95 614 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
phungductung 0:e87aa4c49e95 615
phungductung 0:e87aa4c49e95 616 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:e87aa4c49e95 617 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 618 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 619 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 620
phungductung 0:e87aa4c49e95 621 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:e87aa4c49e95 622 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:e87aa4c49e95 623 {
phungductung 0:e87aa4c49e95 624 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 625 }
phungductung 0:e87aa4c49e95 626
phungductung 0:e87aa4c49e95 627 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
phungductung 0:e87aa4c49e95 628
phungductung 0:e87aa4c49e95 629 /* Get Data into Buffer */
phungductung 0:e87aa4c49e95 630 for(index = 0; index < size; index++)
phungductung 0:e87aa4c49e95 631 {
phungductung 0:e87aa4c49e95 632 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
phungductung 0:e87aa4c49e95 633 }
phungductung 0:e87aa4c49e95 634
phungductung 0:e87aa4c49e95 635 /* Increment read spare areas number */
phungductung 0:e87aa4c49e95 636 numSpareAreaRead++;
phungductung 0:e87aa4c49e95 637
phungductung 0:e87aa4c49e95 638 /* Decrement spare areas to read */
phungductung 0:e87aa4c49e95 639 NumSpareAreaToRead--;
phungductung 0:e87aa4c49e95 640
phungductung 0:e87aa4c49e95 641 /* Increment the NAND address */
phungductung 0:e87aa4c49e95 642 nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
phungductung 0:e87aa4c49e95 643 }
phungductung 0:e87aa4c49e95 644
phungductung 0:e87aa4c49e95 645 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 646 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 647
phungductung 0:e87aa4c49e95 648 /* Process unlocked */
phungductung 0:e87aa4c49e95 649 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 650
phungductung 0:e87aa4c49e95 651 return HAL_OK;
phungductung 0:e87aa4c49e95 652 }
phungductung 0:e87aa4c49e95 653
phungductung 0:e87aa4c49e95 654 /**
phungductung 0:e87aa4c49e95 655 * @brief Write Spare area(s) to NAND memory
phungductung 0:e87aa4c49e95 656 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 657 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 658 * @param pAddress : pointer to NAND address structure
phungductung 0:e87aa4c49e95 659 * @param pBuffer : pointer to source buffer to write
phungductung 0:e87aa4c49e95 660 * @param NumSpareAreaTowrite : number of spare areas to write to block
phungductung 0:e87aa4c49e95 661 * @retval HAL status
phungductung 0:e87aa4c49e95 662 */
phungductung 0:e87aa4c49e95 663 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
phungductung 0:e87aa4c49e95 664 {
phungductung 0:e87aa4c49e95 665 __IO uint32_t index = 0;
phungductung 0:e87aa4c49e95 666 uint32_t tickstart = 0;
phungductung 0:e87aa4c49e95 667 uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
phungductung 0:e87aa4c49e95 668
phungductung 0:e87aa4c49e95 669 /* Process Locked */
phungductung 0:e87aa4c49e95 670 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 671
phungductung 0:e87aa4c49e95 672 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 673 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 674 {
phungductung 0:e87aa4c49e95 675 return HAL_BUSY;
phungductung 0:e87aa4c49e95 676 }
phungductung 0:e87aa4c49e95 677
phungductung 0:e87aa4c49e95 678 /* Identify the device address */
phungductung 0:e87aa4c49e95 679 deviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 680
phungductung 0:e87aa4c49e95 681 /* Update the FMC_NAND controller state */
phungductung 0:e87aa4c49e95 682 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 683
phungductung 0:e87aa4c49e95 684 /* NAND raw address calculation */
phungductung 0:e87aa4c49e95 685 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:e87aa4c49e95 686
phungductung 0:e87aa4c49e95 687 /* Spare area(s) write loop */
phungductung 0:e87aa4c49e95 688 while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
phungductung 0:e87aa4c49e95 689 {
phungductung 0:e87aa4c49e95 690 /* update the buffer size */
phungductung 0:e87aa4c49e95 691 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
phungductung 0:e87aa4c49e95 692
phungductung 0:e87aa4c49e95 693 /* Send write Spare area command sequence */
phungductung 0:e87aa4c49e95 694 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
phungductung 0:e87aa4c49e95 695 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
phungductung 0:e87aa4c49e95 696
phungductung 0:e87aa4c49e95 697 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:e87aa4c49e95 698 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 699 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 700 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 701 __DSB();
phungductung 0:e87aa4c49e95 702 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:e87aa4c49e95 703 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:e87aa4c49e95 704 {
phungductung 0:e87aa4c49e95 705 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:e87aa4c49e95 706 __DSB();
phungductung 0:e87aa4c49e95 707 }
phungductung 0:e87aa4c49e95 708
phungductung 0:e87aa4c49e95 709 /* Write data to memory */
phungductung 0:e87aa4c49e95 710 for(index = 0; index < size; index++)
phungductung 0:e87aa4c49e95 711 {
phungductung 0:e87aa4c49e95 712 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
phungductung 0:e87aa4c49e95 713 __DSB();
phungductung 0:e87aa4c49e95 714 }
phungductung 0:e87aa4c49e95 715
phungductung 0:e87aa4c49e95 716 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
phungductung 0:e87aa4c49e95 717 __DSB();
phungductung 0:e87aa4c49e95 718
phungductung 0:e87aa4c49e95 719 /* Read status until NAND is ready */
phungductung 0:e87aa4c49e95 720 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
phungductung 0:e87aa4c49e95 721 {
phungductung 0:e87aa4c49e95 722 /* Get tick */
phungductung 0:e87aa4c49e95 723 tickstart = HAL_GetTick();
phungductung 0:e87aa4c49e95 724
phungductung 0:e87aa4c49e95 725 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
phungductung 0:e87aa4c49e95 726 {
phungductung 0:e87aa4c49e95 727 return HAL_TIMEOUT;
phungductung 0:e87aa4c49e95 728 }
phungductung 0:e87aa4c49e95 729 }
phungductung 0:e87aa4c49e95 730
phungductung 0:e87aa4c49e95 731 /* Increment written spare areas number */
phungductung 0:e87aa4c49e95 732 numSpareAreaWritten++;
phungductung 0:e87aa4c49e95 733
phungductung 0:e87aa4c49e95 734 /* Decrement spare areas to write */
phungductung 0:e87aa4c49e95 735 NumSpareAreaTowrite--;
phungductung 0:e87aa4c49e95 736
phungductung 0:e87aa4c49e95 737 /* Increment the NAND address */
phungductung 0:e87aa4c49e95 738 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
phungductung 0:e87aa4c49e95 739 }
phungductung 0:e87aa4c49e95 740
phungductung 0:e87aa4c49e95 741 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 742 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 743
phungductung 0:e87aa4c49e95 744 /* Process unlocked */
phungductung 0:e87aa4c49e95 745 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 746
phungductung 0:e87aa4c49e95 747 return HAL_OK;
phungductung 0:e87aa4c49e95 748 }
phungductung 0:e87aa4c49e95 749
phungductung 0:e87aa4c49e95 750 /**
phungductung 0:e87aa4c49e95 751 * @brief NAND memory Block erase
phungductung 0:e87aa4c49e95 752 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 753 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 754 * @param pAddress : pointer to NAND address structure
phungductung 0:e87aa4c49e95 755 * @retval HAL status
phungductung 0:e87aa4c49e95 756 */
phungductung 0:e87aa4c49e95 757 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
phungductung 0:e87aa4c49e95 758 {
phungductung 0:e87aa4c49e95 759 uint32_t DeviceAddress = 0;
phungductung 0:e87aa4c49e95 760
phungductung 0:e87aa4c49e95 761 /* Process Locked */
phungductung 0:e87aa4c49e95 762 __HAL_LOCK(hnand);
phungductung 0:e87aa4c49e95 763
phungductung 0:e87aa4c49e95 764 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 765 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 766 {
phungductung 0:e87aa4c49e95 767 return HAL_BUSY;
phungductung 0:e87aa4c49e95 768 }
phungductung 0:e87aa4c49e95 769
phungductung 0:e87aa4c49e95 770 /* Identify the device address */
phungductung 0:e87aa4c49e95 771 DeviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 772
phungductung 0:e87aa4c49e95 773 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 774 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 775
phungductung 0:e87aa4c49e95 776 /* Send Erase block command sequence */
phungductung 0:e87aa4c49e95 777 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
phungductung 0:e87aa4c49e95 778
phungductung 0:e87aa4c49e95 779 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:e87aa4c49e95 780 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:e87aa4c49e95 781 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:e87aa4c49e95 782 __DSB();
phungductung 0:e87aa4c49e95 783
phungductung 0:e87aa4c49e95 784 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:e87aa4c49e95 785 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:e87aa4c49e95 786 {
phungductung 0:e87aa4c49e95 787 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:e87aa4c49e95 788 __DSB();
phungductung 0:e87aa4c49e95 789 }
phungductung 0:e87aa4c49e95 790
phungductung 0:e87aa4c49e95 791 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
phungductung 0:e87aa4c49e95 792 __DSB();
phungductung 0:e87aa4c49e95 793
phungductung 0:e87aa4c49e95 794 /* Update the NAND controller state */
phungductung 0:e87aa4c49e95 795 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 796
phungductung 0:e87aa4c49e95 797 /* Process unlocked */
phungductung 0:e87aa4c49e95 798 __HAL_UNLOCK(hnand);
phungductung 0:e87aa4c49e95 799
phungductung 0:e87aa4c49e95 800 return HAL_OK;
phungductung 0:e87aa4c49e95 801 }
phungductung 0:e87aa4c49e95 802
phungductung 0:e87aa4c49e95 803 /**
phungductung 0:e87aa4c49e95 804 * @brief NAND memory read status
phungductung 0:e87aa4c49e95 805 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 806 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 807 * @retval NAND status
phungductung 0:e87aa4c49e95 808 */
phungductung 0:e87aa4c49e95 809 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 810 {
phungductung 0:e87aa4c49e95 811 uint32_t data = 0;
phungductung 0:e87aa4c49e95 812 uint32_t DeviceAddress = 0;
phungductung 0:e87aa4c49e95 813
phungductung 0:e87aa4c49e95 814 /* Identify the device address */
phungductung 0:e87aa4c49e95 815 DeviceAddress = NAND_DEVICE;
phungductung 0:e87aa4c49e95 816
phungductung 0:e87aa4c49e95 817 /* Send Read status operation command */
phungductung 0:e87aa4c49e95 818 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
phungductung 0:e87aa4c49e95 819
phungductung 0:e87aa4c49e95 820 /* Read status register data */
phungductung 0:e87aa4c49e95 821 data = *(__IO uint8_t *)DeviceAddress;
phungductung 0:e87aa4c49e95 822
phungductung 0:e87aa4c49e95 823 /* Return the status */
phungductung 0:e87aa4c49e95 824 if((data & NAND_ERROR) == NAND_ERROR)
phungductung 0:e87aa4c49e95 825 {
phungductung 0:e87aa4c49e95 826 return NAND_ERROR;
phungductung 0:e87aa4c49e95 827 }
phungductung 0:e87aa4c49e95 828 else if((data & NAND_READY) == NAND_READY)
phungductung 0:e87aa4c49e95 829 {
phungductung 0:e87aa4c49e95 830 return NAND_READY;
phungductung 0:e87aa4c49e95 831 }
phungductung 0:e87aa4c49e95 832
phungductung 0:e87aa4c49e95 833 return NAND_BUSY;
phungductung 0:e87aa4c49e95 834 }
phungductung 0:e87aa4c49e95 835
phungductung 0:e87aa4c49e95 836 /**
phungductung 0:e87aa4c49e95 837 * @brief Increment the NAND memory address
phungductung 0:e87aa4c49e95 838 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 839 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 840 * @param pAddress: pointer to NAND address structure
phungductung 0:e87aa4c49e95 841 * @retval The new status of the increment address operation. It can be:
phungductung 0:e87aa4c49e95 842 * - NAND_VALID_ADDRESS: When the new address is valid address
phungductung 0:e87aa4c49e95 843 * - NAND_INVALID_ADDRESS: When the new address is invalid address
phungductung 0:e87aa4c49e95 844 */
phungductung 0:e87aa4c49e95 845 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
phungductung 0:e87aa4c49e95 846 {
phungductung 0:e87aa4c49e95 847 uint32_t status = NAND_VALID_ADDRESS;
phungductung 0:e87aa4c49e95 848
phungductung 0:e87aa4c49e95 849 /* Increment page address */
phungductung 0:e87aa4c49e95 850 pAddress->Page++;
phungductung 0:e87aa4c49e95 851
phungductung 0:e87aa4c49e95 852 /* Check NAND address is valid */
phungductung 0:e87aa4c49e95 853 if(pAddress->Page == hnand->Info.BlockSize)
phungductung 0:e87aa4c49e95 854 {
phungductung 0:e87aa4c49e95 855 pAddress->Page = 0;
phungductung 0:e87aa4c49e95 856 pAddress->Block++;
phungductung 0:e87aa4c49e95 857
phungductung 0:e87aa4c49e95 858 if(pAddress->Block == hnand->Info.ZoneSize)
phungductung 0:e87aa4c49e95 859 {
phungductung 0:e87aa4c49e95 860 pAddress->Block = 0;
phungductung 0:e87aa4c49e95 861 pAddress->Zone++;
phungductung 0:e87aa4c49e95 862
phungductung 0:e87aa4c49e95 863 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
phungductung 0:e87aa4c49e95 864 {
phungductung 0:e87aa4c49e95 865 status = NAND_INVALID_ADDRESS;
phungductung 0:e87aa4c49e95 866 }
phungductung 0:e87aa4c49e95 867 }
phungductung 0:e87aa4c49e95 868 }
phungductung 0:e87aa4c49e95 869
phungductung 0:e87aa4c49e95 870 return (status);
phungductung 0:e87aa4c49e95 871 }
phungductung 0:e87aa4c49e95 872 /**
phungductung 0:e87aa4c49e95 873 * @}
phungductung 0:e87aa4c49e95 874 */
phungductung 0:e87aa4c49e95 875
phungductung 0:e87aa4c49e95 876 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
phungductung 0:e87aa4c49e95 877 * @brief management functions
phungductung 0:e87aa4c49e95 878 *
phungductung 0:e87aa4c49e95 879 @verbatim
phungductung 0:e87aa4c49e95 880 ==============================================================================
phungductung 0:e87aa4c49e95 881 ##### NAND Control functions #####
phungductung 0:e87aa4c49e95 882 ==============================================================================
phungductung 0:e87aa4c49e95 883 [..]
phungductung 0:e87aa4c49e95 884 This subsection provides a set of functions allowing to control dynamically
phungductung 0:e87aa4c49e95 885 the NAND interface.
phungductung 0:e87aa4c49e95 886
phungductung 0:e87aa4c49e95 887 @endverbatim
phungductung 0:e87aa4c49e95 888 * @{
phungductung 0:e87aa4c49e95 889 */
phungductung 0:e87aa4c49e95 890
phungductung 0:e87aa4c49e95 891
phungductung 0:e87aa4c49e95 892 /**
phungductung 0:e87aa4c49e95 893 * @brief Enables dynamically NAND ECC feature.
phungductung 0:e87aa4c49e95 894 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 895 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 896 * @retval HAL status
phungductung 0:e87aa4c49e95 897 */
phungductung 0:e87aa4c49e95 898 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 899 {
phungductung 0:e87aa4c49e95 900 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 901 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 902 {
phungductung 0:e87aa4c49e95 903 return HAL_BUSY;
phungductung 0:e87aa4c49e95 904 }
phungductung 0:e87aa4c49e95 905
phungductung 0:e87aa4c49e95 906 /* Update the NAND state */
phungductung 0:e87aa4c49e95 907 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 908
phungductung 0:e87aa4c49e95 909 /* Enable ECC feature */
phungductung 0:e87aa4c49e95 910 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
phungductung 0:e87aa4c49e95 911
phungductung 0:e87aa4c49e95 912 /* Update the NAND state */
phungductung 0:e87aa4c49e95 913 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 914
phungductung 0:e87aa4c49e95 915 return HAL_OK;
phungductung 0:e87aa4c49e95 916 }
phungductung 0:e87aa4c49e95 917
phungductung 0:e87aa4c49e95 918 /**
phungductung 0:e87aa4c49e95 919 * @brief Disables dynamically FMC_NAND ECC feature.
phungductung 0:e87aa4c49e95 920 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 921 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 922 * @retval HAL status
phungductung 0:e87aa4c49e95 923 */
phungductung 0:e87aa4c49e95 924 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 925 {
phungductung 0:e87aa4c49e95 926 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 927 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 928 {
phungductung 0:e87aa4c49e95 929 return HAL_BUSY;
phungductung 0:e87aa4c49e95 930 }
phungductung 0:e87aa4c49e95 931
phungductung 0:e87aa4c49e95 932 /* Update the NAND state */
phungductung 0:e87aa4c49e95 933 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 934
phungductung 0:e87aa4c49e95 935 /* Disable ECC feature */
phungductung 0:e87aa4c49e95 936 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
phungductung 0:e87aa4c49e95 937
phungductung 0:e87aa4c49e95 938 /* Update the NAND state */
phungductung 0:e87aa4c49e95 939 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 940
phungductung 0:e87aa4c49e95 941 return HAL_OK;
phungductung 0:e87aa4c49e95 942 }
phungductung 0:e87aa4c49e95 943
phungductung 0:e87aa4c49e95 944 /**
phungductung 0:e87aa4c49e95 945 * @brief Disables dynamically NAND ECC feature.
phungductung 0:e87aa4c49e95 946 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 947 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 948 * @param ECCval: pointer to ECC value
phungductung 0:e87aa4c49e95 949 * @param Timeout: maximum timeout to wait
phungductung 0:e87aa4c49e95 950 * @retval HAL status
phungductung 0:e87aa4c49e95 951 */
phungductung 0:e87aa4c49e95 952 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
phungductung 0:e87aa4c49e95 953 {
phungductung 0:e87aa4c49e95 954 HAL_StatusTypeDef status = HAL_OK;
phungductung 0:e87aa4c49e95 955
phungductung 0:e87aa4c49e95 956 /* Check the NAND controller state */
phungductung 0:e87aa4c49e95 957 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:e87aa4c49e95 958 {
phungductung 0:e87aa4c49e95 959 return HAL_BUSY;
phungductung 0:e87aa4c49e95 960 }
phungductung 0:e87aa4c49e95 961
phungductung 0:e87aa4c49e95 962 /* Update the NAND state */
phungductung 0:e87aa4c49e95 963 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:e87aa4c49e95 964
phungductung 0:e87aa4c49e95 965 /* Get NAND ECC value */
phungductung 0:e87aa4c49e95 966 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
phungductung 0:e87aa4c49e95 967
phungductung 0:e87aa4c49e95 968 /* Update the NAND state */
phungductung 0:e87aa4c49e95 969 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:e87aa4c49e95 970
phungductung 0:e87aa4c49e95 971 return status;
phungductung 0:e87aa4c49e95 972 }
phungductung 0:e87aa4c49e95 973
phungductung 0:e87aa4c49e95 974 /**
phungductung 0:e87aa4c49e95 975 * @}
phungductung 0:e87aa4c49e95 976 */
phungductung 0:e87aa4c49e95 977
phungductung 0:e87aa4c49e95 978
phungductung 0:e87aa4c49e95 979 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
phungductung 0:e87aa4c49e95 980 * @brief Peripheral State functions
phungductung 0:e87aa4c49e95 981 *
phungductung 0:e87aa4c49e95 982 @verbatim
phungductung 0:e87aa4c49e95 983 ==============================================================================
phungductung 0:e87aa4c49e95 984 ##### NAND State functions #####
phungductung 0:e87aa4c49e95 985 ==============================================================================
phungductung 0:e87aa4c49e95 986 [..]
phungductung 0:e87aa4c49e95 987 This subsection permits to get in run-time the status of the NAND controller
phungductung 0:e87aa4c49e95 988 and the data flow.
phungductung 0:e87aa4c49e95 989
phungductung 0:e87aa4c49e95 990 @endverbatim
phungductung 0:e87aa4c49e95 991 * @{
phungductung 0:e87aa4c49e95 992 */
phungductung 0:e87aa4c49e95 993
phungductung 0:e87aa4c49e95 994 /**
phungductung 0:e87aa4c49e95 995 * @brief return the NAND state
phungductung 0:e87aa4c49e95 996 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:e87aa4c49e95 997 * the configuration information for NAND module.
phungductung 0:e87aa4c49e95 998 * @retval HAL state
phungductung 0:e87aa4c49e95 999 */
phungductung 0:e87aa4c49e95 1000 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
phungductung 0:e87aa4c49e95 1001 {
phungductung 0:e87aa4c49e95 1002 return hnand->State;
phungductung 0:e87aa4c49e95 1003 }
phungductung 0:e87aa4c49e95 1004
phungductung 0:e87aa4c49e95 1005 /**
phungductung 0:e87aa4c49e95 1006 * @}
phungductung 0:e87aa4c49e95 1007 */
phungductung 0:e87aa4c49e95 1008
phungductung 0:e87aa4c49e95 1009 /**
phungductung 0:e87aa4c49e95 1010 * @}
phungductung 0:e87aa4c49e95 1011 */
phungductung 0:e87aa4c49e95 1012
phungductung 0:e87aa4c49e95 1013 #endif /* HAL_NAND_MODULE_ENABLED */
phungductung 0:e87aa4c49e95 1014
phungductung 0:e87aa4c49e95 1015 /**
phungductung 0:e87aa4c49e95 1016 * @}
phungductung 0:e87aa4c49e95 1017 */
phungductung 0:e87aa4c49e95 1018
phungductung 0:e87aa4c49e95 1019 /**
phungductung 0:e87aa4c49e95 1020 * @}
phungductung 0:e87aa4c49e95 1021 */
phungductung 0:e87aa4c49e95 1022
phungductung 0:e87aa4c49e95 1023 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/