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SRC_STM32F7/targets/cmsis/core_cm3.h@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:37:21 2019 +0000
Revision:
0:8ede47d38d10
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phungductung 0:8ede47d38d10 1 /**************************************************************************//**
phungductung 0:8ede47d38d10 2 * @file core_cm3.h
phungductung 0:8ede47d38d10 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
phungductung 0:8ede47d38d10 4 * @version V4.10
phungductung 0:8ede47d38d10 5 * @date 18. March 2015
phungductung 0:8ede47d38d10 6 *
phungductung 0:8ede47d38d10 7 * @note
phungductung 0:8ede47d38d10 8 *
phungductung 0:8ede47d38d10 9 ******************************************************************************/
phungductung 0:8ede47d38d10 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
phungductung 0:8ede47d38d10 11
phungductung 0:8ede47d38d10 12 All rights reserved.
phungductung 0:8ede47d38d10 13 Redistribution and use in source and binary forms, with or without
phungductung 0:8ede47d38d10 14 modification, are permitted provided that the following conditions are met:
phungductung 0:8ede47d38d10 15 - Redistributions of source code must retain the above copyright
phungductung 0:8ede47d38d10 16 notice, this list of conditions and the following disclaimer.
phungductung 0:8ede47d38d10 17 - Redistributions in binary form must reproduce the above copyright
phungductung 0:8ede47d38d10 18 notice, this list of conditions and the following disclaimer in the
phungductung 0:8ede47d38d10 19 documentation and/or other materials provided with the distribution.
phungductung 0:8ede47d38d10 20 - Neither the name of ARM nor the names of its contributors may be used
phungductung 0:8ede47d38d10 21 to endorse or promote products derived from this software without
phungductung 0:8ede47d38d10 22 specific prior written permission.
phungductung 0:8ede47d38d10 23 *
phungductung 0:8ede47d38d10 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:8ede47d38d10 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:8ede47d38d10 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
phungductung 0:8ede47d38d10 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
phungductung 0:8ede47d38d10 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
phungductung 0:8ede47d38d10 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
phungductung 0:8ede47d38d10 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
phungductung 0:8ede47d38d10 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
phungductung 0:8ede47d38d10 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
phungductung 0:8ede47d38d10 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
phungductung 0:8ede47d38d10 34 POSSIBILITY OF SUCH DAMAGE.
phungductung 0:8ede47d38d10 35 ---------------------------------------------------------------------------*/
phungductung 0:8ede47d38d10 36
phungductung 0:8ede47d38d10 37
phungductung 0:8ede47d38d10 38 #if defined ( __ICCARM__ )
phungductung 0:8ede47d38d10 39 #pragma system_include /* treat file as system include file for MISRA check */
phungductung 0:8ede47d38d10 40 #endif
phungductung 0:8ede47d38d10 41
phungductung 0:8ede47d38d10 42 #ifndef __CORE_CM3_H_GENERIC
phungductung 0:8ede47d38d10 43 #define __CORE_CM3_H_GENERIC
phungductung 0:8ede47d38d10 44
phungductung 0:8ede47d38d10 45 #ifdef __cplusplus
phungductung 0:8ede47d38d10 46 extern "C" {
phungductung 0:8ede47d38d10 47 #endif
phungductung 0:8ede47d38d10 48
phungductung 0:8ede47d38d10 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
phungductung 0:8ede47d38d10 50 CMSIS violates the following MISRA-C:2004 rules:
phungductung 0:8ede47d38d10 51
phungductung 0:8ede47d38d10 52 \li Required Rule 8.5, object/function definition in header file.<br>
phungductung 0:8ede47d38d10 53 Function definitions in header files are used to allow 'inlining'.
phungductung 0:8ede47d38d10 54
phungductung 0:8ede47d38d10 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
phungductung 0:8ede47d38d10 56 Unions are used for effective representation of core registers.
phungductung 0:8ede47d38d10 57
phungductung 0:8ede47d38d10 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
phungductung 0:8ede47d38d10 59 Function-like macros are used to allow more efficient code.
phungductung 0:8ede47d38d10 60 */
phungductung 0:8ede47d38d10 61
phungductung 0:8ede47d38d10 62
phungductung 0:8ede47d38d10 63 /*******************************************************************************
phungductung 0:8ede47d38d10 64 * CMSIS definitions
phungductung 0:8ede47d38d10 65 ******************************************************************************/
phungductung 0:8ede47d38d10 66 /** \ingroup Cortex_M3
phungductung 0:8ede47d38d10 67 @{
phungductung 0:8ede47d38d10 68 */
phungductung 0:8ede47d38d10 69
phungductung 0:8ede47d38d10 70 /* CMSIS CM3 definitions */
phungductung 0:8ede47d38d10 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
phungductung 0:8ede47d38d10 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
phungductung 0:8ede47d38d10 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
phungductung 0:8ede47d38d10 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
phungductung 0:8ede47d38d10 75
phungductung 0:8ede47d38d10 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
phungductung 0:8ede47d38d10 77
phungductung 0:8ede47d38d10 78
phungductung 0:8ede47d38d10 79 #if defined ( __CC_ARM )
phungductung 0:8ede47d38d10 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
phungductung 0:8ede47d38d10 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
phungductung 0:8ede47d38d10 82 #define __STATIC_INLINE static __inline
phungductung 0:8ede47d38d10 83
phungductung 0:8ede47d38d10 84 #elif defined ( __GNUC__ )
phungductung 0:8ede47d38d10 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
phungductung 0:8ede47d38d10 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
phungductung 0:8ede47d38d10 87 #define __STATIC_INLINE static inline
phungductung 0:8ede47d38d10 88
phungductung 0:8ede47d38d10 89 #elif defined ( __ICCARM__ )
phungductung 0:8ede47d38d10 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
phungductung 0:8ede47d38d10 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
phungductung 0:8ede47d38d10 92 #define __STATIC_INLINE static inline
phungductung 0:8ede47d38d10 93
phungductung 0:8ede47d38d10 94 #elif defined ( __TMS470__ )
phungductung 0:8ede47d38d10 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
phungductung 0:8ede47d38d10 96 #define __STATIC_INLINE static inline
phungductung 0:8ede47d38d10 97
phungductung 0:8ede47d38d10 98 #elif defined ( __TASKING__ )
phungductung 0:8ede47d38d10 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
phungductung 0:8ede47d38d10 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
phungductung 0:8ede47d38d10 101 #define __STATIC_INLINE static inline
phungductung 0:8ede47d38d10 102
phungductung 0:8ede47d38d10 103 #elif defined ( __CSMC__ )
phungductung 0:8ede47d38d10 104 #define __packed
phungductung 0:8ede47d38d10 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
phungductung 0:8ede47d38d10 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
phungductung 0:8ede47d38d10 107 #define __STATIC_INLINE static inline
phungductung 0:8ede47d38d10 108
phungductung 0:8ede47d38d10 109 #endif
phungductung 0:8ede47d38d10 110
phungductung 0:8ede47d38d10 111 /** __FPU_USED indicates whether an FPU is used or not.
phungductung 0:8ede47d38d10 112 This core does not support an FPU at all
phungductung 0:8ede47d38d10 113 */
phungductung 0:8ede47d38d10 114 #define __FPU_USED 0
phungductung 0:8ede47d38d10 115
phungductung 0:8ede47d38d10 116 #if defined ( __CC_ARM )
phungductung 0:8ede47d38d10 117 #if defined __TARGET_FPU_VFP
phungductung 0:8ede47d38d10 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:8ede47d38d10 119 #endif
phungductung 0:8ede47d38d10 120
phungductung 0:8ede47d38d10 121 #elif defined ( __GNUC__ )
phungductung 0:8ede47d38d10 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
phungductung 0:8ede47d38d10 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:8ede47d38d10 124 #endif
phungductung 0:8ede47d38d10 125
phungductung 0:8ede47d38d10 126 #elif defined ( __ICCARM__ )
phungductung 0:8ede47d38d10 127 #if defined __ARMVFP__
phungductung 0:8ede47d38d10 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:8ede47d38d10 129 #endif
phungductung 0:8ede47d38d10 130
phungductung 0:8ede47d38d10 131 #elif defined ( __TMS470__ )
phungductung 0:8ede47d38d10 132 #if defined __TI__VFP_SUPPORT____
phungductung 0:8ede47d38d10 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:8ede47d38d10 134 #endif
phungductung 0:8ede47d38d10 135
phungductung 0:8ede47d38d10 136 #elif defined ( __TASKING__ )
phungductung 0:8ede47d38d10 137 #if defined __FPU_VFP__
phungductung 0:8ede47d38d10 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:8ede47d38d10 139 #endif
phungductung 0:8ede47d38d10 140
phungductung 0:8ede47d38d10 141 #elif defined ( __CSMC__ ) /* Cosmic */
phungductung 0:8ede47d38d10 142 #if ( __CSMC__ & 0x400) // FPU present for parser
phungductung 0:8ede47d38d10 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
phungductung 0:8ede47d38d10 144 #endif
phungductung 0:8ede47d38d10 145 #endif
phungductung 0:8ede47d38d10 146
phungductung 0:8ede47d38d10 147 #include <stdint.h> /* standard types definitions */
phungductung 0:8ede47d38d10 148 #include <core_cmInstr.h> /* Core Instruction Access */
phungductung 0:8ede47d38d10 149 #include <core_cmFunc.h> /* Core Function Access */
phungductung 0:8ede47d38d10 150
phungductung 0:8ede47d38d10 151 #ifdef __cplusplus
phungductung 0:8ede47d38d10 152 }
phungductung 0:8ede47d38d10 153 #endif
phungductung 0:8ede47d38d10 154
phungductung 0:8ede47d38d10 155 #endif /* __CORE_CM3_H_GENERIC */
phungductung 0:8ede47d38d10 156
phungductung 0:8ede47d38d10 157 #ifndef __CMSIS_GENERIC
phungductung 0:8ede47d38d10 158
phungductung 0:8ede47d38d10 159 #ifndef __CORE_CM3_H_DEPENDANT
phungductung 0:8ede47d38d10 160 #define __CORE_CM3_H_DEPENDANT
phungductung 0:8ede47d38d10 161
phungductung 0:8ede47d38d10 162 #ifdef __cplusplus
phungductung 0:8ede47d38d10 163 extern "C" {
phungductung 0:8ede47d38d10 164 #endif
phungductung 0:8ede47d38d10 165
phungductung 0:8ede47d38d10 166 /* check device defines and use defaults */
phungductung 0:8ede47d38d10 167 #if defined __CHECK_DEVICE_DEFINES
phungductung 0:8ede47d38d10 168 #ifndef __CM3_REV
phungductung 0:8ede47d38d10 169 #define __CM3_REV 0x0200
phungductung 0:8ede47d38d10 170 #warning "__CM3_REV not defined in device header file; using default!"
phungductung 0:8ede47d38d10 171 #endif
phungductung 0:8ede47d38d10 172
phungductung 0:8ede47d38d10 173 #ifndef __MPU_PRESENT
phungductung 0:8ede47d38d10 174 #define __MPU_PRESENT 0
phungductung 0:8ede47d38d10 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
phungductung 0:8ede47d38d10 176 #endif
phungductung 0:8ede47d38d10 177
phungductung 0:8ede47d38d10 178 #ifndef __NVIC_PRIO_BITS
phungductung 0:8ede47d38d10 179 #define __NVIC_PRIO_BITS 4
phungductung 0:8ede47d38d10 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
phungductung 0:8ede47d38d10 181 #endif
phungductung 0:8ede47d38d10 182
phungductung 0:8ede47d38d10 183 #ifndef __Vendor_SysTickConfig
phungductung 0:8ede47d38d10 184 #define __Vendor_SysTickConfig 0
phungductung 0:8ede47d38d10 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
phungductung 0:8ede47d38d10 186 #endif
phungductung 0:8ede47d38d10 187 #endif
phungductung 0:8ede47d38d10 188
phungductung 0:8ede47d38d10 189 /* IO definitions (access restrictions to peripheral registers) */
phungductung 0:8ede47d38d10 190 /**
phungductung 0:8ede47d38d10 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
phungductung 0:8ede47d38d10 192
phungductung 0:8ede47d38d10 193 <strong>IO Type Qualifiers</strong> are used
phungductung 0:8ede47d38d10 194 \li to specify the access to peripheral variables.
phungductung 0:8ede47d38d10 195 \li for automatic generation of peripheral register debug information.
phungductung 0:8ede47d38d10 196 */
phungductung 0:8ede47d38d10 197 #ifdef __cplusplus
phungductung 0:8ede47d38d10 198 #define __I volatile /*!< Defines 'read only' permissions */
phungductung 0:8ede47d38d10 199 #else
phungductung 0:8ede47d38d10 200 #define __I volatile const /*!< Defines 'read only' permissions */
phungductung 0:8ede47d38d10 201 #endif
phungductung 0:8ede47d38d10 202 #define __O volatile /*!< Defines 'write only' permissions */
phungductung 0:8ede47d38d10 203 #define __IO volatile /*!< Defines 'read / write' permissions */
phungductung 0:8ede47d38d10 204
phungductung 0:8ede47d38d10 205 /*@} end of group Cortex_M3 */
phungductung 0:8ede47d38d10 206
phungductung 0:8ede47d38d10 207
phungductung 0:8ede47d38d10 208
phungductung 0:8ede47d38d10 209 /*******************************************************************************
phungductung 0:8ede47d38d10 210 * Register Abstraction
phungductung 0:8ede47d38d10 211 Core Register contain:
phungductung 0:8ede47d38d10 212 - Core Register
phungductung 0:8ede47d38d10 213 - Core NVIC Register
phungductung 0:8ede47d38d10 214 - Core SCB Register
phungductung 0:8ede47d38d10 215 - Core SysTick Register
phungductung 0:8ede47d38d10 216 - Core Debug Register
phungductung 0:8ede47d38d10 217 - Core MPU Register
phungductung 0:8ede47d38d10 218 ******************************************************************************/
phungductung 0:8ede47d38d10 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
phungductung 0:8ede47d38d10 220 \brief Type definitions and defines for Cortex-M processor based devices.
phungductung 0:8ede47d38d10 221 */
phungductung 0:8ede47d38d10 222
phungductung 0:8ede47d38d10 223 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 224 \defgroup CMSIS_CORE Status and Control Registers
phungductung 0:8ede47d38d10 225 \brief Core Register type definitions.
phungductung 0:8ede47d38d10 226 @{
phungductung 0:8ede47d38d10 227 */
phungductung 0:8ede47d38d10 228
phungductung 0:8ede47d38d10 229 /** \brief Union type to access the Application Program Status Register (APSR).
phungductung 0:8ede47d38d10 230 */
phungductung 0:8ede47d38d10 231 typedef union
phungductung 0:8ede47d38d10 232 {
phungductung 0:8ede47d38d10 233 struct
phungductung 0:8ede47d38d10 234 {
phungductung 0:8ede47d38d10 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
phungductung 0:8ede47d38d10 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
phungductung 0:8ede47d38d10 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
phungductung 0:8ede47d38d10 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
phungductung 0:8ede47d38d10 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
phungductung 0:8ede47d38d10 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
phungductung 0:8ede47d38d10 241 } b; /*!< Structure used for bit access */
phungductung 0:8ede47d38d10 242 uint32_t w; /*!< Type used for word access */
phungductung 0:8ede47d38d10 243 } APSR_Type;
phungductung 0:8ede47d38d10 244
phungductung 0:8ede47d38d10 245 /* APSR Register Definitions */
phungductung 0:8ede47d38d10 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
phungductung 0:8ede47d38d10 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
phungductung 0:8ede47d38d10 248
phungductung 0:8ede47d38d10 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
phungductung 0:8ede47d38d10 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
phungductung 0:8ede47d38d10 251
phungductung 0:8ede47d38d10 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
phungductung 0:8ede47d38d10 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
phungductung 0:8ede47d38d10 254
phungductung 0:8ede47d38d10 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
phungductung 0:8ede47d38d10 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
phungductung 0:8ede47d38d10 257
phungductung 0:8ede47d38d10 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
phungductung 0:8ede47d38d10 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
phungductung 0:8ede47d38d10 260
phungductung 0:8ede47d38d10 261
phungductung 0:8ede47d38d10 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
phungductung 0:8ede47d38d10 263 */
phungductung 0:8ede47d38d10 264 typedef union
phungductung 0:8ede47d38d10 265 {
phungductung 0:8ede47d38d10 266 struct
phungductung 0:8ede47d38d10 267 {
phungductung 0:8ede47d38d10 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
phungductung 0:8ede47d38d10 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
phungductung 0:8ede47d38d10 270 } b; /*!< Structure used for bit access */
phungductung 0:8ede47d38d10 271 uint32_t w; /*!< Type used for word access */
phungductung 0:8ede47d38d10 272 } IPSR_Type;
phungductung 0:8ede47d38d10 273
phungductung 0:8ede47d38d10 274 /* IPSR Register Definitions */
phungductung 0:8ede47d38d10 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
phungductung 0:8ede47d38d10 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
phungductung 0:8ede47d38d10 277
phungductung 0:8ede47d38d10 278
phungductung 0:8ede47d38d10 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
phungductung 0:8ede47d38d10 280 */
phungductung 0:8ede47d38d10 281 typedef union
phungductung 0:8ede47d38d10 282 {
phungductung 0:8ede47d38d10 283 struct
phungductung 0:8ede47d38d10 284 {
phungductung 0:8ede47d38d10 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
phungductung 0:8ede47d38d10 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
phungductung 0:8ede47d38d10 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
phungductung 0:8ede47d38d10 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
phungductung 0:8ede47d38d10 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
phungductung 0:8ede47d38d10 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
phungductung 0:8ede47d38d10 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
phungductung 0:8ede47d38d10 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
phungductung 0:8ede47d38d10 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
phungductung 0:8ede47d38d10 294 } b; /*!< Structure used for bit access */
phungductung 0:8ede47d38d10 295 uint32_t w; /*!< Type used for word access */
phungductung 0:8ede47d38d10 296 } xPSR_Type;
phungductung 0:8ede47d38d10 297
phungductung 0:8ede47d38d10 298 /* xPSR Register Definitions */
phungductung 0:8ede47d38d10 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
phungductung 0:8ede47d38d10 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
phungductung 0:8ede47d38d10 301
phungductung 0:8ede47d38d10 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
phungductung 0:8ede47d38d10 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
phungductung 0:8ede47d38d10 304
phungductung 0:8ede47d38d10 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
phungductung 0:8ede47d38d10 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
phungductung 0:8ede47d38d10 307
phungductung 0:8ede47d38d10 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
phungductung 0:8ede47d38d10 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
phungductung 0:8ede47d38d10 310
phungductung 0:8ede47d38d10 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
phungductung 0:8ede47d38d10 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
phungductung 0:8ede47d38d10 313
phungductung 0:8ede47d38d10 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
phungductung 0:8ede47d38d10 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
phungductung 0:8ede47d38d10 316
phungductung 0:8ede47d38d10 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
phungductung 0:8ede47d38d10 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
phungductung 0:8ede47d38d10 319
phungductung 0:8ede47d38d10 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
phungductung 0:8ede47d38d10 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
phungductung 0:8ede47d38d10 322
phungductung 0:8ede47d38d10 323
phungductung 0:8ede47d38d10 324 /** \brief Union type to access the Control Registers (CONTROL).
phungductung 0:8ede47d38d10 325 */
phungductung 0:8ede47d38d10 326 typedef union
phungductung 0:8ede47d38d10 327 {
phungductung 0:8ede47d38d10 328 struct
phungductung 0:8ede47d38d10 329 {
phungductung 0:8ede47d38d10 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
phungductung 0:8ede47d38d10 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
phungductung 0:8ede47d38d10 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
phungductung 0:8ede47d38d10 333 } b; /*!< Structure used for bit access */
phungductung 0:8ede47d38d10 334 uint32_t w; /*!< Type used for word access */
phungductung 0:8ede47d38d10 335 } CONTROL_Type;
phungductung 0:8ede47d38d10 336
phungductung 0:8ede47d38d10 337 /* CONTROL Register Definitions */
phungductung 0:8ede47d38d10 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
phungductung 0:8ede47d38d10 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
phungductung 0:8ede47d38d10 340
phungductung 0:8ede47d38d10 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
phungductung 0:8ede47d38d10 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
phungductung 0:8ede47d38d10 343
phungductung 0:8ede47d38d10 344 /*@} end of group CMSIS_CORE */
phungductung 0:8ede47d38d10 345
phungductung 0:8ede47d38d10 346
phungductung 0:8ede47d38d10 347 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
phungductung 0:8ede47d38d10 349 \brief Type definitions for the NVIC Registers
phungductung 0:8ede47d38d10 350 @{
phungductung 0:8ede47d38d10 351 */
phungductung 0:8ede47d38d10 352
phungductung 0:8ede47d38d10 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
phungductung 0:8ede47d38d10 354 */
phungductung 0:8ede47d38d10 355 typedef struct
phungductung 0:8ede47d38d10 356 {
phungductung 0:8ede47d38d10 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
phungductung 0:8ede47d38d10 358 uint32_t RESERVED0[24];
phungductung 0:8ede47d38d10 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
phungductung 0:8ede47d38d10 360 uint32_t RSERVED1[24];
phungductung 0:8ede47d38d10 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
phungductung 0:8ede47d38d10 362 uint32_t RESERVED2[24];
phungductung 0:8ede47d38d10 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
phungductung 0:8ede47d38d10 364 uint32_t RESERVED3[24];
phungductung 0:8ede47d38d10 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
phungductung 0:8ede47d38d10 366 uint32_t RESERVED4[56];
phungductung 0:8ede47d38d10 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
phungductung 0:8ede47d38d10 368 uint32_t RESERVED5[644];
phungductung 0:8ede47d38d10 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
phungductung 0:8ede47d38d10 370 } NVIC_Type;
phungductung 0:8ede47d38d10 371
phungductung 0:8ede47d38d10 372 /* Software Triggered Interrupt Register Definitions */
phungductung 0:8ede47d38d10 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
phungductung 0:8ede47d38d10 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
phungductung 0:8ede47d38d10 375
phungductung 0:8ede47d38d10 376 /*@} end of group CMSIS_NVIC */
phungductung 0:8ede47d38d10 377
phungductung 0:8ede47d38d10 378
phungductung 0:8ede47d38d10 379 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 380 \defgroup CMSIS_SCB System Control Block (SCB)
phungductung 0:8ede47d38d10 381 \brief Type definitions for the System Control Block Registers
phungductung 0:8ede47d38d10 382 @{
phungductung 0:8ede47d38d10 383 */
phungductung 0:8ede47d38d10 384
phungductung 0:8ede47d38d10 385 /** \brief Structure type to access the System Control Block (SCB).
phungductung 0:8ede47d38d10 386 */
phungductung 0:8ede47d38d10 387 typedef struct
phungductung 0:8ede47d38d10 388 {
phungductung 0:8ede47d38d10 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
phungductung 0:8ede47d38d10 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
phungductung 0:8ede47d38d10 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
phungductung 0:8ede47d38d10 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
phungductung 0:8ede47d38d10 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
phungductung 0:8ede47d38d10 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
phungductung 0:8ede47d38d10 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
phungductung 0:8ede47d38d10 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
phungductung 0:8ede47d38d10 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
phungductung 0:8ede47d38d10 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
phungductung 0:8ede47d38d10 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
phungductung 0:8ede47d38d10 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
phungductung 0:8ede47d38d10 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
phungductung 0:8ede47d38d10 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
phungductung 0:8ede47d38d10 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
phungductung 0:8ede47d38d10 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
phungductung 0:8ede47d38d10 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
phungductung 0:8ede47d38d10 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
phungductung 0:8ede47d38d10 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
phungductung 0:8ede47d38d10 408 uint32_t RESERVED0[5];
phungductung 0:8ede47d38d10 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
phungductung 0:8ede47d38d10 410 } SCB_Type;
phungductung 0:8ede47d38d10 411
phungductung 0:8ede47d38d10 412 /* SCB CPUID Register Definitions */
phungductung 0:8ede47d38d10 413 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
phungductung 0:8ede47d38d10 414 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
phungductung 0:8ede47d38d10 415
phungductung 0:8ede47d38d10 416 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
phungductung 0:8ede47d38d10 417 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
phungductung 0:8ede47d38d10 418
phungductung 0:8ede47d38d10 419 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
phungductung 0:8ede47d38d10 420 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
phungductung 0:8ede47d38d10 421
phungductung 0:8ede47d38d10 422 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
phungductung 0:8ede47d38d10 423 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
phungductung 0:8ede47d38d10 424
phungductung 0:8ede47d38d10 425 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
phungductung 0:8ede47d38d10 426 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
phungductung 0:8ede47d38d10 427
phungductung 0:8ede47d38d10 428 /* SCB Interrupt Control State Register Definitions */
phungductung 0:8ede47d38d10 429 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
phungductung 0:8ede47d38d10 430 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
phungductung 0:8ede47d38d10 431
phungductung 0:8ede47d38d10 432 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
phungductung 0:8ede47d38d10 433 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
phungductung 0:8ede47d38d10 434
phungductung 0:8ede47d38d10 435 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
phungductung 0:8ede47d38d10 436 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
phungductung 0:8ede47d38d10 437
phungductung 0:8ede47d38d10 438 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
phungductung 0:8ede47d38d10 439 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
phungductung 0:8ede47d38d10 440
phungductung 0:8ede47d38d10 441 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
phungductung 0:8ede47d38d10 442 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
phungductung 0:8ede47d38d10 443
phungductung 0:8ede47d38d10 444 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
phungductung 0:8ede47d38d10 445 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
phungductung 0:8ede47d38d10 446
phungductung 0:8ede47d38d10 447 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
phungductung 0:8ede47d38d10 448 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
phungductung 0:8ede47d38d10 449
phungductung 0:8ede47d38d10 450 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
phungductung 0:8ede47d38d10 451 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
phungductung 0:8ede47d38d10 452
phungductung 0:8ede47d38d10 453 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
phungductung 0:8ede47d38d10 454 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
phungductung 0:8ede47d38d10 455
phungductung 0:8ede47d38d10 456 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
phungductung 0:8ede47d38d10 457 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
phungductung 0:8ede47d38d10 458
phungductung 0:8ede47d38d10 459 /* SCB Vector Table Offset Register Definitions */
phungductung 0:8ede47d38d10 460 #if (__CM3_REV < 0x0201) /* core r2p1 */
phungductung 0:8ede47d38d10 461 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
phungductung 0:8ede47d38d10 462 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
phungductung 0:8ede47d38d10 463
phungductung 0:8ede47d38d10 464 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
phungductung 0:8ede47d38d10 465 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
phungductung 0:8ede47d38d10 466 #else
phungductung 0:8ede47d38d10 467 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
phungductung 0:8ede47d38d10 468 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
phungductung 0:8ede47d38d10 469 #endif
phungductung 0:8ede47d38d10 470
phungductung 0:8ede47d38d10 471 /* SCB Application Interrupt and Reset Control Register Definitions */
phungductung 0:8ede47d38d10 472 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
phungductung 0:8ede47d38d10 473 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
phungductung 0:8ede47d38d10 474
phungductung 0:8ede47d38d10 475 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
phungductung 0:8ede47d38d10 476 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
phungductung 0:8ede47d38d10 477
phungductung 0:8ede47d38d10 478 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
phungductung 0:8ede47d38d10 479 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
phungductung 0:8ede47d38d10 480
phungductung 0:8ede47d38d10 481 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
phungductung 0:8ede47d38d10 482 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
phungductung 0:8ede47d38d10 483
phungductung 0:8ede47d38d10 484 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
phungductung 0:8ede47d38d10 485 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
phungductung 0:8ede47d38d10 486
phungductung 0:8ede47d38d10 487 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
phungductung 0:8ede47d38d10 488 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
phungductung 0:8ede47d38d10 489
phungductung 0:8ede47d38d10 490 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
phungductung 0:8ede47d38d10 491 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
phungductung 0:8ede47d38d10 492
phungductung 0:8ede47d38d10 493 /* SCB System Control Register Definitions */
phungductung 0:8ede47d38d10 494 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
phungductung 0:8ede47d38d10 495 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
phungductung 0:8ede47d38d10 496
phungductung 0:8ede47d38d10 497 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
phungductung 0:8ede47d38d10 498 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
phungductung 0:8ede47d38d10 499
phungductung 0:8ede47d38d10 500 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
phungductung 0:8ede47d38d10 501 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
phungductung 0:8ede47d38d10 502
phungductung 0:8ede47d38d10 503 /* SCB Configuration Control Register Definitions */
phungductung 0:8ede47d38d10 504 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
phungductung 0:8ede47d38d10 505 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
phungductung 0:8ede47d38d10 506
phungductung 0:8ede47d38d10 507 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
phungductung 0:8ede47d38d10 508 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
phungductung 0:8ede47d38d10 509
phungductung 0:8ede47d38d10 510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
phungductung 0:8ede47d38d10 511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
phungductung 0:8ede47d38d10 512
phungductung 0:8ede47d38d10 513 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
phungductung 0:8ede47d38d10 514 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
phungductung 0:8ede47d38d10 515
phungductung 0:8ede47d38d10 516 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
phungductung 0:8ede47d38d10 517 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
phungductung 0:8ede47d38d10 518
phungductung 0:8ede47d38d10 519 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
phungductung 0:8ede47d38d10 520 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
phungductung 0:8ede47d38d10 521
phungductung 0:8ede47d38d10 522 /* SCB System Handler Control and State Register Definitions */
phungductung 0:8ede47d38d10 523 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
phungductung 0:8ede47d38d10 524 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
phungductung 0:8ede47d38d10 525
phungductung 0:8ede47d38d10 526 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
phungductung 0:8ede47d38d10 527 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
phungductung 0:8ede47d38d10 528
phungductung 0:8ede47d38d10 529 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
phungductung 0:8ede47d38d10 530 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
phungductung 0:8ede47d38d10 531
phungductung 0:8ede47d38d10 532 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
phungductung 0:8ede47d38d10 533 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
phungductung 0:8ede47d38d10 534
phungductung 0:8ede47d38d10 535 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
phungductung 0:8ede47d38d10 536 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
phungductung 0:8ede47d38d10 537
phungductung 0:8ede47d38d10 538 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
phungductung 0:8ede47d38d10 539 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
phungductung 0:8ede47d38d10 540
phungductung 0:8ede47d38d10 541 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
phungductung 0:8ede47d38d10 542 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
phungductung 0:8ede47d38d10 543
phungductung 0:8ede47d38d10 544 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
phungductung 0:8ede47d38d10 545 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
phungductung 0:8ede47d38d10 546
phungductung 0:8ede47d38d10 547 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
phungductung 0:8ede47d38d10 548 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
phungductung 0:8ede47d38d10 549
phungductung 0:8ede47d38d10 550 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
phungductung 0:8ede47d38d10 551 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
phungductung 0:8ede47d38d10 552
phungductung 0:8ede47d38d10 553 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
phungductung 0:8ede47d38d10 554 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
phungductung 0:8ede47d38d10 555
phungductung 0:8ede47d38d10 556 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
phungductung 0:8ede47d38d10 557 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
phungductung 0:8ede47d38d10 558
phungductung 0:8ede47d38d10 559 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
phungductung 0:8ede47d38d10 560 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
phungductung 0:8ede47d38d10 561
phungductung 0:8ede47d38d10 562 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
phungductung 0:8ede47d38d10 563 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
phungductung 0:8ede47d38d10 564
phungductung 0:8ede47d38d10 565 /* SCB Configurable Fault Status Registers Definitions */
phungductung 0:8ede47d38d10 566 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
phungductung 0:8ede47d38d10 567 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
phungductung 0:8ede47d38d10 568
phungductung 0:8ede47d38d10 569 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
phungductung 0:8ede47d38d10 570 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
phungductung 0:8ede47d38d10 571
phungductung 0:8ede47d38d10 572 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
phungductung 0:8ede47d38d10 573 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
phungductung 0:8ede47d38d10 574
phungductung 0:8ede47d38d10 575 /* SCB Hard Fault Status Registers Definitions */
phungductung 0:8ede47d38d10 576 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
phungductung 0:8ede47d38d10 577 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
phungductung 0:8ede47d38d10 578
phungductung 0:8ede47d38d10 579 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
phungductung 0:8ede47d38d10 580 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
phungductung 0:8ede47d38d10 581
phungductung 0:8ede47d38d10 582 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
phungductung 0:8ede47d38d10 583 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
phungductung 0:8ede47d38d10 584
phungductung 0:8ede47d38d10 585 /* SCB Debug Fault Status Register Definitions */
phungductung 0:8ede47d38d10 586 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
phungductung 0:8ede47d38d10 587 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
phungductung 0:8ede47d38d10 588
phungductung 0:8ede47d38d10 589 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
phungductung 0:8ede47d38d10 590 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
phungductung 0:8ede47d38d10 591
phungductung 0:8ede47d38d10 592 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
phungductung 0:8ede47d38d10 593 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
phungductung 0:8ede47d38d10 594
phungductung 0:8ede47d38d10 595 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
phungductung 0:8ede47d38d10 596 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
phungductung 0:8ede47d38d10 597
phungductung 0:8ede47d38d10 598 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
phungductung 0:8ede47d38d10 599 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
phungductung 0:8ede47d38d10 600
phungductung 0:8ede47d38d10 601 /*@} end of group CMSIS_SCB */
phungductung 0:8ede47d38d10 602
phungductung 0:8ede47d38d10 603
phungductung 0:8ede47d38d10 604 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 605 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
phungductung 0:8ede47d38d10 606 \brief Type definitions for the System Control and ID Register not in the SCB
phungductung 0:8ede47d38d10 607 @{
phungductung 0:8ede47d38d10 608 */
phungductung 0:8ede47d38d10 609
phungductung 0:8ede47d38d10 610 /** \brief Structure type to access the System Control and ID Register not in the SCB.
phungductung 0:8ede47d38d10 611 */
phungductung 0:8ede47d38d10 612 typedef struct
phungductung 0:8ede47d38d10 613 {
phungductung 0:8ede47d38d10 614 uint32_t RESERVED0[1];
phungductung 0:8ede47d38d10 615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
phungductung 0:8ede47d38d10 616 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
phungductung 0:8ede47d38d10 617 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
phungductung 0:8ede47d38d10 618 #else
phungductung 0:8ede47d38d10 619 uint32_t RESERVED1[1];
phungductung 0:8ede47d38d10 620 #endif
phungductung 0:8ede47d38d10 621 } SCnSCB_Type;
phungductung 0:8ede47d38d10 622
phungductung 0:8ede47d38d10 623 /* Interrupt Controller Type Register Definitions */
phungductung 0:8ede47d38d10 624 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
phungductung 0:8ede47d38d10 625 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
phungductung 0:8ede47d38d10 626
phungductung 0:8ede47d38d10 627 /* Auxiliary Control Register Definitions */
phungductung 0:8ede47d38d10 628
phungductung 0:8ede47d38d10 629 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
phungductung 0:8ede47d38d10 630 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
phungductung 0:8ede47d38d10 631
phungductung 0:8ede47d38d10 632 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
phungductung 0:8ede47d38d10 633 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
phungductung 0:8ede47d38d10 634
phungductung 0:8ede47d38d10 635 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
phungductung 0:8ede47d38d10 636 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
phungductung 0:8ede47d38d10 637
phungductung 0:8ede47d38d10 638 /*@} end of group CMSIS_SCnotSCB */
phungductung 0:8ede47d38d10 639
phungductung 0:8ede47d38d10 640
phungductung 0:8ede47d38d10 641 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 642 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
phungductung 0:8ede47d38d10 643 \brief Type definitions for the System Timer Registers.
phungductung 0:8ede47d38d10 644 @{
phungductung 0:8ede47d38d10 645 */
phungductung 0:8ede47d38d10 646
phungductung 0:8ede47d38d10 647 /** \brief Structure type to access the System Timer (SysTick).
phungductung 0:8ede47d38d10 648 */
phungductung 0:8ede47d38d10 649 typedef struct
phungductung 0:8ede47d38d10 650 {
phungductung 0:8ede47d38d10 651 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
phungductung 0:8ede47d38d10 652 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
phungductung 0:8ede47d38d10 653 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
phungductung 0:8ede47d38d10 654 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
phungductung 0:8ede47d38d10 655 } SysTick_Type;
phungductung 0:8ede47d38d10 656
phungductung 0:8ede47d38d10 657 /* SysTick Control / Status Register Definitions */
phungductung 0:8ede47d38d10 658 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
phungductung 0:8ede47d38d10 659 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
phungductung 0:8ede47d38d10 660
phungductung 0:8ede47d38d10 661 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
phungductung 0:8ede47d38d10 662 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
phungductung 0:8ede47d38d10 663
phungductung 0:8ede47d38d10 664 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
phungductung 0:8ede47d38d10 665 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
phungductung 0:8ede47d38d10 666
phungductung 0:8ede47d38d10 667 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
phungductung 0:8ede47d38d10 668 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
phungductung 0:8ede47d38d10 669
phungductung 0:8ede47d38d10 670 /* SysTick Reload Register Definitions */
phungductung 0:8ede47d38d10 671 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
phungductung 0:8ede47d38d10 672 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
phungductung 0:8ede47d38d10 673
phungductung 0:8ede47d38d10 674 /* SysTick Current Register Definitions */
phungductung 0:8ede47d38d10 675 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
phungductung 0:8ede47d38d10 676 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
phungductung 0:8ede47d38d10 677
phungductung 0:8ede47d38d10 678 /* SysTick Calibration Register Definitions */
phungductung 0:8ede47d38d10 679 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
phungductung 0:8ede47d38d10 680 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
phungductung 0:8ede47d38d10 681
phungductung 0:8ede47d38d10 682 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
phungductung 0:8ede47d38d10 683 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
phungductung 0:8ede47d38d10 684
phungductung 0:8ede47d38d10 685 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
phungductung 0:8ede47d38d10 686 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
phungductung 0:8ede47d38d10 687
phungductung 0:8ede47d38d10 688 /*@} end of group CMSIS_SysTick */
phungductung 0:8ede47d38d10 689
phungductung 0:8ede47d38d10 690
phungductung 0:8ede47d38d10 691 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 692 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
phungductung 0:8ede47d38d10 693 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
phungductung 0:8ede47d38d10 694 @{
phungductung 0:8ede47d38d10 695 */
phungductung 0:8ede47d38d10 696
phungductung 0:8ede47d38d10 697 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
phungductung 0:8ede47d38d10 698 */
phungductung 0:8ede47d38d10 699 typedef struct
phungductung 0:8ede47d38d10 700 {
phungductung 0:8ede47d38d10 701 __O union
phungductung 0:8ede47d38d10 702 {
phungductung 0:8ede47d38d10 703 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
phungductung 0:8ede47d38d10 704 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
phungductung 0:8ede47d38d10 705 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
phungductung 0:8ede47d38d10 706 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
phungductung 0:8ede47d38d10 707 uint32_t RESERVED0[864];
phungductung 0:8ede47d38d10 708 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
phungductung 0:8ede47d38d10 709 uint32_t RESERVED1[15];
phungductung 0:8ede47d38d10 710 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
phungductung 0:8ede47d38d10 711 uint32_t RESERVED2[15];
phungductung 0:8ede47d38d10 712 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
phungductung 0:8ede47d38d10 713 uint32_t RESERVED3[29];
phungductung 0:8ede47d38d10 714 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
phungductung 0:8ede47d38d10 715 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
phungductung 0:8ede47d38d10 716 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
phungductung 0:8ede47d38d10 717 uint32_t RESERVED4[43];
phungductung 0:8ede47d38d10 718 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
phungductung 0:8ede47d38d10 719 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
phungductung 0:8ede47d38d10 720 uint32_t RESERVED5[6];
phungductung 0:8ede47d38d10 721 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
phungductung 0:8ede47d38d10 722 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
phungductung 0:8ede47d38d10 723 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
phungductung 0:8ede47d38d10 724 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
phungductung 0:8ede47d38d10 725 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
phungductung 0:8ede47d38d10 726 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
phungductung 0:8ede47d38d10 727 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
phungductung 0:8ede47d38d10 728 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
phungductung 0:8ede47d38d10 729 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
phungductung 0:8ede47d38d10 730 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
phungductung 0:8ede47d38d10 731 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
phungductung 0:8ede47d38d10 732 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
phungductung 0:8ede47d38d10 733 } ITM_Type;
phungductung 0:8ede47d38d10 734
phungductung 0:8ede47d38d10 735 /* ITM Trace Privilege Register Definitions */
phungductung 0:8ede47d38d10 736 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
phungductung 0:8ede47d38d10 737 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
phungductung 0:8ede47d38d10 738
phungductung 0:8ede47d38d10 739 /* ITM Trace Control Register Definitions */
phungductung 0:8ede47d38d10 740 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
phungductung 0:8ede47d38d10 741 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
phungductung 0:8ede47d38d10 742
phungductung 0:8ede47d38d10 743 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
phungductung 0:8ede47d38d10 744 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
phungductung 0:8ede47d38d10 745
phungductung 0:8ede47d38d10 746 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
phungductung 0:8ede47d38d10 747 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
phungductung 0:8ede47d38d10 748
phungductung 0:8ede47d38d10 749 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
phungductung 0:8ede47d38d10 750 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
phungductung 0:8ede47d38d10 751
phungductung 0:8ede47d38d10 752 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
phungductung 0:8ede47d38d10 753 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
phungductung 0:8ede47d38d10 754
phungductung 0:8ede47d38d10 755 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
phungductung 0:8ede47d38d10 756 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
phungductung 0:8ede47d38d10 757
phungductung 0:8ede47d38d10 758 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
phungductung 0:8ede47d38d10 759 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
phungductung 0:8ede47d38d10 760
phungductung 0:8ede47d38d10 761 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
phungductung 0:8ede47d38d10 762 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
phungductung 0:8ede47d38d10 763
phungductung 0:8ede47d38d10 764 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
phungductung 0:8ede47d38d10 765 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
phungductung 0:8ede47d38d10 766
phungductung 0:8ede47d38d10 767 /* ITM Integration Write Register Definitions */
phungductung 0:8ede47d38d10 768 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
phungductung 0:8ede47d38d10 769 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
phungductung 0:8ede47d38d10 770
phungductung 0:8ede47d38d10 771 /* ITM Integration Read Register Definitions */
phungductung 0:8ede47d38d10 772 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
phungductung 0:8ede47d38d10 773 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
phungductung 0:8ede47d38d10 774
phungductung 0:8ede47d38d10 775 /* ITM Integration Mode Control Register Definitions */
phungductung 0:8ede47d38d10 776 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
phungductung 0:8ede47d38d10 777 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
phungductung 0:8ede47d38d10 778
phungductung 0:8ede47d38d10 779 /* ITM Lock Status Register Definitions */
phungductung 0:8ede47d38d10 780 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
phungductung 0:8ede47d38d10 781 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
phungductung 0:8ede47d38d10 782
phungductung 0:8ede47d38d10 783 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
phungductung 0:8ede47d38d10 784 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
phungductung 0:8ede47d38d10 785
phungductung 0:8ede47d38d10 786 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
phungductung 0:8ede47d38d10 787 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
phungductung 0:8ede47d38d10 788
phungductung 0:8ede47d38d10 789 /*@}*/ /* end of group CMSIS_ITM */
phungductung 0:8ede47d38d10 790
phungductung 0:8ede47d38d10 791
phungductung 0:8ede47d38d10 792 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 793 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
phungductung 0:8ede47d38d10 794 \brief Type definitions for the Data Watchpoint and Trace (DWT)
phungductung 0:8ede47d38d10 795 @{
phungductung 0:8ede47d38d10 796 */
phungductung 0:8ede47d38d10 797
phungductung 0:8ede47d38d10 798 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
phungductung 0:8ede47d38d10 799 */
phungductung 0:8ede47d38d10 800 typedef struct
phungductung 0:8ede47d38d10 801 {
phungductung 0:8ede47d38d10 802 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
phungductung 0:8ede47d38d10 803 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
phungductung 0:8ede47d38d10 804 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
phungductung 0:8ede47d38d10 805 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
phungductung 0:8ede47d38d10 806 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
phungductung 0:8ede47d38d10 807 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
phungductung 0:8ede47d38d10 808 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
phungductung 0:8ede47d38d10 809 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
phungductung 0:8ede47d38d10 810 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
phungductung 0:8ede47d38d10 811 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
phungductung 0:8ede47d38d10 812 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
phungductung 0:8ede47d38d10 813 uint32_t RESERVED0[1];
phungductung 0:8ede47d38d10 814 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
phungductung 0:8ede47d38d10 815 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
phungductung 0:8ede47d38d10 816 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
phungductung 0:8ede47d38d10 817 uint32_t RESERVED1[1];
phungductung 0:8ede47d38d10 818 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
phungductung 0:8ede47d38d10 819 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
phungductung 0:8ede47d38d10 820 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
phungductung 0:8ede47d38d10 821 uint32_t RESERVED2[1];
phungductung 0:8ede47d38d10 822 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
phungductung 0:8ede47d38d10 823 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
phungductung 0:8ede47d38d10 824 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
phungductung 0:8ede47d38d10 825 } DWT_Type;
phungductung 0:8ede47d38d10 826
phungductung 0:8ede47d38d10 827 /* DWT Control Register Definitions */
phungductung 0:8ede47d38d10 828 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
phungductung 0:8ede47d38d10 829 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
phungductung 0:8ede47d38d10 830
phungductung 0:8ede47d38d10 831 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
phungductung 0:8ede47d38d10 832 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
phungductung 0:8ede47d38d10 833
phungductung 0:8ede47d38d10 834 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
phungductung 0:8ede47d38d10 835 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
phungductung 0:8ede47d38d10 836
phungductung 0:8ede47d38d10 837 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
phungductung 0:8ede47d38d10 838 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
phungductung 0:8ede47d38d10 839
phungductung 0:8ede47d38d10 840 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
phungductung 0:8ede47d38d10 841 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
phungductung 0:8ede47d38d10 842
phungductung 0:8ede47d38d10 843 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
phungductung 0:8ede47d38d10 844 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
phungductung 0:8ede47d38d10 845
phungductung 0:8ede47d38d10 846 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
phungductung 0:8ede47d38d10 847 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
phungductung 0:8ede47d38d10 848
phungductung 0:8ede47d38d10 849 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
phungductung 0:8ede47d38d10 850 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
phungductung 0:8ede47d38d10 851
phungductung 0:8ede47d38d10 852 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
phungductung 0:8ede47d38d10 853 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
phungductung 0:8ede47d38d10 854
phungductung 0:8ede47d38d10 855 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
phungductung 0:8ede47d38d10 856 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
phungductung 0:8ede47d38d10 857
phungductung 0:8ede47d38d10 858 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
phungductung 0:8ede47d38d10 859 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
phungductung 0:8ede47d38d10 860
phungductung 0:8ede47d38d10 861 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
phungductung 0:8ede47d38d10 862 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
phungductung 0:8ede47d38d10 863
phungductung 0:8ede47d38d10 864 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
phungductung 0:8ede47d38d10 865 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
phungductung 0:8ede47d38d10 866
phungductung 0:8ede47d38d10 867 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
phungductung 0:8ede47d38d10 868 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
phungductung 0:8ede47d38d10 869
phungductung 0:8ede47d38d10 870 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
phungductung 0:8ede47d38d10 871 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
phungductung 0:8ede47d38d10 872
phungductung 0:8ede47d38d10 873 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
phungductung 0:8ede47d38d10 874 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
phungductung 0:8ede47d38d10 875
phungductung 0:8ede47d38d10 876 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
phungductung 0:8ede47d38d10 877 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
phungductung 0:8ede47d38d10 878
phungductung 0:8ede47d38d10 879 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
phungductung 0:8ede47d38d10 880 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
phungductung 0:8ede47d38d10 881
phungductung 0:8ede47d38d10 882 /* DWT CPI Count Register Definitions */
phungductung 0:8ede47d38d10 883 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
phungductung 0:8ede47d38d10 884 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
phungductung 0:8ede47d38d10 885
phungductung 0:8ede47d38d10 886 /* DWT Exception Overhead Count Register Definitions */
phungductung 0:8ede47d38d10 887 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
phungductung 0:8ede47d38d10 888 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
phungductung 0:8ede47d38d10 889
phungductung 0:8ede47d38d10 890 /* DWT Sleep Count Register Definitions */
phungductung 0:8ede47d38d10 891 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
phungductung 0:8ede47d38d10 892 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
phungductung 0:8ede47d38d10 893
phungductung 0:8ede47d38d10 894 /* DWT LSU Count Register Definitions */
phungductung 0:8ede47d38d10 895 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
phungductung 0:8ede47d38d10 896 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
phungductung 0:8ede47d38d10 897
phungductung 0:8ede47d38d10 898 /* DWT Folded-instruction Count Register Definitions */
phungductung 0:8ede47d38d10 899 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
phungductung 0:8ede47d38d10 900 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
phungductung 0:8ede47d38d10 901
phungductung 0:8ede47d38d10 902 /* DWT Comparator Mask Register Definitions */
phungductung 0:8ede47d38d10 903 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
phungductung 0:8ede47d38d10 904 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
phungductung 0:8ede47d38d10 905
phungductung 0:8ede47d38d10 906 /* DWT Comparator Function Register Definitions */
phungductung 0:8ede47d38d10 907 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
phungductung 0:8ede47d38d10 908 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
phungductung 0:8ede47d38d10 909
phungductung 0:8ede47d38d10 910 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
phungductung 0:8ede47d38d10 911 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
phungductung 0:8ede47d38d10 912
phungductung 0:8ede47d38d10 913 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
phungductung 0:8ede47d38d10 914 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
phungductung 0:8ede47d38d10 915
phungductung 0:8ede47d38d10 916 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
phungductung 0:8ede47d38d10 917 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
phungductung 0:8ede47d38d10 918
phungductung 0:8ede47d38d10 919 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
phungductung 0:8ede47d38d10 920 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
phungductung 0:8ede47d38d10 921
phungductung 0:8ede47d38d10 922 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
phungductung 0:8ede47d38d10 923 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
phungductung 0:8ede47d38d10 924
phungductung 0:8ede47d38d10 925 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
phungductung 0:8ede47d38d10 926 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
phungductung 0:8ede47d38d10 927
phungductung 0:8ede47d38d10 928 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
phungductung 0:8ede47d38d10 929 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
phungductung 0:8ede47d38d10 930
phungductung 0:8ede47d38d10 931 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
phungductung 0:8ede47d38d10 932 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
phungductung 0:8ede47d38d10 933
phungductung 0:8ede47d38d10 934 /*@}*/ /* end of group CMSIS_DWT */
phungductung 0:8ede47d38d10 935
phungductung 0:8ede47d38d10 936
phungductung 0:8ede47d38d10 937 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 938 \defgroup CMSIS_TPI Trace Port Interface (TPI)
phungductung 0:8ede47d38d10 939 \brief Type definitions for the Trace Port Interface (TPI)
phungductung 0:8ede47d38d10 940 @{
phungductung 0:8ede47d38d10 941 */
phungductung 0:8ede47d38d10 942
phungductung 0:8ede47d38d10 943 /** \brief Structure type to access the Trace Port Interface Register (TPI).
phungductung 0:8ede47d38d10 944 */
phungductung 0:8ede47d38d10 945 typedef struct
phungductung 0:8ede47d38d10 946 {
phungductung 0:8ede47d38d10 947 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
phungductung 0:8ede47d38d10 948 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
phungductung 0:8ede47d38d10 949 uint32_t RESERVED0[2];
phungductung 0:8ede47d38d10 950 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
phungductung 0:8ede47d38d10 951 uint32_t RESERVED1[55];
phungductung 0:8ede47d38d10 952 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
phungductung 0:8ede47d38d10 953 uint32_t RESERVED2[131];
phungductung 0:8ede47d38d10 954 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
phungductung 0:8ede47d38d10 955 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
phungductung 0:8ede47d38d10 956 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
phungductung 0:8ede47d38d10 957 uint32_t RESERVED3[759];
phungductung 0:8ede47d38d10 958 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
phungductung 0:8ede47d38d10 959 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
phungductung 0:8ede47d38d10 960 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
phungductung 0:8ede47d38d10 961 uint32_t RESERVED4[1];
phungductung 0:8ede47d38d10 962 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
phungductung 0:8ede47d38d10 963 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
phungductung 0:8ede47d38d10 964 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
phungductung 0:8ede47d38d10 965 uint32_t RESERVED5[39];
phungductung 0:8ede47d38d10 966 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
phungductung 0:8ede47d38d10 967 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
phungductung 0:8ede47d38d10 968 uint32_t RESERVED7[8];
phungductung 0:8ede47d38d10 969 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
phungductung 0:8ede47d38d10 970 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
phungductung 0:8ede47d38d10 971 } TPI_Type;
phungductung 0:8ede47d38d10 972
phungductung 0:8ede47d38d10 973 /* TPI Asynchronous Clock Prescaler Register Definitions */
phungductung 0:8ede47d38d10 974 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
phungductung 0:8ede47d38d10 975 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
phungductung 0:8ede47d38d10 976
phungductung 0:8ede47d38d10 977 /* TPI Selected Pin Protocol Register Definitions */
phungductung 0:8ede47d38d10 978 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
phungductung 0:8ede47d38d10 979 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
phungductung 0:8ede47d38d10 980
phungductung 0:8ede47d38d10 981 /* TPI Formatter and Flush Status Register Definitions */
phungductung 0:8ede47d38d10 982 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
phungductung 0:8ede47d38d10 983 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
phungductung 0:8ede47d38d10 984
phungductung 0:8ede47d38d10 985 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
phungductung 0:8ede47d38d10 986 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
phungductung 0:8ede47d38d10 987
phungductung 0:8ede47d38d10 988 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
phungductung 0:8ede47d38d10 989 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
phungductung 0:8ede47d38d10 990
phungductung 0:8ede47d38d10 991 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
phungductung 0:8ede47d38d10 992 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
phungductung 0:8ede47d38d10 993
phungductung 0:8ede47d38d10 994 /* TPI Formatter and Flush Control Register Definitions */
phungductung 0:8ede47d38d10 995 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
phungductung 0:8ede47d38d10 996 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
phungductung 0:8ede47d38d10 997
phungductung 0:8ede47d38d10 998 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
phungductung 0:8ede47d38d10 999 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
phungductung 0:8ede47d38d10 1000
phungductung 0:8ede47d38d10 1001 /* TPI TRIGGER Register Definitions */
phungductung 0:8ede47d38d10 1002 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
phungductung 0:8ede47d38d10 1003 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
phungductung 0:8ede47d38d10 1004
phungductung 0:8ede47d38d10 1005 /* TPI Integration ETM Data Register Definitions (FIFO0) */
phungductung 0:8ede47d38d10 1006 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
phungductung 0:8ede47d38d10 1007 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
phungductung 0:8ede47d38d10 1008
phungductung 0:8ede47d38d10 1009 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
phungductung 0:8ede47d38d10 1010 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
phungductung 0:8ede47d38d10 1011
phungductung 0:8ede47d38d10 1012 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
phungductung 0:8ede47d38d10 1013 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
phungductung 0:8ede47d38d10 1014
phungductung 0:8ede47d38d10 1015 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
phungductung 0:8ede47d38d10 1016 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
phungductung 0:8ede47d38d10 1017
phungductung 0:8ede47d38d10 1018 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
phungductung 0:8ede47d38d10 1019 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
phungductung 0:8ede47d38d10 1020
phungductung 0:8ede47d38d10 1021 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
phungductung 0:8ede47d38d10 1022 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
phungductung 0:8ede47d38d10 1023
phungductung 0:8ede47d38d10 1024 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
phungductung 0:8ede47d38d10 1025 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
phungductung 0:8ede47d38d10 1026
phungductung 0:8ede47d38d10 1027 /* TPI ITATBCTR2 Register Definitions */
phungductung 0:8ede47d38d10 1028 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
phungductung 0:8ede47d38d10 1029 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
phungductung 0:8ede47d38d10 1030
phungductung 0:8ede47d38d10 1031 /* TPI Integration ITM Data Register Definitions (FIFO1) */
phungductung 0:8ede47d38d10 1032 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
phungductung 0:8ede47d38d10 1033 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
phungductung 0:8ede47d38d10 1034
phungductung 0:8ede47d38d10 1035 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
phungductung 0:8ede47d38d10 1036 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
phungductung 0:8ede47d38d10 1037
phungductung 0:8ede47d38d10 1038 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
phungductung 0:8ede47d38d10 1039 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
phungductung 0:8ede47d38d10 1040
phungductung 0:8ede47d38d10 1041 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
phungductung 0:8ede47d38d10 1042 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
phungductung 0:8ede47d38d10 1043
phungductung 0:8ede47d38d10 1044 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
phungductung 0:8ede47d38d10 1045 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
phungductung 0:8ede47d38d10 1046
phungductung 0:8ede47d38d10 1047 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
phungductung 0:8ede47d38d10 1048 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
phungductung 0:8ede47d38d10 1049
phungductung 0:8ede47d38d10 1050 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
phungductung 0:8ede47d38d10 1051 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
phungductung 0:8ede47d38d10 1052
phungductung 0:8ede47d38d10 1053 /* TPI ITATBCTR0 Register Definitions */
phungductung 0:8ede47d38d10 1054 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
phungductung 0:8ede47d38d10 1055 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
phungductung 0:8ede47d38d10 1056
phungductung 0:8ede47d38d10 1057 /* TPI Integration Mode Control Register Definitions */
phungductung 0:8ede47d38d10 1058 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
phungductung 0:8ede47d38d10 1059 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
phungductung 0:8ede47d38d10 1060
phungductung 0:8ede47d38d10 1061 /* TPI DEVID Register Definitions */
phungductung 0:8ede47d38d10 1062 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
phungductung 0:8ede47d38d10 1063 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
phungductung 0:8ede47d38d10 1064
phungductung 0:8ede47d38d10 1065 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
phungductung 0:8ede47d38d10 1066 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
phungductung 0:8ede47d38d10 1067
phungductung 0:8ede47d38d10 1068 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
phungductung 0:8ede47d38d10 1069 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
phungductung 0:8ede47d38d10 1070
phungductung 0:8ede47d38d10 1071 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
phungductung 0:8ede47d38d10 1072 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
phungductung 0:8ede47d38d10 1073
phungductung 0:8ede47d38d10 1074 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
phungductung 0:8ede47d38d10 1075 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
phungductung 0:8ede47d38d10 1076
phungductung 0:8ede47d38d10 1077 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
phungductung 0:8ede47d38d10 1078 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
phungductung 0:8ede47d38d10 1079
phungductung 0:8ede47d38d10 1080 /* TPI DEVTYPE Register Definitions */
phungductung 0:8ede47d38d10 1081 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
phungductung 0:8ede47d38d10 1082 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
phungductung 0:8ede47d38d10 1083
phungductung 0:8ede47d38d10 1084 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
phungductung 0:8ede47d38d10 1085 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
phungductung 0:8ede47d38d10 1086
phungductung 0:8ede47d38d10 1087 /*@}*/ /* end of group CMSIS_TPI */
phungductung 0:8ede47d38d10 1088
phungductung 0:8ede47d38d10 1089
phungductung 0:8ede47d38d10 1090 #if (__MPU_PRESENT == 1)
phungductung 0:8ede47d38d10 1091 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 1092 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
phungductung 0:8ede47d38d10 1093 \brief Type definitions for the Memory Protection Unit (MPU)
phungductung 0:8ede47d38d10 1094 @{
phungductung 0:8ede47d38d10 1095 */
phungductung 0:8ede47d38d10 1096
phungductung 0:8ede47d38d10 1097 /** \brief Structure type to access the Memory Protection Unit (MPU).
phungductung 0:8ede47d38d10 1098 */
phungductung 0:8ede47d38d10 1099 typedef struct
phungductung 0:8ede47d38d10 1100 {
phungductung 0:8ede47d38d10 1101 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
phungductung 0:8ede47d38d10 1102 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
phungductung 0:8ede47d38d10 1103 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
phungductung 0:8ede47d38d10 1104 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
phungductung 0:8ede47d38d10 1105 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
phungductung 0:8ede47d38d10 1106 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
phungductung 0:8ede47d38d10 1107 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
phungductung 0:8ede47d38d10 1108 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
phungductung 0:8ede47d38d10 1109 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
phungductung 0:8ede47d38d10 1110 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
phungductung 0:8ede47d38d10 1111 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
phungductung 0:8ede47d38d10 1112 } MPU_Type;
phungductung 0:8ede47d38d10 1113
phungductung 0:8ede47d38d10 1114 /* MPU Type Register */
phungductung 0:8ede47d38d10 1115 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
phungductung 0:8ede47d38d10 1116 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
phungductung 0:8ede47d38d10 1117
phungductung 0:8ede47d38d10 1118 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
phungductung 0:8ede47d38d10 1119 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
phungductung 0:8ede47d38d10 1120
phungductung 0:8ede47d38d10 1121 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
phungductung 0:8ede47d38d10 1122 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
phungductung 0:8ede47d38d10 1123
phungductung 0:8ede47d38d10 1124 /* MPU Control Register */
phungductung 0:8ede47d38d10 1125 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
phungductung 0:8ede47d38d10 1126 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
phungductung 0:8ede47d38d10 1127
phungductung 0:8ede47d38d10 1128 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
phungductung 0:8ede47d38d10 1129 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
phungductung 0:8ede47d38d10 1130
phungductung 0:8ede47d38d10 1131 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
phungductung 0:8ede47d38d10 1132 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
phungductung 0:8ede47d38d10 1133
phungductung 0:8ede47d38d10 1134 /* MPU Region Number Register */
phungductung 0:8ede47d38d10 1135 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
phungductung 0:8ede47d38d10 1136 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
phungductung 0:8ede47d38d10 1137
phungductung 0:8ede47d38d10 1138 /* MPU Region Base Address Register */
phungductung 0:8ede47d38d10 1139 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
phungductung 0:8ede47d38d10 1140 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
phungductung 0:8ede47d38d10 1141
phungductung 0:8ede47d38d10 1142 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
phungductung 0:8ede47d38d10 1143 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
phungductung 0:8ede47d38d10 1144
phungductung 0:8ede47d38d10 1145 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
phungductung 0:8ede47d38d10 1146 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
phungductung 0:8ede47d38d10 1147
phungductung 0:8ede47d38d10 1148 /* MPU Region Attribute and Size Register */
phungductung 0:8ede47d38d10 1149 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
phungductung 0:8ede47d38d10 1150 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
phungductung 0:8ede47d38d10 1151
phungductung 0:8ede47d38d10 1152 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
phungductung 0:8ede47d38d10 1153 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
phungductung 0:8ede47d38d10 1154
phungductung 0:8ede47d38d10 1155 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
phungductung 0:8ede47d38d10 1156 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
phungductung 0:8ede47d38d10 1157
phungductung 0:8ede47d38d10 1158 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
phungductung 0:8ede47d38d10 1159 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
phungductung 0:8ede47d38d10 1160
phungductung 0:8ede47d38d10 1161 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
phungductung 0:8ede47d38d10 1162 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
phungductung 0:8ede47d38d10 1163
phungductung 0:8ede47d38d10 1164 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
phungductung 0:8ede47d38d10 1165 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
phungductung 0:8ede47d38d10 1166
phungductung 0:8ede47d38d10 1167 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
phungductung 0:8ede47d38d10 1168 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
phungductung 0:8ede47d38d10 1169
phungductung 0:8ede47d38d10 1170 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
phungductung 0:8ede47d38d10 1171 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
phungductung 0:8ede47d38d10 1172
phungductung 0:8ede47d38d10 1173 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
phungductung 0:8ede47d38d10 1174 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
phungductung 0:8ede47d38d10 1175
phungductung 0:8ede47d38d10 1176 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
phungductung 0:8ede47d38d10 1177 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
phungductung 0:8ede47d38d10 1178
phungductung 0:8ede47d38d10 1179 /*@} end of group CMSIS_MPU */
phungductung 0:8ede47d38d10 1180 #endif
phungductung 0:8ede47d38d10 1181
phungductung 0:8ede47d38d10 1182
phungductung 0:8ede47d38d10 1183 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 1184 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
phungductung 0:8ede47d38d10 1185 \brief Type definitions for the Core Debug Registers
phungductung 0:8ede47d38d10 1186 @{
phungductung 0:8ede47d38d10 1187 */
phungductung 0:8ede47d38d10 1188
phungductung 0:8ede47d38d10 1189 /** \brief Structure type to access the Core Debug Register (CoreDebug).
phungductung 0:8ede47d38d10 1190 */
phungductung 0:8ede47d38d10 1191 typedef struct
phungductung 0:8ede47d38d10 1192 {
phungductung 0:8ede47d38d10 1193 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
phungductung 0:8ede47d38d10 1194 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
phungductung 0:8ede47d38d10 1195 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
phungductung 0:8ede47d38d10 1196 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
phungductung 0:8ede47d38d10 1197 } CoreDebug_Type;
phungductung 0:8ede47d38d10 1198
phungductung 0:8ede47d38d10 1199 /* Debug Halting Control and Status Register */
phungductung 0:8ede47d38d10 1200 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
phungductung 0:8ede47d38d10 1201 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
phungductung 0:8ede47d38d10 1202
phungductung 0:8ede47d38d10 1203 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
phungductung 0:8ede47d38d10 1204 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
phungductung 0:8ede47d38d10 1205
phungductung 0:8ede47d38d10 1206 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
phungductung 0:8ede47d38d10 1207 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
phungductung 0:8ede47d38d10 1208
phungductung 0:8ede47d38d10 1209 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
phungductung 0:8ede47d38d10 1210 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
phungductung 0:8ede47d38d10 1211
phungductung 0:8ede47d38d10 1212 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
phungductung 0:8ede47d38d10 1213 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
phungductung 0:8ede47d38d10 1214
phungductung 0:8ede47d38d10 1215 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
phungductung 0:8ede47d38d10 1216 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
phungductung 0:8ede47d38d10 1217
phungductung 0:8ede47d38d10 1218 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
phungductung 0:8ede47d38d10 1219 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
phungductung 0:8ede47d38d10 1220
phungductung 0:8ede47d38d10 1221 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
phungductung 0:8ede47d38d10 1222 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
phungductung 0:8ede47d38d10 1223
phungductung 0:8ede47d38d10 1224 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
phungductung 0:8ede47d38d10 1225 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
phungductung 0:8ede47d38d10 1226
phungductung 0:8ede47d38d10 1227 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
phungductung 0:8ede47d38d10 1228 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
phungductung 0:8ede47d38d10 1229
phungductung 0:8ede47d38d10 1230 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
phungductung 0:8ede47d38d10 1231 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
phungductung 0:8ede47d38d10 1232
phungductung 0:8ede47d38d10 1233 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
phungductung 0:8ede47d38d10 1234 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
phungductung 0:8ede47d38d10 1235
phungductung 0:8ede47d38d10 1236 /* Debug Core Register Selector Register */
phungductung 0:8ede47d38d10 1237 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
phungductung 0:8ede47d38d10 1238 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
phungductung 0:8ede47d38d10 1239
phungductung 0:8ede47d38d10 1240 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
phungductung 0:8ede47d38d10 1241 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
phungductung 0:8ede47d38d10 1242
phungductung 0:8ede47d38d10 1243 /* Debug Exception and Monitor Control Register */
phungductung 0:8ede47d38d10 1244 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
phungductung 0:8ede47d38d10 1245 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
phungductung 0:8ede47d38d10 1246
phungductung 0:8ede47d38d10 1247 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
phungductung 0:8ede47d38d10 1248 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
phungductung 0:8ede47d38d10 1249
phungductung 0:8ede47d38d10 1250 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
phungductung 0:8ede47d38d10 1251 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
phungductung 0:8ede47d38d10 1252
phungductung 0:8ede47d38d10 1253 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
phungductung 0:8ede47d38d10 1254 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
phungductung 0:8ede47d38d10 1255
phungductung 0:8ede47d38d10 1256 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
phungductung 0:8ede47d38d10 1257 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
phungductung 0:8ede47d38d10 1258
phungductung 0:8ede47d38d10 1259 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
phungductung 0:8ede47d38d10 1260 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
phungductung 0:8ede47d38d10 1261
phungductung 0:8ede47d38d10 1262 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
phungductung 0:8ede47d38d10 1263 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
phungductung 0:8ede47d38d10 1264
phungductung 0:8ede47d38d10 1265 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
phungductung 0:8ede47d38d10 1266 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
phungductung 0:8ede47d38d10 1267
phungductung 0:8ede47d38d10 1268 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
phungductung 0:8ede47d38d10 1269 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
phungductung 0:8ede47d38d10 1270
phungductung 0:8ede47d38d10 1271 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
phungductung 0:8ede47d38d10 1272 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
phungductung 0:8ede47d38d10 1273
phungductung 0:8ede47d38d10 1274 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
phungductung 0:8ede47d38d10 1275 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
phungductung 0:8ede47d38d10 1276
phungductung 0:8ede47d38d10 1277 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
phungductung 0:8ede47d38d10 1278 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
phungductung 0:8ede47d38d10 1279
phungductung 0:8ede47d38d10 1280 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
phungductung 0:8ede47d38d10 1281 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
phungductung 0:8ede47d38d10 1282
phungductung 0:8ede47d38d10 1283 /*@} end of group CMSIS_CoreDebug */
phungductung 0:8ede47d38d10 1284
phungductung 0:8ede47d38d10 1285
phungductung 0:8ede47d38d10 1286 /** \ingroup CMSIS_core_register
phungductung 0:8ede47d38d10 1287 \defgroup CMSIS_core_base Core Definitions
phungductung 0:8ede47d38d10 1288 \brief Definitions for base addresses, unions, and structures.
phungductung 0:8ede47d38d10 1289 @{
phungductung 0:8ede47d38d10 1290 */
phungductung 0:8ede47d38d10 1291
phungductung 0:8ede47d38d10 1292 /* Memory mapping of Cortex-M3 Hardware */
phungductung 0:8ede47d38d10 1293 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
phungductung 0:8ede47d38d10 1294 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
phungductung 0:8ede47d38d10 1295 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
phungductung 0:8ede47d38d10 1296 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
phungductung 0:8ede47d38d10 1297 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
phungductung 0:8ede47d38d10 1298 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
phungductung 0:8ede47d38d10 1299 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
phungductung 0:8ede47d38d10 1300 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
phungductung 0:8ede47d38d10 1301
phungductung 0:8ede47d38d10 1302 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
phungductung 0:8ede47d38d10 1303 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
phungductung 0:8ede47d38d10 1304 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
phungductung 0:8ede47d38d10 1305 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
phungductung 0:8ede47d38d10 1306 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
phungductung 0:8ede47d38d10 1307 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
phungductung 0:8ede47d38d10 1308 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
phungductung 0:8ede47d38d10 1309 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
phungductung 0:8ede47d38d10 1310
phungductung 0:8ede47d38d10 1311 #if (__MPU_PRESENT == 1)
phungductung 0:8ede47d38d10 1312 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
phungductung 0:8ede47d38d10 1313 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
phungductung 0:8ede47d38d10 1314 #endif
phungductung 0:8ede47d38d10 1315
phungductung 0:8ede47d38d10 1316 /*@} */
phungductung 0:8ede47d38d10 1317
phungductung 0:8ede47d38d10 1318
phungductung 0:8ede47d38d10 1319
phungductung 0:8ede47d38d10 1320 /*******************************************************************************
phungductung 0:8ede47d38d10 1321 * Hardware Abstraction Layer
phungductung 0:8ede47d38d10 1322 Core Function Interface contains:
phungductung 0:8ede47d38d10 1323 - Core NVIC Functions
phungductung 0:8ede47d38d10 1324 - Core SysTick Functions
phungductung 0:8ede47d38d10 1325 - Core Debug Functions
phungductung 0:8ede47d38d10 1326 - Core Register Access Functions
phungductung 0:8ede47d38d10 1327 ******************************************************************************/
phungductung 0:8ede47d38d10 1328 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
phungductung 0:8ede47d38d10 1329 */
phungductung 0:8ede47d38d10 1330
phungductung 0:8ede47d38d10 1331
phungductung 0:8ede47d38d10 1332
phungductung 0:8ede47d38d10 1333 /* ########################## NVIC functions #################################### */
phungductung 0:8ede47d38d10 1334 /** \ingroup CMSIS_Core_FunctionInterface
phungductung 0:8ede47d38d10 1335 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
phungductung 0:8ede47d38d10 1336 \brief Functions that manage interrupts and exceptions via the NVIC.
phungductung 0:8ede47d38d10 1337 @{
phungductung 0:8ede47d38d10 1338 */
phungductung 0:8ede47d38d10 1339
phungductung 0:8ede47d38d10 1340 /** \brief Set Priority Grouping
phungductung 0:8ede47d38d10 1341
phungductung 0:8ede47d38d10 1342 The function sets the priority grouping field using the required unlock sequence.
phungductung 0:8ede47d38d10 1343 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
phungductung 0:8ede47d38d10 1344 Only values from 0..7 are used.
phungductung 0:8ede47d38d10 1345 In case of a conflict between priority grouping and available
phungductung 0:8ede47d38d10 1346 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
phungductung 0:8ede47d38d10 1347
phungductung 0:8ede47d38d10 1348 \param [in] PriorityGroup Priority grouping field.
phungductung 0:8ede47d38d10 1349 */
phungductung 0:8ede47d38d10 1350 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
phungductung 0:8ede47d38d10 1351 {
phungductung 0:8ede47d38d10 1352 uint32_t reg_value;
phungductung 0:8ede47d38d10 1353 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung 0:8ede47d38d10 1354
phungductung 0:8ede47d38d10 1355 reg_value = SCB->AIRCR; /* read old register configuration */
phungductung 0:8ede47d38d10 1356 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
phungductung 0:8ede47d38d10 1357 reg_value = (reg_value |
phungductung 0:8ede47d38d10 1358 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
phungductung 0:8ede47d38d10 1359 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
phungductung 0:8ede47d38d10 1360 SCB->AIRCR = reg_value;
phungductung 0:8ede47d38d10 1361 }
phungductung 0:8ede47d38d10 1362
phungductung 0:8ede47d38d10 1363
phungductung 0:8ede47d38d10 1364 /** \brief Get Priority Grouping
phungductung 0:8ede47d38d10 1365
phungductung 0:8ede47d38d10 1366 The function reads the priority grouping field from the NVIC Interrupt Controller.
phungductung 0:8ede47d38d10 1367
phungductung 0:8ede47d38d10 1368 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
phungductung 0:8ede47d38d10 1369 */
phungductung 0:8ede47d38d10 1370 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
phungductung 0:8ede47d38d10 1371 {
phungductung 0:8ede47d38d10 1372 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
phungductung 0:8ede47d38d10 1373 }
phungductung 0:8ede47d38d10 1374
phungductung 0:8ede47d38d10 1375
phungductung 0:8ede47d38d10 1376 /** \brief Enable External Interrupt
phungductung 0:8ede47d38d10 1377
phungductung 0:8ede47d38d10 1378 The function enables a device-specific interrupt in the NVIC interrupt controller.
phungductung 0:8ede47d38d10 1379
phungductung 0:8ede47d38d10 1380 \param [in] IRQn External interrupt number. Value cannot be negative.
phungductung 0:8ede47d38d10 1381 */
phungductung 0:8ede47d38d10 1382 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1383 {
phungductung 0:8ede47d38d10 1384 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:8ede47d38d10 1385 }
phungductung 0:8ede47d38d10 1386
phungductung 0:8ede47d38d10 1387
phungductung 0:8ede47d38d10 1388 /** \brief Disable External Interrupt
phungductung 0:8ede47d38d10 1389
phungductung 0:8ede47d38d10 1390 The function disables a device-specific interrupt in the NVIC interrupt controller.
phungductung 0:8ede47d38d10 1391
phungductung 0:8ede47d38d10 1392 \param [in] IRQn External interrupt number. Value cannot be negative.
phungductung 0:8ede47d38d10 1393 */
phungductung 0:8ede47d38d10 1394 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1395 {
phungductung 0:8ede47d38d10 1396 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:8ede47d38d10 1397 }
phungductung 0:8ede47d38d10 1398
phungductung 0:8ede47d38d10 1399
phungductung 0:8ede47d38d10 1400 /** \brief Get Pending Interrupt
phungductung 0:8ede47d38d10 1401
phungductung 0:8ede47d38d10 1402 The function reads the pending register in the NVIC and returns the pending bit
phungductung 0:8ede47d38d10 1403 for the specified interrupt.
phungductung 0:8ede47d38d10 1404
phungductung 0:8ede47d38d10 1405 \param [in] IRQn Interrupt number.
phungductung 0:8ede47d38d10 1406
phungductung 0:8ede47d38d10 1407 \return 0 Interrupt status is not pending.
phungductung 0:8ede47d38d10 1408 \return 1 Interrupt status is pending.
phungductung 0:8ede47d38d10 1409 */
phungductung 0:8ede47d38d10 1410 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1411 {
phungductung 0:8ede47d38d10 1412 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung 0:8ede47d38d10 1413 }
phungductung 0:8ede47d38d10 1414
phungductung 0:8ede47d38d10 1415
phungductung 0:8ede47d38d10 1416 /** \brief Set Pending Interrupt
phungductung 0:8ede47d38d10 1417
phungductung 0:8ede47d38d10 1418 The function sets the pending bit of an external interrupt.
phungductung 0:8ede47d38d10 1419
phungductung 0:8ede47d38d10 1420 \param [in] IRQn Interrupt number. Value cannot be negative.
phungductung 0:8ede47d38d10 1421 */
phungductung 0:8ede47d38d10 1422 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1423 {
phungductung 0:8ede47d38d10 1424 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:8ede47d38d10 1425 }
phungductung 0:8ede47d38d10 1426
phungductung 0:8ede47d38d10 1427
phungductung 0:8ede47d38d10 1428 /** \brief Clear Pending Interrupt
phungductung 0:8ede47d38d10 1429
phungductung 0:8ede47d38d10 1430 The function clears the pending bit of an external interrupt.
phungductung 0:8ede47d38d10 1431
phungductung 0:8ede47d38d10 1432 \param [in] IRQn External interrupt number. Value cannot be negative.
phungductung 0:8ede47d38d10 1433 */
phungductung 0:8ede47d38d10 1434 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1435 {
phungductung 0:8ede47d38d10 1436 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
phungductung 0:8ede47d38d10 1437 }
phungductung 0:8ede47d38d10 1438
phungductung 0:8ede47d38d10 1439
phungductung 0:8ede47d38d10 1440 /** \brief Get Active Interrupt
phungductung 0:8ede47d38d10 1441
phungductung 0:8ede47d38d10 1442 The function reads the active register in NVIC and returns the active bit.
phungductung 0:8ede47d38d10 1443
phungductung 0:8ede47d38d10 1444 \param [in] IRQn Interrupt number.
phungductung 0:8ede47d38d10 1445
phungductung 0:8ede47d38d10 1446 \return 0 Interrupt status is not active.
phungductung 0:8ede47d38d10 1447 \return 1 Interrupt status is active.
phungductung 0:8ede47d38d10 1448 */
phungductung 0:8ede47d38d10 1449 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1450 {
phungductung 0:8ede47d38d10 1451 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
phungductung 0:8ede47d38d10 1452 }
phungductung 0:8ede47d38d10 1453
phungductung 0:8ede47d38d10 1454
phungductung 0:8ede47d38d10 1455 /** \brief Set Interrupt Priority
phungductung 0:8ede47d38d10 1456
phungductung 0:8ede47d38d10 1457 The function sets the priority of an interrupt.
phungductung 0:8ede47d38d10 1458
phungductung 0:8ede47d38d10 1459 \note The priority cannot be set for every core interrupt.
phungductung 0:8ede47d38d10 1460
phungductung 0:8ede47d38d10 1461 \param [in] IRQn Interrupt number.
phungductung 0:8ede47d38d10 1462 \param [in] priority Priority to set.
phungductung 0:8ede47d38d10 1463 */
phungductung 0:8ede47d38d10 1464 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
phungductung 0:8ede47d38d10 1465 {
phungductung 0:8ede47d38d10 1466 if((int32_t)IRQn < 0) {
phungductung 0:8ede47d38d10 1467 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
phungductung 0:8ede47d38d10 1468 }
phungductung 0:8ede47d38d10 1469 else {
phungductung 0:8ede47d38d10 1470 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
phungductung 0:8ede47d38d10 1471 }
phungductung 0:8ede47d38d10 1472 }
phungductung 0:8ede47d38d10 1473
phungductung 0:8ede47d38d10 1474
phungductung 0:8ede47d38d10 1475 /** \brief Get Interrupt Priority
phungductung 0:8ede47d38d10 1476
phungductung 0:8ede47d38d10 1477 The function reads the priority of an interrupt. The interrupt
phungductung 0:8ede47d38d10 1478 number can be positive to specify an external (device specific)
phungductung 0:8ede47d38d10 1479 interrupt, or negative to specify an internal (core) interrupt.
phungductung 0:8ede47d38d10 1480
phungductung 0:8ede47d38d10 1481
phungductung 0:8ede47d38d10 1482 \param [in] IRQn Interrupt number.
phungductung 0:8ede47d38d10 1483 \return Interrupt Priority. Value is aligned automatically to the implemented
phungductung 0:8ede47d38d10 1484 priority bits of the microcontroller.
phungductung 0:8ede47d38d10 1485 */
phungductung 0:8ede47d38d10 1486 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
phungductung 0:8ede47d38d10 1487 {
phungductung 0:8ede47d38d10 1488
phungductung 0:8ede47d38d10 1489 if((int32_t)IRQn < 0) {
phungductung 0:8ede47d38d10 1490 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
phungductung 0:8ede47d38d10 1491 }
phungductung 0:8ede47d38d10 1492 else {
phungductung 0:8ede47d38d10 1493 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
phungductung 0:8ede47d38d10 1494 }
phungductung 0:8ede47d38d10 1495 }
phungductung 0:8ede47d38d10 1496
phungductung 0:8ede47d38d10 1497
phungductung 0:8ede47d38d10 1498 /** \brief Encode Priority
phungductung 0:8ede47d38d10 1499
phungductung 0:8ede47d38d10 1500 The function encodes the priority for an interrupt with the given priority group,
phungductung 0:8ede47d38d10 1501 preemptive priority value, and subpriority value.
phungductung 0:8ede47d38d10 1502 In case of a conflict between priority grouping and available
phungductung 0:8ede47d38d10 1503 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
phungductung 0:8ede47d38d10 1504
phungductung 0:8ede47d38d10 1505 \param [in] PriorityGroup Used priority group.
phungductung 0:8ede47d38d10 1506 \param [in] PreemptPriority Preemptive priority value (starting from 0).
phungductung 0:8ede47d38d10 1507 \param [in] SubPriority Subpriority value (starting from 0).
phungductung 0:8ede47d38d10 1508 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
phungductung 0:8ede47d38d10 1509 */
phungductung 0:8ede47d38d10 1510 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
phungductung 0:8ede47d38d10 1511 {
phungductung 0:8ede47d38d10 1512 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung 0:8ede47d38d10 1513 uint32_t PreemptPriorityBits;
phungductung 0:8ede47d38d10 1514 uint32_t SubPriorityBits;
phungductung 0:8ede47d38d10 1515
phungductung 0:8ede47d38d10 1516 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
phungductung 0:8ede47d38d10 1517 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
phungductung 0:8ede47d38d10 1518
phungductung 0:8ede47d38d10 1519 return (
phungductung 0:8ede47d38d10 1520 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
phungductung 0:8ede47d38d10 1521 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
phungductung 0:8ede47d38d10 1522 );
phungductung 0:8ede47d38d10 1523 }
phungductung 0:8ede47d38d10 1524
phungductung 0:8ede47d38d10 1525
phungductung 0:8ede47d38d10 1526 /** \brief Decode Priority
phungductung 0:8ede47d38d10 1527
phungductung 0:8ede47d38d10 1528 The function decodes an interrupt priority value with a given priority group to
phungductung 0:8ede47d38d10 1529 preemptive priority value and subpriority value.
phungductung 0:8ede47d38d10 1530 In case of a conflict between priority grouping and available
phungductung 0:8ede47d38d10 1531 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
phungductung 0:8ede47d38d10 1532
phungductung 0:8ede47d38d10 1533 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
phungductung 0:8ede47d38d10 1534 \param [in] PriorityGroup Used priority group.
phungductung 0:8ede47d38d10 1535 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
phungductung 0:8ede47d38d10 1536 \param [out] pSubPriority Subpriority value (starting from 0).
phungductung 0:8ede47d38d10 1537 */
phungductung 0:8ede47d38d10 1538 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
phungductung 0:8ede47d38d10 1539 {
phungductung 0:8ede47d38d10 1540 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
phungductung 0:8ede47d38d10 1541 uint32_t PreemptPriorityBits;
phungductung 0:8ede47d38d10 1542 uint32_t SubPriorityBits;
phungductung 0:8ede47d38d10 1543
phungductung 0:8ede47d38d10 1544 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
phungductung 0:8ede47d38d10 1545 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
phungductung 0:8ede47d38d10 1546
phungductung 0:8ede47d38d10 1547 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
phungductung 0:8ede47d38d10 1548 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
phungductung 0:8ede47d38d10 1549 }
phungductung 0:8ede47d38d10 1550
phungductung 0:8ede47d38d10 1551
phungductung 0:8ede47d38d10 1552 /** \brief System Reset
phungductung 0:8ede47d38d10 1553
phungductung 0:8ede47d38d10 1554 The function initiates a system reset request to reset the MCU.
phungductung 0:8ede47d38d10 1555 */
phungductung 0:8ede47d38d10 1556 __STATIC_INLINE void NVIC_SystemReset(void)
phungductung 0:8ede47d38d10 1557 {
phungductung 0:8ede47d38d10 1558 __DSB(); /* Ensure all outstanding memory accesses included
phungductung 0:8ede47d38d10 1559 buffered write are completed before reset */
phungductung 0:8ede47d38d10 1560 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
phungductung 0:8ede47d38d10 1561 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
phungductung 0:8ede47d38d10 1562 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
phungductung 0:8ede47d38d10 1563 __DSB(); /* Ensure completion of memory access */
phungductung 0:8ede47d38d10 1564 while(1) { __NOP(); } /* wait until reset */
phungductung 0:8ede47d38d10 1565 }
phungductung 0:8ede47d38d10 1566
phungductung 0:8ede47d38d10 1567 /*@} end of CMSIS_Core_NVICFunctions */
phungductung 0:8ede47d38d10 1568
phungductung 0:8ede47d38d10 1569
phungductung 0:8ede47d38d10 1570
phungductung 0:8ede47d38d10 1571 /* ################################## SysTick function ############################################ */
phungductung 0:8ede47d38d10 1572 /** \ingroup CMSIS_Core_FunctionInterface
phungductung 0:8ede47d38d10 1573 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
phungductung 0:8ede47d38d10 1574 \brief Functions that configure the System.
phungductung 0:8ede47d38d10 1575 @{
phungductung 0:8ede47d38d10 1576 */
phungductung 0:8ede47d38d10 1577
phungductung 0:8ede47d38d10 1578 #if (__Vendor_SysTickConfig == 0)
phungductung 0:8ede47d38d10 1579
phungductung 0:8ede47d38d10 1580 /** \brief System Tick Configuration
phungductung 0:8ede47d38d10 1581
phungductung 0:8ede47d38d10 1582 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
phungductung 0:8ede47d38d10 1583 Counter is in free running mode to generate periodic interrupts.
phungductung 0:8ede47d38d10 1584
phungductung 0:8ede47d38d10 1585 \param [in] ticks Number of ticks between two interrupts.
phungductung 0:8ede47d38d10 1586
phungductung 0:8ede47d38d10 1587 \return 0 Function succeeded.
phungductung 0:8ede47d38d10 1588 \return 1 Function failed.
phungductung 0:8ede47d38d10 1589
phungductung 0:8ede47d38d10 1590 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
phungductung 0:8ede47d38d10 1591 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
phungductung 0:8ede47d38d10 1592 must contain a vendor-specific implementation of this function.
phungductung 0:8ede47d38d10 1593
phungductung 0:8ede47d38d10 1594 */
phungductung 0:8ede47d38d10 1595 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
phungductung 0:8ede47d38d10 1596 {
phungductung 0:8ede47d38d10 1597 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
phungductung 0:8ede47d38d10 1598
phungductung 0:8ede47d38d10 1599 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
phungductung 0:8ede47d38d10 1600 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
phungductung 0:8ede47d38d10 1601 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
phungductung 0:8ede47d38d10 1602 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
phungductung 0:8ede47d38d10 1603 SysTick_CTRL_TICKINT_Msk |
phungductung 0:8ede47d38d10 1604 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
phungductung 0:8ede47d38d10 1605 return (0UL); /* Function successful */
phungductung 0:8ede47d38d10 1606 }
phungductung 0:8ede47d38d10 1607
phungductung 0:8ede47d38d10 1608 #endif
phungductung 0:8ede47d38d10 1609
phungductung 0:8ede47d38d10 1610 /*@} end of CMSIS_Core_SysTickFunctions */
phungductung 0:8ede47d38d10 1611
phungductung 0:8ede47d38d10 1612
phungductung 0:8ede47d38d10 1613
phungductung 0:8ede47d38d10 1614 /* ##################################### Debug In/Output function ########################################### */
phungductung 0:8ede47d38d10 1615 /** \ingroup CMSIS_Core_FunctionInterface
phungductung 0:8ede47d38d10 1616 \defgroup CMSIS_core_DebugFunctions ITM Functions
phungductung 0:8ede47d38d10 1617 \brief Functions that access the ITM debug interface.
phungductung 0:8ede47d38d10 1618 @{
phungductung 0:8ede47d38d10 1619 */
phungductung 0:8ede47d38d10 1620
phungductung 0:8ede47d38d10 1621 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
phungductung 0:8ede47d38d10 1622 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
phungductung 0:8ede47d38d10 1623
phungductung 0:8ede47d38d10 1624
phungductung 0:8ede47d38d10 1625 /** \brief ITM Send Character
phungductung 0:8ede47d38d10 1626
phungductung 0:8ede47d38d10 1627 The function transmits a character via the ITM channel 0, and
phungductung 0:8ede47d38d10 1628 \li Just returns when no debugger is connected that has booked the output.
phungductung 0:8ede47d38d10 1629 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
phungductung 0:8ede47d38d10 1630
phungductung 0:8ede47d38d10 1631 \param [in] ch Character to transmit.
phungductung 0:8ede47d38d10 1632
phungductung 0:8ede47d38d10 1633 \returns Character to transmit.
phungductung 0:8ede47d38d10 1634 */
phungductung 0:8ede47d38d10 1635 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
phungductung 0:8ede47d38d10 1636 {
phungductung 0:8ede47d38d10 1637 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
phungductung 0:8ede47d38d10 1638 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
phungductung 0:8ede47d38d10 1639 {
phungductung 0:8ede47d38d10 1640 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
phungductung 0:8ede47d38d10 1641 ITM->PORT[0].u8 = (uint8_t)ch;
phungductung 0:8ede47d38d10 1642 }
phungductung 0:8ede47d38d10 1643 return (ch);
phungductung 0:8ede47d38d10 1644 }
phungductung 0:8ede47d38d10 1645
phungductung 0:8ede47d38d10 1646
phungductung 0:8ede47d38d10 1647 /** \brief ITM Receive Character
phungductung 0:8ede47d38d10 1648
phungductung 0:8ede47d38d10 1649 The function inputs a character via the external variable \ref ITM_RxBuffer.
phungductung 0:8ede47d38d10 1650
phungductung 0:8ede47d38d10 1651 \return Received character.
phungductung 0:8ede47d38d10 1652 \return -1 No character pending.
phungductung 0:8ede47d38d10 1653 */
phungductung 0:8ede47d38d10 1654 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
phungductung 0:8ede47d38d10 1655 int32_t ch = -1; /* no character available */
phungductung 0:8ede47d38d10 1656
phungductung 0:8ede47d38d10 1657 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
phungductung 0:8ede47d38d10 1658 ch = ITM_RxBuffer;
phungductung 0:8ede47d38d10 1659 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
phungductung 0:8ede47d38d10 1660 }
phungductung 0:8ede47d38d10 1661
phungductung 0:8ede47d38d10 1662 return (ch);
phungductung 0:8ede47d38d10 1663 }
phungductung 0:8ede47d38d10 1664
phungductung 0:8ede47d38d10 1665
phungductung 0:8ede47d38d10 1666 /** \brief ITM Check Character
phungductung 0:8ede47d38d10 1667
phungductung 0:8ede47d38d10 1668 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
phungductung 0:8ede47d38d10 1669
phungductung 0:8ede47d38d10 1670 \return 0 No character available.
phungductung 0:8ede47d38d10 1671 \return 1 Character available.
phungductung 0:8ede47d38d10 1672 */
phungductung 0:8ede47d38d10 1673 __STATIC_INLINE int32_t ITM_CheckChar (void) {
phungductung 0:8ede47d38d10 1674
phungductung 0:8ede47d38d10 1675 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
phungductung 0:8ede47d38d10 1676 return (0); /* no character available */
phungductung 0:8ede47d38d10 1677 } else {
phungductung 0:8ede47d38d10 1678 return (1); /* character available */
phungductung 0:8ede47d38d10 1679 }
phungductung 0:8ede47d38d10 1680 }
phungductung 0:8ede47d38d10 1681
phungductung 0:8ede47d38d10 1682 /*@} end of CMSIS_core_DebugFunctions */
phungductung 0:8ede47d38d10 1683
phungductung 0:8ede47d38d10 1684
phungductung 0:8ede47d38d10 1685
phungductung 0:8ede47d38d10 1686
phungductung 0:8ede47d38d10 1687 #ifdef __cplusplus
phungductung 0:8ede47d38d10 1688 }
phungductung 0:8ede47d38d10 1689 #endif
phungductung 0:8ede47d38d10 1690
phungductung 0:8ede47d38d10 1691 #endif /* __CORE_CM3_H_DEPENDANT */
phungductung 0:8ede47d38d10 1692
phungductung 0:8ede47d38d10 1693 #endif /* __CMSIS_GENERIC */