DISCO-F746_WAV_PLAYER - SPKT

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Dependencies: F746_GUI SD_PlayerSkeleton F746_SAI_IO

SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:37:21 2019 +0000
Revision:: 0:8ede47d38d10

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User	Revision	Line number	New contents of line
phungductung	0:8ede47d38d10	1	/**
phungductung	0:8ede47d38d10	2	******************************************************************************
phungductung	0:8ede47d38d10	3	* @file stm32f7xx_ll_fmc.h
phungductung	0:8ede47d38d10	4	* @author MCD Application Team
phungductung	0:8ede47d38d10	5	* @version V1.0.4
phungductung	0:8ede47d38d10	6	* @date 09-December-2015
phungductung	0:8ede47d38d10	7	* @brief Header file of FMC HAL module.
phungductung	0:8ede47d38d10	8	******************************************************************************
phungductung	0:8ede47d38d10	9	* @attention
phungductung	0:8ede47d38d10	10	*
phungductung	0:8ede47d38d10	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung	0:8ede47d38d10	12	*
phungductung	0:8ede47d38d10	13	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:8ede47d38d10	14	* are permitted provided that the following conditions are met:
phungductung	0:8ede47d38d10	15	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:8ede47d38d10	16	* this list of conditions and the following disclaimer.
phungductung	0:8ede47d38d10	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:8ede47d38d10	18	* this list of conditions and the following disclaimer in the documentation
phungductung	0:8ede47d38d10	19	* and/or other materials provided with the distribution.
phungductung	0:8ede47d38d10	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:8ede47d38d10	21	* may be used to endorse or promote products derived from this software
phungductung	0:8ede47d38d10	22	* without specific prior written permission.
phungductung	0:8ede47d38d10	23	*
phungductung	0:8ede47d38d10	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:8ede47d38d10	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:8ede47d38d10	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:8ede47d38d10	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:8ede47d38d10	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:8ede47d38d10	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:8ede47d38d10	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:8ede47d38d10	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:8ede47d38d10	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:8ede47d38d10	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:8ede47d38d10	34	*
phungductung	0:8ede47d38d10	35	******************************************************************************
phungductung	0:8ede47d38d10	36	*/
phungductung	0:8ede47d38d10	37
phungductung	0:8ede47d38d10	38	/* Define to prevent recursive inclusion -------------------------------------*/
phungductung	0:8ede47d38d10	39	#ifndef __STM32F7xx_LL_FMC_H
phungductung	0:8ede47d38d10	40	#define __STM32F7xx_LL_FMC_H
phungductung	0:8ede47d38d10	41
phungductung	0:8ede47d38d10	42	#ifdef __cplusplus
phungductung	0:8ede47d38d10	43	extern "C" {
phungductung	0:8ede47d38d10	44	#endif
phungductung	0:8ede47d38d10	45
phungductung	0:8ede47d38d10	46	/* Includes ------------------------------------------------------------------*/
phungductung	0:8ede47d38d10	47	#include "stm32f7xx_hal_def.h"
phungductung	0:8ede47d38d10	48
phungductung	0:8ede47d38d10	49	/** @addtogroup STM32F7xx_HAL_Driver
phungductung	0:8ede47d38d10	50	* @{
phungductung	0:8ede47d38d10	51	*/
phungductung	0:8ede47d38d10	52
phungductung	0:8ede47d38d10	53	/** @addtogroup FMC_LL
phungductung	0:8ede47d38d10	54	* @{
phungductung	0:8ede47d38d10	55	*/
phungductung	0:8ede47d38d10	56
phungductung	0:8ede47d38d10	57	/** @addtogroup FMC_LL_Private_Macros
phungductung	0:8ede47d38d10	58	* @{
phungductung	0:8ede47d38d10	59	*/
phungductung	0:8ede47d38d10	60	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
phungductung	0:8ede47d38d10	61	((BANK) == FMC_NORSRAM_BANK2) \|\| \
phungductung	0:8ede47d38d10	62	((BANK) == FMC_NORSRAM_BANK3) \|\| \
phungductung	0:8ede47d38d10	63	((BANK) == FMC_NORSRAM_BANK4))
phungductung	0:8ede47d38d10	64
phungductung	0:8ede47d38d10	65	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
phungductung	0:8ede47d38d10	66	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
phungductung	0:8ede47d38d10	67
phungductung	0:8ede47d38d10	68	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
phungductung	0:8ede47d38d10	69	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
phungductung	0:8ede47d38d10	70	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
phungductung	0:8ede47d38d10	71
phungductung	0:8ede47d38d10	72	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
phungductung	0:8ede47d38d10	73	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
phungductung	0:8ede47d38d10	74	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
phungductung	0:8ede47d38d10	75
phungductung	0:8ede47d38d10	76	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
phungductung	0:8ede47d38d10	77	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
phungductung	0:8ede47d38d10	78	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
phungductung	0:8ede47d38d10	79	((__MODE__) == FMC_ACCESS_MODE_D))
phungductung	0:8ede47d38d10	80
phungductung	0:8ede47d38d10	81	#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
phungductung	0:8ede47d38d10	82
phungductung	0:8ede47d38d10	83	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) \|\| \
phungductung	0:8ede47d38d10	84	((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
phungductung	0:8ede47d38d10	85
phungductung	0:8ede47d38d10	86	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) \|\| \
phungductung	0:8ede47d38d10	87	((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
phungductung	0:8ede47d38d10	88
phungductung	0:8ede47d38d10	89	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
phungductung	0:8ede47d38d10	90	((STATE) == FMC_NAND_ECC_ENABLE))
phungductung	0:8ede47d38d10	91
phungductung	0:8ede47d38d10	92	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
phungductung	0:8ede47d38d10	93	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
phungductung	0:8ede47d38d10	94	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
phungductung	0:8ede47d38d10	95	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
phungductung	0:8ede47d38d10	96	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
phungductung	0:8ede47d38d10	97	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
phungductung	0:8ede47d38d10	98
phungductung	0:8ede47d38d10	99	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
phungductung	0:8ede47d38d10	100	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
phungductung	0:8ede47d38d10	101	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
phungductung	0:8ede47d38d10	102
phungductung	0:8ede47d38d10	103	#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
phungductung	0:8ede47d38d10	104	((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
phungductung	0:8ede47d38d10	105
phungductung	0:8ede47d38d10	106	#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
phungductung	0:8ede47d38d10	107	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
phungductung	0:8ede47d38d10	108	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
phungductung	0:8ede47d38d10	109
phungductung	0:8ede47d38d10	110	#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) \|\| \
phungductung	0:8ede47d38d10	111	((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
phungductung	0:8ede47d38d10	112
phungductung	0:8ede47d38d10	113	#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
phungductung	0:8ede47d38d10	114	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
phungductung	0:8ede47d38d10	115	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
phungductung	0:8ede47d38d10	116
phungductung	0:8ede47d38d10	117	#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
phungductung	0:8ede47d38d10	118	((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
phungductung	0:8ede47d38d10	119	((__COMMAND__) == FMC_SDRAM_CMD_PALL) \|\| \
phungductung	0:8ede47d38d10	120	((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
phungductung	0:8ede47d38d10	121	((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
phungductung	0:8ede47d38d10	122	((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
phungductung	0:8ede47d38d10	123	((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
phungductung	0:8ede47d38d10	124
phungductung	0:8ede47d38d10	125	#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
phungductung	0:8ede47d38d10	126	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
phungductung	0:8ede47d38d10	127	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
phungductung	0:8ede47d38d10	128
phungductung	0:8ede47d38d10	129	/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
phungductung	0:8ede47d38d10	130	* @{
phungductung	0:8ede47d38d10	131	*/
phungductung	0:8ede47d38d10	132	#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
phungductung	0:8ede47d38d10	133	/**
phungductung	0:8ede47d38d10	134	* @}
phungductung	0:8ede47d38d10	135	*/
phungductung	0:8ede47d38d10	136
phungductung	0:8ede47d38d10	137	/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
phungductung	0:8ede47d38d10	138	* @{
phungductung	0:8ede47d38d10	139	*/
phungductung	0:8ede47d38d10	140	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
phungductung	0:8ede47d38d10	141	/**
phungductung	0:8ede47d38d10	142	* @}
phungductung	0:8ede47d38d10	143	*/
phungductung	0:8ede47d38d10	144
phungductung	0:8ede47d38d10	145	/** @defgroup FMC_Setup_Time FMC Setup Time
phungductung	0:8ede47d38d10	146	* @{
phungductung	0:8ede47d38d10	147	*/
phungductung	0:8ede47d38d10	148	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
phungductung	0:8ede47d38d10	149	/**
phungductung	0:8ede47d38d10	150	* @}
phungductung	0:8ede47d38d10	151	*/
phungductung	0:8ede47d38d10	152
phungductung	0:8ede47d38d10	153	/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
phungductung	0:8ede47d38d10	154	* @{
phungductung	0:8ede47d38d10	155	*/
phungductung	0:8ede47d38d10	156	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
phungductung	0:8ede47d38d10	157	/**
phungductung	0:8ede47d38d10	158	* @}
phungductung	0:8ede47d38d10	159	*/
phungductung	0:8ede47d38d10	160
phungductung	0:8ede47d38d10	161	/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
phungductung	0:8ede47d38d10	162	* @{
phungductung	0:8ede47d38d10	163	*/
phungductung	0:8ede47d38d10	164	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
phungductung	0:8ede47d38d10	165	/**
phungductung	0:8ede47d38d10	166	* @}
phungductung	0:8ede47d38d10	167	*/
phungductung	0:8ede47d38d10	168
phungductung	0:8ede47d38d10	169	/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
phungductung	0:8ede47d38d10	170	* @{
phungductung	0:8ede47d38d10	171	*/
phungductung	0:8ede47d38d10	172	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
phungductung	0:8ede47d38d10	173	/**
phungductung	0:8ede47d38d10	174	* @}
phungductung	0:8ede47d38d10	175	*/
phungductung	0:8ede47d38d10	176
phungductung	0:8ede47d38d10	177	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
phungductung	0:8ede47d38d10	178	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
phungductung	0:8ede47d38d10	179
phungductung	0:8ede47d38d10	180	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
phungductung	0:8ede47d38d10	181	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
phungductung	0:8ede47d38d10	182
phungductung	0:8ede47d38d10	183	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
phungductung	0:8ede47d38d10	184	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
phungductung	0:8ede47d38d10	185
phungductung	0:8ede47d38d10	186	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
phungductung	0:8ede47d38d10	187	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
phungductung	0:8ede47d38d10	188
phungductung	0:8ede47d38d10	189	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
phungductung	0:8ede47d38d10	190	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
phungductung	0:8ede47d38d10	191
phungductung	0:8ede47d38d10	192	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
phungductung	0:8ede47d38d10	193	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
phungductung	0:8ede47d38d10	194
phungductung	0:8ede47d38d10	195	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
phungductung	0:8ede47d38d10	196	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
phungductung	0:8ede47d38d10	197
phungductung	0:8ede47d38d10	198	/** @defgroup FMC_Data_Latency FMC Data Latency
phungductung	0:8ede47d38d10	199	* @{
phungductung	0:8ede47d38d10	200	*/
phungductung	0:8ede47d38d10	201	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
phungductung	0:8ede47d38d10	202	/**
phungductung	0:8ede47d38d10	203	* @}
phungductung	0:8ede47d38d10	204	*/
phungductung	0:8ede47d38d10	205
phungductung	0:8ede47d38d10	206	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
phungductung	0:8ede47d38d10	207	((__BURST__) == FMC_WRITE_BURST_ENABLE))
phungductung	0:8ede47d38d10	208
phungductung	0:8ede47d38d10	209	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
phungductung	0:8ede47d38d10	210	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
phungductung	0:8ede47d38d10	211
phungductung	0:8ede47d38d10	212
phungductung	0:8ede47d38d10	213	/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
phungductung	0:8ede47d38d10	214	* @{
phungductung	0:8ede47d38d10	215	*/
phungductung	0:8ede47d38d10	216	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
phungductung	0:8ede47d38d10	217	/**
phungductung	0:8ede47d38d10	218	* @}
phungductung	0:8ede47d38d10	219	*/
phungductung	0:8ede47d38d10	220
phungductung	0:8ede47d38d10	221	/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
phungductung	0:8ede47d38d10	222	* @{
phungductung	0:8ede47d38d10	223	*/
phungductung	0:8ede47d38d10	224	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
phungductung	0:8ede47d38d10	225	/**
phungductung	0:8ede47d38d10	226	* @}
phungductung	0:8ede47d38d10	227	*/
phungductung	0:8ede47d38d10	228
phungductung	0:8ede47d38d10	229	/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
phungductung	0:8ede47d38d10	230	* @{
phungductung	0:8ede47d38d10	231	*/
phungductung	0:8ede47d38d10	232	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
phungductung	0:8ede47d38d10	233	/**
phungductung	0:8ede47d38d10	234	* @}
phungductung	0:8ede47d38d10	235	*/
phungductung	0:8ede47d38d10	236
phungductung	0:8ede47d38d10	237	/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
phungductung	0:8ede47d38d10	238	* @{
phungductung	0:8ede47d38d10	239	*/
phungductung	0:8ede47d38d10	240	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
phungductung	0:8ede47d38d10	241	/**
phungductung	0:8ede47d38d10	242	* @}
phungductung	0:8ede47d38d10	243	*/
phungductung	0:8ede47d38d10	244
phungductung	0:8ede47d38d10	245	/** @defgroup FMC_CLK_Division FMC CLK Division
phungductung	0:8ede47d38d10	246	* @{
phungductung	0:8ede47d38d10	247	*/
phungductung	0:8ede47d38d10	248	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
phungductung	0:8ede47d38d10	249	/**
phungductung	0:8ede47d38d10	250	* @}
phungductung	0:8ede47d38d10	251	*/
phungductung	0:8ede47d38d10	252
phungductung	0:8ede47d38d10	253	/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
phungductung	0:8ede47d38d10	254	* @{
phungductung	0:8ede47d38d10	255	*/
phungductung	0:8ede47d38d10	256	#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
phungductung	0:8ede47d38d10	257	/**
phungductung	0:8ede47d38d10	258	* @}
phungductung	0:8ede47d38d10	259	*/
phungductung	0:8ede47d38d10	260
phungductung	0:8ede47d38d10	261	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
phungductung	0:8ede47d38d10	262	* @{
phungductung	0:8ede47d38d10	263	*/
phungductung	0:8ede47d38d10	264	#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
phungductung	0:8ede47d38d10	265	/**
phungductung	0:8ede47d38d10	266	* @}
phungductung	0:8ede47d38d10	267	*/
phungductung	0:8ede47d38d10	268
phungductung	0:8ede47d38d10	269	/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
phungductung	0:8ede47d38d10	270	* @{
phungductung	0:8ede47d38d10	271	*/
phungductung	0:8ede47d38d10	272	#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
phungductung	0:8ede47d38d10	273	/**
phungductung	0:8ede47d38d10	274	* @}
phungductung	0:8ede47d38d10	275	*/
phungductung	0:8ede47d38d10	276
phungductung	0:8ede47d38d10	277	/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
phungductung	0:8ede47d38d10	278	* @{
phungductung	0:8ede47d38d10	279	*/
phungductung	0:8ede47d38d10	280	#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
phungductung	0:8ede47d38d10	281	/**
phungductung	0:8ede47d38d10	282	* @}
phungductung	0:8ede47d38d10	283	*/
phungductung	0:8ede47d38d10	284
phungductung	0:8ede47d38d10	285	/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
phungductung	0:8ede47d38d10	286	* @{
phungductung	0:8ede47d38d10	287	*/
phungductung	0:8ede47d38d10	288	#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
phungductung	0:8ede47d38d10	289	/**
phungductung	0:8ede47d38d10	290	* @}
phungductung	0:8ede47d38d10	291	*/
phungductung	0:8ede47d38d10	292
phungductung	0:8ede47d38d10	293	/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
phungductung	0:8ede47d38d10	294	* @{
phungductung	0:8ede47d38d10	295	*/
phungductung	0:8ede47d38d10	296	#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
phungductung	0:8ede47d38d10	297	/**
phungductung	0:8ede47d38d10	298	* @}
phungductung	0:8ede47d38d10	299	*/
phungductung	0:8ede47d38d10	300
phungductung	0:8ede47d38d10	301	/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
phungductung	0:8ede47d38d10	302	* @{
phungductung	0:8ede47d38d10	303	*/
phungductung	0:8ede47d38d10	304	#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
phungductung	0:8ede47d38d10	305	/**
phungductung	0:8ede47d38d10	306	* @}
phungductung	0:8ede47d38d10	307	*/
phungductung	0:8ede47d38d10	308
phungductung	0:8ede47d38d10	309	/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
phungductung	0:8ede47d38d10	310	* @{
phungductung	0:8ede47d38d10	311	*/
phungductung	0:8ede47d38d10	312	#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
phungductung	0:8ede47d38d10	313	/**
phungductung	0:8ede47d38d10	314	* @}
phungductung	0:8ede47d38d10	315	*/
phungductung	0:8ede47d38d10	316
phungductung	0:8ede47d38d10	317	/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
phungductung	0:8ede47d38d10	318	* @{
phungductung	0:8ede47d38d10	319	*/
phungductung	0:8ede47d38d10	320	#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
phungductung	0:8ede47d38d10	321	/**
phungductung	0:8ede47d38d10	322	* @}
phungductung	0:8ede47d38d10	323	*/
phungductung	0:8ede47d38d10	324
phungductung	0:8ede47d38d10	325	/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
phungductung	0:8ede47d38d10	326	* @{
phungductung	0:8ede47d38d10	327	*/
phungductung	0:8ede47d38d10	328	#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
phungductung	0:8ede47d38d10	329	/**
phungductung	0:8ede47d38d10	330	* @}
phungductung	0:8ede47d38d10	331	*/
phungductung	0:8ede47d38d10	332
phungductung	0:8ede47d38d10	333	/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
phungductung	0:8ede47d38d10	334	* @{
phungductung	0:8ede47d38d10	335	*/
phungductung	0:8ede47d38d10	336	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
phungductung	0:8ede47d38d10	337	/**
phungductung	0:8ede47d38d10	338	* @}
phungductung	0:8ede47d38d10	339	*/
phungductung	0:8ede47d38d10	340
phungductung	0:8ede47d38d10	341	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
phungductung	0:8ede47d38d10	342	* @{
phungductung	0:8ede47d38d10	343	*/
phungductung	0:8ede47d38d10	344	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
phungductung	0:8ede47d38d10	345	/**
phungductung	0:8ede47d38d10	346	* @}
phungductung	0:8ede47d38d10	347	*/
phungductung	0:8ede47d38d10	348
phungductung	0:8ede47d38d10	349	/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
phungductung	0:8ede47d38d10	350	* @{
phungductung	0:8ede47d38d10	351	*/
phungductung	0:8ede47d38d10	352	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
phungductung	0:8ede47d38d10	353	/**
phungductung	0:8ede47d38d10	354	* @}
phungductung	0:8ede47d38d10	355	*/
phungductung	0:8ede47d38d10	356
phungductung	0:8ede47d38d10	357	/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
phungductung	0:8ede47d38d10	358	* @{
phungductung	0:8ede47d38d10	359	*/
phungductung	0:8ede47d38d10	360	#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
phungductung	0:8ede47d38d10	361	/**
phungductung	0:8ede47d38d10	362	* @}
phungductung	0:8ede47d38d10	363	*/
phungductung	0:8ede47d38d10	364
phungductung	0:8ede47d38d10	365	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
phungductung	0:8ede47d38d10	366	((BANK) == FMC_SDRAM_BANK2))
phungductung	0:8ede47d38d10	367
phungductung	0:8ede47d38d10	368	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
phungductung	0:8ede47d38d10	369	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
phungductung	0:8ede47d38d10	370	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
phungductung	0:8ede47d38d10	371	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
phungductung	0:8ede47d38d10	372
phungductung	0:8ede47d38d10	373	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
phungductung	0:8ede47d38d10	374	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
phungductung	0:8ede47d38d10	375	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
phungductung	0:8ede47d38d10	376
phungductung	0:8ede47d38d10	377	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
phungductung	0:8ede47d38d10	378	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
phungductung	0:8ede47d38d10	379
phungductung	0:8ede47d38d10	380
phungductung	0:8ede47d38d10	381	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
phungductung	0:8ede47d38d10	382	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
phungductung	0:8ede47d38d10	383	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
phungductung	0:8ede47d38d10	384
phungductung	0:8ede47d38d10	385	#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) \|\| \
phungductung	0:8ede47d38d10	386	((__SIZE__) == FMC_PAGE_SIZE_128) \|\| \
phungductung	0:8ede47d38d10	387	((__SIZE__) == FMC_PAGE_SIZE_256) \|\| \
phungductung	0:8ede47d38d10	388	((__SIZE__) == FMC_PAGE_SIZE_512) \|\| \
phungductung	0:8ede47d38d10	389	((__SIZE__) == FMC_PAGE_SIZE_1024))
phungductung	0:8ede47d38d10	390
phungductung	0:8ede47d38d10	391	#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) \|\| \
phungductung	0:8ede47d38d10	392	((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
phungductung	0:8ede47d38d10	393	/**
phungductung	0:8ede47d38d10	394	* @}
phungductung	0:8ede47d38d10	395	*/
phungductung	0:8ede47d38d10	396
phungductung	0:8ede47d38d10	397	/* Exported typedef ----------------------------------------------------------*/
phungductung	0:8ede47d38d10	398	/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
phungductung	0:8ede47d38d10	399	* @{
phungductung	0:8ede47d38d10	400	*/
phungductung	0:8ede47d38d10	401	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
phungductung	0:8ede47d38d10	402	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
phungductung	0:8ede47d38d10	403	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
phungductung	0:8ede47d38d10	404	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
phungductung	0:8ede47d38d10	405
phungductung	0:8ede47d38d10	406	#define FMC_NORSRAM_DEVICE FMC_Bank1
phungductung	0:8ede47d38d10	407	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
phungductung	0:8ede47d38d10	408	#define FMC_NAND_DEVICE FMC_Bank3
phungductung	0:8ede47d38d10	409	#define FMC_SDRAM_DEVICE FMC_Bank5_6
phungductung	0:8ede47d38d10	410
phungductung	0:8ede47d38d10	411	/**
phungductung	0:8ede47d38d10	412	* @brief FMC NORSRAM Configuration Structure definition
phungductung	0:8ede47d38d10	413	*/
phungductung	0:8ede47d38d10	414	typedef struct
phungductung	0:8ede47d38d10	415	{
phungductung	0:8ede47d38d10	416	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
phungductung	0:8ede47d38d10	417	This parameter can be a value of @ref FMC_NORSRAM_Bank */
phungductung	0:8ede47d38d10	418
phungductung	0:8ede47d38d10	419	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
phungductung	0:8ede47d38d10	420	multiplexed on the data bus or not.
phungductung	0:8ede47d38d10	421	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
phungductung	0:8ede47d38d10	422
phungductung	0:8ede47d38d10	423	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
phungductung	0:8ede47d38d10	424	the corresponding memory device.
phungductung	0:8ede47d38d10	425	This parameter can be a value of @ref FMC_Memory_Type */
phungductung	0:8ede47d38d10	426
phungductung	0:8ede47d38d10	427	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
phungductung	0:8ede47d38d10	428	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
phungductung	0:8ede47d38d10	429
phungductung	0:8ede47d38d10	430	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
phungductung	0:8ede47d38d10	431	valid only with synchronous burst Flash memories.
phungductung	0:8ede47d38d10	432	This parameter can be a value of @ref FMC_Burst_Access_Mode */
phungductung	0:8ede47d38d10	433
phungductung	0:8ede47d38d10	434	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
phungductung	0:8ede47d38d10	435	the Flash memory in burst mode.
phungductung	0:8ede47d38d10	436	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
phungductung	0:8ede47d38d10	437
phungductung	0:8ede47d38d10	438	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
phungductung	0:8ede47d38d10	439	clock cycle before the wait state or during the wait state,
phungductung	0:8ede47d38d10	440	valid only when accessing memories in burst mode.
phungductung	0:8ede47d38d10	441	This parameter can be a value of @ref FMC_Wait_Timing */
phungductung	0:8ede47d38d10	442
phungductung	0:8ede47d38d10	443	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
phungductung	0:8ede47d38d10	444	This parameter can be a value of @ref FMC_Write_Operation */
phungductung	0:8ede47d38d10	445
phungductung	0:8ede47d38d10	446	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
phungductung	0:8ede47d38d10	447	signal, valid for Flash memory access in burst mode.
phungductung	0:8ede47d38d10	448	This parameter can be a value of @ref FMC_Wait_Signal */
phungductung	0:8ede47d38d10	449
phungductung	0:8ede47d38d10	450	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
phungductung	0:8ede47d38d10	451	This parameter can be a value of @ref FMC_Extended_Mode */
phungductung	0:8ede47d38d10	452
phungductung	0:8ede47d38d10	453	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
phungductung	0:8ede47d38d10	454	valid only with asynchronous Flash memories.
phungductung	0:8ede47d38d10	455	This parameter can be a value of @ref FMC_AsynchronousWait */
phungductung	0:8ede47d38d10	456
phungductung	0:8ede47d38d10	457	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
phungductung	0:8ede47d38d10	458	This parameter can be a value of @ref FMC_Write_Burst */
phungductung	0:8ede47d38d10	459
phungductung	0:8ede47d38d10	460	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
phungductung	0:8ede47d38d10	461	This parameter is only enabled through the FMC_BCR1 register, and don't care
phungductung	0:8ede47d38d10	462	through FMC_BCR2..4 registers.
phungductung	0:8ede47d38d10	463	This parameter can be a value of @ref FMC_Continous_Clock */
phungductung	0:8ede47d38d10	464
phungductung	0:8ede47d38d10	465	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
phungductung	0:8ede47d38d10	466	This parameter is only enabled through the FMC_BCR1 register, and don't care
phungductung	0:8ede47d38d10	467	through FMC_BCR2..4 registers.
phungductung	0:8ede47d38d10	468	This parameter can be a value of @ref FMC_Write_FIFO */
phungductung	0:8ede47d38d10	469
phungductung	0:8ede47d38d10	470	uint32_t PageSize; /*!< Specifies the memory page size.
phungductung	0:8ede47d38d10	471	This parameter can be a value of @ref FMC_Page_Size */
phungductung	0:8ede47d38d10	472
phungductung	0:8ede47d38d10	473	}FMC_NORSRAM_InitTypeDef;
phungductung	0:8ede47d38d10	474
phungductung	0:8ede47d38d10	475	/**
phungductung	0:8ede47d38d10	476	* @brief FMC NORSRAM Timing parameters structure definition
phungductung	0:8ede47d38d10	477	*/
phungductung	0:8ede47d38d10	478	typedef struct
phungductung	0:8ede47d38d10	479	{
phungductung	0:8ede47d38d10	480	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
phungductung	0:8ede47d38d10	481	the duration of the address setup time.
phungductung	0:8ede47d38d10	482	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
phungductung	0:8ede47d38d10	483	@note This parameter is not used with synchronous NOR Flash memories. */
phungductung	0:8ede47d38d10	484
phungductung	0:8ede47d38d10	485	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
phungductung	0:8ede47d38d10	486	the duration of the address hold time.
phungductung	0:8ede47d38d10	487	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
phungductung	0:8ede47d38d10	488	@note This parameter is not used with synchronous NOR Flash memories. */
phungductung	0:8ede47d38d10	489
phungductung	0:8ede47d38d10	490	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
phungductung	0:8ede47d38d10	491	the duration of the data setup time.
phungductung	0:8ede47d38d10	492	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
phungductung	0:8ede47d38d10	493	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
phungductung	0:8ede47d38d10	494	NOR Flash memories. */
phungductung	0:8ede47d38d10	495
phungductung	0:8ede47d38d10	496	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
phungductung	0:8ede47d38d10	497	the duration of the bus turnaround.
phungductung	0:8ede47d38d10	498	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
phungductung	0:8ede47d38d10	499	@note This parameter is only used for multiplexed NOR Flash memories. */
phungductung	0:8ede47d38d10	500
phungductung	0:8ede47d38d10	501	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
phungductung	0:8ede47d38d10	502	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
phungductung	0:8ede47d38d10	503	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
phungductung	0:8ede47d38d10	504	accesses. */
phungductung	0:8ede47d38d10	505
phungductung	0:8ede47d38d10	506	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
phungductung	0:8ede47d38d10	507	to the memory before getting the first data.
phungductung	0:8ede47d38d10	508	The parameter value depends on the memory type as shown below:
phungductung	0:8ede47d38d10	509	- It must be set to 0 in case of a CRAM
phungductung	0:8ede47d38d10	510	- It is don't care in asynchronous NOR, SRAM or ROM accesses
phungductung	0:8ede47d38d10	511	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
phungductung	0:8ede47d38d10	512	with synchronous burst mode enable */
phungductung	0:8ede47d38d10	513
phungductung	0:8ede47d38d10	514	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
phungductung	0:8ede47d38d10	515	This parameter can be a value of @ref FMC_Access_Mode */
phungductung	0:8ede47d38d10	516	}FMC_NORSRAM_TimingTypeDef;
phungductung	0:8ede47d38d10	517
phungductung	0:8ede47d38d10	518	/**
phungductung	0:8ede47d38d10	519	* @brief FMC NAND Configuration Structure definition
phungductung	0:8ede47d38d10	520	*/
phungductung	0:8ede47d38d10	521	typedef struct
phungductung	0:8ede47d38d10	522	{
phungductung	0:8ede47d38d10	523	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
phungductung	0:8ede47d38d10	524	This parameter can be a value of @ref FMC_NAND_Bank */
phungductung	0:8ede47d38d10	525
phungductung	0:8ede47d38d10	526	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
phungductung	0:8ede47d38d10	527	This parameter can be any value of @ref FMC_Wait_feature */
phungductung	0:8ede47d38d10	528
phungductung	0:8ede47d38d10	529	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
phungductung	0:8ede47d38d10	530	This parameter can be any value of @ref FMC_NAND_Data_Width */
phungductung	0:8ede47d38d10	531
phungductung	0:8ede47d38d10	532	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
phungductung	0:8ede47d38d10	533	This parameter can be any value of @ref FMC_ECC */
phungductung	0:8ede47d38d10	534
phungductung	0:8ede47d38d10	535	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
phungductung	0:8ede47d38d10	536	This parameter can be any value of @ref FMC_ECC_Page_Size */
phungductung	0:8ede47d38d10	537
phungductung	0:8ede47d38d10	538	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
phungductung	0:8ede47d38d10	539	delay between CLE low and RE low.
phungductung	0:8ede47d38d10	540	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
phungductung	0:8ede47d38d10	541
phungductung	0:8ede47d38d10	542	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
phungductung	0:8ede47d38d10	543	delay between ALE low and RE low.
phungductung	0:8ede47d38d10	544	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
phungductung	0:8ede47d38d10	545	}FMC_NAND_InitTypeDef;
phungductung	0:8ede47d38d10	546
phungductung	0:8ede47d38d10	547	/**
phungductung	0:8ede47d38d10	548	* @brief FMC NAND Timing parameters structure definition
phungductung	0:8ede47d38d10	549	*/
phungductung	0:8ede47d38d10	550	typedef struct
phungductung	0:8ede47d38d10	551	{
phungductung	0:8ede47d38d10	552	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
phungductung	0:8ede47d38d10	553	the command assertion for NAND-Flash read or write access
phungductung	0:8ede47d38d10	554	to common/Attribute or I/O memory space (depending on
phungductung	0:8ede47d38d10	555	the memory space timing to be configured).
phungductung	0:8ede47d38d10	556	This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
phungductung	0:8ede47d38d10	557
phungductung	0:8ede47d38d10	558	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
phungductung	0:8ede47d38d10	559	command for NAND-Flash read or write access to
phungductung	0:8ede47d38d10	560	common/Attribute or I/O memory space (depending on the
phungductung	0:8ede47d38d10	561	memory space timing to be configured).
phungductung	0:8ede47d38d10	562	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
phungductung	0:8ede47d38d10	563
phungductung	0:8ede47d38d10	564	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
phungductung	0:8ede47d38d10	565	(and data for write access) after the command de-assertion
phungductung	0:8ede47d38d10	566	for NAND-Flash read or write access to common/Attribute
phungductung	0:8ede47d38d10	567	or I/O memory space (depending on the memory space timing
phungductung	0:8ede47d38d10	568	to be configured).
phungductung	0:8ede47d38d10	569	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
phungductung	0:8ede47d38d10	570
phungductung	0:8ede47d38d10	571	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
phungductung	0:8ede47d38d10	572	data bus is kept in HiZ after the start of a NAND-Flash
phungductung	0:8ede47d38d10	573	write access to common/Attribute or I/O memory space (depending
phungductung	0:8ede47d38d10	574	on the memory space timing to be configured).
phungductung	0:8ede47d38d10	575	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
phungductung	0:8ede47d38d10	576	}FMC_NAND_PCC_TimingTypeDef;
phungductung	0:8ede47d38d10	577
phungductung	0:8ede47d38d10	578	/**
phungductung	0:8ede47d38d10	579	* @brief FMC SDRAM Configuration Structure definition
phungductung	0:8ede47d38d10	580	*/
phungductung	0:8ede47d38d10	581	typedef struct
phungductung	0:8ede47d38d10	582	{
phungductung	0:8ede47d38d10	583	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
phungductung	0:8ede47d38d10	584	This parameter can be a value of @ref FMC_SDRAM_Bank */
phungductung	0:8ede47d38d10	585
phungductung	0:8ede47d38d10	586	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
phungductung	0:8ede47d38d10	587	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
phungductung	0:8ede47d38d10	588
phungductung	0:8ede47d38d10	589	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
phungductung	0:8ede47d38d10	590	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
phungductung	0:8ede47d38d10	591
phungductung	0:8ede47d38d10	592	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
phungductung	0:8ede47d38d10	593	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
phungductung	0:8ede47d38d10	594
phungductung	0:8ede47d38d10	595	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
phungductung	0:8ede47d38d10	596	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
phungductung	0:8ede47d38d10	597
phungductung	0:8ede47d38d10	598	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
phungductung	0:8ede47d38d10	599	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
phungductung	0:8ede47d38d10	600
phungductung	0:8ede47d38d10	601	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
phungductung	0:8ede47d38d10	602	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
phungductung	0:8ede47d38d10	603
phungductung	0:8ede47d38d10	604	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
phungductung	0:8ede47d38d10	605	to disable the clock before changing frequency.
phungductung	0:8ede47d38d10	606	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
phungductung	0:8ede47d38d10	607
phungductung	0:8ede47d38d10	608	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
phungductung	0:8ede47d38d10	609	commands during the CAS latency and stores data in the Read FIFO.
phungductung	0:8ede47d38d10	610	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
phungductung	0:8ede47d38d10	611
phungductung	0:8ede47d38d10	612	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
phungductung	0:8ede47d38d10	613	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
phungductung	0:8ede47d38d10	614	}FMC_SDRAM_InitTypeDef;
phungductung	0:8ede47d38d10	615
phungductung	0:8ede47d38d10	616	/**
phungductung	0:8ede47d38d10	617	* @brief FMC SDRAM Timing parameters structure definition
phungductung	0:8ede47d38d10	618	*/
phungductung	0:8ede47d38d10	619	typedef struct
phungductung	0:8ede47d38d10	620	{
phungductung	0:8ede47d38d10	621	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
phungductung	0:8ede47d38d10	622	an active or Refresh command in number of memory clock cycles.
phungductung	0:8ede47d38d10	623	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	624
phungductung	0:8ede47d38d10	625	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
phungductung	0:8ede47d38d10	626	issuing the Activate command in number of memory clock cycles.
phungductung	0:8ede47d38d10	627	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	628
phungductung	0:8ede47d38d10	629	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
phungductung	0:8ede47d38d10	630	cycles.
phungductung	0:8ede47d38d10	631	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	632
phungductung	0:8ede47d38d10	633	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
phungductung	0:8ede47d38d10	634	and the delay between two consecutive Refresh commands in number of
phungductung	0:8ede47d38d10	635	memory clock cycles.
phungductung	0:8ede47d38d10	636	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	637
phungductung	0:8ede47d38d10	638	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
phungductung	0:8ede47d38d10	639	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	640
phungductung	0:8ede47d38d10	641	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
phungductung	0:8ede47d38d10	642	in number of memory clock cycles.
phungductung	0:8ede47d38d10	643	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	644
phungductung	0:8ede47d38d10	645	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
phungductung	0:8ede47d38d10	646	command in number of memory clock cycles.
phungductung	0:8ede47d38d10	647	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	648	}FMC_SDRAM_TimingTypeDef;
phungductung	0:8ede47d38d10	649
phungductung	0:8ede47d38d10	650	/**
phungductung	0:8ede47d38d10	651	* @brief SDRAM command parameters structure definition
phungductung	0:8ede47d38d10	652	*/
phungductung	0:8ede47d38d10	653	typedef struct
phungductung	0:8ede47d38d10	654	{
phungductung	0:8ede47d38d10	655	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
phungductung	0:8ede47d38d10	656	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
phungductung	0:8ede47d38d10	657
phungductung	0:8ede47d38d10	658	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
phungductung	0:8ede47d38d10	659	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
phungductung	0:8ede47d38d10	660
phungductung	0:8ede47d38d10	661	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
phungductung	0:8ede47d38d10	662	in auto refresh mode.
phungductung	0:8ede47d38d10	663	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
phungductung	0:8ede47d38d10	664	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
phungductung	0:8ede47d38d10	665	}FMC_SDRAM_CommandTypeDef;
phungductung	0:8ede47d38d10	666	/**
phungductung	0:8ede47d38d10	667	* @}
phungductung	0:8ede47d38d10	668	*/
phungductung	0:8ede47d38d10	669
phungductung	0:8ede47d38d10	670	/* Exported constants --------------------------------------------------------*/
phungductung	0:8ede47d38d10	671	/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
phungductung	0:8ede47d38d10	672	* @{
phungductung	0:8ede47d38d10	673	*/
phungductung	0:8ede47d38d10	674
phungductung	0:8ede47d38d10	675	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
phungductung	0:8ede47d38d10	676	* @{
phungductung	0:8ede47d38d10	677	*/
phungductung	0:8ede47d38d10	678
phungductung	0:8ede47d38d10	679	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
phungductung	0:8ede47d38d10	680	* @{
phungductung	0:8ede47d38d10	681	*/
phungductung	0:8ede47d38d10	682	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	683	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
phungductung	0:8ede47d38d10	684	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
phungductung	0:8ede47d38d10	685	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
phungductung	0:8ede47d38d10	686	/**
phungductung	0:8ede47d38d10	687	* @}
phungductung	0:8ede47d38d10	688	*/
phungductung	0:8ede47d38d10	689
phungductung	0:8ede47d38d10	690	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
phungductung	0:8ede47d38d10	691	* @{
phungductung	0:8ede47d38d10	692	*/
phungductung	0:8ede47d38d10	693	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	694	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
phungductung	0:8ede47d38d10	695	/**
phungductung	0:8ede47d38d10	696	* @}
phungductung	0:8ede47d38d10	697	*/
phungductung	0:8ede47d38d10	698
phungductung	0:8ede47d38d10	699	/** @defgroup FMC_Memory_Type FMC Memory Type
phungductung	0:8ede47d38d10	700	* @{
phungductung	0:8ede47d38d10	701	*/
phungductung	0:8ede47d38d10	702	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	703	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
phungductung	0:8ede47d38d10	704	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
phungductung	0:8ede47d38d10	705	/**
phungductung	0:8ede47d38d10	706	* @}
phungductung	0:8ede47d38d10	707	*/
phungductung	0:8ede47d38d10	708
phungductung	0:8ede47d38d10	709	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
phungductung	0:8ede47d38d10	710	* @{
phungductung	0:8ede47d38d10	711	*/
phungductung	0:8ede47d38d10	712	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	713	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
phungductung	0:8ede47d38d10	714	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
phungductung	0:8ede47d38d10	715	/**
phungductung	0:8ede47d38d10	716	* @}
phungductung	0:8ede47d38d10	717	*/
phungductung	0:8ede47d38d10	718
phungductung	0:8ede47d38d10	719	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
phungductung	0:8ede47d38d10	720	* @{
phungductung	0:8ede47d38d10	721	*/
phungductung	0:8ede47d38d10	722	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
phungductung	0:8ede47d38d10	723	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	724	/**
phungductung	0:8ede47d38d10	725	* @}
phungductung	0:8ede47d38d10	726	*/
phungductung	0:8ede47d38d10	727
phungductung	0:8ede47d38d10	728	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
phungductung	0:8ede47d38d10	729	* @{
phungductung	0:8ede47d38d10	730	*/
phungductung	0:8ede47d38d10	731	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	732	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
phungductung	0:8ede47d38d10	733	/**
phungductung	0:8ede47d38d10	734	* @}
phungductung	0:8ede47d38d10	735	*/
phungductung	0:8ede47d38d10	736
phungductung	0:8ede47d38d10	737	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
phungductung	0:8ede47d38d10	738	* @{
phungductung	0:8ede47d38d10	739	*/
phungductung	0:8ede47d38d10	740	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	741	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
phungductung	0:8ede47d38d10	742	/**
phungductung	0:8ede47d38d10	743	* @}
phungductung	0:8ede47d38d10	744	*/
phungductung	0:8ede47d38d10	745
phungductung	0:8ede47d38d10	746	/** @defgroup FMC_Wait_Timing FMC Wait Timing
phungductung	0:8ede47d38d10	747	* @{
phungductung	0:8ede47d38d10	748	*/
phungductung	0:8ede47d38d10	749	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	750	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
phungductung	0:8ede47d38d10	751	/**
phungductung	0:8ede47d38d10	752	* @}
phungductung	0:8ede47d38d10	753	*/
phungductung	0:8ede47d38d10	754
phungductung	0:8ede47d38d10	755	/** @defgroup FMC_Write_Operation FMC Write Operation
phungductung	0:8ede47d38d10	756	* @{
phungductung	0:8ede47d38d10	757	*/
phungductung	0:8ede47d38d10	758	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	759	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
phungductung	0:8ede47d38d10	760	/**
phungductung	0:8ede47d38d10	761	* @}
phungductung	0:8ede47d38d10	762	*/
phungductung	0:8ede47d38d10	763
phungductung	0:8ede47d38d10	764	/** @defgroup FMC_Wait_Signal FMC Wait Signal
phungductung	0:8ede47d38d10	765	* @{
phungductung	0:8ede47d38d10	766	*/
phungductung	0:8ede47d38d10	767	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	768	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
phungductung	0:8ede47d38d10	769	/**
phungductung	0:8ede47d38d10	770	* @}
phungductung	0:8ede47d38d10	771	*/
phungductung	0:8ede47d38d10	772
phungductung	0:8ede47d38d10	773	/** @defgroup FMC_Extended_Mode FMC Extended Mode
phungductung	0:8ede47d38d10	774	* @{
phungductung	0:8ede47d38d10	775	*/
phungductung	0:8ede47d38d10	776	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	777	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
phungductung	0:8ede47d38d10	778	/**
phungductung	0:8ede47d38d10	779	* @}
phungductung	0:8ede47d38d10	780	*/
phungductung	0:8ede47d38d10	781
phungductung	0:8ede47d38d10	782	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
phungductung	0:8ede47d38d10	783	* @{
phungductung	0:8ede47d38d10	784	*/
phungductung	0:8ede47d38d10	785	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	786	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
phungductung	0:8ede47d38d10	787	/**
phungductung	0:8ede47d38d10	788	* @}
phungductung	0:8ede47d38d10	789	*/
phungductung	0:8ede47d38d10	790
phungductung	0:8ede47d38d10	791	/** @defgroup FMC_Page_Size FMC Page Size
phungductung	0:8ede47d38d10	792	* @{
phungductung	0:8ede47d38d10	793	*/
phungductung	0:8ede47d38d10	794	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	795	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
phungductung	0:8ede47d38d10	796	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
phungductung	0:8ede47d38d10	797	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
phungductung	0:8ede47d38d10	798	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
phungductung	0:8ede47d38d10	799	/**
phungductung	0:8ede47d38d10	800	* @}
phungductung	0:8ede47d38d10	801	*/
phungductung	0:8ede47d38d10	802
phungductung	0:8ede47d38d10	803	/** @defgroup FMC_Write_Burst FMC Write Burst
phungductung	0:8ede47d38d10	804	* @{
phungductung	0:8ede47d38d10	805	*/
phungductung	0:8ede47d38d10	806	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	807	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
phungductung	0:8ede47d38d10	808	/**
phungductung	0:8ede47d38d10	809	* @}
phungductung	0:8ede47d38d10	810	*/
phungductung	0:8ede47d38d10	811
phungductung	0:8ede47d38d10	812	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
phungductung	0:8ede47d38d10	813	* @{
phungductung	0:8ede47d38d10	814	*/
phungductung	0:8ede47d38d10	815	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	816	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
phungductung	0:8ede47d38d10	817	/**
phungductung	0:8ede47d38d10	818	* @}
phungductung	0:8ede47d38d10	819	*/
phungductung	0:8ede47d38d10	820
phungductung	0:8ede47d38d10	821	/** @defgroup FMC_Write_FIFO FMC Write FIFO
phungductung	0:8ede47d38d10	822	* @{
phungductung	0:8ede47d38d10	823	*/
phungductung	0:8ede47d38d10	824	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
phungductung	0:8ede47d38d10	825	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	826	/**
phungductung	0:8ede47d38d10	827	* @}
phungductung	0:8ede47d38d10	828	*/
phungductung	0:8ede47d38d10	829
phungductung	0:8ede47d38d10	830	/** @defgroup FMC_Access_Mode FMC Access Mode
phungductung	0:8ede47d38d10	831	* @{
phungductung	0:8ede47d38d10	832	*/
phungductung	0:8ede47d38d10	833	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	834	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
phungductung	0:8ede47d38d10	835	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
phungductung	0:8ede47d38d10	836	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
phungductung	0:8ede47d38d10	837	/**
phungductung	0:8ede47d38d10	838	* @}
phungductung	0:8ede47d38d10	839	*/
phungductung	0:8ede47d38d10	840
phungductung	0:8ede47d38d10	841	/**
phungductung	0:8ede47d38d10	842	* @}
phungductung	0:8ede47d38d10	843	*/
phungductung	0:8ede47d38d10	844
phungductung	0:8ede47d38d10	845	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
phungductung	0:8ede47d38d10	846	* @{
phungductung	0:8ede47d38d10	847	*/
phungductung	0:8ede47d38d10	848	/** @defgroup FMC_NAND_Bank FMC NAND Bank
phungductung	0:8ede47d38d10	849	* @{
phungductung	0:8ede47d38d10	850	*/
phungductung	0:8ede47d38d10	851	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
phungductung	0:8ede47d38d10	852	/**
phungductung	0:8ede47d38d10	853	* @}
phungductung	0:8ede47d38d10	854	*/
phungductung	0:8ede47d38d10	855
phungductung	0:8ede47d38d10	856	/** @defgroup FMC_Wait_feature FMC Wait feature
phungductung	0:8ede47d38d10	857	* @{
phungductung	0:8ede47d38d10	858	*/
phungductung	0:8ede47d38d10	859	#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	860	#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
phungductung	0:8ede47d38d10	861	/**
phungductung	0:8ede47d38d10	862	* @}
phungductung	0:8ede47d38d10	863	*/
phungductung	0:8ede47d38d10	864
phungductung	0:8ede47d38d10	865	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
phungductung	0:8ede47d38d10	866	* @{
phungductung	0:8ede47d38d10	867	*/
phungductung	0:8ede47d38d10	868	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
phungductung	0:8ede47d38d10	869	/**
phungductung	0:8ede47d38d10	870	* @}
phungductung	0:8ede47d38d10	871	*/
phungductung	0:8ede47d38d10	872
phungductung	0:8ede47d38d10	873	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
phungductung	0:8ede47d38d10	874	* @{
phungductung	0:8ede47d38d10	875	*/
phungductung	0:8ede47d38d10	876	#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	877	#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
phungductung	0:8ede47d38d10	878	/**
phungductung	0:8ede47d38d10	879	* @}
phungductung	0:8ede47d38d10	880	*/
phungductung	0:8ede47d38d10	881
phungductung	0:8ede47d38d10	882	/** @defgroup FMC_ECC FMC ECC
phungductung	0:8ede47d38d10	883	* @{
phungductung	0:8ede47d38d10	884	*/
phungductung	0:8ede47d38d10	885	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	886	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
phungductung	0:8ede47d38d10	887	/**
phungductung	0:8ede47d38d10	888	* @}
phungductung	0:8ede47d38d10	889	*/
phungductung	0:8ede47d38d10	890
phungductung	0:8ede47d38d10	891	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
phungductung	0:8ede47d38d10	892	* @{
phungductung	0:8ede47d38d10	893	*/
phungductung	0:8ede47d38d10	894	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	895	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
phungductung	0:8ede47d38d10	896	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
phungductung	0:8ede47d38d10	897	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
phungductung	0:8ede47d38d10	898	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
phungductung	0:8ede47d38d10	899	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
phungductung	0:8ede47d38d10	900	/**
phungductung	0:8ede47d38d10	901	* @}
phungductung	0:8ede47d38d10	902	*/
phungductung	0:8ede47d38d10	903
phungductung	0:8ede47d38d10	904	/**
phungductung	0:8ede47d38d10	905	* @}
phungductung	0:8ede47d38d10	906	*/
phungductung	0:8ede47d38d10	907
phungductung	0:8ede47d38d10	908	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
phungductung	0:8ede47d38d10	909	* @{
phungductung	0:8ede47d38d10	910	*/
phungductung	0:8ede47d38d10	911	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
phungductung	0:8ede47d38d10	912	* @{
phungductung	0:8ede47d38d10	913	*/
phungductung	0:8ede47d38d10	914	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	915	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
phungductung	0:8ede47d38d10	916	/**
phungductung	0:8ede47d38d10	917	* @}
phungductung	0:8ede47d38d10	918	*/
phungductung	0:8ede47d38d10	919
phungductung	0:8ede47d38d10	920	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
phungductung	0:8ede47d38d10	921	* @{
phungductung	0:8ede47d38d10	922	*/
phungductung	0:8ede47d38d10	923	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	924	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
phungductung	0:8ede47d38d10	925	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
phungductung	0:8ede47d38d10	926	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
phungductung	0:8ede47d38d10	927	/**
phungductung	0:8ede47d38d10	928	* @}
phungductung	0:8ede47d38d10	929	*/
phungductung	0:8ede47d38d10	930
phungductung	0:8ede47d38d10	931	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
phungductung	0:8ede47d38d10	932	* @{
phungductung	0:8ede47d38d10	933	*/
phungductung	0:8ede47d38d10	934	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	935	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
phungductung	0:8ede47d38d10	936	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
phungductung	0:8ede47d38d10	937	/**
phungductung	0:8ede47d38d10	938	* @}
phungductung	0:8ede47d38d10	939	*/
phungductung	0:8ede47d38d10	940
phungductung	0:8ede47d38d10	941	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
phungductung	0:8ede47d38d10	942	* @{
phungductung	0:8ede47d38d10	943	*/
phungductung	0:8ede47d38d10	944	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	945	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
phungductung	0:8ede47d38d10	946	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
phungductung	0:8ede47d38d10	947	/**
phungductung	0:8ede47d38d10	948	* @}
phungductung	0:8ede47d38d10	949	*/
phungductung	0:8ede47d38d10	950
phungductung	0:8ede47d38d10	951	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
phungductung	0:8ede47d38d10	952	* @{
phungductung	0:8ede47d38d10	953	*/
phungductung	0:8ede47d38d10	954	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	955	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
phungductung	0:8ede47d38d10	956	/**
phungductung	0:8ede47d38d10	957	* @}
phungductung	0:8ede47d38d10	958	*/
phungductung	0:8ede47d38d10	959
phungductung	0:8ede47d38d10	960	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
phungductung	0:8ede47d38d10	961	* @{
phungductung	0:8ede47d38d10	962	*/
phungductung	0:8ede47d38d10	963	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
phungductung	0:8ede47d38d10	964	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
phungductung	0:8ede47d38d10	965	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
phungductung	0:8ede47d38d10	966	/**
phungductung	0:8ede47d38d10	967	* @}
phungductung	0:8ede47d38d10	968	*/
phungductung	0:8ede47d38d10	969
phungductung	0:8ede47d38d10	970	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
phungductung	0:8ede47d38d10	971	* @{
phungductung	0:8ede47d38d10	972	*/
phungductung	0:8ede47d38d10	973	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	974	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
phungductung	0:8ede47d38d10	975	/**
phungductung	0:8ede47d38d10	976	* @}
phungductung	0:8ede47d38d10	977	*/
phungductung	0:8ede47d38d10	978
phungductung	0:8ede47d38d10	979	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
phungductung	0:8ede47d38d10	980	* @{
phungductung	0:8ede47d38d10	981	*/
phungductung	0:8ede47d38d10	982	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	983	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
phungductung	0:8ede47d38d10	984	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
phungductung	0:8ede47d38d10	985	/**
phungductung	0:8ede47d38d10	986	* @}
phungductung	0:8ede47d38d10	987	*/
phungductung	0:8ede47d38d10	988
phungductung	0:8ede47d38d10	989	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
phungductung	0:8ede47d38d10	990	* @{
phungductung	0:8ede47d38d10	991	*/
phungductung	0:8ede47d38d10	992	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	993	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
phungductung	0:8ede47d38d10	994	/**
phungductung	0:8ede47d38d10	995	* @}
phungductung	0:8ede47d38d10	996	*/
phungductung	0:8ede47d38d10	997
phungductung	0:8ede47d38d10	998	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
phungductung	0:8ede47d38d10	999	* @{
phungductung	0:8ede47d38d10	1000	*/
phungductung	0:8ede47d38d10	1001	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	1002	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
phungductung	0:8ede47d38d10	1003	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
phungductung	0:8ede47d38d10	1004	/**
phungductung	0:8ede47d38d10	1005	* @}
phungductung	0:8ede47d38d10	1006	*/
phungductung	0:8ede47d38d10	1007
phungductung	0:8ede47d38d10	1008	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
phungductung	0:8ede47d38d10	1009	* @{
phungductung	0:8ede47d38d10	1010	*/
phungductung	0:8ede47d38d10	1011	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	1012	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
phungductung	0:8ede47d38d10	1013	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
phungductung	0:8ede47d38d10	1014	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
phungductung	0:8ede47d38d10	1015	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
phungductung	0:8ede47d38d10	1016	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
phungductung	0:8ede47d38d10	1017	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
phungductung	0:8ede47d38d10	1018	/**
phungductung	0:8ede47d38d10	1019	* @}
phungductung	0:8ede47d38d10	1020	*/
phungductung	0:8ede47d38d10	1021
phungductung	0:8ede47d38d10	1022	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
phungductung	0:8ede47d38d10	1023	* @{
phungductung	0:8ede47d38d10	1024	*/
phungductung	0:8ede47d38d10	1025	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
phungductung	0:8ede47d38d10	1026	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
phungductung	0:8ede47d38d10	1027	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
phungductung	0:8ede47d38d10	1028	/**
phungductung	0:8ede47d38d10	1029	* @}
phungductung	0:8ede47d38d10	1030	*/
phungductung	0:8ede47d38d10	1031
phungductung	0:8ede47d38d10	1032	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
phungductung	0:8ede47d38d10	1033	* @{
phungductung	0:8ede47d38d10	1034	*/
phungductung	0:8ede47d38d10	1035	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
phungductung	0:8ede47d38d10	1036	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
phungductung	0:8ede47d38d10	1037	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
phungductung	0:8ede47d38d10	1038	/**
phungductung	0:8ede47d38d10	1039	* @}
phungductung	0:8ede47d38d10	1040	*/
phungductung	0:8ede47d38d10	1041
phungductung	0:8ede47d38d10	1042	/**
phungductung	0:8ede47d38d10	1043	* @}
phungductung	0:8ede47d38d10	1044	*/
phungductung	0:8ede47d38d10	1045
phungductung	0:8ede47d38d10	1046	/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
phungductung	0:8ede47d38d10	1047	* @{
phungductung	0:8ede47d38d10	1048	*/
phungductung	0:8ede47d38d10	1049	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
phungductung	0:8ede47d38d10	1050	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
phungductung	0:8ede47d38d10	1051	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
phungductung	0:8ede47d38d10	1052	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
phungductung	0:8ede47d38d10	1053	/**
phungductung	0:8ede47d38d10	1054	* @}
phungductung	0:8ede47d38d10	1055	*/
phungductung	0:8ede47d38d10	1056
phungductung	0:8ede47d38d10	1057	/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
phungductung	0:8ede47d38d10	1058	* @{
phungductung	0:8ede47d38d10	1059	*/
phungductung	0:8ede47d38d10	1060	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
phungductung	0:8ede47d38d10	1061	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
phungductung	0:8ede47d38d10	1062	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
phungductung	0:8ede47d38d10	1063	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
phungductung	0:8ede47d38d10	1064	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
phungductung	0:8ede47d38d10	1065	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
phungductung	0:8ede47d38d10	1066	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
phungductung	0:8ede47d38d10	1067	/**
phungductung	0:8ede47d38d10	1068	* @}
phungductung	0:8ede47d38d10	1069	*/
phungductung	0:8ede47d38d10	1070	/**
phungductung	0:8ede47d38d10	1071	* @}
phungductung	0:8ede47d38d10	1072	*/
phungductung	0:8ede47d38d10	1073
phungductung	0:8ede47d38d10	1074	/**
phungductung	0:8ede47d38d10	1075	* @}
phungductung	0:8ede47d38d10	1076	*/
phungductung	0:8ede47d38d10	1077
phungductung	0:8ede47d38d10	1078	/* Private macro -------------------------------------------------------------*/
phungductung	0:8ede47d38d10	1079	/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
phungductung	0:8ede47d38d10	1080	* @{
phungductung	0:8ede47d38d10	1081	*/
phungductung	0:8ede47d38d10	1082
phungductung	0:8ede47d38d10	1083	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
phungductung	0:8ede47d38d10	1084	* @brief macros to handle NOR device enable/disable and read/write operations
phungductung	0:8ede47d38d10	1085	* @{
phungductung	0:8ede47d38d10	1086	*/
phungductung	0:8ede47d38d10	1087
phungductung	0:8ede47d38d10	1088	/**
phungductung	0:8ede47d38d10	1089	* @brief Enable the NORSRAM device access.
phungductung	0:8ede47d38d10	1090	* @param __INSTANCE__: FMC_NORSRAM Instance
phungductung	0:8ede47d38d10	1091	* @param __BANK__: FMC_NORSRAM Bank
phungductung	0:8ede47d38d10	1092	* @retval None
phungductung	0:8ede47d38d10	1093	*/
phungductung	0:8ede47d38d10	1094	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
phungductung	0:8ede47d38d10	1095
phungductung	0:8ede47d38d10	1096	/**
phungductung	0:8ede47d38d10	1097	* @brief Disable the NORSRAM device access.
phungductung	0:8ede47d38d10	1098	* @param __INSTANCE__: FMC_NORSRAM Instance
phungductung	0:8ede47d38d10	1099	* @param __BANK__: FMC_NORSRAM Bank
phungductung	0:8ede47d38d10	1100	* @retval None
phungductung	0:8ede47d38d10	1101	*/
phungductung	0:8ede47d38d10	1102	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
phungductung	0:8ede47d38d10	1103
phungductung	0:8ede47d38d10	1104	/**
phungductung	0:8ede47d38d10	1105	* @}
phungductung	0:8ede47d38d10	1106	*/
phungductung	0:8ede47d38d10	1107
phungductung	0:8ede47d38d10	1108	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
phungductung	0:8ede47d38d10	1109	* @brief macros to handle NAND device enable/disable
phungductung	0:8ede47d38d10	1110	* @{
phungductung	0:8ede47d38d10	1111	*/
phungductung	0:8ede47d38d10	1112
phungductung	0:8ede47d38d10	1113	/**
phungductung	0:8ede47d38d10	1114	* @brief Enable the NAND device access.
phungductung	0:8ede47d38d10	1115	* @param __INSTANCE__: FMC_NAND Instance
phungductung	0:8ede47d38d10	1116	* @retval None
phungductung	0:8ede47d38d10	1117	*/
phungductung	0:8ede47d38d10	1118	#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
phungductung	0:8ede47d38d10	1119
phungductung	0:8ede47d38d10	1120	/**
phungductung	0:8ede47d38d10	1121	* @brief Disable the NAND device access.
phungductung	0:8ede47d38d10	1122	* @param __INSTANCE__: FMC_NAND Instance
phungductung	0:8ede47d38d10	1123	* @retval None
phungductung	0:8ede47d38d10	1124	*/
phungductung	0:8ede47d38d10	1125	#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
phungductung	0:8ede47d38d10	1126
phungductung	0:8ede47d38d10	1127	/**
phungductung	0:8ede47d38d10	1128	* @}
phungductung	0:8ede47d38d10	1129	*/
phungductung	0:8ede47d38d10	1130
phungductung	0:8ede47d38d10	1131	/** @defgroup FMC_Interrupt FMC Interrupt
phungductung	0:8ede47d38d10	1132	* @brief macros to handle FMC interrupts
phungductung	0:8ede47d38d10	1133	* @{
phungductung	0:8ede47d38d10	1134	*/
phungductung	0:8ede47d38d10	1135
phungductung	0:8ede47d38d10	1136	/**
phungductung	0:8ede47d38d10	1137	* @brief Enable the NAND device interrupt.
phungductung	0:8ede47d38d10	1138	* @param __INSTANCE__: FMC_NAND instance
phungductung	0:8ede47d38d10	1139	* @param __INTERRUPT__: FMC_NAND interrupt
phungductung	0:8ede47d38d10	1140	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1141	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
phungductung	0:8ede47d38d10	1142	* @arg FMC_IT_LEVEL: Interrupt level.
phungductung	0:8ede47d38d10	1143	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
phungductung	0:8ede47d38d10	1144	* @retval None
phungductung	0:8ede47d38d10	1145	*/
phungductung	0:8ede47d38d10	1146	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
phungductung	0:8ede47d38d10	1147
phungductung	0:8ede47d38d10	1148	/**
phungductung	0:8ede47d38d10	1149	* @brief Disable the NAND device interrupt.
phungductung	0:8ede47d38d10	1150	* @param __INSTANCE__: FMC_NAND Instance
phungductung	0:8ede47d38d10	1151	* @param __INTERRUPT__: FMC_NAND interrupt
phungductung	0:8ede47d38d10	1152	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1153	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
phungductung	0:8ede47d38d10	1154	* @arg FMC_IT_LEVEL: Interrupt level.
phungductung	0:8ede47d38d10	1155	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
phungductung	0:8ede47d38d10	1156	* @retval None
phungductung	0:8ede47d38d10	1157	*/
phungductung	0:8ede47d38d10	1158	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
phungductung	0:8ede47d38d10	1159
phungductung	0:8ede47d38d10	1160	/**
phungductung	0:8ede47d38d10	1161	* @brief Get flag status of the NAND device.
phungductung	0:8ede47d38d10	1162	* @param __INSTANCE__: FMC_NAND Instance
phungductung	0:8ede47d38d10	1163	* @param __BANK__: FMC_NAND Bank
phungductung	0:8ede47d38d10	1164	* @param __FLAG__: FMC_NAND flag
phungductung	0:8ede47d38d10	1165	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1166	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
phungductung	0:8ede47d38d10	1167	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
phungductung	0:8ede47d38d10	1168	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
phungductung	0:8ede47d38d10	1169	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
phungductung	0:8ede47d38d10	1170	* @retval The state of FLAG (SET or RESET).
phungductung	0:8ede47d38d10	1171	*/
phungductung	0:8ede47d38d10	1172	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
phungductung	0:8ede47d38d10	1173
phungductung	0:8ede47d38d10	1174	/**
phungductung	0:8ede47d38d10	1175	* @brief Clear flag status of the NAND device.
phungductung	0:8ede47d38d10	1176	* @param __INSTANCE__: FMC_NAND Instance
phungductung	0:8ede47d38d10	1177	* @param __FLAG__: FMC_NAND flag
phungductung	0:8ede47d38d10	1178	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1179	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
phungductung	0:8ede47d38d10	1180	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
phungductung	0:8ede47d38d10	1181	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
phungductung	0:8ede47d38d10	1182	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
phungductung	0:8ede47d38d10	1183	* @retval None
phungductung	0:8ede47d38d10	1184	*/
phungductung	0:8ede47d38d10	1185	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
phungductung	0:8ede47d38d10	1186
phungductung	0:8ede47d38d10	1187	/**
phungductung	0:8ede47d38d10	1188	* @brief Enable the SDRAM device interrupt.
phungductung	0:8ede47d38d10	1189	* @param __INSTANCE__: FMC_SDRAM instance
phungductung	0:8ede47d38d10	1190	* @param __INTERRUPT__: FMC_SDRAM interrupt
phungductung	0:8ede47d38d10	1191	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1192	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
phungductung	0:8ede47d38d10	1193	* @retval None
phungductung	0:8ede47d38d10	1194	*/
phungductung	0:8ede47d38d10	1195	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
phungductung	0:8ede47d38d10	1196
phungductung	0:8ede47d38d10	1197	/**
phungductung	0:8ede47d38d10	1198	* @brief Disable the SDRAM device interrupt.
phungductung	0:8ede47d38d10	1199	* @param __INSTANCE__: FMC_SDRAM instance
phungductung	0:8ede47d38d10	1200	* @param __INTERRUPT__: FMC_SDRAM interrupt
phungductung	0:8ede47d38d10	1201	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1202	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
phungductung	0:8ede47d38d10	1203	* @retval None
phungductung	0:8ede47d38d10	1204	*/
phungductung	0:8ede47d38d10	1205	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
phungductung	0:8ede47d38d10	1206
phungductung	0:8ede47d38d10	1207	/**
phungductung	0:8ede47d38d10	1208	* @brief Get flag status of the SDRAM device.
phungductung	0:8ede47d38d10	1209	* @param __INSTANCE__: FMC_SDRAM instance
phungductung	0:8ede47d38d10	1210	* @param __FLAG__: FMC_SDRAM flag
phungductung	0:8ede47d38d10	1211	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1212	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
phungductung	0:8ede47d38d10	1213	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
phungductung	0:8ede47d38d10	1214	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
phungductung	0:8ede47d38d10	1215	* @retval The state of FLAG (SET or RESET).
phungductung	0:8ede47d38d10	1216	*/
phungductung	0:8ede47d38d10	1217	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
phungductung	0:8ede47d38d10	1218
phungductung	0:8ede47d38d10	1219	/**
phungductung	0:8ede47d38d10	1220	* @brief Clear flag status of the SDRAM device.
phungductung	0:8ede47d38d10	1221	* @param __INSTANCE__: FMC_SDRAM instance
phungductung	0:8ede47d38d10	1222	* @param __FLAG__: FMC_SDRAM flag
phungductung	0:8ede47d38d10	1223	* This parameter can be any combination of the following values:
phungductung	0:8ede47d38d10	1224	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
phungductung	0:8ede47d38d10	1225	* @retval None
phungductung	0:8ede47d38d10	1226	*/
phungductung	0:8ede47d38d10	1227	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
phungductung	0:8ede47d38d10	1228	/**
phungductung	0:8ede47d38d10	1229	* @}
phungductung	0:8ede47d38d10	1230	*/
phungductung	0:8ede47d38d10	1231
phungductung	0:8ede47d38d10	1232	/**
phungductung	0:8ede47d38d10	1233	* @}
phungductung	0:8ede47d38d10	1234	*/
phungductung	0:8ede47d38d10	1235
phungductung	0:8ede47d38d10	1236	/* Private functions ---------------------------------------------------------*/
phungductung	0:8ede47d38d10	1237	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
phungductung	0:8ede47d38d10	1238	* @{
phungductung	0:8ede47d38d10	1239	*/
phungductung	0:8ede47d38d10	1240
phungductung	0:8ede47d38d10	1241	/** @defgroup FMC_LL_NORSRAM NOR SRAM
phungductung	0:8ede47d38d10	1242	* @{
phungductung	0:8ede47d38d10	1243	*/
phungductung	0:8ede47d38d10	1244	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
phungductung	0:8ede47d38d10	1245	* @{
phungductung	0:8ede47d38d10	1246	*/
phungductung	0:8ede47d38d10	1247	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
phungductung	0:8ede47d38d10	1248	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
phungductung	0:8ede47d38d10	1249	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
phungductung	0:8ede47d38d10	1250	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
phungductung	0:8ede47d38d10	1251	/**
phungductung	0:8ede47d38d10	1252	* @}
phungductung	0:8ede47d38d10	1253	*/
phungductung	0:8ede47d38d10	1254
phungductung	0:8ede47d38d10	1255	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
phungductung	0:8ede47d38d10	1256	* @{
phungductung	0:8ede47d38d10	1257	*/
phungductung	0:8ede47d38d10	1258	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1259	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1260	/**
phungductung	0:8ede47d38d10	1261	* @}
phungductung	0:8ede47d38d10	1262	*/
phungductung	0:8ede47d38d10	1263	/**
phungductung	0:8ede47d38d10	1264	* @}
phungductung	0:8ede47d38d10	1265	*/
phungductung	0:8ede47d38d10	1266
phungductung	0:8ede47d38d10	1267	/** @defgroup FMC_LL_NAND NAND
phungductung	0:8ede47d38d10	1268	* @{
phungductung	0:8ede47d38d10	1269	*/
phungductung	0:8ede47d38d10	1270	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
phungductung	0:8ede47d38d10	1271	* @{
phungductung	0:8ede47d38d10	1272	*/
phungductung	0:8ede47d38d10	1273	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
phungductung	0:8ede47d38d10	1274	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
phungductung	0:8ede47d38d10	1275	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
phungductung	0:8ede47d38d10	1276	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1277	/**
phungductung	0:8ede47d38d10	1278	* @}
phungductung	0:8ede47d38d10	1279	*/
phungductung	0:8ede47d38d10	1280
phungductung	0:8ede47d38d10	1281	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
phungductung	0:8ede47d38d10	1282	* @{
phungductung	0:8ede47d38d10	1283	*/
phungductung	0:8ede47d38d10	1284	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1285	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1286	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
phungductung	0:8ede47d38d10	1287	/**
phungductung	0:8ede47d38d10	1288	* @}
phungductung	0:8ede47d38d10	1289	*/
phungductung	0:8ede47d38d10	1290
phungductung	0:8ede47d38d10	1291	/** @defgroup FMC_LL_SDRAM SDRAM
phungductung	0:8ede47d38d10	1292	* @{
phungductung	0:8ede47d38d10	1293	*/
phungductung	0:8ede47d38d10	1294	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
phungductung	0:8ede47d38d10	1295	* @{
phungductung	0:8ede47d38d10	1296	*/
phungductung	0:8ede47d38d10	1297	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
phungductung	0:8ede47d38d10	1298	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
phungductung	0:8ede47d38d10	1299	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1300
phungductung	0:8ede47d38d10	1301	/**
phungductung	0:8ede47d38d10	1302	* @}
phungductung	0:8ede47d38d10	1303	*/
phungductung	0:8ede47d38d10	1304
phungductung	0:8ede47d38d10	1305	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
phungductung	0:8ede47d38d10	1306	* @{
phungductung	0:8ede47d38d10	1307	*/
phungductung	0:8ede47d38d10	1308	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1309	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1310	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
phungductung	0:8ede47d38d10	1311	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
phungductung	0:8ede47d38d10	1312	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
phungductung	0:8ede47d38d10	1313	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
phungductung	0:8ede47d38d10	1314	/**
phungductung	0:8ede47d38d10	1315	* @}
phungductung	0:8ede47d38d10	1316	*/
phungductung	0:8ede47d38d10	1317
phungductung	0:8ede47d38d10	1318	/**
phungductung	0:8ede47d38d10	1319	* @}
phungductung	0:8ede47d38d10	1320	*/
phungductung	0:8ede47d38d10	1321
phungductung	0:8ede47d38d10	1322	/**
phungductung	0:8ede47d38d10	1323	* @}
phungductung	0:8ede47d38d10	1324	*/
phungductung	0:8ede47d38d10	1325
phungductung	0:8ede47d38d10	1326	/**
phungductung	0:8ede47d38d10	1327	* @}
phungductung	0:8ede47d38d10	1328	*/
phungductung	0:8ede47d38d10	1329
phungductung	0:8ede47d38d10	1330	/**
phungductung	0:8ede47d38d10	1331	* @}
phungductung	0:8ede47d38d10	1332	*/
phungductung	0:8ede47d38d10	1333	#ifdef __cplusplus
phungductung	0:8ede47d38d10	1334	}
phungductung	0:8ede47d38d10	1335	#endif
phungductung	0:8ede47d38d10	1336
phungductung	0:8ede47d38d10	1337	#endif /* __STM32F7xx_LL_FMC_H */
phungductung	0:8ede47d38d10	1338
phungductung	0:8ede47d38d10	1339	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	04 Jun 2019
Imports:	17
Forks:	0
Commits:	1
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SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h@0:8ede47d38d10, 2019-06-04 (annotated)

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