PHung Tung
SPKT
Dependencies: F746_GUI SD_PlayerSkeleton F746_SAI_IO
SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.c@0:8ede47d38d10, 2019-06-04 (annotated)
- Committer:
- phungductung
- Date:
- Tue Jun 04 21:37:21 2019 +0000
- Revision:
- 0:8ede47d38d10
SPKT
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| phungductung | 0:8ede47d38d10 | 1 | /** |
| phungductung | 0:8ede47d38d10 | 2 | ****************************************************************************** |
| phungductung | 0:8ede47d38d10 | 3 | * @file stm32f7xx_ll_fmc.c |
| phungductung | 0:8ede47d38d10 | 4 | * @author MCD Application Team |
| phungductung | 0:8ede47d38d10 | 5 | * @version V1.0.4 |
| phungductung | 0:8ede47d38d10 | 6 | * @date 09-December-2015 |
| phungductung | 0:8ede47d38d10 | 7 | * @brief FMC Low Layer HAL module driver. |
| phungductung | 0:8ede47d38d10 | 8 | * |
| phungductung | 0:8ede47d38d10 | 9 | * This file provides firmware functions to manage the following |
| phungductung | 0:8ede47d38d10 | 10 | * functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
| phungductung | 0:8ede47d38d10 | 11 | * + Initialization/de-initialization functions |
| phungductung | 0:8ede47d38d10 | 12 | * + Peripheral Control functions |
| phungductung | 0:8ede47d38d10 | 13 | * + Peripheral State functions |
| phungductung | 0:8ede47d38d10 | 14 | * |
| phungductung | 0:8ede47d38d10 | 15 | @verbatim |
| phungductung | 0:8ede47d38d10 | 16 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 17 | ##### FMC peripheral features ##### |
| phungductung | 0:8ede47d38d10 | 18 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 19 | [..] The Flexible memory controller (FMC) includes three memory controllers: |
| phungductung | 0:8ede47d38d10 | 20 | (+) The NOR/PSRAM memory controller |
| phungductung | 0:8ede47d38d10 | 21 | (+) The NAND memory controller |
| phungductung | 0:8ede47d38d10 | 22 | (+) The Synchronous DRAM (SDRAM) controller |
| phungductung | 0:8ede47d38d10 | 23 | |
| phungductung | 0:8ede47d38d10 | 24 | [..] The FMC functional block makes the interface with synchronous and asynchronous static |
| phungductung | 0:8ede47d38d10 | 25 | memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: |
| phungductung | 0:8ede47d38d10 | 26 | (+) to translate AHB transactions into the appropriate external device protocol |
| phungductung | 0:8ede47d38d10 | 27 | (+) to meet the access time requirements of the external memory devices |
| phungductung | 0:8ede47d38d10 | 28 | |
| phungductung | 0:8ede47d38d10 | 29 | [..] All external memories share the addresses, data and control signals with the controller. |
| phungductung | 0:8ede47d38d10 | 30 | Each external device is accessed by means of a unique Chip Select. The FMC performs |
| phungductung | 0:8ede47d38d10 | 31 | only one access at a time to an external device. |
| phungductung | 0:8ede47d38d10 | 32 | The main features of the FMC controller are the following: |
| phungductung | 0:8ede47d38d10 | 33 | (+) Interface with static-memory mapped devices including: |
| phungductung | 0:8ede47d38d10 | 34 | (++) Static random access memory (SRAM) |
| phungductung | 0:8ede47d38d10 | 35 | (++) Read-only memory (ROM) |
| phungductung | 0:8ede47d38d10 | 36 | (++) NOR Flash memory/OneNAND Flash memory |
| phungductung | 0:8ede47d38d10 | 37 | (++) PSRAM (4 memory banks) |
| phungductung | 0:8ede47d38d10 | 38 | (++) 16-bit PC Card compatible devices |
| phungductung | 0:8ede47d38d10 | 39 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
| phungductung | 0:8ede47d38d10 | 40 | data |
| phungductung | 0:8ede47d38d10 | 41 | (+) Interface with synchronous DRAM (SDRAM) memories |
| phungductung | 0:8ede47d38d10 | 42 | (+) Independent Chip Select control for each memory bank |
| phungductung | 0:8ede47d38d10 | 43 | (+) Independent configuration for each memory bank |
| phungductung | 0:8ede47d38d10 | 44 | |
| phungductung | 0:8ede47d38d10 | 45 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 46 | ****************************************************************************** |
| phungductung | 0:8ede47d38d10 | 47 | * @attention |
| phungductung | 0:8ede47d38d10 | 48 | * |
| phungductung | 0:8ede47d38d10 | 49 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| phungductung | 0:8ede47d38d10 | 50 | * |
| phungductung | 0:8ede47d38d10 | 51 | * Redistribution and use in source and binary forms, with or without modification, |
| phungductung | 0:8ede47d38d10 | 52 | * are permitted provided that the following conditions are met: |
| phungductung | 0:8ede47d38d10 | 53 | * 1. Redistributions of source code must retain the above copyright notice, |
| phungductung | 0:8ede47d38d10 | 54 | * this list of conditions and the following disclaimer. |
| phungductung | 0:8ede47d38d10 | 55 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| phungductung | 0:8ede47d38d10 | 56 | * this list of conditions and the following disclaimer in the documentation |
| phungductung | 0:8ede47d38d10 | 57 | * and/or other materials provided with the distribution. |
| phungductung | 0:8ede47d38d10 | 58 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| phungductung | 0:8ede47d38d10 | 59 | * may be used to endorse or promote products derived from this software |
| phungductung | 0:8ede47d38d10 | 60 | * without specific prior written permission. |
| phungductung | 0:8ede47d38d10 | 61 | * |
| phungductung | 0:8ede47d38d10 | 62 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| phungductung | 0:8ede47d38d10 | 63 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| phungductung | 0:8ede47d38d10 | 64 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| phungductung | 0:8ede47d38d10 | 65 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| phungductung | 0:8ede47d38d10 | 66 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| phungductung | 0:8ede47d38d10 | 67 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| phungductung | 0:8ede47d38d10 | 68 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| phungductung | 0:8ede47d38d10 | 69 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| phungductung | 0:8ede47d38d10 | 70 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| phungductung | 0:8ede47d38d10 | 71 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| phungductung | 0:8ede47d38d10 | 72 | * |
| phungductung | 0:8ede47d38d10 | 73 | ****************************************************************************** |
| phungductung | 0:8ede47d38d10 | 74 | */ |
| phungductung | 0:8ede47d38d10 | 75 | |
| phungductung | 0:8ede47d38d10 | 76 | /* Includes ------------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 77 | #include "stm32f7xx_hal.h" |
| phungductung | 0:8ede47d38d10 | 78 | |
| phungductung | 0:8ede47d38d10 | 79 | /** @addtogroup STM32F7xx_HAL_Driver |
| phungductung | 0:8ede47d38d10 | 80 | * @{ |
| phungductung | 0:8ede47d38d10 | 81 | */ |
| phungductung | 0:8ede47d38d10 | 82 | |
| phungductung | 0:8ede47d38d10 | 83 | /** @defgroup FMC_LL FMC Low Layer |
| phungductung | 0:8ede47d38d10 | 84 | * @brief FMC driver modules |
| phungductung | 0:8ede47d38d10 | 85 | * @{ |
| phungductung | 0:8ede47d38d10 | 86 | */ |
| phungductung | 0:8ede47d38d10 | 87 | |
| phungductung | 0:8ede47d38d10 | 88 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) |
| phungductung | 0:8ede47d38d10 | 89 | |
| phungductung | 0:8ede47d38d10 | 90 | /* Private typedef -----------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 91 | /* Private define ------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 92 | /* Private macro -------------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 93 | /* Private variables ---------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 94 | /* Private function prototypes -----------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 95 | /* Exported functions --------------------------------------------------------*/ |
| phungductung | 0:8ede47d38d10 | 96 | |
| phungductung | 0:8ede47d38d10 | 97 | /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions |
| phungductung | 0:8ede47d38d10 | 98 | * @{ |
| phungductung | 0:8ede47d38d10 | 99 | */ |
| phungductung | 0:8ede47d38d10 | 100 | |
| phungductung | 0:8ede47d38d10 | 101 | /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions |
| phungductung | 0:8ede47d38d10 | 102 | * @brief NORSRAM Controller functions |
| phungductung | 0:8ede47d38d10 | 103 | * |
| phungductung | 0:8ede47d38d10 | 104 | @verbatim |
| phungductung | 0:8ede47d38d10 | 105 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 106 | ##### How to use NORSRAM device driver ##### |
| phungductung | 0:8ede47d38d10 | 107 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 108 | |
| phungductung | 0:8ede47d38d10 | 109 | [..] |
| phungductung | 0:8ede47d38d10 | 110 | This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
| phungductung | 0:8ede47d38d10 | 111 | to run the NORSRAM external devices. |
| phungductung | 0:8ede47d38d10 | 112 | |
| phungductung | 0:8ede47d38d10 | 113 | (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
| phungductung | 0:8ede47d38d10 | 114 | (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
| phungductung | 0:8ede47d38d10 | 115 | (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
| phungductung | 0:8ede47d38d10 | 116 | (+) FMC NORSRAM bank extended timing configuration using the function |
| phungductung | 0:8ede47d38d10 | 117 | FMC_NORSRAM_Extended_Timing_Init() |
| phungductung | 0:8ede47d38d10 | 118 | (+) FMC NORSRAM bank enable/disable write operation using the functions |
| phungductung | 0:8ede47d38d10 | 119 | FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
| phungductung | 0:8ede47d38d10 | 120 | |
| phungductung | 0:8ede47d38d10 | 121 | |
| phungductung | 0:8ede47d38d10 | 122 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 123 | * @{ |
| phungductung | 0:8ede47d38d10 | 124 | */ |
| phungductung | 0:8ede47d38d10 | 125 | |
| phungductung | 0:8ede47d38d10 | 126 | /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
| phungductung | 0:8ede47d38d10 | 127 | * @brief Initialization and Configuration functions |
| phungductung | 0:8ede47d38d10 | 128 | * |
| phungductung | 0:8ede47d38d10 | 129 | @verbatim |
| phungductung | 0:8ede47d38d10 | 130 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 131 | ##### Initialization and de_initialization functions ##### |
| phungductung | 0:8ede47d38d10 | 132 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 133 | [..] |
| phungductung | 0:8ede47d38d10 | 134 | This section provides functions allowing to: |
| phungductung | 0:8ede47d38d10 | 135 | (+) Initialize and configure the FMC NORSRAM interface |
| phungductung | 0:8ede47d38d10 | 136 | (+) De-initialize the FMC NORSRAM interface |
| phungductung | 0:8ede47d38d10 | 137 | (+) Configure the FMC clock and associated GPIOs |
| phungductung | 0:8ede47d38d10 | 138 | |
| phungductung | 0:8ede47d38d10 | 139 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 140 | * @{ |
| phungductung | 0:8ede47d38d10 | 141 | */ |
| phungductung | 0:8ede47d38d10 | 142 | |
| phungductung | 0:8ede47d38d10 | 143 | /** |
| phungductung | 0:8ede47d38d10 | 144 | * @brief Initialize the FMC_NORSRAM device according to the specified |
| phungductung | 0:8ede47d38d10 | 145 | * control parameters in the FMC_NORSRAM_InitTypeDef |
| phungductung | 0:8ede47d38d10 | 146 | * @param Device: Pointer to NORSRAM device instance |
| phungductung | 0:8ede47d38d10 | 147 | * @param Init: Pointer to NORSRAM Initialization structure |
| phungductung | 0:8ede47d38d10 | 148 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 149 | */ |
| phungductung | 0:8ede47d38d10 | 150 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) |
| phungductung | 0:8ede47d38d10 | 151 | { |
| phungductung | 0:8ede47d38d10 | 152 | uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 153 | |
| phungductung | 0:8ede47d38d10 | 154 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 155 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 156 | assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
| phungductung | 0:8ede47d38d10 | 157 | assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
| phungductung | 0:8ede47d38d10 | 158 | assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
| phungductung | 0:8ede47d38d10 | 159 | assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| phungductung | 0:8ede47d38d10 | 160 | assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
| phungductung | 0:8ede47d38d10 | 161 | assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
| phungductung | 0:8ede47d38d10 | 162 | assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
| phungductung | 0:8ede47d38d10 | 163 | assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
| phungductung | 0:8ede47d38d10 | 164 | assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
| phungductung | 0:8ede47d38d10 | 165 | assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
| phungductung | 0:8ede47d38d10 | 166 | assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
| phungductung | 0:8ede47d38d10 | 167 | assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
| phungductung | 0:8ede47d38d10 | 168 | assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
| phungductung | 0:8ede47d38d10 | 169 | assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); |
| phungductung | 0:8ede47d38d10 | 170 | assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
| phungductung | 0:8ede47d38d10 | 171 | |
| phungductung | 0:8ede47d38d10 | 172 | /* Get the BTCR register value */ |
| phungductung | 0:8ede47d38d10 | 173 | tmpr = Device->BTCR[Init->NSBank]; |
| phungductung | 0:8ede47d38d10 | 174 | |
| phungductung | 0:8ede47d38d10 | 175 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, |
| phungductung | 0:8ede47d38d10 | 176 | WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ |
| phungductung | 0:8ede47d38d10 | 177 | tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
| phungductung | 0:8ede47d38d10 | 178 | FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
| phungductung | 0:8ede47d38d10 | 179 | FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \ |
| phungductung | 0:8ede47d38d10 | 180 | FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
| phungductung | 0:8ede47d38d10 | 181 | FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS)); |
| phungductung | 0:8ede47d38d10 | 182 | |
| phungductung | 0:8ede47d38d10 | 183 | /* Set NORSRAM device control parameters */ |
| phungductung | 0:8ede47d38d10 | 184 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
| phungductung | 0:8ede47d38d10 | 185 | Init->MemoryType |\ |
| phungductung | 0:8ede47d38d10 | 186 | Init->MemoryDataWidth |\ |
| phungductung | 0:8ede47d38d10 | 187 | Init->BurstAccessMode |\ |
| phungductung | 0:8ede47d38d10 | 188 | Init->WaitSignalPolarity |\ |
| phungductung | 0:8ede47d38d10 | 189 | Init->WaitSignalActive |\ |
| phungductung | 0:8ede47d38d10 | 190 | Init->WriteOperation |\ |
| phungductung | 0:8ede47d38d10 | 191 | Init->WaitSignal |\ |
| phungductung | 0:8ede47d38d10 | 192 | Init->ExtendedMode |\ |
| phungductung | 0:8ede47d38d10 | 193 | Init->AsynchronousWait |\ |
| phungductung | 0:8ede47d38d10 | 194 | Init->WriteBurst |\ |
| phungductung | 0:8ede47d38d10 | 195 | Init->ContinuousClock |\ |
| phungductung | 0:8ede47d38d10 | 196 | Init->PageSize |\ |
| phungductung | 0:8ede47d38d10 | 197 | Init->WriteFifo); |
| phungductung | 0:8ede47d38d10 | 198 | |
| phungductung | 0:8ede47d38d10 | 199 | if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
| phungductung | 0:8ede47d38d10 | 200 | { |
| phungductung | 0:8ede47d38d10 | 201 | tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; |
| phungductung | 0:8ede47d38d10 | 202 | } |
| phungductung | 0:8ede47d38d10 | 203 | |
| phungductung | 0:8ede47d38d10 | 204 | Device->BTCR[Init->NSBank] = tmpr; |
| phungductung | 0:8ede47d38d10 | 205 | |
| phungductung | 0:8ede47d38d10 | 206 | /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
| phungductung | 0:8ede47d38d10 | 207 | if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) |
| phungductung | 0:8ede47d38d10 | 208 | { |
| phungductung | 0:8ede47d38d10 | 209 | Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; |
| phungductung | 0:8ede47d38d10 | 210 | Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\ |
| phungductung | 0:8ede47d38d10 | 211 | Init->ContinuousClock); |
| phungductung | 0:8ede47d38d10 | 212 | } |
| phungductung | 0:8ede47d38d10 | 213 | if(Init->NSBank != FMC_NORSRAM_BANK1) |
| phungductung | 0:8ede47d38d10 | 214 | { |
| phungductung | 0:8ede47d38d10 | 215 | Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); |
| phungductung | 0:8ede47d38d10 | 216 | } |
| phungductung | 0:8ede47d38d10 | 217 | |
| phungductung | 0:8ede47d38d10 | 218 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 219 | } |
| phungductung | 0:8ede47d38d10 | 220 | |
| phungductung | 0:8ede47d38d10 | 221 | |
| phungductung | 0:8ede47d38d10 | 222 | /** |
| phungductung | 0:8ede47d38d10 | 223 | * @brief DeInitialize the FMC_NORSRAM peripheral |
| phungductung | 0:8ede47d38d10 | 224 | * @param Device: Pointer to NORSRAM device instance |
| phungductung | 0:8ede47d38d10 | 225 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
| phungductung | 0:8ede47d38d10 | 226 | * @param Bank: NORSRAM bank number |
| phungductung | 0:8ede47d38d10 | 227 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 228 | */ |
| phungductung | 0:8ede47d38d10 | 229 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 230 | { |
| phungductung | 0:8ede47d38d10 | 231 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 232 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 233 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
| phungductung | 0:8ede47d38d10 | 234 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 235 | |
| phungductung | 0:8ede47d38d10 | 236 | /* Disable the FMC_NORSRAM device */ |
| phungductung | 0:8ede47d38d10 | 237 | __FMC_NORSRAM_DISABLE(Device, Bank); |
| phungductung | 0:8ede47d38d10 | 238 | |
| phungductung | 0:8ede47d38d10 | 239 | /* De-initialize the FMC_NORSRAM device */ |
| phungductung | 0:8ede47d38d10 | 240 | /* FMC_NORSRAM_BANK1 */ |
| phungductung | 0:8ede47d38d10 | 241 | if(Bank == FMC_NORSRAM_BANK1) |
| phungductung | 0:8ede47d38d10 | 242 | { |
| phungductung | 0:8ede47d38d10 | 243 | Device->BTCR[Bank] = 0x000030DB; |
| phungductung | 0:8ede47d38d10 | 244 | } |
| phungductung | 0:8ede47d38d10 | 245 | /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
| phungductung | 0:8ede47d38d10 | 246 | else |
| phungductung | 0:8ede47d38d10 | 247 | { |
| phungductung | 0:8ede47d38d10 | 248 | Device->BTCR[Bank] = 0x000030D2; |
| phungductung | 0:8ede47d38d10 | 249 | } |
| phungductung | 0:8ede47d38d10 | 250 | |
| phungductung | 0:8ede47d38d10 | 251 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
| phungductung | 0:8ede47d38d10 | 252 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
| phungductung | 0:8ede47d38d10 | 253 | |
| phungductung | 0:8ede47d38d10 | 254 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 255 | } |
| phungductung | 0:8ede47d38d10 | 256 | |
| phungductung | 0:8ede47d38d10 | 257 | |
| phungductung | 0:8ede47d38d10 | 258 | /** |
| phungductung | 0:8ede47d38d10 | 259 | * @brief Initialize the FMC_NORSRAM Timing according to the specified |
| phungductung | 0:8ede47d38d10 | 260 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| phungductung | 0:8ede47d38d10 | 261 | * @param Device: Pointer to NORSRAM device instance |
| phungductung | 0:8ede47d38d10 | 262 | * @param Timing: Pointer to NORSRAM Timing structure |
| phungductung | 0:8ede47d38d10 | 263 | * @param Bank: NORSRAM bank number |
| phungductung | 0:8ede47d38d10 | 264 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 265 | */ |
| phungductung | 0:8ede47d38d10 | 266 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 267 | { |
| phungductung | 0:8ede47d38d10 | 268 | uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 269 | |
| phungductung | 0:8ede47d38d10 | 270 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 271 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 272 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| phungductung | 0:8ede47d38d10 | 273 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| phungductung | 0:8ede47d38d10 | 274 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| phungductung | 0:8ede47d38d10 | 275 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| phungductung | 0:8ede47d38d10 | 276 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
| phungductung | 0:8ede47d38d10 | 277 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
| phungductung | 0:8ede47d38d10 | 278 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| phungductung | 0:8ede47d38d10 | 279 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 280 | |
| phungductung | 0:8ede47d38d10 | 281 | /* Get the BTCR register value */ |
| phungductung | 0:8ede47d38d10 | 282 | tmpr = Device->BTCR[Bank + 1]; |
| phungductung | 0:8ede47d38d10 | 283 | |
| phungductung | 0:8ede47d38d10 | 284 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
| phungductung | 0:8ede47d38d10 | 285 | tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ |
| phungductung | 0:8ede47d38d10 | 286 | FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ |
| phungductung | 0:8ede47d38d10 | 287 | FMC_BTR1_ACCMOD)); |
| phungductung | 0:8ede47d38d10 | 288 | |
| phungductung | 0:8ede47d38d10 | 289 | /* Set FMC_NORSRAM device timing parameters */ |
| phungductung | 0:8ede47d38d10 | 290 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
| phungductung | 0:8ede47d38d10 | 291 | ((Timing->AddressHoldTime) << 4) |\ |
| phungductung | 0:8ede47d38d10 | 292 | ((Timing->DataSetupTime) << 8) |\ |
| phungductung | 0:8ede47d38d10 | 293 | ((Timing->BusTurnAroundDuration) << 16) |\ |
| phungductung | 0:8ede47d38d10 | 294 | (((Timing->CLKDivision)-1) << 20) |\ |
| phungductung | 0:8ede47d38d10 | 295 | (((Timing->DataLatency)-2) << 24) |\ |
| phungductung | 0:8ede47d38d10 | 296 | (Timing->AccessMode) |
| phungductung | 0:8ede47d38d10 | 297 | ); |
| phungductung | 0:8ede47d38d10 | 298 | |
| phungductung | 0:8ede47d38d10 | 299 | Device->BTCR[Bank + 1] = tmpr; |
| phungductung | 0:8ede47d38d10 | 300 | |
| phungductung | 0:8ede47d38d10 | 301 | /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
| phungductung | 0:8ede47d38d10 | 302 | if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
| phungductung | 0:8ede47d38d10 | 303 | { |
| phungductung | 0:8ede47d38d10 | 304 | tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); |
| phungductung | 0:8ede47d38d10 | 305 | tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); |
| phungductung | 0:8ede47d38d10 | 306 | Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; |
| phungductung | 0:8ede47d38d10 | 307 | } |
| phungductung | 0:8ede47d38d10 | 308 | |
| phungductung | 0:8ede47d38d10 | 309 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 310 | } |
| phungductung | 0:8ede47d38d10 | 311 | |
| phungductung | 0:8ede47d38d10 | 312 | /** |
| phungductung | 0:8ede47d38d10 | 313 | * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
| phungductung | 0:8ede47d38d10 | 314 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| phungductung | 0:8ede47d38d10 | 315 | * @param Device: Pointer to NORSRAM device instance |
| phungductung | 0:8ede47d38d10 | 316 | * @param Timing: Pointer to NORSRAM Timing structure |
| phungductung | 0:8ede47d38d10 | 317 | * @param Bank: NORSRAM bank number |
| phungductung | 0:8ede47d38d10 | 318 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 319 | */ |
| phungductung | 0:8ede47d38d10 | 320 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
| phungductung | 0:8ede47d38d10 | 321 | { |
| phungductung | 0:8ede47d38d10 | 322 | uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 323 | |
| phungductung | 0:8ede47d38d10 | 324 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 325 | assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
| phungductung | 0:8ede47d38d10 | 326 | |
| phungductung | 0:8ede47d38d10 | 327 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| phungductung | 0:8ede47d38d10 | 328 | if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
| phungductung | 0:8ede47d38d10 | 329 | { |
| phungductung | 0:8ede47d38d10 | 330 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 331 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 332 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| phungductung | 0:8ede47d38d10 | 333 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| phungductung | 0:8ede47d38d10 | 334 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| phungductung | 0:8ede47d38d10 | 335 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| phungductung | 0:8ede47d38d10 | 336 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
| phungductung | 0:8ede47d38d10 | 337 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
| phungductung | 0:8ede47d38d10 | 338 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| phungductung | 0:8ede47d38d10 | 339 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 340 | |
| phungductung | 0:8ede47d38d10 | 341 | /* Get the BWTR register value */ |
| phungductung | 0:8ede47d38d10 | 342 | tmpr = Device->BWTR[Bank]; |
| phungductung | 0:8ede47d38d10 | 343 | |
| phungductung | 0:8ede47d38d10 | 344 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
| phungductung | 0:8ede47d38d10 | 345 | tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ |
| phungductung | 0:8ede47d38d10 | 346 | FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); |
| phungductung | 0:8ede47d38d10 | 347 | |
| phungductung | 0:8ede47d38d10 | 348 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
| phungductung | 0:8ede47d38d10 | 349 | ((Timing->AddressHoldTime) << 4) |\ |
| phungductung | 0:8ede47d38d10 | 350 | ((Timing->DataSetupTime) << 8) |\ |
| phungductung | 0:8ede47d38d10 | 351 | ((Timing->BusTurnAroundDuration) << 16) |\ |
| phungductung | 0:8ede47d38d10 | 352 | (Timing->AccessMode)); |
| phungductung | 0:8ede47d38d10 | 353 | |
| phungductung | 0:8ede47d38d10 | 354 | Device->BWTR[Bank] = tmpr; |
| phungductung | 0:8ede47d38d10 | 355 | } |
| phungductung | 0:8ede47d38d10 | 356 | else |
| phungductung | 0:8ede47d38d10 | 357 | { |
| phungductung | 0:8ede47d38d10 | 358 | Device->BWTR[Bank] = 0x0FFFFFFF; |
| phungductung | 0:8ede47d38d10 | 359 | } |
| phungductung | 0:8ede47d38d10 | 360 | |
| phungductung | 0:8ede47d38d10 | 361 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 362 | } |
| phungductung | 0:8ede47d38d10 | 363 | /** |
| phungductung | 0:8ede47d38d10 | 364 | * @} |
| phungductung | 0:8ede47d38d10 | 365 | */ |
| phungductung | 0:8ede47d38d10 | 366 | |
| phungductung | 0:8ede47d38d10 | 367 | /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 |
| phungductung | 0:8ede47d38d10 | 368 | * @brief management functions |
| phungductung | 0:8ede47d38d10 | 369 | * |
| phungductung | 0:8ede47d38d10 | 370 | @verbatim |
| phungductung | 0:8ede47d38d10 | 371 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 372 | ##### FMC_NORSRAM Control functions ##### |
| phungductung | 0:8ede47d38d10 | 373 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 374 | [..] |
| phungductung | 0:8ede47d38d10 | 375 | This subsection provides a set of functions allowing to control dynamically |
| phungductung | 0:8ede47d38d10 | 376 | the FMC NORSRAM interface. |
| phungductung | 0:8ede47d38d10 | 377 | |
| phungductung | 0:8ede47d38d10 | 378 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 379 | * @{ |
| phungductung | 0:8ede47d38d10 | 380 | */ |
| phungductung | 0:8ede47d38d10 | 381 | |
| phungductung | 0:8ede47d38d10 | 382 | /** |
| phungductung | 0:8ede47d38d10 | 383 | * @brief Enables dynamically FMC_NORSRAM write operation. |
| phungductung | 0:8ede47d38d10 | 384 | * @param Device: Pointer to NORSRAM device instance |
| phungductung | 0:8ede47d38d10 | 385 | * @param Bank: NORSRAM bank number |
| phungductung | 0:8ede47d38d10 | 386 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 387 | */ |
| phungductung | 0:8ede47d38d10 | 388 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 389 | { |
| phungductung | 0:8ede47d38d10 | 390 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 391 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 392 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 393 | |
| phungductung | 0:8ede47d38d10 | 394 | /* Enable write operation */ |
| phungductung | 0:8ede47d38d10 | 395 | Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; |
| phungductung | 0:8ede47d38d10 | 396 | |
| phungductung | 0:8ede47d38d10 | 397 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 398 | } |
| phungductung | 0:8ede47d38d10 | 399 | |
| phungductung | 0:8ede47d38d10 | 400 | /** |
| phungductung | 0:8ede47d38d10 | 401 | * @brief Disables dynamically FMC_NORSRAM write operation. |
| phungductung | 0:8ede47d38d10 | 402 | * @param Device: Pointer to NORSRAM device instance |
| phungductung | 0:8ede47d38d10 | 403 | * @param Bank: NORSRAM bank number |
| phungductung | 0:8ede47d38d10 | 404 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 405 | */ |
| phungductung | 0:8ede47d38d10 | 406 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 407 | { |
| phungductung | 0:8ede47d38d10 | 408 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 409 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 410 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 411 | |
| phungductung | 0:8ede47d38d10 | 412 | /* Disable write operation */ |
| phungductung | 0:8ede47d38d10 | 413 | Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; |
| phungductung | 0:8ede47d38d10 | 414 | |
| phungductung | 0:8ede47d38d10 | 415 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 416 | } |
| phungductung | 0:8ede47d38d10 | 417 | |
| phungductung | 0:8ede47d38d10 | 418 | /** |
| phungductung | 0:8ede47d38d10 | 419 | * @} |
| phungductung | 0:8ede47d38d10 | 420 | */ |
| phungductung | 0:8ede47d38d10 | 421 | |
| phungductung | 0:8ede47d38d10 | 422 | /** |
| phungductung | 0:8ede47d38d10 | 423 | * @} |
| phungductung | 0:8ede47d38d10 | 424 | */ |
| phungductung | 0:8ede47d38d10 | 425 | |
| phungductung | 0:8ede47d38d10 | 426 | /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions |
| phungductung | 0:8ede47d38d10 | 427 | * @brief NAND Controller functions |
| phungductung | 0:8ede47d38d10 | 428 | * |
| phungductung | 0:8ede47d38d10 | 429 | @verbatim |
| phungductung | 0:8ede47d38d10 | 430 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 431 | ##### How to use NAND device driver ##### |
| phungductung | 0:8ede47d38d10 | 432 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 433 | [..] |
| phungductung | 0:8ede47d38d10 | 434 | This driver contains a set of APIs to interface with the FMC NAND banks in order |
| phungductung | 0:8ede47d38d10 | 435 | to run the NAND external devices. |
| phungductung | 0:8ede47d38d10 | 436 | |
| phungductung | 0:8ede47d38d10 | 437 | (+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
| phungductung | 0:8ede47d38d10 | 438 | (+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
| phungductung | 0:8ede47d38d10 | 439 | (+) FMC NAND bank common space timing configuration using the function |
| phungductung | 0:8ede47d38d10 | 440 | FMC_NAND_CommonSpace_Timing_Init() |
| phungductung | 0:8ede47d38d10 | 441 | (+) FMC NAND bank attribute space timing configuration using the function |
| phungductung | 0:8ede47d38d10 | 442 | FMC_NAND_AttributeSpace_Timing_Init() |
| phungductung | 0:8ede47d38d10 | 443 | (+) FMC NAND bank enable/disable ECC correction feature using the functions |
| phungductung | 0:8ede47d38d10 | 444 | FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
| phungductung | 0:8ede47d38d10 | 445 | (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
| phungductung | 0:8ede47d38d10 | 446 | |
| phungductung | 0:8ede47d38d10 | 447 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 448 | * @{ |
| phungductung | 0:8ede47d38d10 | 449 | */ |
| phungductung | 0:8ede47d38d10 | 450 | |
| phungductung | 0:8ede47d38d10 | 451 | /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
| phungductung | 0:8ede47d38d10 | 452 | * @brief Initialization and Configuration functions |
| phungductung | 0:8ede47d38d10 | 453 | * |
| phungductung | 0:8ede47d38d10 | 454 | @verbatim |
| phungductung | 0:8ede47d38d10 | 455 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 456 | ##### Initialization and de_initialization functions ##### |
| phungductung | 0:8ede47d38d10 | 457 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 458 | [..] |
| phungductung | 0:8ede47d38d10 | 459 | This section provides functions allowing to: |
| phungductung | 0:8ede47d38d10 | 460 | (+) Initialize and configure the FMC NAND interface |
| phungductung | 0:8ede47d38d10 | 461 | (+) De-initialize the FMC NAND interface |
| phungductung | 0:8ede47d38d10 | 462 | (+) Configure the FMC clock and associated GPIOs |
| phungductung | 0:8ede47d38d10 | 463 | |
| phungductung | 0:8ede47d38d10 | 464 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 465 | * @{ |
| phungductung | 0:8ede47d38d10 | 466 | */ |
| phungductung | 0:8ede47d38d10 | 467 | |
| phungductung | 0:8ede47d38d10 | 468 | /** |
| phungductung | 0:8ede47d38d10 | 469 | * @brief Initializes the FMC_NAND device according to the specified |
| phungductung | 0:8ede47d38d10 | 470 | * control parameters in the FMC_NAND_HandleTypeDef |
| phungductung | 0:8ede47d38d10 | 471 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 472 | * @param Init: Pointer to NAND Initialization structure |
| phungductung | 0:8ede47d38d10 | 473 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 474 | */ |
| phungductung | 0:8ede47d38d10 | 475 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
| phungductung | 0:8ede47d38d10 | 476 | { |
| phungductung | 0:8ede47d38d10 | 477 | uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 478 | |
| phungductung | 0:8ede47d38d10 | 479 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 480 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 481 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
| phungductung | 0:8ede47d38d10 | 482 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
| phungductung | 0:8ede47d38d10 | 483 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| phungductung | 0:8ede47d38d10 | 484 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
| phungductung | 0:8ede47d38d10 | 485 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
| phungductung | 0:8ede47d38d10 | 486 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
| phungductung | 0:8ede47d38d10 | 487 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
| phungductung | 0:8ede47d38d10 | 488 | |
| phungductung | 0:8ede47d38d10 | 489 | /* Get the NAND bank 3 register value */ |
| phungductung | 0:8ede47d38d10 | 490 | tmpr = Device->PCR; |
| phungductung | 0:8ede47d38d10 | 491 | |
| phungductung | 0:8ede47d38d10 | 492 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
| phungductung | 0:8ede47d38d10 | 493 | tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ |
| phungductung | 0:8ede47d38d10 | 494 | FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ |
| phungductung | 0:8ede47d38d10 | 495 | FMC_PCR_TAR | FMC_PCR_ECCPS)); |
| phungductung | 0:8ede47d38d10 | 496 | /* Set NAND device control parameters */ |
| phungductung | 0:8ede47d38d10 | 497 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
| phungductung | 0:8ede47d38d10 | 498 | FMC_PCR_MEMORY_TYPE_NAND |\ |
| phungductung | 0:8ede47d38d10 | 499 | Init->MemoryDataWidth |\ |
| phungductung | 0:8ede47d38d10 | 500 | Init->EccComputation |\ |
| phungductung | 0:8ede47d38d10 | 501 | Init->ECCPageSize |\ |
| phungductung | 0:8ede47d38d10 | 502 | ((Init->TCLRSetupTime) << 9) |\ |
| phungductung | 0:8ede47d38d10 | 503 | ((Init->TARSetupTime) << 13)); |
| phungductung | 0:8ede47d38d10 | 504 | |
| phungductung | 0:8ede47d38d10 | 505 | /* NAND bank 3 registers configuration */ |
| phungductung | 0:8ede47d38d10 | 506 | Device->PCR = tmpr; |
| phungductung | 0:8ede47d38d10 | 507 | |
| phungductung | 0:8ede47d38d10 | 508 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 509 | |
| phungductung | 0:8ede47d38d10 | 510 | } |
| phungductung | 0:8ede47d38d10 | 511 | |
| phungductung | 0:8ede47d38d10 | 512 | /** |
| phungductung | 0:8ede47d38d10 | 513 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
| phungductung | 0:8ede47d38d10 | 514 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| phungductung | 0:8ede47d38d10 | 515 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 516 | * @param Timing: Pointer to NAND timing structure |
| phungductung | 0:8ede47d38d10 | 517 | * @param Bank: NAND bank number |
| phungductung | 0:8ede47d38d10 | 518 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 519 | */ |
| phungductung | 0:8ede47d38d10 | 520 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 521 | { |
| phungductung | 0:8ede47d38d10 | 522 | uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 523 | |
| phungductung | 0:8ede47d38d10 | 524 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 525 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 526 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| phungductung | 0:8ede47d38d10 | 527 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| phungductung | 0:8ede47d38d10 | 528 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| phungductung | 0:8ede47d38d10 | 529 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| phungductung | 0:8ede47d38d10 | 530 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 531 | |
| phungductung | 0:8ede47d38d10 | 532 | /* Get the NAND bank 3 register value */ |
| phungductung | 0:8ede47d38d10 | 533 | tmpr = Device->PMEM; |
| phungductung | 0:8ede47d38d10 | 534 | |
| phungductung | 0:8ede47d38d10 | 535 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
| phungductung | 0:8ede47d38d10 | 536 | tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \ |
| phungductung | 0:8ede47d38d10 | 537 | FMC_PMEM_MEMHIZ3)); |
| phungductung | 0:8ede47d38d10 | 538 | /* Set FMC_NAND device timing parameters */ |
| phungductung | 0:8ede47d38d10 | 539 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| phungductung | 0:8ede47d38d10 | 540 | ((Timing->WaitSetupTime) << 8) |\ |
| phungductung | 0:8ede47d38d10 | 541 | ((Timing->HoldSetupTime) << 16) |\ |
| phungductung | 0:8ede47d38d10 | 542 | ((Timing->HiZSetupTime) << 24) |
| phungductung | 0:8ede47d38d10 | 543 | ); |
| phungductung | 0:8ede47d38d10 | 544 | |
| phungductung | 0:8ede47d38d10 | 545 | /* NAND bank 3 registers configuration */ |
| phungductung | 0:8ede47d38d10 | 546 | Device->PMEM = tmpr; |
| phungductung | 0:8ede47d38d10 | 547 | |
| phungductung | 0:8ede47d38d10 | 548 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 549 | } |
| phungductung | 0:8ede47d38d10 | 550 | |
| phungductung | 0:8ede47d38d10 | 551 | /** |
| phungductung | 0:8ede47d38d10 | 552 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
| phungductung | 0:8ede47d38d10 | 553 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| phungductung | 0:8ede47d38d10 | 554 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 555 | * @param Timing: Pointer to NAND timing structure |
| phungductung | 0:8ede47d38d10 | 556 | * @param Bank: NAND bank number |
| phungductung | 0:8ede47d38d10 | 557 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 558 | */ |
| phungductung | 0:8ede47d38d10 | 559 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 560 | { |
| phungductung | 0:8ede47d38d10 | 561 | uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 562 | |
| phungductung | 0:8ede47d38d10 | 563 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 564 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 565 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| phungductung | 0:8ede47d38d10 | 566 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| phungductung | 0:8ede47d38d10 | 567 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| phungductung | 0:8ede47d38d10 | 568 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| phungductung | 0:8ede47d38d10 | 569 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 570 | |
| phungductung | 0:8ede47d38d10 | 571 | /* Get the NAND bank 3 register value */ |
| phungductung | 0:8ede47d38d10 | 572 | tmpr = Device->PATT; |
| phungductung | 0:8ede47d38d10 | 573 | |
| phungductung | 0:8ede47d38d10 | 574 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
| phungductung | 0:8ede47d38d10 | 575 | tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \ |
| phungductung | 0:8ede47d38d10 | 576 | FMC_PATT_ATTHIZ3)); |
| phungductung | 0:8ede47d38d10 | 577 | /* Set FMC_NAND device timing parameters */ |
| phungductung | 0:8ede47d38d10 | 578 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| phungductung | 0:8ede47d38d10 | 579 | ((Timing->WaitSetupTime) << 8) |\ |
| phungductung | 0:8ede47d38d10 | 580 | ((Timing->HoldSetupTime) << 16) |\ |
| phungductung | 0:8ede47d38d10 | 581 | ((Timing->HiZSetupTime) << 24)); |
| phungductung | 0:8ede47d38d10 | 582 | |
| phungductung | 0:8ede47d38d10 | 583 | /* NAND bank 3 registers configuration */ |
| phungductung | 0:8ede47d38d10 | 584 | Device->PATT = tmpr; |
| phungductung | 0:8ede47d38d10 | 585 | |
| phungductung | 0:8ede47d38d10 | 586 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 587 | } |
| phungductung | 0:8ede47d38d10 | 588 | |
| phungductung | 0:8ede47d38d10 | 589 | /** |
| phungductung | 0:8ede47d38d10 | 590 | * @brief DeInitializes the FMC_NAND device |
| phungductung | 0:8ede47d38d10 | 591 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 592 | * @param Bank: NAND bank number |
| phungductung | 0:8ede47d38d10 | 593 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 594 | */ |
| phungductung | 0:8ede47d38d10 | 595 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 596 | { |
| phungductung | 0:8ede47d38d10 | 597 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 598 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 599 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 600 | |
| phungductung | 0:8ede47d38d10 | 601 | /* Disable the NAND Bank */ |
| phungductung | 0:8ede47d38d10 | 602 | __FMC_NAND_DISABLE(Device); |
| phungductung | 0:8ede47d38d10 | 603 | |
| phungductung | 0:8ede47d38d10 | 604 | /* Set the FMC_NAND_BANK3 registers to their reset values */ |
| phungductung | 0:8ede47d38d10 | 605 | Device->PCR = 0x00000018; |
| phungductung | 0:8ede47d38d10 | 606 | Device->SR = 0x00000040; |
| phungductung | 0:8ede47d38d10 | 607 | Device->PMEM = 0xFCFCFCFC; |
| phungductung | 0:8ede47d38d10 | 608 | Device->PATT = 0xFCFCFCFC; |
| phungductung | 0:8ede47d38d10 | 609 | |
| phungductung | 0:8ede47d38d10 | 610 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 611 | } |
| phungductung | 0:8ede47d38d10 | 612 | |
| phungductung | 0:8ede47d38d10 | 613 | /** |
| phungductung | 0:8ede47d38d10 | 614 | * @} |
| phungductung | 0:8ede47d38d10 | 615 | */ |
| phungductung | 0:8ede47d38d10 | 616 | |
| phungductung | 0:8ede47d38d10 | 617 | /** @defgroup HAL_FMC_NAND_Group3 Control functions |
| phungductung | 0:8ede47d38d10 | 618 | * @brief management functions |
| phungductung | 0:8ede47d38d10 | 619 | * |
| phungductung | 0:8ede47d38d10 | 620 | @verbatim |
| phungductung | 0:8ede47d38d10 | 621 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 622 | ##### FMC_NAND Control functions ##### |
| phungductung | 0:8ede47d38d10 | 623 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 624 | [..] |
| phungductung | 0:8ede47d38d10 | 625 | This subsection provides a set of functions allowing to control dynamically |
| phungductung | 0:8ede47d38d10 | 626 | the FMC NAND interface. |
| phungductung | 0:8ede47d38d10 | 627 | |
| phungductung | 0:8ede47d38d10 | 628 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 629 | * @{ |
| phungductung | 0:8ede47d38d10 | 630 | */ |
| phungductung | 0:8ede47d38d10 | 631 | |
| phungductung | 0:8ede47d38d10 | 632 | |
| phungductung | 0:8ede47d38d10 | 633 | /** |
| phungductung | 0:8ede47d38d10 | 634 | * @brief Enables dynamically FMC_NAND ECC feature. |
| phungductung | 0:8ede47d38d10 | 635 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 636 | * @param Bank: NAND bank number |
| phungductung | 0:8ede47d38d10 | 637 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 638 | */ |
| phungductung | 0:8ede47d38d10 | 639 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 640 | { |
| phungductung | 0:8ede47d38d10 | 641 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 642 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 643 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 644 | |
| phungductung | 0:8ede47d38d10 | 645 | /* Enable ECC feature */ |
| phungductung | 0:8ede47d38d10 | 646 | Device->PCR |= FMC_PCR_ECCEN; |
| phungductung | 0:8ede47d38d10 | 647 | |
| phungductung | 0:8ede47d38d10 | 648 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 649 | } |
| phungductung | 0:8ede47d38d10 | 650 | |
| phungductung | 0:8ede47d38d10 | 651 | |
| phungductung | 0:8ede47d38d10 | 652 | /** |
| phungductung | 0:8ede47d38d10 | 653 | * @brief Disables dynamically FMC_NAND ECC feature. |
| phungductung | 0:8ede47d38d10 | 654 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 655 | * @param Bank: NAND bank number |
| phungductung | 0:8ede47d38d10 | 656 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 657 | */ |
| phungductung | 0:8ede47d38d10 | 658 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 659 | { |
| phungductung | 0:8ede47d38d10 | 660 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 661 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 662 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 663 | |
| phungductung | 0:8ede47d38d10 | 664 | /* Disable ECC feature */ |
| phungductung | 0:8ede47d38d10 | 665 | Device->PCR &= ~FMC_PCR_ECCEN; |
| phungductung | 0:8ede47d38d10 | 666 | |
| phungductung | 0:8ede47d38d10 | 667 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 668 | } |
| phungductung | 0:8ede47d38d10 | 669 | |
| phungductung | 0:8ede47d38d10 | 670 | /** |
| phungductung | 0:8ede47d38d10 | 671 | * @brief Disables dynamically FMC_NAND ECC feature. |
| phungductung | 0:8ede47d38d10 | 672 | * @param Device: Pointer to NAND device instance |
| phungductung | 0:8ede47d38d10 | 673 | * @param ECCval: Pointer to ECC value |
| phungductung | 0:8ede47d38d10 | 674 | * @param Bank: NAND bank number |
| phungductung | 0:8ede47d38d10 | 675 | * @param Timeout: Timeout wait value |
| phungductung | 0:8ede47d38d10 | 676 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 677 | */ |
| phungductung | 0:8ede47d38d10 | 678 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
| phungductung | 0:8ede47d38d10 | 679 | { |
| phungductung | 0:8ede47d38d10 | 680 | uint32_t tickstart = 0; |
| phungductung | 0:8ede47d38d10 | 681 | |
| phungductung | 0:8ede47d38d10 | 682 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 683 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 684 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 685 | |
| phungductung | 0:8ede47d38d10 | 686 | /* Get tick */ |
| phungductung | 0:8ede47d38d10 | 687 | tickstart = HAL_GetTick(); |
| phungductung | 0:8ede47d38d10 | 688 | |
| phungductung | 0:8ede47d38d10 | 689 | /* Wait until FIFO is empty */ |
| phungductung | 0:8ede47d38d10 | 690 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
| phungductung | 0:8ede47d38d10 | 691 | { |
| phungductung | 0:8ede47d38d10 | 692 | /* Check for the Timeout */ |
| phungductung | 0:8ede47d38d10 | 693 | if(Timeout != HAL_MAX_DELAY) |
| phungductung | 0:8ede47d38d10 | 694 | { |
| phungductung | 0:8ede47d38d10 | 695 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| phungductung | 0:8ede47d38d10 | 696 | { |
| phungductung | 0:8ede47d38d10 | 697 | return HAL_TIMEOUT; |
| phungductung | 0:8ede47d38d10 | 698 | } |
| phungductung | 0:8ede47d38d10 | 699 | } |
| phungductung | 0:8ede47d38d10 | 700 | } |
| phungductung | 0:8ede47d38d10 | 701 | |
| phungductung | 0:8ede47d38d10 | 702 | /* Get the ECCR register value */ |
| phungductung | 0:8ede47d38d10 | 703 | *ECCval = (uint32_t)Device->ECCR; |
| phungductung | 0:8ede47d38d10 | 704 | |
| phungductung | 0:8ede47d38d10 | 705 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 706 | } |
| phungductung | 0:8ede47d38d10 | 707 | |
| phungductung | 0:8ede47d38d10 | 708 | /** |
| phungductung | 0:8ede47d38d10 | 709 | * @} |
| phungductung | 0:8ede47d38d10 | 710 | */ |
| phungductung | 0:8ede47d38d10 | 711 | |
| phungductung | 0:8ede47d38d10 | 712 | /** |
| phungductung | 0:8ede47d38d10 | 713 | * @} |
| phungductung | 0:8ede47d38d10 | 714 | */ |
| phungductung | 0:8ede47d38d10 | 715 | |
| phungductung | 0:8ede47d38d10 | 716 | /** @defgroup FMC_LL_SDRAM |
| phungductung | 0:8ede47d38d10 | 717 | * @brief SDRAM Controller functions |
| phungductung | 0:8ede47d38d10 | 718 | * |
| phungductung | 0:8ede47d38d10 | 719 | @verbatim |
| phungductung | 0:8ede47d38d10 | 720 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 721 | ##### How to use SDRAM device driver ##### |
| phungductung | 0:8ede47d38d10 | 722 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 723 | [..] |
| phungductung | 0:8ede47d38d10 | 724 | This driver contains a set of APIs to interface with the FMC SDRAM banks in order |
| phungductung | 0:8ede47d38d10 | 725 | to run the SDRAM external devices. |
| phungductung | 0:8ede47d38d10 | 726 | |
| phungductung | 0:8ede47d38d10 | 727 | (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() |
| phungductung | 0:8ede47d38d10 | 728 | (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() |
| phungductung | 0:8ede47d38d10 | 729 | (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() |
| phungductung | 0:8ede47d38d10 | 730 | (+) FMC SDRAM bank enable/disable write operation using the functions |
| phungductung | 0:8ede47d38d10 | 731 | FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() |
| phungductung | 0:8ede47d38d10 | 732 | (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() |
| phungductung | 0:8ede47d38d10 | 733 | |
| phungductung | 0:8ede47d38d10 | 734 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 735 | * @{ |
| phungductung | 0:8ede47d38d10 | 736 | */ |
| phungductung | 0:8ede47d38d10 | 737 | |
| phungductung | 0:8ede47d38d10 | 738 | /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 |
| phungductung | 0:8ede47d38d10 | 739 | * @brief Initialization and Configuration functions |
| phungductung | 0:8ede47d38d10 | 740 | * |
| phungductung | 0:8ede47d38d10 | 741 | @verbatim |
| phungductung | 0:8ede47d38d10 | 742 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 743 | ##### Initialization and de_initialization functions ##### |
| phungductung | 0:8ede47d38d10 | 744 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 745 | [..] |
| phungductung | 0:8ede47d38d10 | 746 | This section provides functions allowing to: |
| phungductung | 0:8ede47d38d10 | 747 | (+) Initialize and configure the FMC SDRAM interface |
| phungductung | 0:8ede47d38d10 | 748 | (+) De-initialize the FMC SDRAM interface |
| phungductung | 0:8ede47d38d10 | 749 | (+) Configure the FMC clock and associated GPIOs |
| phungductung | 0:8ede47d38d10 | 750 | |
| phungductung | 0:8ede47d38d10 | 751 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 752 | * @{ |
| phungductung | 0:8ede47d38d10 | 753 | */ |
| phungductung | 0:8ede47d38d10 | 754 | |
| phungductung | 0:8ede47d38d10 | 755 | /** |
| phungductung | 0:8ede47d38d10 | 756 | * @brief Initializes the FMC_SDRAM device according to the specified |
| phungductung | 0:8ede47d38d10 | 757 | * control parameters in the FMC_SDRAM_InitTypeDef |
| phungductung | 0:8ede47d38d10 | 758 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 759 | * @param Init: Pointer to SDRAM Initialization structure |
| phungductung | 0:8ede47d38d10 | 760 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 761 | */ |
| phungductung | 0:8ede47d38d10 | 762 | HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) |
| phungductung | 0:8ede47d38d10 | 763 | { |
| phungductung | 0:8ede47d38d10 | 764 | uint32_t tmpr1 = 0; |
| phungductung | 0:8ede47d38d10 | 765 | uint32_t tmpr2 = 0; |
| phungductung | 0:8ede47d38d10 | 766 | |
| phungductung | 0:8ede47d38d10 | 767 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 768 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 769 | assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); |
| phungductung | 0:8ede47d38d10 | 770 | assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); |
| phungductung | 0:8ede47d38d10 | 771 | assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); |
| phungductung | 0:8ede47d38d10 | 772 | assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); |
| phungductung | 0:8ede47d38d10 | 773 | assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); |
| phungductung | 0:8ede47d38d10 | 774 | assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); |
| phungductung | 0:8ede47d38d10 | 775 | assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); |
| phungductung | 0:8ede47d38d10 | 776 | assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); |
| phungductung | 0:8ede47d38d10 | 777 | assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); |
| phungductung | 0:8ede47d38d10 | 778 | assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); |
| phungductung | 0:8ede47d38d10 | 779 | |
| phungductung | 0:8ede47d38d10 | 780 | /* Set SDRAM bank configuration parameters */ |
| phungductung | 0:8ede47d38d10 | 781 | if (Init->SDBank != FMC_SDRAM_BANK2) |
| phungductung | 0:8ede47d38d10 | 782 | { |
| phungductung | 0:8ede47d38d10 | 783 | tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
| phungductung | 0:8ede47d38d10 | 784 | |
| phungductung | 0:8ede47d38d10 | 785 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
| phungductung | 0:8ede47d38d10 | 786 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
| phungductung | 0:8ede47d38d10 | 787 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
| phungductung | 0:8ede47d38d10 | 788 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
| phungductung | 0:8ede47d38d10 | 789 | |
| phungductung | 0:8ede47d38d10 | 790 | tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ |
| phungductung | 0:8ede47d38d10 | 791 | Init->RowBitsNumber |\ |
| phungductung | 0:8ede47d38d10 | 792 | Init->MemoryDataWidth |\ |
| phungductung | 0:8ede47d38d10 | 793 | Init->InternalBankNumber |\ |
| phungductung | 0:8ede47d38d10 | 794 | Init->CASLatency |\ |
| phungductung | 0:8ede47d38d10 | 795 | Init->WriteProtection |\ |
| phungductung | 0:8ede47d38d10 | 796 | Init->SDClockPeriod |\ |
| phungductung | 0:8ede47d38d10 | 797 | Init->ReadBurst |\ |
| phungductung | 0:8ede47d38d10 | 798 | Init->ReadPipeDelay |
| phungductung | 0:8ede47d38d10 | 799 | ); |
| phungductung | 0:8ede47d38d10 | 800 | Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
| phungductung | 0:8ede47d38d10 | 801 | } |
| phungductung | 0:8ede47d38d10 | 802 | else /* FMC_Bank2_SDRAM */ |
| phungductung | 0:8ede47d38d10 | 803 | { |
| phungductung | 0:8ede47d38d10 | 804 | tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
| phungductung | 0:8ede47d38d10 | 805 | |
| phungductung | 0:8ede47d38d10 | 806 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
| phungductung | 0:8ede47d38d10 | 807 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
| phungductung | 0:8ede47d38d10 | 808 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
| phungductung | 0:8ede47d38d10 | 809 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
| phungductung | 0:8ede47d38d10 | 810 | |
| phungductung | 0:8ede47d38d10 | 811 | tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ |
| phungductung | 0:8ede47d38d10 | 812 | Init->ReadBurst |\ |
| phungductung | 0:8ede47d38d10 | 813 | Init->ReadPipeDelay); |
| phungductung | 0:8ede47d38d10 | 814 | |
| phungductung | 0:8ede47d38d10 | 815 | tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; |
| phungductung | 0:8ede47d38d10 | 816 | |
| phungductung | 0:8ede47d38d10 | 817 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
| phungductung | 0:8ede47d38d10 | 818 | tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
| phungductung | 0:8ede47d38d10 | 819 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
| phungductung | 0:8ede47d38d10 | 820 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
| phungductung | 0:8ede47d38d10 | 821 | |
| phungductung | 0:8ede47d38d10 | 822 | tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ |
| phungductung | 0:8ede47d38d10 | 823 | Init->RowBitsNumber |\ |
| phungductung | 0:8ede47d38d10 | 824 | Init->MemoryDataWidth |\ |
| phungductung | 0:8ede47d38d10 | 825 | Init->InternalBankNumber |\ |
| phungductung | 0:8ede47d38d10 | 826 | Init->CASLatency |\ |
| phungductung | 0:8ede47d38d10 | 827 | Init->WriteProtection); |
| phungductung | 0:8ede47d38d10 | 828 | |
| phungductung | 0:8ede47d38d10 | 829 | Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
| phungductung | 0:8ede47d38d10 | 830 | Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; |
| phungductung | 0:8ede47d38d10 | 831 | } |
| phungductung | 0:8ede47d38d10 | 832 | |
| phungductung | 0:8ede47d38d10 | 833 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 834 | } |
| phungductung | 0:8ede47d38d10 | 835 | |
| phungductung | 0:8ede47d38d10 | 836 | /** |
| phungductung | 0:8ede47d38d10 | 837 | * @brief Initializes the FMC_SDRAM device timing according to the specified |
| phungductung | 0:8ede47d38d10 | 838 | * parameters in the FMC_SDRAM_TimingTypeDef |
| phungductung | 0:8ede47d38d10 | 839 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 840 | * @param Timing: Pointer to SDRAM Timing structure |
| phungductung | 0:8ede47d38d10 | 841 | * @param Bank: SDRAM bank number |
| phungductung | 0:8ede47d38d10 | 842 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 843 | */ |
| phungductung | 0:8ede47d38d10 | 844 | HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 845 | { |
| phungductung | 0:8ede47d38d10 | 846 | uint32_t tmpr1 = 0; |
| phungductung | 0:8ede47d38d10 | 847 | uint32_t tmpr2 = 0; |
| phungductung | 0:8ede47d38d10 | 848 | |
| phungductung | 0:8ede47d38d10 | 849 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 850 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 851 | assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); |
| phungductung | 0:8ede47d38d10 | 852 | assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); |
| phungductung | 0:8ede47d38d10 | 853 | assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); |
| phungductung | 0:8ede47d38d10 | 854 | assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); |
| phungductung | 0:8ede47d38d10 | 855 | assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); |
| phungductung | 0:8ede47d38d10 | 856 | assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); |
| phungductung | 0:8ede47d38d10 | 857 | assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); |
| phungductung | 0:8ede47d38d10 | 858 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 859 | |
| phungductung | 0:8ede47d38d10 | 860 | /* Set SDRAM device timing parameters */ |
| phungductung | 0:8ede47d38d10 | 861 | if (Bank != FMC_SDRAM_BANK2) |
| phungductung | 0:8ede47d38d10 | 862 | { |
| phungductung | 0:8ede47d38d10 | 863 | tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; |
| phungductung | 0:8ede47d38d10 | 864 | |
| phungductung | 0:8ede47d38d10 | 865 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
| phungductung | 0:8ede47d38d10 | 866 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
| phungductung | 0:8ede47d38d10 | 867 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
| phungductung | 0:8ede47d38d10 | 868 | FMC_SDTR1_TRCD)); |
| phungductung | 0:8ede47d38d10 | 869 | |
| phungductung | 0:8ede47d38d10 | 870 | tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ |
| phungductung | 0:8ede47d38d10 | 871 | (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ |
| phungductung | 0:8ede47d38d10 | 872 | (((Timing->SelfRefreshTime)-1) << 8) |\ |
| phungductung | 0:8ede47d38d10 | 873 | (((Timing->RowCycleDelay)-1) << 12) |\ |
| phungductung | 0:8ede47d38d10 | 874 | (((Timing->WriteRecoveryTime)-1) <<16) |\ |
| phungductung | 0:8ede47d38d10 | 875 | (((Timing->RPDelay)-1) << 20) |\ |
| phungductung | 0:8ede47d38d10 | 876 | (((Timing->RCDDelay)-1) << 24)); |
| phungductung | 0:8ede47d38d10 | 877 | Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; |
| phungductung | 0:8ede47d38d10 | 878 | } |
| phungductung | 0:8ede47d38d10 | 879 | else /* FMC_Bank2_SDRAM */ |
| phungductung | 0:8ede47d38d10 | 880 | { |
| phungductung | 0:8ede47d38d10 | 881 | tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; |
| phungductung | 0:8ede47d38d10 | 882 | |
| phungductung | 0:8ede47d38d10 | 883 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
| phungductung | 0:8ede47d38d10 | 884 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
| phungductung | 0:8ede47d38d10 | 885 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
| phungductung | 0:8ede47d38d10 | 886 | FMC_SDTR1_TRCD)); |
| phungductung | 0:8ede47d38d10 | 887 | |
| phungductung | 0:8ede47d38d10 | 888 | tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ |
| phungductung | 0:8ede47d38d10 | 889 | (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ |
| phungductung | 0:8ede47d38d10 | 890 | (((Timing->SelfRefreshTime)-1) << 8) |\ |
| phungductung | 0:8ede47d38d10 | 891 | (((Timing->WriteRecoveryTime)-1) <<16) |\ |
| phungductung | 0:8ede47d38d10 | 892 | (((Timing->RCDDelay)-1) << 24)); |
| phungductung | 0:8ede47d38d10 | 893 | |
| phungductung | 0:8ede47d38d10 | 894 | tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; |
| phungductung | 0:8ede47d38d10 | 895 | |
| phungductung | 0:8ede47d38d10 | 896 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
| phungductung | 0:8ede47d38d10 | 897 | tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
| phungductung | 0:8ede47d38d10 | 898 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
| phungductung | 0:8ede47d38d10 | 899 | FMC_SDTR1_TRCD)); |
| phungductung | 0:8ede47d38d10 | 900 | tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ |
| phungductung | 0:8ede47d38d10 | 901 | (((Timing->RPDelay)-1) << 20)); |
| phungductung | 0:8ede47d38d10 | 902 | |
| phungductung | 0:8ede47d38d10 | 903 | Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; |
| phungductung | 0:8ede47d38d10 | 904 | Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; |
| phungductung | 0:8ede47d38d10 | 905 | } |
| phungductung | 0:8ede47d38d10 | 906 | |
| phungductung | 0:8ede47d38d10 | 907 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 908 | } |
| phungductung | 0:8ede47d38d10 | 909 | |
| phungductung | 0:8ede47d38d10 | 910 | /** |
| phungductung | 0:8ede47d38d10 | 911 | * @brief DeInitializes the FMC_SDRAM peripheral |
| phungductung | 0:8ede47d38d10 | 912 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 913 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 914 | */ |
| phungductung | 0:8ede47d38d10 | 915 | HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 916 | { |
| phungductung | 0:8ede47d38d10 | 917 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 918 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 919 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 920 | |
| phungductung | 0:8ede47d38d10 | 921 | /* De-initialize the SDRAM device */ |
| phungductung | 0:8ede47d38d10 | 922 | Device->SDCR[Bank] = 0x000002D0; |
| phungductung | 0:8ede47d38d10 | 923 | Device->SDTR[Bank] = 0x0FFFFFFF; |
| phungductung | 0:8ede47d38d10 | 924 | Device->SDCMR = 0x00000000; |
| phungductung | 0:8ede47d38d10 | 925 | Device->SDRTR = 0x00000000; |
| phungductung | 0:8ede47d38d10 | 926 | Device->SDSR = 0x00000000; |
| phungductung | 0:8ede47d38d10 | 927 | |
| phungductung | 0:8ede47d38d10 | 928 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 929 | } |
| phungductung | 0:8ede47d38d10 | 930 | |
| phungductung | 0:8ede47d38d10 | 931 | /** |
| phungductung | 0:8ede47d38d10 | 932 | * @} |
| phungductung | 0:8ede47d38d10 | 933 | */ |
| phungductung | 0:8ede47d38d10 | 934 | |
| phungductung | 0:8ede47d38d10 | 935 | /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 |
| phungductung | 0:8ede47d38d10 | 936 | * @brief management functions |
| phungductung | 0:8ede47d38d10 | 937 | * |
| phungductung | 0:8ede47d38d10 | 938 | @verbatim |
| phungductung | 0:8ede47d38d10 | 939 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 940 | ##### FMC_SDRAM Control functions ##### |
| phungductung | 0:8ede47d38d10 | 941 | ============================================================================== |
| phungductung | 0:8ede47d38d10 | 942 | [..] |
| phungductung | 0:8ede47d38d10 | 943 | This subsection provides a set of functions allowing to control dynamically |
| phungductung | 0:8ede47d38d10 | 944 | the FMC SDRAM interface. |
| phungductung | 0:8ede47d38d10 | 945 | |
| phungductung | 0:8ede47d38d10 | 946 | @endverbatim |
| phungductung | 0:8ede47d38d10 | 947 | * @{ |
| phungductung | 0:8ede47d38d10 | 948 | */ |
| phungductung | 0:8ede47d38d10 | 949 | |
| phungductung | 0:8ede47d38d10 | 950 | /** |
| phungductung | 0:8ede47d38d10 | 951 | * @brief Enables dynamically FMC_SDRAM write protection. |
| phungductung | 0:8ede47d38d10 | 952 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 953 | * @param Bank: SDRAM bank number |
| phungductung | 0:8ede47d38d10 | 954 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 955 | */ |
| phungductung | 0:8ede47d38d10 | 956 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 957 | { |
| phungductung | 0:8ede47d38d10 | 958 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 959 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 960 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 961 | |
| phungductung | 0:8ede47d38d10 | 962 | /* Enable write protection */ |
| phungductung | 0:8ede47d38d10 | 963 | Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
| phungductung | 0:8ede47d38d10 | 964 | |
| phungductung | 0:8ede47d38d10 | 965 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 966 | } |
| phungductung | 0:8ede47d38d10 | 967 | |
| phungductung | 0:8ede47d38d10 | 968 | /** |
| phungductung | 0:8ede47d38d10 | 969 | * @brief Disables dynamically FMC_SDRAM write protection. |
| phungductung | 0:8ede47d38d10 | 970 | * @param hsdram: FMC_SDRAM handle |
| phungductung | 0:8ede47d38d10 | 971 | * @retval HAL status |
| phungductung | 0:8ede47d38d10 | 972 | */ |
| phungductung | 0:8ede47d38d10 | 973 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 974 | { |
| phungductung | 0:8ede47d38d10 | 975 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 976 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 977 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 978 | |
| phungductung | 0:8ede47d38d10 | 979 | /* Disable write protection */ |
| phungductung | 0:8ede47d38d10 | 980 | Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
| phungductung | 0:8ede47d38d10 | 981 | |
| phungductung | 0:8ede47d38d10 | 982 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 983 | } |
| phungductung | 0:8ede47d38d10 | 984 | |
| phungductung | 0:8ede47d38d10 | 985 | /** |
| phungductung | 0:8ede47d38d10 | 986 | * @brief Send Command to the FMC SDRAM bank |
| phungductung | 0:8ede47d38d10 | 987 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 988 | * @param Command: Pointer to SDRAM command structure |
| phungductung | 0:8ede47d38d10 | 989 | * @param Timing: Pointer to SDRAM Timing structure |
| phungductung | 0:8ede47d38d10 | 990 | * @param Timeout: Timeout wait value |
| phungductung | 0:8ede47d38d10 | 991 | * @retval HAL state |
| phungductung | 0:8ede47d38d10 | 992 | */ |
| phungductung | 0:8ede47d38d10 | 993 | HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
| phungductung | 0:8ede47d38d10 | 994 | { |
| phungductung | 0:8ede47d38d10 | 995 | __IO uint32_t tmpr = 0; |
| phungductung | 0:8ede47d38d10 | 996 | uint32_t tickstart = 0; |
| phungductung | 0:8ede47d38d10 | 997 | |
| phungductung | 0:8ede47d38d10 | 998 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 999 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 1000 | assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); |
| phungductung | 0:8ede47d38d10 | 1001 | assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); |
| phungductung | 0:8ede47d38d10 | 1002 | assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); |
| phungductung | 0:8ede47d38d10 | 1003 | assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); |
| phungductung | 0:8ede47d38d10 | 1004 | |
| phungductung | 0:8ede47d38d10 | 1005 | /* Set command register */ |
| phungductung | 0:8ede47d38d10 | 1006 | tmpr = (uint32_t)((Command->CommandMode) |\ |
| phungductung | 0:8ede47d38d10 | 1007 | (Command->CommandTarget) |\ |
| phungductung | 0:8ede47d38d10 | 1008 | (((Command->AutoRefreshNumber)-1) << 5) |\ |
| phungductung | 0:8ede47d38d10 | 1009 | ((Command->ModeRegisterDefinition) << 9) |
| phungductung | 0:8ede47d38d10 | 1010 | ); |
| phungductung | 0:8ede47d38d10 | 1011 | |
| phungductung | 0:8ede47d38d10 | 1012 | Device->SDCMR = tmpr; |
| phungductung | 0:8ede47d38d10 | 1013 | |
| phungductung | 0:8ede47d38d10 | 1014 | /* Get tick */ |
| phungductung | 0:8ede47d38d10 | 1015 | tickstart = HAL_GetTick(); |
| phungductung | 0:8ede47d38d10 | 1016 | |
| phungductung | 0:8ede47d38d10 | 1017 | /* wait until command is send */ |
| phungductung | 0:8ede47d38d10 | 1018 | while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) |
| phungductung | 0:8ede47d38d10 | 1019 | { |
| phungductung | 0:8ede47d38d10 | 1020 | /* Check for the Timeout */ |
| phungductung | 0:8ede47d38d10 | 1021 | if(Timeout != HAL_MAX_DELAY) |
| phungductung | 0:8ede47d38d10 | 1022 | { |
| phungductung | 0:8ede47d38d10 | 1023 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| phungductung | 0:8ede47d38d10 | 1024 | { |
| phungductung | 0:8ede47d38d10 | 1025 | return HAL_TIMEOUT; |
| phungductung | 0:8ede47d38d10 | 1026 | } |
| phungductung | 0:8ede47d38d10 | 1027 | } |
| phungductung | 0:8ede47d38d10 | 1028 | } |
| phungductung | 0:8ede47d38d10 | 1029 | |
| phungductung | 0:8ede47d38d10 | 1030 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 1031 | } |
| phungductung | 0:8ede47d38d10 | 1032 | |
| phungductung | 0:8ede47d38d10 | 1033 | /** |
| phungductung | 0:8ede47d38d10 | 1034 | * @brief Program the SDRAM Memory Refresh rate. |
| phungductung | 0:8ede47d38d10 | 1035 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 1036 | * @param RefreshRate: The SDRAM refresh rate value. |
| phungductung | 0:8ede47d38d10 | 1037 | * @retval HAL state |
| phungductung | 0:8ede47d38d10 | 1038 | */ |
| phungductung | 0:8ede47d38d10 | 1039 | HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) |
| phungductung | 0:8ede47d38d10 | 1040 | { |
| phungductung | 0:8ede47d38d10 | 1041 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 1042 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 1043 | assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); |
| phungductung | 0:8ede47d38d10 | 1044 | |
| phungductung | 0:8ede47d38d10 | 1045 | /* Set the refresh rate in command register */ |
| phungductung | 0:8ede47d38d10 | 1046 | Device->SDRTR |= (RefreshRate<<1); |
| phungductung | 0:8ede47d38d10 | 1047 | |
| phungductung | 0:8ede47d38d10 | 1048 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 1049 | } |
| phungductung | 0:8ede47d38d10 | 1050 | |
| phungductung | 0:8ede47d38d10 | 1051 | /** |
| phungductung | 0:8ede47d38d10 | 1052 | * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. |
| phungductung | 0:8ede47d38d10 | 1053 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 1054 | * @param AutoRefreshNumber: Specifies the auto Refresh number. |
| phungductung | 0:8ede47d38d10 | 1055 | * @retval None |
| phungductung | 0:8ede47d38d10 | 1056 | */ |
| phungductung | 0:8ede47d38d10 | 1057 | HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) |
| phungductung | 0:8ede47d38d10 | 1058 | { |
| phungductung | 0:8ede47d38d10 | 1059 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 1060 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 1061 | assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); |
| phungductung | 0:8ede47d38d10 | 1062 | |
| phungductung | 0:8ede47d38d10 | 1063 | /* Set the Auto-refresh number in command register */ |
| phungductung | 0:8ede47d38d10 | 1064 | Device->SDCMR |= (AutoRefreshNumber << 5); |
| phungductung | 0:8ede47d38d10 | 1065 | |
| phungductung | 0:8ede47d38d10 | 1066 | return HAL_OK; |
| phungductung | 0:8ede47d38d10 | 1067 | } |
| phungductung | 0:8ede47d38d10 | 1068 | |
| phungductung | 0:8ede47d38d10 | 1069 | /** |
| phungductung | 0:8ede47d38d10 | 1070 | * @brief Returns the indicated FMC SDRAM bank mode status. |
| phungductung | 0:8ede47d38d10 | 1071 | * @param Device: Pointer to SDRAM device instance |
| phungductung | 0:8ede47d38d10 | 1072 | * @param Bank: Defines the FMC SDRAM bank. This parameter can be |
| phungductung | 0:8ede47d38d10 | 1073 | * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. |
| phungductung | 0:8ede47d38d10 | 1074 | * @retval The FMC SDRAM bank mode status, could be on of the following values: |
| phungductung | 0:8ede47d38d10 | 1075 | * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or |
| phungductung | 0:8ede47d38d10 | 1076 | * FMC_SDRAM_POWER_DOWN_MODE. |
| phungductung | 0:8ede47d38d10 | 1077 | */ |
| phungductung | 0:8ede47d38d10 | 1078 | uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| phungductung | 0:8ede47d38d10 | 1079 | { |
| phungductung | 0:8ede47d38d10 | 1080 | uint32_t tmpreg = 0; |
| phungductung | 0:8ede47d38d10 | 1081 | |
| phungductung | 0:8ede47d38d10 | 1082 | /* Check the parameters */ |
| phungductung | 0:8ede47d38d10 | 1083 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| phungductung | 0:8ede47d38d10 | 1084 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| phungductung | 0:8ede47d38d10 | 1085 | |
| phungductung | 0:8ede47d38d10 | 1086 | /* Get the corresponding bank mode */ |
| phungductung | 0:8ede47d38d10 | 1087 | if(Bank == FMC_SDRAM_BANK1) |
| phungductung | 0:8ede47d38d10 | 1088 | { |
| phungductung | 0:8ede47d38d10 | 1089 | tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); |
| phungductung | 0:8ede47d38d10 | 1090 | } |
| phungductung | 0:8ede47d38d10 | 1091 | else |
| phungductung | 0:8ede47d38d10 | 1092 | { |
| phungductung | 0:8ede47d38d10 | 1093 | tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); |
| phungductung | 0:8ede47d38d10 | 1094 | } |
| phungductung | 0:8ede47d38d10 | 1095 | |
| phungductung | 0:8ede47d38d10 | 1096 | /* Return the mode status */ |
| phungductung | 0:8ede47d38d10 | 1097 | return tmpreg; |
| phungductung | 0:8ede47d38d10 | 1098 | } |
| phungductung | 0:8ede47d38d10 | 1099 | |
| phungductung | 0:8ede47d38d10 | 1100 | /** |
| phungductung | 0:8ede47d38d10 | 1101 | * @} |
| phungductung | 0:8ede47d38d10 | 1102 | */ |
| phungductung | 0:8ede47d38d10 | 1103 | |
| phungductung | 0:8ede47d38d10 | 1104 | /** |
| phungductung | 0:8ede47d38d10 | 1105 | * @} |
| phungductung | 0:8ede47d38d10 | 1106 | */ |
| phungductung | 0:8ede47d38d10 | 1107 | |
| phungductung | 0:8ede47d38d10 | 1108 | /** |
| phungductung | 0:8ede47d38d10 | 1109 | * @} |
| phungductung | 0:8ede47d38d10 | 1110 | */ |
| phungductung | 0:8ede47d38d10 | 1111 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ |
| phungductung | 0:8ede47d38d10 | 1112 | |
| phungductung | 0:8ede47d38d10 | 1113 | /** |
| phungductung | 0:8ede47d38d10 | 1114 | * @} |
| phungductung | 0:8ede47d38d10 | 1115 | */ |
| phungductung | 0:8ede47d38d10 | 1116 | |
| phungductung | 0:8ede47d38d10 | 1117 | /** |
| phungductung | 0:8ede47d38d10 | 1118 | * @} |
| phungductung | 0:8ede47d38d10 | 1119 | */ |
| phungductung | 0:8ede47d38d10 | 1120 | |
| phungductung | 0:8ede47d38d10 | 1121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |