DISCO-F746_WAV_PLAYER - SPKT

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Dependencies: F746_GUI SD_PlayerSkeleton F746_SAI_IO

SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:: phungductung
Date:: Tue Jun 04 21:37:21 2019 +0000
Revision:: 0:8ede47d38d10

SPKT

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User	Revision	Line number	New contents of line
phungductung	0:8ede47d38d10	1	/**
phungductung	0:8ede47d38d10	2	******************************************************************************
phungductung	0:8ede47d38d10	3	* @file stm32f7xx_hal_spi.c
phungductung	0:8ede47d38d10	4	* @author MCD Application Team
phungductung	0:8ede47d38d10	5	* @version V1.0.4
phungductung	0:8ede47d38d10	6	* @date 09-December-2015
phungductung	0:8ede47d38d10	7	* @brief SPI HAL module driver.
phungductung	0:8ede47d38d10	8	* This file provides firmware functions to manage the following
phungductung	0:8ede47d38d10	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
phungductung	0:8ede47d38d10	10	* + Initialization and de-initialization functions
phungductung	0:8ede47d38d10	11	* + IO operation functions
phungductung	0:8ede47d38d10	12	* + Peripheral Control functions
phungductung	0:8ede47d38d10	13	* + Peripheral State functions
phungductung	0:8ede47d38d10	14	@verbatim
phungductung	0:8ede47d38d10	15	==============================================================================
phungductung	0:8ede47d38d10	16	##### How to use this driver #####
phungductung	0:8ede47d38d10	17	==============================================================================
phungductung	0:8ede47d38d10	18	[..]
phungductung	0:8ede47d38d10	19	The SPI HAL driver can be used as follows:
phungductung	0:8ede47d38d10	20
phungductung	0:8ede47d38d10	21	(#) Declare a SPI_HandleTypeDef handle structure, for example:
phungductung	0:8ede47d38d10	22	SPI_HandleTypeDef hspi;
phungductung	0:8ede47d38d10	23
phungductung	0:8ede47d38d10	24	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
phungductung	0:8ede47d38d10	25	(##) Enable the SPIx interface clock
phungductung	0:8ede47d38d10	26	(##) SPI pins configuration
phungductung	0:8ede47d38d10	27	(+++) Enable the clock for the SPI GPIOs
phungductung	0:8ede47d38d10	28	(+++) Configure these SPI pins as alternate function push-pull
phungductung	0:8ede47d38d10	29	(##) NVIC configuration if you need to use interrupt process
phungductung	0:8ede47d38d10	30	(+++) Configure the SPIx interrupt priority
phungductung	0:8ede47d38d10	31	(+++) Enable the NVIC SPI IRQ handle
phungductung	0:8ede47d38d10	32	(##) DMA Configuration if you need to use DMA process
phungductung	0:8ede47d38d10	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
phungductung	0:8ede47d38d10	34	(+++) Enable the DMAx clock
phungductung	0:8ede47d38d10	35	(+++) Configure the DMA handle parameters
phungductung	0:8ede47d38d10	36	(+++) Configure the DMA Tx or Rx channel
phungductung	0:8ede47d38d10	37	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
phungductung	0:8ede47d38d10	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
phungductung	0:8ede47d38d10	39
phungductung	0:8ede47d38d10	40	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
phungductung	0:8ede47d38d10	41	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
phungductung	0:8ede47d38d10	42
phungductung	0:8ede47d38d10	43	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
phungductung	0:8ede47d38d10	44	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
phungductung	0:8ede47d38d10	45	by calling the customised HAL_SPI_MspInit() API.
phungductung	0:8ede47d38d10	46	[..]
phungductung	0:8ede47d38d10	47	Circular mode restriction:
phungductung	0:8ede47d38d10	48	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
phungductung	0:8ede47d38d10	49	(##) Master 2Lines RxOnly
phungductung	0:8ede47d38d10	50	(##) Master 1Line Rx
phungductung	0:8ede47d38d10	51	(#) The CRC feature is not managed when the DMA circular mode is enabled
phungductung	0:8ede47d38d10	52	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
phungductung	0:8ede47d38d10	53	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
phungductung	0:8ede47d38d10	54
phungductung	0:8ede47d38d10	55	@endverbatim
phungductung	0:8ede47d38d10	56	******************************************************************************
phungductung	0:8ede47d38d10	57	* @attention
phungductung	0:8ede47d38d10	58	*
phungductung	0:8ede47d38d10	59	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung	0:8ede47d38d10	60	*
phungductung	0:8ede47d38d10	61	* Redistribution and use in source and binary forms, with or without modification,
phungductung	0:8ede47d38d10	62	* are permitted provided that the following conditions are met:
phungductung	0:8ede47d38d10	63	* 1. Redistributions of source code must retain the above copyright notice,
phungductung	0:8ede47d38d10	64	* this list of conditions and the following disclaimer.
phungductung	0:8ede47d38d10	65	* 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung	0:8ede47d38d10	66	* this list of conditions and the following disclaimer in the documentation
phungductung	0:8ede47d38d10	67	* and/or other materials provided with the distribution.
phungductung	0:8ede47d38d10	68	* 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung	0:8ede47d38d10	69	* may be used to endorse or promote products derived from this software
phungductung	0:8ede47d38d10	70	* without specific prior written permission.
phungductung	0:8ede47d38d10	71	*
phungductung	0:8ede47d38d10	72	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung	0:8ede47d38d10	73	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung	0:8ede47d38d10	74	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung	0:8ede47d38d10	75	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung	0:8ede47d38d10	76	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung	0:8ede47d38d10	77	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung	0:8ede47d38d10	78	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung	0:8ede47d38d10	79	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung	0:8ede47d38d10	80	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung	0:8ede47d38d10	81	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung	0:8ede47d38d10	82	*
phungductung	0:8ede47d38d10	83	******************************************************************************
phungductung	0:8ede47d38d10	84	*/
phungductung	0:8ede47d38d10	85
phungductung	0:8ede47d38d10	86	/* Includes ------------------------------------------------------------------*/
phungductung	0:8ede47d38d10	87	#include "stm32f7xx_hal.h"
phungductung	0:8ede47d38d10	88
phungductung	0:8ede47d38d10	89	/** @addtogroup STM32F7xx_HAL_Driver
phungductung	0:8ede47d38d10	90	* @{
phungductung	0:8ede47d38d10	91	*/
phungductung	0:8ede47d38d10	92
phungductung	0:8ede47d38d10	93	/** @defgroup SPI SPI
phungductung	0:8ede47d38d10	94	* @brief SPI HAL module driver
phungductung	0:8ede47d38d10	95	* @{
phungductung	0:8ede47d38d10	96	*/
phungductung	0:8ede47d38d10	97	#ifdef HAL_SPI_MODULE_ENABLED
phungductung	0:8ede47d38d10	98
phungductung	0:8ede47d38d10	99	/* Private typedef -----------------------------------------------------------*/
phungductung	0:8ede47d38d10	100	/* Private defines -----------------------------------------------------------*/
phungductung	0:8ede47d38d10	101	/** @defgroup SPI_Private_Constants SPI Private Constants
phungductung	0:8ede47d38d10	102	* @{
phungductung	0:8ede47d38d10	103	*/
phungductung	0:8ede47d38d10	104	#define SPI_DEFAULT_TIMEOUT 50
phungductung	0:8ede47d38d10	105	/**
phungductung	0:8ede47d38d10	106	* @}
phungductung	0:8ede47d38d10	107	*/
phungductung	0:8ede47d38d10	108
phungductung	0:8ede47d38d10	109	/* Private macro -------------------------------------------------------------*/
phungductung	0:8ede47d38d10	110	/* Private variables ---------------------------------------------------------*/
phungductung	0:8ede47d38d10	111	/* Private function prototypes -----------------------------------------------*/
phungductung	0:8ede47d38d10	112	/** @addtogroup SPI_Private_Functions
phungductung	0:8ede47d38d10	113	* @{
phungductung	0:8ede47d38d10	114	*/
phungductung	0:8ede47d38d10	115	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	116	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	117	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	118	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	119	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	120	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	121	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
phungductung	0:8ede47d38d10	122	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
phungductung	0:8ede47d38d10	123	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
phungductung	0:8ede47d38d10	124	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	125	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	126	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	127	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	128	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	129	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	130	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	131	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	132	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	133	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	134	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	135	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	136	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	137	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	138	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
phungductung	0:8ede47d38d10	139	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
phungductung	0:8ede47d38d10	140	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
phungductung	0:8ede47d38d10	141	/**
phungductung	0:8ede47d38d10	142	* @}
phungductung	0:8ede47d38d10	143	*/
phungductung	0:8ede47d38d10	144
phungductung	0:8ede47d38d10	145	/* Exported functions ---------------------------------------------------------*/
phungductung	0:8ede47d38d10	146
phungductung	0:8ede47d38d10	147	/** @defgroup SPI_Exported_Functions SPI Exported Functions
phungductung	0:8ede47d38d10	148	* @{
phungductung	0:8ede47d38d10	149	*/
phungductung	0:8ede47d38d10	150
phungductung	0:8ede47d38d10	151	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung	0:8ede47d38d10	152	* @brief Initialization and Configuration functions
phungductung	0:8ede47d38d10	153	*
phungductung	0:8ede47d38d10	154	@verbatim
phungductung	0:8ede47d38d10	155	===============================================================================
phungductung	0:8ede47d38d10	156	##### Initialization and de-initialization functions #####
phungductung	0:8ede47d38d10	157	===============================================================================
phungductung	0:8ede47d38d10	158	[..] This subsection provides a set of functions allowing to initialize and
phungductung	0:8ede47d38d10	159	de-initialize the SPIx peripheral:
phungductung	0:8ede47d38d10	160
phungductung	0:8ede47d38d10	161	(+) User must implement HAL_SPI_MspInit() function in which he configures
phungductung	0:8ede47d38d10	162	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
phungductung	0:8ede47d38d10	163
phungductung	0:8ede47d38d10	164	(+) Call the function HAL_SPI_Init() to configure the selected device with
phungductung	0:8ede47d38d10	165	the selected configuration:
phungductung	0:8ede47d38d10	166	(++) Mode
phungductung	0:8ede47d38d10	167	(++) Direction
phungductung	0:8ede47d38d10	168	(++) Data Size
phungductung	0:8ede47d38d10	169	(++) Clock Polarity and Phase
phungductung	0:8ede47d38d10	170	(++) NSS Management
phungductung	0:8ede47d38d10	171	(++) BaudRate Prescaler
phungductung	0:8ede47d38d10	172	(++) FirstBit
phungductung	0:8ede47d38d10	173	(++) TIMode
phungductung	0:8ede47d38d10	174	(++) CRC Calculation
phungductung	0:8ede47d38d10	175	(++) CRC Polynomial if CRC enabled
phungductung	0:8ede47d38d10	176	(++) CRC Length, used only with Data8 and Data16
phungductung	0:8ede47d38d10	177	(++) FIFO reception threshold
phungductung	0:8ede47d38d10	178
phungductung	0:8ede47d38d10	179	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
phungductung	0:8ede47d38d10	180	of the selected SPIx peripheral.
phungductung	0:8ede47d38d10	181
phungductung	0:8ede47d38d10	182	@endverbatim
phungductung	0:8ede47d38d10	183	* @{
phungductung	0:8ede47d38d10	184	*/
phungductung	0:8ede47d38d10	185
phungductung	0:8ede47d38d10	186	/**
phungductung	0:8ede47d38d10	187	* @brief Initializes the SPI according to the specified parameters
phungductung	0:8ede47d38d10	188	* in the SPI_InitTypeDef and create the associated handle.
phungductung	0:8ede47d38d10	189	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	190	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	191	* @retval HAL status
phungductung	0:8ede47d38d10	192	*/
phungductung	0:8ede47d38d10	193	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	194	{
phungductung	0:8ede47d38d10	195	uint32_t frxth;
phungductung	0:8ede47d38d10	196
phungductung	0:8ede47d38d10	197	/* Check the SPI handle allocation */
phungductung	0:8ede47d38d10	198	if(hspi == NULL)
phungductung	0:8ede47d38d10	199	{
phungductung	0:8ede47d38d10	200	return HAL_ERROR;
phungductung	0:8ede47d38d10	201	}
phungductung	0:8ede47d38d10	202
phungductung	0:8ede47d38d10	203	/* Check the parameters */
phungductung	0:8ede47d38d10	204	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
phungductung	0:8ede47d38d10	205	assert_param(IS_SPI_MODE(hspi->Init.Mode));
phungductung	0:8ede47d38d10	206	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
phungductung	0:8ede47d38d10	207	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
phungductung	0:8ede47d38d10	208	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
phungductung	0:8ede47d38d10	209	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
phungductung	0:8ede47d38d10	210	assert_param(IS_SPI_NSS(hspi->Init.NSS));
phungductung	0:8ede47d38d10	211	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
phungductung	0:8ede47d38d10	212	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
phungductung	0:8ede47d38d10	213	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
phungductung	0:8ede47d38d10	214	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
phungductung	0:8ede47d38d10	215	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
phungductung	0:8ede47d38d10	216	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
phungductung	0:8ede47d38d10	217	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
phungductung	0:8ede47d38d10	218
phungductung	0:8ede47d38d10	219	if(hspi->State == HAL_SPI_STATE_RESET)
phungductung	0:8ede47d38d10	220	{
phungductung	0:8ede47d38d10	221	/* Allocate lock resource and initialize it */
phungductung	0:8ede47d38d10	222	hspi->Lock = HAL_UNLOCKED;
phungductung	0:8ede47d38d10	223
phungductung	0:8ede47d38d10	224	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
phungductung	0:8ede47d38d10	225	HAL_SPI_MspInit(hspi);
phungductung	0:8ede47d38d10	226	}
phungductung	0:8ede47d38d10	227
phungductung	0:8ede47d38d10	228	hspi->State = HAL_SPI_STATE_BUSY;
phungductung	0:8ede47d38d10	229
phungductung	0:8ede47d38d10	230	/* Disable the selected SPI peripheral */
phungductung	0:8ede47d38d10	231	__HAL_SPI_DISABLE(hspi);
phungductung	0:8ede47d38d10	232
phungductung	0:8ede47d38d10	233	/* Align by default the rs fifo threshold on the data size */
phungductung	0:8ede47d38d10	234	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	235	{
phungductung	0:8ede47d38d10	236	frxth = SPI_RXFIFO_THRESHOLD_HF;
phungductung	0:8ede47d38d10	237	}
phungductung	0:8ede47d38d10	238	else
phungductung	0:8ede47d38d10	239	{
phungductung	0:8ede47d38d10	240	frxth = SPI_RXFIFO_THRESHOLD_QF;
phungductung	0:8ede47d38d10	241	}
phungductung	0:8ede47d38d10	242
phungductung	0:8ede47d38d10	243	/* CRC calculation is valid only for 16Bit and 8 Bit */
phungductung	0:8ede47d38d10	244	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
phungductung	0:8ede47d38d10	245	{
phungductung	0:8ede47d38d10	246	/* CRC must be disabled */
phungductung	0:8ede47d38d10	247	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
phungductung	0:8ede47d38d10	248	}
phungductung	0:8ede47d38d10	249
phungductung	0:8ede47d38d10	250	/* Align the CRC Length on the data size */
phungductung	0:8ede47d38d10	251	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
phungductung	0:8ede47d38d10	252	{
phungductung	0:8ede47d38d10	253	/* CRC Length aligned on the data size : value set by default */
phungductung	0:8ede47d38d10	254	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	255	{
phungductung	0:8ede47d38d10	256	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
phungductung	0:8ede47d38d10	257	}
phungductung	0:8ede47d38d10	258	else
phungductung	0:8ede47d38d10	259	{
phungductung	0:8ede47d38d10	260	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
phungductung	0:8ede47d38d10	261	}
phungductung	0:8ede47d38d10	262	}
phungductung	0:8ede47d38d10	263
phungductung	0:8ede47d38d10	264	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
phungductung	0:8ede47d38d10	265	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
phungductung	0:8ede47d38d10	266	Communication speed, First bit, CRC calculation state, CRC Length */
phungductung	0:8ede47d38d10	267	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
phungductung	0:8ede47d38d10	268	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
phungductung	0:8ede47d38d10	269	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
phungductung	0:8ede47d38d10	270
phungductung	0:8ede47d38d10	271	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
phungductung	0:8ede47d38d10	272	{
phungductung	0:8ede47d38d10	273	hspi->Instance->CR1\|= SPI_CR1_CRCL;
phungductung	0:8ede47d38d10	274	}
phungductung	0:8ede47d38d10	275
phungductung	0:8ede47d38d10	276	/* Configure : NSS management */
phungductung	0:8ede47d38d10	277	/* Configure : Rx Fifo Threshold */
phungductung	0:8ede47d38d10	278	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
phungductung	0:8ede47d38d10	279	hspi->Init.DataSize ) \| frxth;
phungductung	0:8ede47d38d10	280
phungductung	0:8ede47d38d10	281	/---------------------------- SPIx CRCPOLY Configuration --------------------/
phungductung	0:8ede47d38d10	282	/* Configure : CRC Polynomial */
phungductung	0:8ede47d38d10	283	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
phungductung	0:8ede47d38d10	284
phungductung	0:8ede47d38d10	285	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	286	hspi->State= HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	287
phungductung	0:8ede47d38d10	288	return HAL_OK;
phungductung	0:8ede47d38d10	289	}
phungductung	0:8ede47d38d10	290
phungductung	0:8ede47d38d10	291	/**
phungductung	0:8ede47d38d10	292	* @brief DeInitializes the SPI peripheral
phungductung	0:8ede47d38d10	293	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	294	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	295	* @retval HAL status
phungductung	0:8ede47d38d10	296	*/
phungductung	0:8ede47d38d10	297	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	298	{
phungductung	0:8ede47d38d10	299	/* Check the SPI handle allocation */
phungductung	0:8ede47d38d10	300	if(hspi == NULL)
phungductung	0:8ede47d38d10	301	{
phungductung	0:8ede47d38d10	302	return HAL_ERROR;
phungductung	0:8ede47d38d10	303	}
phungductung	0:8ede47d38d10	304
phungductung	0:8ede47d38d10	305	/* Check the parameters */
phungductung	0:8ede47d38d10	306	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
phungductung	0:8ede47d38d10	307
phungductung	0:8ede47d38d10	308	hspi->State = HAL_SPI_STATE_BUSY;
phungductung	0:8ede47d38d10	309
phungductung	0:8ede47d38d10	310	/* check flag before the SPI disable */
phungductung	0:8ede47d38d10	311	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
phungductung	0:8ede47d38d10	312	SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
phungductung	0:8ede47d38d10	313	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
phungductung	0:8ede47d38d10	314
phungductung	0:8ede47d38d10	315	/* Disable the SPI Peripheral Clock */
phungductung	0:8ede47d38d10	316	__HAL_SPI_DISABLE(hspi);
phungductung	0:8ede47d38d10	317
phungductung	0:8ede47d38d10	318	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
phungductung	0:8ede47d38d10	319	HAL_SPI_MspDeInit(hspi);
phungductung	0:8ede47d38d10	320
phungductung	0:8ede47d38d10	321	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	322	hspi->State = HAL_SPI_STATE_RESET;
phungductung	0:8ede47d38d10	323
phungductung	0:8ede47d38d10	324	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	325
phungductung	0:8ede47d38d10	326	return HAL_OK;
phungductung	0:8ede47d38d10	327	}
phungductung	0:8ede47d38d10	328
phungductung	0:8ede47d38d10	329	/**
phungductung	0:8ede47d38d10	330	* @brief SPI MSP Init
phungductung	0:8ede47d38d10	331	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	332	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	333	* @retval None
phungductung	0:8ede47d38d10	334	*/
phungductung	0:8ede47d38d10	335	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	336	{
phungductung	0:8ede47d38d10	337	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	338	UNUSED(hspi);
phungductung	0:8ede47d38d10	339
phungductung	0:8ede47d38d10	340	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	341	the HAL_SPI_MspInit should be implemented in the user file
phungductung	0:8ede47d38d10	342	*/
phungductung	0:8ede47d38d10	343	}
phungductung	0:8ede47d38d10	344
phungductung	0:8ede47d38d10	345	/**
phungductung	0:8ede47d38d10	346	* @brief SPI MSP DeInit
phungductung	0:8ede47d38d10	347	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	348	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	349	* @retval None
phungductung	0:8ede47d38d10	350	*/
phungductung	0:8ede47d38d10	351	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	352	{
phungductung	0:8ede47d38d10	353	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	354	UNUSED(hspi);
phungductung	0:8ede47d38d10	355
phungductung	0:8ede47d38d10	356	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	357	the HAL_SPI_MspDeInit should be implemented in the user file
phungductung	0:8ede47d38d10	358	*/
phungductung	0:8ede47d38d10	359	}
phungductung	0:8ede47d38d10	360
phungductung	0:8ede47d38d10	361	/**
phungductung	0:8ede47d38d10	362	* @}
phungductung	0:8ede47d38d10	363	*/
phungductung	0:8ede47d38d10	364
phungductung	0:8ede47d38d10	365	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
phungductung	0:8ede47d38d10	366	* @brief Data transfers functions
phungductung	0:8ede47d38d10	367	*
phungductung	0:8ede47d38d10	368	@verbatim
phungductung	0:8ede47d38d10	369	==============================================================================
phungductung	0:8ede47d38d10	370	##### IO operation functions #####
phungductung	0:8ede47d38d10	371	===============================================================================
phungductung	0:8ede47d38d10	372	This subsection provides a set of functions allowing to manage the SPI
phungductung	0:8ede47d38d10	373	data transfers.
phungductung	0:8ede47d38d10	374
phungductung	0:8ede47d38d10	375	[..] The SPI supports master and slave mode :
phungductung	0:8ede47d38d10	376
phungductung	0:8ede47d38d10	377	(#) There are two modes of transfer:
phungductung	0:8ede47d38d10	378	(++) Blocking mode: The communication is performed in polling mode.
phungductung	0:8ede47d38d10	379	The HAL status of all data processing is returned by the same function
phungductung	0:8ede47d38d10	380	after finishing transfer.
phungductung	0:8ede47d38d10	381	(++) No-Blocking mode: The communication is performed using Interrupts
phungductung	0:8ede47d38d10	382	or DMA, These APIs return the HAL status.
phungductung	0:8ede47d38d10	383	The end of the data processing will be indicated through the
phungductung	0:8ede47d38d10	384	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
phungductung	0:8ede47d38d10	385	using DMA mode.
phungductung	0:8ede47d38d10	386	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
phungductung	0:8ede47d38d10	387	will be executed respectively at the end of the transmit or Receive process
phungductung	0:8ede47d38d10	388	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
phungductung	0:8ede47d38d10	389
phungductung	0:8ede47d38d10	390	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
phungductung	0:8ede47d38d10	391	exist for 1Line (simplex) and 2Lines (full duplex) modes.
phungductung	0:8ede47d38d10	392
phungductung	0:8ede47d38d10	393	@endverbatim
phungductung	0:8ede47d38d10	394	* @{
phungductung	0:8ede47d38d10	395	*/
phungductung	0:8ede47d38d10	396
phungductung	0:8ede47d38d10	397	/**
phungductung	0:8ede47d38d10	398	* @brief Transmit an amount of data in blocking mode
phungductung	0:8ede47d38d10	399	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	400	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	401	* @param pData: pointer to data buffer
phungductung	0:8ede47d38d10	402	* @param Size: amount of data to be sent
phungductung	0:8ede47d38d10	403	* @param Timeout: Timeout duration
phungductung	0:8ede47d38d10	404	* @retval HAL status
phungductung	0:8ede47d38d10	405	*/
phungductung	0:8ede47d38d10	406	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
phungductung	0:8ede47d38d10	407	{
phungductung	0:8ede47d38d10	408	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
phungductung	0:8ede47d38d10	409
phungductung	0:8ede47d38d10	410	/* Process Locked */
phungductung	0:8ede47d38d10	411	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	412
phungductung	0:8ede47d38d10	413	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	414	{
phungductung	0:8ede47d38d10	415	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	416	/* Process Unlocked */
phungductung	0:8ede47d38d10	417	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	418	return HAL_BUSY;
phungductung	0:8ede47d38d10	419	}
phungductung	0:8ede47d38d10	420
phungductung	0:8ede47d38d10	421	if((pData == NULL ) \|\| (Size == 0))
phungductung	0:8ede47d38d10	422	{
phungductung	0:8ede47d38d10	423	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	424	/* Process Unlocked */
phungductung	0:8ede47d38d10	425	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	426	return HAL_ERROR;
phungductung	0:8ede47d38d10	427	}
phungductung	0:8ede47d38d10	428
phungductung	0:8ede47d38d10	429	/* Set the transaction information */
phungductung	0:8ede47d38d10	430	hspi->State = HAL_SPI_STATE_BUSY_TX;
phungductung	0:8ede47d38d10	431	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	432	hspi->pTxBuffPtr = pData;
phungductung	0:8ede47d38d10	433	hspi->TxXferSize = Size;
phungductung	0:8ede47d38d10	434	hspi->TxXferCount = Size;
phungductung	0:8ede47d38d10	435	hspi->pRxBuffPtr = (uint8_t *)NULL;
phungductung	0:8ede47d38d10	436	hspi->RxXferSize = 0;
phungductung	0:8ede47d38d10	437	hspi->RxXferCount = 0;
phungductung	0:8ede47d38d10	438
phungductung	0:8ede47d38d10	439	/* Configure communication direction : 1Line */
phungductung	0:8ede47d38d10	440	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:8ede47d38d10	441	{
phungductung	0:8ede47d38d10	442	SPI_1LINE_TX(hspi);
phungductung	0:8ede47d38d10	443	}
phungductung	0:8ede47d38d10	444
phungductung	0:8ede47d38d10	445	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	446	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	447	{
phungductung	0:8ede47d38d10	448	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	449	}
phungductung	0:8ede47d38d10	450
phungductung	0:8ede47d38d10	451	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	452	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	453	{
phungductung	0:8ede47d38d10	454	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	455	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	456	}
phungductung	0:8ede47d38d10	457
phungductung	0:8ede47d38d10	458	/* Transmit data in 16 Bit mode */
phungductung	0:8ede47d38d10	459	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	460	{
phungductung	0:8ede47d38d10	461	/* Transmit data in 16 Bit mode */
phungductung	0:8ede47d38d10	462	while (hspi->TxXferCount > 0)
phungductung	0:8ede47d38d10	463	{
phungductung	0:8ede47d38d10	464	/* Wait until TXE flag is set to send data */
phungductung	0:8ede47d38d10	465	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	466	{
phungductung	0:8ede47d38d10	467	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	468	/* Process Unlocked */
phungductung	0:8ede47d38d10	469	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	470	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	471	}
phungductung	0:8ede47d38d10	472	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	473	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	474	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	475	}
phungductung	0:8ede47d38d10	476	}
phungductung	0:8ede47d38d10	477	/* Transmit data in 8 Bit mode */
phungductung	0:8ede47d38d10	478	else
phungductung	0:8ede47d38d10	479	{
phungductung	0:8ede47d38d10	480	while (hspi->TxXferCount > 0)
phungductung	0:8ede47d38d10	481	{
phungductung	0:8ede47d38d10	482	if(hspi->TxXferCount != 0x1)
phungductung	0:8ede47d38d10	483	{
phungductung	0:8ede47d38d10	484	/* Wait until TXE flag is set to send data */
phungductung	0:8ede47d38d10	485	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	486	{
phungductung	0:8ede47d38d10	487	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	488	/* Process Unlocked */
phungductung	0:8ede47d38d10	489	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	490	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	491	}
phungductung	0:8ede47d38d10	492	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	493	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	494	hspi->TxXferCount -= 2;
phungductung	0:8ede47d38d10	495	}
phungductung	0:8ede47d38d10	496	else
phungductung	0:8ede47d38d10	497	{
phungductung	0:8ede47d38d10	498	/* Wait until TXE flag is set to send data */
phungductung	0:8ede47d38d10	499	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	500	{
phungductung	0:8ede47d38d10	501	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	502	}
phungductung	0:8ede47d38d10	503	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
phungductung	0:8ede47d38d10	504	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	505	}
phungductung	0:8ede47d38d10	506	}
phungductung	0:8ede47d38d10	507	}
phungductung	0:8ede47d38d10	508
phungductung	0:8ede47d38d10	509	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	510	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	511	{
phungductung	0:8ede47d38d10	512	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	513	}
phungductung	0:8ede47d38d10	514
phungductung	0:8ede47d38d10	515	/* Check the end of the transaction */
phungductung	0:8ede47d38d10	516	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	517	{
phungductung	0:8ede47d38d10	518	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	519	}
phungductung	0:8ede47d38d10	520
phungductung	0:8ede47d38d10	521	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
phungductung	0:8ede47d38d10	522	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
phungductung	0:8ede47d38d10	523	{
phungductung	0:8ede47d38d10	524	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:8ede47d38d10	525	}
phungductung	0:8ede47d38d10	526
phungductung	0:8ede47d38d10	527	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	528
phungductung	0:8ede47d38d10	529	/* Process Unlocked */
phungductung	0:8ede47d38d10	530	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	531
phungductung	0:8ede47d38d10	532	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	533	{
phungductung	0:8ede47d38d10	534	return HAL_ERROR;
phungductung	0:8ede47d38d10	535	}
phungductung	0:8ede47d38d10	536	else
phungductung	0:8ede47d38d10	537	{
phungductung	0:8ede47d38d10	538	return HAL_OK;
phungductung	0:8ede47d38d10	539	}
phungductung	0:8ede47d38d10	540	}
phungductung	0:8ede47d38d10	541
phungductung	0:8ede47d38d10	542	/**
phungductung	0:8ede47d38d10	543	* @brief Receive an amount of data in blocking mode
phungductung	0:8ede47d38d10	544	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	545	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	546	* @param pData: pointer to data buffer
phungductung	0:8ede47d38d10	547	* @param Size: amount of data to be received
phungductung	0:8ede47d38d10	548	* @param Timeout: Timeout duration
phungductung	0:8ede47d38d10	549	* @retval HAL status
phungductung	0:8ede47d38d10	550	*/
phungductung	0:8ede47d38d10	551	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
phungductung	0:8ede47d38d10	552	{
phungductung	0:8ede47d38d10	553	__IO uint16_t tmpreg;
phungductung	0:8ede47d38d10	554
phungductung	0:8ede47d38d10	555	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	556	{
phungductung	0:8ede47d38d10	557	return HAL_BUSY;
phungductung	0:8ede47d38d10	558	}
phungductung	0:8ede47d38d10	559
phungductung	0:8ede47d38d10	560	if((pData == NULL ) \|\| (Size == 0))
phungductung	0:8ede47d38d10	561	{
phungductung	0:8ede47d38d10	562	return HAL_ERROR;
phungductung	0:8ede47d38d10	563	}
phungductung	0:8ede47d38d10	564
phungductung	0:8ede47d38d10	565	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
phungductung	0:8ede47d38d10	566	{
phungductung	0:8ede47d38d10	567	/* the receive process is not supported in 2Lines direction master mode */
phungductung	0:8ede47d38d10	568	/* in this case we call the transmitReceive process */
phungductung	0:8ede47d38d10	569	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
phungductung	0:8ede47d38d10	570	}
phungductung	0:8ede47d38d10	571
phungductung	0:8ede47d38d10	572	/* Process Locked */
phungductung	0:8ede47d38d10	573	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	574
phungductung	0:8ede47d38d10	575	hspi->State = HAL_SPI_STATE_BUSY_RX;
phungductung	0:8ede47d38d10	576	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	577	hspi->pRxBuffPtr = pData;
phungductung	0:8ede47d38d10	578	hspi->RxXferSize = Size;
phungductung	0:8ede47d38d10	579	hspi->RxXferCount = Size;
phungductung	0:8ede47d38d10	580	hspi->pTxBuffPtr = (uint8_t *)NULL;
phungductung	0:8ede47d38d10	581	hspi->TxXferSize = 0;
phungductung	0:8ede47d38d10	582	hspi->TxXferCount = 0;
phungductung	0:8ede47d38d10	583
phungductung	0:8ede47d38d10	584	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	585	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	586	{
phungductung	0:8ede47d38d10	587	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	588	/* this is done to handle the CRCNEXT before the latest data */
phungductung	0:8ede47d38d10	589	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	590	}
phungductung	0:8ede47d38d10	591
phungductung	0:8ede47d38d10	592	/* Set the Rx Fido threshold */
phungductung	0:8ede47d38d10	593	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	594	{
phungductung	0:8ede47d38d10	595	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:8ede47d38d10	596	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	597	}
phungductung	0:8ede47d38d10	598	else
phungductung	0:8ede47d38d10	599	{
phungductung	0:8ede47d38d10	600	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:8ede47d38d10	601	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	602	}
phungductung	0:8ede47d38d10	603
phungductung	0:8ede47d38d10	604	/* Configure communication direction 1Line and enabled SPI if needed */
phungductung	0:8ede47d38d10	605	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:8ede47d38d10	606	{
phungductung	0:8ede47d38d10	607	SPI_1LINE_RX(hspi);
phungductung	0:8ede47d38d10	608	}
phungductung	0:8ede47d38d10	609
phungductung	0:8ede47d38d10	610	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	611	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	612	{
phungductung	0:8ede47d38d10	613	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	614	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	615	}
phungductung	0:8ede47d38d10	616
phungductung	0:8ede47d38d10	617	/* Receive data in 8 Bit mode */
phungductung	0:8ede47d38d10	618	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	619	{
phungductung	0:8ede47d38d10	620	while(hspi->RxXferCount > 1)
phungductung	0:8ede47d38d10	621	{
phungductung	0:8ede47d38d10	622	/* Wait until the RXNE flag */
phungductung	0:8ede47d38d10	623	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	624	{
phungductung	0:8ede47d38d10	625	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	626	}
phungductung	0:8ede47d38d10	627	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
phungductung	0:8ede47d38d10	628	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	629	}
phungductung	0:8ede47d38d10	630	}
phungductung	0:8ede47d38d10	631	else /* Receive data in 16 Bit mode */
phungductung	0:8ede47d38d10	632	{
phungductung	0:8ede47d38d10	633	while(hspi->RxXferCount > 1 )
phungductung	0:8ede47d38d10	634	{
phungductung	0:8ede47d38d10	635	/* Wait until RXNE flag is reset to read data */
phungductung	0:8ede47d38d10	636	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	637	{
phungductung	0:8ede47d38d10	638	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	639	}
phungductung	0:8ede47d38d10	640	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	641	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	642	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	643	}
phungductung	0:8ede47d38d10	644	}
phungductung	0:8ede47d38d10	645
phungductung	0:8ede47d38d10	646	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	647	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	648	{
phungductung	0:8ede47d38d10	649	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	650	}
phungductung	0:8ede47d38d10	651
phungductung	0:8ede47d38d10	652	/* Wait until RXNE flag is set */
phungductung	0:8ede47d38d10	653	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	654	{
phungductung	0:8ede47d38d10	655	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	656	}
phungductung	0:8ede47d38d10	657
phungductung	0:8ede47d38d10	658	/* Receive last data in 16 Bit mode */
phungductung	0:8ede47d38d10	659	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	660	{
phungductung	0:8ede47d38d10	661	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	662	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	663	}
phungductung	0:8ede47d38d10	664	/* Receive last data in 8 Bit mode */
phungductung	0:8ede47d38d10	665	else
phungductung	0:8ede47d38d10	666	{
phungductung	0:8ede47d38d10	667	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
phungductung	0:8ede47d38d10	668	}
phungductung	0:8ede47d38d10	669	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	670
phungductung	0:8ede47d38d10	671	/* Read CRC from DR to close CRC calculation process */
phungductung	0:8ede47d38d10	672	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	673	{
phungductung	0:8ede47d38d10	674	/* Wait until TXE flag */
phungductung	0:8ede47d38d10	675	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	676	{
phungductung	0:8ede47d38d10	677	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	678	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	679	}
phungductung	0:8ede47d38d10	680	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	681	{
phungductung	0:8ede47d38d10	682	tmpreg = hspi->Instance->DR;
phungductung	0:8ede47d38d10	683	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	684	}
phungductung	0:8ede47d38d10	685	else
phungductung	0:8ede47d38d10	686	{
phungductung	0:8ede47d38d10	687	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	688	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	689
phungductung	0:8ede47d38d10	690	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
phungductung	0:8ede47d38d10	691	{
phungductung	0:8ede47d38d10	692	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	693	{
phungductung	0:8ede47d38d10	694	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	695	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
phungductung	0:8ede47d38d10	696	}
phungductung	0:8ede47d38d10	697	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	698	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	699	}
phungductung	0:8ede47d38d10	700	}
phungductung	0:8ede47d38d10	701	}
phungductung	0:8ede47d38d10	702
phungductung	0:8ede47d38d10	703	/* Check the end of the transaction */
phungductung	0:8ede47d38d10	704	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	705	{
phungductung	0:8ede47d38d10	706	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	707	}
phungductung	0:8ede47d38d10	708
phungductung	0:8ede47d38d10	709	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	710
phungductung	0:8ede47d38d10	711	/* Check if CRC error occurred */
phungductung	0:8ede47d38d10	712	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:8ede47d38d10	713	{
phungductung	0:8ede47d38d10	714	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	715	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:8ede47d38d10	716
phungductung	0:8ede47d38d10	717	/* Process Unlocked */
phungductung	0:8ede47d38d10	718	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	719	return HAL_ERROR;
phungductung	0:8ede47d38d10	720	}
phungductung	0:8ede47d38d10	721
phungductung	0:8ede47d38d10	722	/* Process Unlocked */
phungductung	0:8ede47d38d10	723	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	724
phungductung	0:8ede47d38d10	725	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	726	{
phungductung	0:8ede47d38d10	727	return HAL_ERROR;
phungductung	0:8ede47d38d10	728	}
phungductung	0:8ede47d38d10	729	else
phungductung	0:8ede47d38d10	730	{
phungductung	0:8ede47d38d10	731	return HAL_OK;
phungductung	0:8ede47d38d10	732	}
phungductung	0:8ede47d38d10	733	}
phungductung	0:8ede47d38d10	734
phungductung	0:8ede47d38d10	735	/**
phungductung	0:8ede47d38d10	736	* @brief Transmit and Receive an amount of data in blocking mode
phungductung	0:8ede47d38d10	737	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	738	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	739	* @param pTxData: pointer to transmission data buffer
phungductung	0:8ede47d38d10	740	* @param pRxData: pointer to reception data buffer
phungductung	0:8ede47d38d10	741	* @param Size: amount of data to be sent and received
phungductung	0:8ede47d38d10	742	* @param Timeout: Timeout duration
phungductung	0:8ede47d38d10	743	* @retval HAL status
phungductung	0:8ede47d38d10	744	*/
phungductung	0:8ede47d38d10	745	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
phungductung	0:8ede47d38d10	746	{
phungductung	0:8ede47d38d10	747	__IO uint16_t tmpreg = 0;
phungductung	0:8ede47d38d10	748	uint32_t tickstart = HAL_GetTick();
phungductung	0:8ede47d38d10	749
phungductung	0:8ede47d38d10	750	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
phungductung	0:8ede47d38d10	751
phungductung	0:8ede47d38d10	752	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	753	{
phungductung	0:8ede47d38d10	754	return HAL_BUSY;
phungductung	0:8ede47d38d10	755	}
phungductung	0:8ede47d38d10	756
phungductung	0:8ede47d38d10	757	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
phungductung	0:8ede47d38d10	758	{
phungductung	0:8ede47d38d10	759	return HAL_ERROR;
phungductung	0:8ede47d38d10	760	}
phungductung	0:8ede47d38d10	761
phungductung	0:8ede47d38d10	762
phungductung	0:8ede47d38d10	763	/* Process Locked */
phungductung	0:8ede47d38d10	764	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	765
phungductung	0:8ede47d38d10	766	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
phungductung	0:8ede47d38d10	767	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	768	hspi->pRxBuffPtr = pRxData;
phungductung	0:8ede47d38d10	769	hspi->RxXferCount = Size;
phungductung	0:8ede47d38d10	770	hspi->RxXferSize = Size;
phungductung	0:8ede47d38d10	771	hspi->pTxBuffPtr = pTxData;
phungductung	0:8ede47d38d10	772	hspi->TxXferCount = Size;
phungductung	0:8ede47d38d10	773	hspi->TxXferSize = Size;
phungductung	0:8ede47d38d10	774
phungductung	0:8ede47d38d10	775	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	776	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	777	{
phungductung	0:8ede47d38d10	778	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	779	}
phungductung	0:8ede47d38d10	780
phungductung	0:8ede47d38d10	781	/* Set the Rx Fido threshold */
phungductung	0:8ede47d38d10	782	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
phungductung	0:8ede47d38d10	783	{
phungductung	0:8ede47d38d10	784	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:8ede47d38d10	785	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	786	}
phungductung	0:8ede47d38d10	787	else
phungductung	0:8ede47d38d10	788	{
phungductung	0:8ede47d38d10	789	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:8ede47d38d10	790	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	791	}
phungductung	0:8ede47d38d10	792
phungductung	0:8ede47d38d10	793	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	794	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	795	{
phungductung	0:8ede47d38d10	796	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	797	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	798	}
phungductung	0:8ede47d38d10	799
phungductung	0:8ede47d38d10	800	/* Transmit and Receive data in 16 Bit mode */
phungductung	0:8ede47d38d10	801	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	802	{
phungductung	0:8ede47d38d10	803	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
phungductung	0:8ede47d38d10	804	{
phungductung	0:8ede47d38d10	805	/* Check TXE flag */
phungductung	0:8ede47d38d10	806	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
phungductung	0:8ede47d38d10	807	{
phungductung	0:8ede47d38d10	808	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	809	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	810	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	811
phungductung	0:8ede47d38d10	812	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	813	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:8ede47d38d10	814	{
phungductung	0:8ede47d38d10	815	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
phungductung	0:8ede47d38d10	816	}
phungductung	0:8ede47d38d10	817	}
phungductung	0:8ede47d38d10	818
phungductung	0:8ede47d38d10	819	/* Check RXNE flag */
phungductung	0:8ede47d38d10	820	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
phungductung	0:8ede47d38d10	821	{
phungductung	0:8ede47d38d10	822	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	823	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	824	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	825	}
phungductung	0:8ede47d38d10	826	if(Timeout != HAL_MAX_DELAY)
phungductung	0:8ede47d38d10	827	{
phungductung	0:8ede47d38d10	828	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
phungductung	0:8ede47d38d10	829	{
phungductung	0:8ede47d38d10	830	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	831	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	832	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	833	}
phungductung	0:8ede47d38d10	834	}
phungductung	0:8ede47d38d10	835	}
phungductung	0:8ede47d38d10	836	}
phungductung	0:8ede47d38d10	837	/* Transmit and Receive data in 8 Bit mode */
phungductung	0:8ede47d38d10	838	else
phungductung	0:8ede47d38d10	839	{
phungductung	0:8ede47d38d10	840	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
phungductung	0:8ede47d38d10	841	{
phungductung	0:8ede47d38d10	842	/* check TXE flag */
phungductung	0:8ede47d38d10	843	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
phungductung	0:8ede47d38d10	844	{
phungductung	0:8ede47d38d10	845	if(hspi->TxXferCount > 1)
phungductung	0:8ede47d38d10	846	{
phungductung	0:8ede47d38d10	847	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	848	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	849	hspi->TxXferCount -= 2;
phungductung	0:8ede47d38d10	850	}
phungductung	0:8ede47d38d10	851	else
phungductung	0:8ede47d38d10	852	{
phungductung	0:8ede47d38d10	853	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
phungductung	0:8ede47d38d10	854	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	855	}
phungductung	0:8ede47d38d10	856
phungductung	0:8ede47d38d10	857	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	858	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:8ede47d38d10	859	{
phungductung	0:8ede47d38d10	860	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
phungductung	0:8ede47d38d10	861	}
phungductung	0:8ede47d38d10	862	}
phungductung	0:8ede47d38d10	863
phungductung	0:8ede47d38d10	864	/* Wait until RXNE flag is reset */
phungductung	0:8ede47d38d10	865	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
phungductung	0:8ede47d38d10	866	{
phungductung	0:8ede47d38d10	867	if(hspi->RxXferCount > 1)
phungductung	0:8ede47d38d10	868	{
phungductung	0:8ede47d38d10	869	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	870	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	871	hspi->RxXferCount -= 2;
phungductung	0:8ede47d38d10	872	if(hspi->RxXferCount <= 1)
phungductung	0:8ede47d38d10	873	{
phungductung	0:8ede47d38d10	874	/* set fiforxthreshold before to switch on 8 bit data size */
phungductung	0:8ede47d38d10	875	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	876	}
phungductung	0:8ede47d38d10	877	}
phungductung	0:8ede47d38d10	878	else
phungductung	0:8ede47d38d10	879	{
phungductung	0:8ede47d38d10	880	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
phungductung	0:8ede47d38d10	881	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	882	}
phungductung	0:8ede47d38d10	883	}
phungductung	0:8ede47d38d10	884	if(Timeout != HAL_MAX_DELAY)
phungductung	0:8ede47d38d10	885	{
phungductung	0:8ede47d38d10	886	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
phungductung	0:8ede47d38d10	887	{
phungductung	0:8ede47d38d10	888	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	889	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	890	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	891	}
phungductung	0:8ede47d38d10	892	}
phungductung	0:8ede47d38d10	893	}
phungductung	0:8ede47d38d10	894	}
phungductung	0:8ede47d38d10	895
phungductung	0:8ede47d38d10	896	/* Read CRC from DR to close CRC calculation process */
phungductung	0:8ede47d38d10	897	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	898	{
phungductung	0:8ede47d38d10	899	/* Wait until TXE flag */
phungductung	0:8ede47d38d10	900	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	901	{
phungductung	0:8ede47d38d10	902	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	903	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	904	}
phungductung	0:8ede47d38d10	905
phungductung	0:8ede47d38d10	906	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
phungductung	0:8ede47d38d10	907	{
phungductung	0:8ede47d38d10	908	tmpreg = hspi->Instance->DR;
phungductung	0:8ede47d38d10	909	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	910	}
phungductung	0:8ede47d38d10	911	else
phungductung	0:8ede47d38d10	912	{
phungductung	0:8ede47d38d10	913	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	914	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	915
phungductung	0:8ede47d38d10	916	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
phungductung	0:8ede47d38d10	917	{
phungductung	0:8ede47d38d10	918	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	919	{
phungductung	0:8ede47d38d10	920	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	921	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	922	}
phungductung	0:8ede47d38d10	923	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	924	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	925	}
phungductung	0:8ede47d38d10	926	}
phungductung	0:8ede47d38d10	927	}
phungductung	0:8ede47d38d10	928
phungductung	0:8ede47d38d10	929	/* Check the end of the transaction */
phungductung	0:8ede47d38d10	930	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	931	{
phungductung	0:8ede47d38d10	932	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	933	}
phungductung	0:8ede47d38d10	934
phungductung	0:8ede47d38d10	935	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	936
phungductung	0:8ede47d38d10	937	/* Check if CRC error occurred */
phungductung	0:8ede47d38d10	938	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:8ede47d38d10	939	{
phungductung	0:8ede47d38d10	940	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	941	/* Clear CRC Flag */
phungductung	0:8ede47d38d10	942	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:8ede47d38d10	943
phungductung	0:8ede47d38d10	944	/* Process Unlocked */
phungductung	0:8ede47d38d10	945	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	946
phungductung	0:8ede47d38d10	947	return HAL_ERROR;
phungductung	0:8ede47d38d10	948	}
phungductung	0:8ede47d38d10	949
phungductung	0:8ede47d38d10	950	/* Process Unlocked */
phungductung	0:8ede47d38d10	951	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	952
phungductung	0:8ede47d38d10	953	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	954	{
phungductung	0:8ede47d38d10	955	return HAL_ERROR;
phungductung	0:8ede47d38d10	956	}
phungductung	0:8ede47d38d10	957	else
phungductung	0:8ede47d38d10	958	{
phungductung	0:8ede47d38d10	959	return HAL_OK;
phungductung	0:8ede47d38d10	960	}
phungductung	0:8ede47d38d10	961	}
phungductung	0:8ede47d38d10	962
phungductung	0:8ede47d38d10	963	/**
phungductung	0:8ede47d38d10	964	* @brief Transmit an amount of data in no-blocking mode with Interrupt
phungductung	0:8ede47d38d10	965	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	966	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	967	* @param pData: pointer to data buffer
phungductung	0:8ede47d38d10	968	* @param Size: amount of data to be sent
phungductung	0:8ede47d38d10	969	* @retval HAL status
phungductung	0:8ede47d38d10	970	*/
phungductung	0:8ede47d38d10	971	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:8ede47d38d10	972	{
phungductung	0:8ede47d38d10	973	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
phungductung	0:8ede47d38d10	974
phungductung	0:8ede47d38d10	975	if(hspi->State == HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	976	{
phungductung	0:8ede47d38d10	977	if((pData == NULL) \|\| (Size == 0))
phungductung	0:8ede47d38d10	978	{
phungductung	0:8ede47d38d10	979	return HAL_ERROR;
phungductung	0:8ede47d38d10	980	}
phungductung	0:8ede47d38d10	981
phungductung	0:8ede47d38d10	982	/* Process Locked */
phungductung	0:8ede47d38d10	983	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	984
phungductung	0:8ede47d38d10	985	hspi->State = HAL_SPI_STATE_BUSY_TX;
phungductung	0:8ede47d38d10	986	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	987	hspi->pTxBuffPtr = pData;
phungductung	0:8ede47d38d10	988	hspi->TxXferSize = Size;
phungductung	0:8ede47d38d10	989	hspi->TxXferCount = Size;
phungductung	0:8ede47d38d10	990	hspi->pRxBuffPtr = NULL;
phungductung	0:8ede47d38d10	991	hspi->RxXferSize = 0;
phungductung	0:8ede47d38d10	992	hspi->RxXferCount = 0;
phungductung	0:8ede47d38d10	993
phungductung	0:8ede47d38d10	994	/* Set the function for IT treatement */
phungductung	0:8ede47d38d10	995	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
phungductung	0:8ede47d38d10	996	{
phungductung	0:8ede47d38d10	997	hspi->RxISR = NULL;
phungductung	0:8ede47d38d10	998	hspi->TxISR = SPI_TxISR_16BIT;
phungductung	0:8ede47d38d10	999	}
phungductung	0:8ede47d38d10	1000	else
phungductung	0:8ede47d38d10	1001	{
phungductung	0:8ede47d38d10	1002	hspi->RxISR = NULL;
phungductung	0:8ede47d38d10	1003	hspi->TxISR = SPI_TxISR_8BIT;
phungductung	0:8ede47d38d10	1004	}
phungductung	0:8ede47d38d10	1005
phungductung	0:8ede47d38d10	1006	/* Configure communication direction : 1Line */
phungductung	0:8ede47d38d10	1007	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:8ede47d38d10	1008	{
phungductung	0:8ede47d38d10	1009	SPI_1LINE_TX(hspi);
phungductung	0:8ede47d38d10	1010	}
phungductung	0:8ede47d38d10	1011
phungductung	0:8ede47d38d10	1012	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	1013	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1014	{
phungductung	0:8ede47d38d10	1015	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	1016	}
phungductung	0:8ede47d38d10	1017
phungductung	0:8ede47d38d10	1018	/* Enable TXE and ERR interrupt */
phungductung	0:8ede47d38d10	1019	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
phungductung	0:8ede47d38d10	1020
phungductung	0:8ede47d38d10	1021	/* Process Unlocked */
phungductung	0:8ede47d38d10	1022	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1023
phungductung	0:8ede47d38d10	1024	/* Note : The SPI must be enabled after unlocking current process
phungductung	0:8ede47d38d10	1025	to avoid the risk of SPI interrupt handle execution before current
phungductung	0:8ede47d38d10	1026	process unlock */
phungductung	0:8ede47d38d10	1027
phungductung	0:8ede47d38d10	1028	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	1030	{
phungductung	0:8ede47d38d10	1031	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	1032	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	1033	}
phungductung	0:8ede47d38d10	1034
phungductung	0:8ede47d38d10	1035	return HAL_OK;
phungductung	0:8ede47d38d10	1036	}
phungductung	0:8ede47d38d10	1037	else
phungductung	0:8ede47d38d10	1038	{
phungductung	0:8ede47d38d10	1039	return HAL_BUSY;
phungductung	0:8ede47d38d10	1040	}
phungductung	0:8ede47d38d10	1041	}
phungductung	0:8ede47d38d10	1042
phungductung	0:8ede47d38d10	1043	/**
phungductung	0:8ede47d38d10	1044	* @brief Receive an amount of data in no-blocking mode with Interrupt
phungductung	0:8ede47d38d10	1045	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1046	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1047	* @param pData: pointer to data buffer
phungductung	0:8ede47d38d10	1048	* @param Size: amount of data to be sent
phungductung	0:8ede47d38d10	1049	* @retval HAL status
phungductung	0:8ede47d38d10	1050	*/
phungductung	0:8ede47d38d10	1051	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:8ede47d38d10	1052	{
phungductung	0:8ede47d38d10	1053	if(hspi->State == HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	1054	{
phungductung	0:8ede47d38d10	1055	if((pData == NULL) \|\| (Size == 0))
phungductung	0:8ede47d38d10	1056	{
phungductung	0:8ede47d38d10	1057	return HAL_ERROR;
phungductung	0:8ede47d38d10	1058	}
phungductung	0:8ede47d38d10	1059
phungductung	0:8ede47d38d10	1060	/* Process Locked */
phungductung	0:8ede47d38d10	1061	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1062
phungductung	0:8ede47d38d10	1063	/* Configure communication */
phungductung	0:8ede47d38d10	1064	hspi->State = HAL_SPI_STATE_BUSY_RX;
phungductung	0:8ede47d38d10	1065	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	1066	hspi->pRxBuffPtr = pData;
phungductung	0:8ede47d38d10	1067	hspi->RxXferSize = Size;
phungductung	0:8ede47d38d10	1068	hspi->RxXferCount = Size;
phungductung	0:8ede47d38d10	1069	hspi->pTxBuffPtr = NULL;
phungductung	0:8ede47d38d10	1070	hspi->TxXferSize = 0;
phungductung	0:8ede47d38d10	1071	hspi->TxXferCount = 0;
phungductung	0:8ede47d38d10	1072
phungductung	0:8ede47d38d10	1073	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
phungductung	0:8ede47d38d10	1074	{
phungductung	0:8ede47d38d10	1075	/* Process Unlocked */
phungductung	0:8ede47d38d10	1076	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1077	/* the receive process is not supported in 2Lines direction master mode */
phungductung	0:8ede47d38d10	1078	/* in this we call the transmitReceive process */
phungductung	0:8ede47d38d10	1079	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
phungductung	0:8ede47d38d10	1080	}
phungductung	0:8ede47d38d10	1081
phungductung	0:8ede47d38d10	1082	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1083	{
phungductung	0:8ede47d38d10	1084	hspi->CRCSize = 1;
phungductung	0:8ede47d38d10	1085	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
phungductung	0:8ede47d38d10	1086	{
phungductung	0:8ede47d38d10	1087	hspi->CRCSize = 2;
phungductung	0:8ede47d38d10	1088	}
phungductung	0:8ede47d38d10	1089	}
phungductung	0:8ede47d38d10	1090	else
phungductung	0:8ede47d38d10	1091	{
phungductung	0:8ede47d38d10	1092	hspi->CRCSize = 0;
phungductung	0:8ede47d38d10	1093	}
phungductung	0:8ede47d38d10	1094
phungductung	0:8ede47d38d10	1095	/* check the data size to adapt Rx threshold and the set the function for IT treatment */
phungductung	0:8ede47d38d10	1096	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
phungductung	0:8ede47d38d10	1097	{
phungductung	0:8ede47d38d10	1098	/* set fiforxthreshold according the reception data length: 16 bit */
phungductung	0:8ede47d38d10	1099	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1100	hspi->RxISR = SPI_RxISR_16BIT;
phungductung	0:8ede47d38d10	1101	hspi->TxISR = NULL;
phungductung	0:8ede47d38d10	1102	}
phungductung	0:8ede47d38d10	1103	else
phungductung	0:8ede47d38d10	1104	{
phungductung	0:8ede47d38d10	1105	/* set fiforxthreshold according the reception data length: 8 bit */
phungductung	0:8ede47d38d10	1106	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1107	hspi->RxISR = SPI_RxISR_8BIT;
phungductung	0:8ede47d38d10	1108	hspi->TxISR = NULL;
phungductung	0:8ede47d38d10	1109	}
phungductung	0:8ede47d38d10	1110
phungductung	0:8ede47d38d10	1111	/* Configure communication direction : 1Line */
phungductung	0:8ede47d38d10	1112	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:8ede47d38d10	1113	{
phungductung	0:8ede47d38d10	1114	SPI_1LINE_RX(hspi);
phungductung	0:8ede47d38d10	1115	}
phungductung	0:8ede47d38d10	1116
phungductung	0:8ede47d38d10	1117	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	1118	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1119	{
phungductung	0:8ede47d38d10	1120	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	1121	}
phungductung	0:8ede47d38d10	1122
phungductung	0:8ede47d38d10	1123	/* Enable TXE and ERR interrupt */
phungductung	0:8ede47d38d10	1124	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	1125
phungductung	0:8ede47d38d10	1126	/* Process Unlocked */
phungductung	0:8ede47d38d10	1127	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1128
phungductung	0:8ede47d38d10	1129	/* Note : The SPI must be enabled after unlocking current process
phungductung	0:8ede47d38d10	1130	to avoid the risk of SPI interrupt handle execution before current
phungductung	0:8ede47d38d10	1131	process unlock */
phungductung	0:8ede47d38d10	1132
phungductung	0:8ede47d38d10	1133	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	1134	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	1135	{
phungductung	0:8ede47d38d10	1136	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	1137	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	1138	}
phungductung	0:8ede47d38d10	1139
phungductung	0:8ede47d38d10	1140	return HAL_OK;
phungductung	0:8ede47d38d10	1141	}
phungductung	0:8ede47d38d10	1142	else
phungductung	0:8ede47d38d10	1143	{
phungductung	0:8ede47d38d10	1144	return HAL_BUSY;
phungductung	0:8ede47d38d10	1145	}
phungductung	0:8ede47d38d10	1146	}
phungductung	0:8ede47d38d10	1147
phungductung	0:8ede47d38d10	1148	/**
phungductung	0:8ede47d38d10	1149	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
phungductung	0:8ede47d38d10	1150	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1151	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1152	* @param pTxData: pointer to transmission data buffer
phungductung	0:8ede47d38d10	1153	* @param pRxData: pointer to reception data buffer
phungductung	0:8ede47d38d10	1154	* @param Size: amount of data to be sent and received
phungductung	0:8ede47d38d10	1155	* @retval HAL status
phungductung	0:8ede47d38d10	1156	*/
phungductung	0:8ede47d38d10	1157	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
phungductung	0:8ede47d38d10	1158	{
phungductung	0:8ede47d38d10	1159	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
phungductung	0:8ede47d38d10	1160
phungductung	0:8ede47d38d10	1161	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
phungductung	0:8ede47d38d10	1162	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
phungductung	0:8ede47d38d10	1163	{
phungductung	0:8ede47d38d10	1164	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
phungductung	0:8ede47d38d10	1165	{
phungductung	0:8ede47d38d10	1166	return HAL_ERROR;
phungductung	0:8ede47d38d10	1167	}
phungductung	0:8ede47d38d10	1168
phungductung	0:8ede47d38d10	1169	/* Process locked */
phungductung	0:8ede47d38d10	1170	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1171
phungductung	0:8ede47d38d10	1172	hspi->CRCSize = 0;
phungductung	0:8ede47d38d10	1173	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1174	{
phungductung	0:8ede47d38d10	1175	hspi->CRCSize = 1;
phungductung	0:8ede47d38d10	1176	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
phungductung	0:8ede47d38d10	1177	{
phungductung	0:8ede47d38d10	1178	hspi->CRCSize = 2;
phungductung	0:8ede47d38d10	1179	}
phungductung	0:8ede47d38d10	1180	}
phungductung	0:8ede47d38d10	1181
phungductung	0:8ede47d38d10	1182	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
phungductung	0:8ede47d38d10	1183	{
phungductung	0:8ede47d38d10	1184	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
phungductung	0:8ede47d38d10	1185	}
phungductung	0:8ede47d38d10	1186
phungductung	0:8ede47d38d10	1187	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	1188	hspi->pTxBuffPtr = pTxData;
phungductung	0:8ede47d38d10	1189	hspi->TxXferSize = Size;
phungductung	0:8ede47d38d10	1190	hspi->TxXferCount = Size;
phungductung	0:8ede47d38d10	1191	hspi->pRxBuffPtr = pRxData;
phungductung	0:8ede47d38d10	1192	hspi->RxXferSize = Size;
phungductung	0:8ede47d38d10	1193	hspi->RxXferCount = Size;
phungductung	0:8ede47d38d10	1194
phungductung	0:8ede47d38d10	1195	/* Set the function for IT treatement */
phungductung	0:8ede47d38d10	1196	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
phungductung	0:8ede47d38d10	1197	{
phungductung	0:8ede47d38d10	1198	hspi->RxISR = SPI_2linesRxISR_16BIT;
phungductung	0:8ede47d38d10	1199	hspi->TxISR = SPI_2linesTxISR_16BIT;
phungductung	0:8ede47d38d10	1200	}
phungductung	0:8ede47d38d10	1201	else
phungductung	0:8ede47d38d10	1202	{
phungductung	0:8ede47d38d10	1203	hspi->RxISR = SPI_2linesRxISR_8BIT;
phungductung	0:8ede47d38d10	1204	hspi->TxISR = SPI_2linesTxISR_8BIT;
phungductung	0:8ede47d38d10	1205	}
phungductung	0:8ede47d38d10	1206
phungductung	0:8ede47d38d10	1207	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	1208	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1209	{
phungductung	0:8ede47d38d10	1210	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	1211	}
phungductung	0:8ede47d38d10	1212
phungductung	0:8ede47d38d10	1213	/* check if packing mode is enabled and if there is more than 2 data to receive */
phungductung	0:8ede47d38d10	1214	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
phungductung	0:8ede47d38d10	1215	{
phungductung	0:8ede47d38d10	1216	/* set fiforxthreshold according the reception data length: 16 bit */
phungductung	0:8ede47d38d10	1217	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1218	}
phungductung	0:8ede47d38d10	1219	else
phungductung	0:8ede47d38d10	1220	{
phungductung	0:8ede47d38d10	1221	/* set fiforxthreshold according the reception data length: 8 bit */
phungductung	0:8ede47d38d10	1222	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1223	}
phungductung	0:8ede47d38d10	1224
phungductung	0:8ede47d38d10	1225	/* Enable TXE, RXNE and ERR interrupt */
phungductung	0:8ede47d38d10	1226	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	1227
phungductung	0:8ede47d38d10	1228	/* Process Unlocked */
phungductung	0:8ede47d38d10	1229	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1230
phungductung	0:8ede47d38d10	1231	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	1232	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	1233	{
phungductung	0:8ede47d38d10	1234	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	1235	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	1236	}
phungductung	0:8ede47d38d10	1237
phungductung	0:8ede47d38d10	1238	return HAL_OK;
phungductung	0:8ede47d38d10	1239	}
phungductung	0:8ede47d38d10	1240	else
phungductung	0:8ede47d38d10	1241	{
phungductung	0:8ede47d38d10	1242	return HAL_BUSY;
phungductung	0:8ede47d38d10	1243	}
phungductung	0:8ede47d38d10	1244	}
phungductung	0:8ede47d38d10	1245
phungductung	0:8ede47d38d10	1246	/**
phungductung	0:8ede47d38d10	1247	* @brief Transmit an amount of data in no-blocking mode with DMA
phungductung	0:8ede47d38d10	1248	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1249	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1250	* @param pData: pointer to data buffer
phungductung	0:8ede47d38d10	1251	* @param Size: amount of data to be sent
phungductung	0:8ede47d38d10	1252	* @retval HAL status
phungductung	0:8ede47d38d10	1253	*/
phungductung	0:8ede47d38d10	1254	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:8ede47d38d10	1255	{
phungductung	0:8ede47d38d10	1256	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
phungductung	0:8ede47d38d10	1257
phungductung	0:8ede47d38d10	1258	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	1259	{
phungductung	0:8ede47d38d10	1260	return HAL_BUSY;
phungductung	0:8ede47d38d10	1261	}
phungductung	0:8ede47d38d10	1262
phungductung	0:8ede47d38d10	1263	if((pData == NULL) \|\| (Size == 0))
phungductung	0:8ede47d38d10	1264	{
phungductung	0:8ede47d38d10	1265	return HAL_ERROR;
phungductung	0:8ede47d38d10	1266	}
phungductung	0:8ede47d38d10	1267
phungductung	0:8ede47d38d10	1268	/* Process Locked */
phungductung	0:8ede47d38d10	1269	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1270
phungductung	0:8ede47d38d10	1271	hspi->State = HAL_SPI_STATE_BUSY_TX;
phungductung	0:8ede47d38d10	1272	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	1273	hspi->pTxBuffPtr = pData;
phungductung	0:8ede47d38d10	1274	hspi->TxXferSize = Size;
phungductung	0:8ede47d38d10	1275	hspi->TxXferCount = Size;
phungductung	0:8ede47d38d10	1276	hspi->pRxBuffPtr = (uint8_t *)NULL;
phungductung	0:8ede47d38d10	1277	hspi->RxXferSize = 0;
phungductung	0:8ede47d38d10	1278	hspi->RxXferCount = 0;
phungductung	0:8ede47d38d10	1279
phungductung	0:8ede47d38d10	1280	/* Configure communication direction : 1Line */
phungductung	0:8ede47d38d10	1281	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:8ede47d38d10	1282	{
phungductung	0:8ede47d38d10	1283	SPI_1LINE_TX(hspi);
phungductung	0:8ede47d38d10	1284	}
phungductung	0:8ede47d38d10	1285
phungductung	0:8ede47d38d10	1286	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	1287	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1288	{
phungductung	0:8ede47d38d10	1289	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	1290	}
phungductung	0:8ede47d38d10	1291
phungductung	0:8ede47d38d10	1292	/* Set the SPI TxDMA Half transfer complete callback */
phungductung	0:8ede47d38d10	1293	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
phungductung	0:8ede47d38d10	1294
phungductung	0:8ede47d38d10	1295	/* Set the SPI TxDMA transfer complete callback */
phungductung	0:8ede47d38d10	1296	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
phungductung	0:8ede47d38d10	1297
phungductung	0:8ede47d38d10	1298	/* Set the DMA error callback */
phungductung	0:8ede47d38d10	1299	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
phungductung	0:8ede47d38d10	1300
phungductung	0:8ede47d38d10	1301	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:8ede47d38d10	1302	/* packing mode is enabled only if the DMA setting is HALWORD */
phungductung	0:8ede47d38d10	1303	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
phungductung	0:8ede47d38d10	1304	{
phungductung	0:8ede47d38d10	1305	/* Check the even/odd of the data size + crc if enabled */
phungductung	0:8ede47d38d10	1306	if((hspi->TxXferCount & 0x1) == 0)
phungductung	0:8ede47d38d10	1307	{
phungductung	0:8ede47d38d10	1308	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:8ede47d38d10	1309	hspi->TxXferCount = (hspi->TxXferCount >> 1);
phungductung	0:8ede47d38d10	1310	}
phungductung	0:8ede47d38d10	1311	else
phungductung	0:8ede47d38d10	1312	{
phungductung	0:8ede47d38d10	1313	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:8ede47d38d10	1314	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
phungductung	0:8ede47d38d10	1315	}
phungductung	0:8ede47d38d10	1316	}
phungductung	0:8ede47d38d10	1317
phungductung	0:8ede47d38d10	1318	/* Enable the Tx DMA channel */
phungductung	0:8ede47d38d10	1319	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
phungductung	0:8ede47d38d10	1320
phungductung	0:8ede47d38d10	1321	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	1322	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	1323	{
phungductung	0:8ede47d38d10	1324	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	1325	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	1326	}
phungductung	0:8ede47d38d10	1327
phungductung	0:8ede47d38d10	1328	/* Enable Tx DMA Request */
phungductung	0:8ede47d38d10	1329	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
phungductung	0:8ede47d38d10	1330
phungductung	0:8ede47d38d10	1331	/* Process Unlocked */
phungductung	0:8ede47d38d10	1332	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1333
phungductung	0:8ede47d38d10	1334	return HAL_OK;
phungductung	0:8ede47d38d10	1335	}
phungductung	0:8ede47d38d10	1336
phungductung	0:8ede47d38d10	1337	/**
phungductung	0:8ede47d38d10	1338	* @brief Receive an amount of data in no-blocking mode with DMA
phungductung	0:8ede47d38d10	1339	* @param hspi: SPI handle
phungductung	0:8ede47d38d10	1340	* @param pData: pointer to data buffer
phungductung	0:8ede47d38d10	1341	* @param Size: amount of data to be sent
phungductung	0:8ede47d38d10	1342	* @retval HAL status
phungductung	0:8ede47d38d10	1343	*/
phungductung	0:8ede47d38d10	1344	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
phungductung	0:8ede47d38d10	1345	{
phungductung	0:8ede47d38d10	1346	if(hspi->State != HAL_SPI_STATE_READY)
phungductung	0:8ede47d38d10	1347	{
phungductung	0:8ede47d38d10	1348	return HAL_BUSY;
phungductung	0:8ede47d38d10	1349	}
phungductung	0:8ede47d38d10	1350
phungductung	0:8ede47d38d10	1351	if((pData == NULL) \|\| (Size == 0))
phungductung	0:8ede47d38d10	1352	{
phungductung	0:8ede47d38d10	1353	return HAL_ERROR;
phungductung	0:8ede47d38d10	1354	}
phungductung	0:8ede47d38d10	1355
phungductung	0:8ede47d38d10	1356	/* Process Locked */
phungductung	0:8ede47d38d10	1357	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1358
phungductung	0:8ede47d38d10	1359	hspi->State = HAL_SPI_STATE_BUSY_RX;
phungductung	0:8ede47d38d10	1360	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	1361	hspi->pRxBuffPtr = pData;
phungductung	0:8ede47d38d10	1362	hspi->RxXferSize = Size;
phungductung	0:8ede47d38d10	1363	hspi->RxXferCount = Size;
phungductung	0:8ede47d38d10	1364	hspi->pTxBuffPtr = (uint8_t *)NULL;
phungductung	0:8ede47d38d10	1365	hspi->TxXferSize = 0;
phungductung	0:8ede47d38d10	1366	hspi->TxXferCount = 0;
phungductung	0:8ede47d38d10	1367
phungductung	0:8ede47d38d10	1368	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
phungductung	0:8ede47d38d10	1369	{
phungductung	0:8ede47d38d10	1370	/* Process Unlocked */
phungductung	0:8ede47d38d10	1371	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1372	/* the receive process is not supported in 2Lines direction master mode */
phungductung	0:8ede47d38d10	1373	/* in this case we call the transmitReceive process */
phungductung	0:8ede47d38d10	1374	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
phungductung	0:8ede47d38d10	1375	}
phungductung	0:8ede47d38d10	1376
phungductung	0:8ede47d38d10	1377	/* Configure communication direction : 1Line */
phungductung	0:8ede47d38d10	1378	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
phungductung	0:8ede47d38d10	1379	{
phungductung	0:8ede47d38d10	1380	SPI_1LINE_RX(hspi);
phungductung	0:8ede47d38d10	1381	}
phungductung	0:8ede47d38d10	1382
phungductung	0:8ede47d38d10	1383	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	1384	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1385	{
phungductung	0:8ede47d38d10	1386	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	1387	}
phungductung	0:8ede47d38d10	1388
phungductung	0:8ede47d38d10	1389	/* packing mode management is enabled by the DMA settings */
phungductung	0:8ede47d38d10	1390	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
phungductung	0:8ede47d38d10	1391	{
phungductung	0:8ede47d38d10	1392	/* Process Locked */
phungductung	0:8ede47d38d10	1393	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1394	/* Restriction the DMA data received is not allowed in this mode */
phungductung	0:8ede47d38d10	1395	return HAL_ERROR;
phungductung	0:8ede47d38d10	1396	}
phungductung	0:8ede47d38d10	1397
phungductung	0:8ede47d38d10	1398	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:8ede47d38d10	1399	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	1400	{
phungductung	0:8ede47d38d10	1401	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:8ede47d38d10	1402	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1403	}
phungductung	0:8ede47d38d10	1404	else
phungductung	0:8ede47d38d10	1405	{
phungductung	0:8ede47d38d10	1406	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:8ede47d38d10	1407	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1408	}
phungductung	0:8ede47d38d10	1409
phungductung	0:8ede47d38d10	1410	/* Set the SPI RxDMA Half transfer complete callback */
phungductung	0:8ede47d38d10	1411	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
phungductung	0:8ede47d38d10	1412
phungductung	0:8ede47d38d10	1413	/* Set the SPI Rx DMA transfer complete callback */
phungductung	0:8ede47d38d10	1414	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
phungductung	0:8ede47d38d10	1415
phungductung	0:8ede47d38d10	1416	/* Set the DMA error callback */
phungductung	0:8ede47d38d10	1417	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
phungductung	0:8ede47d38d10	1418
phungductung	0:8ede47d38d10	1419	/* Enable Rx DMA Request */
phungductung	0:8ede47d38d10	1420	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
phungductung	0:8ede47d38d10	1421
phungductung	0:8ede47d38d10	1422	/* Enable the Rx DMA channel */
phungductung	0:8ede47d38d10	1423	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
phungductung	0:8ede47d38d10	1424
phungductung	0:8ede47d38d10	1425	/* Process Unlocked */
phungductung	0:8ede47d38d10	1426	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1427
phungductung	0:8ede47d38d10	1428	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	1429	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	1430	{
phungductung	0:8ede47d38d10	1431	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	1432	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	1433	}
phungductung	0:8ede47d38d10	1434
phungductung	0:8ede47d38d10	1435	return HAL_OK;
phungductung	0:8ede47d38d10	1436	}
phungductung	0:8ede47d38d10	1437
phungductung	0:8ede47d38d10	1438	/**
phungductung	0:8ede47d38d10	1439	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
phungductung	0:8ede47d38d10	1440	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1441	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1442	* @param pTxData: pointer to transmission data buffer
phungductung	0:8ede47d38d10	1443	* @param pRxData: pointer to reception data buffer
phungductung	0:8ede47d38d10	1444	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
phungductung	0:8ede47d38d10	1445	* @param Size: amount of data to be sent
phungductung	0:8ede47d38d10	1446	* @retval HAL status
phungductung	0:8ede47d38d10	1447	*/
phungductung	0:8ede47d38d10	1448	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
phungductung	0:8ede47d38d10	1449	{
phungductung	0:8ede47d38d10	1450	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
phungductung	0:8ede47d38d10	1451
phungductung	0:8ede47d38d10	1452	if((hspi->State == HAL_SPI_STATE_READY) \|\|
phungductung	0:8ede47d38d10	1453	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
phungductung	0:8ede47d38d10	1454	{
phungductung	0:8ede47d38d10	1455	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
phungductung	0:8ede47d38d10	1456	{
phungductung	0:8ede47d38d10	1457	return HAL_ERROR;
phungductung	0:8ede47d38d10	1458	}
phungductung	0:8ede47d38d10	1459
phungductung	0:8ede47d38d10	1460	/* Process locked */
phungductung	0:8ede47d38d10	1461	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1462
phungductung	0:8ede47d38d10	1463	/* check if the transmit Receive function is not called by a receive master */
phungductung	0:8ede47d38d10	1464	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
phungductung	0:8ede47d38d10	1465	{
phungductung	0:8ede47d38d10	1466	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
phungductung	0:8ede47d38d10	1467	}
phungductung	0:8ede47d38d10	1468
phungductung	0:8ede47d38d10	1469	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
phungductung	0:8ede47d38d10	1470	hspi->pTxBuffPtr = (uint8_t *)pTxData;
phungductung	0:8ede47d38d10	1471	hspi->TxXferSize = Size;
phungductung	0:8ede47d38d10	1472	hspi->TxXferCount = Size;
phungductung	0:8ede47d38d10	1473	hspi->pRxBuffPtr = (uint8_t *)pRxData;
phungductung	0:8ede47d38d10	1474	hspi->RxXferSize = Size;
phungductung	0:8ede47d38d10	1475	hspi->RxXferCount = Size;
phungductung	0:8ede47d38d10	1476
phungductung	0:8ede47d38d10	1477	/* Reset CRC Calculation + increase the rxsize */
phungductung	0:8ede47d38d10	1478	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1479	{
phungductung	0:8ede47d38d10	1480	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	1481	}
phungductung	0:8ede47d38d10	1482
phungductung	0:8ede47d38d10	1483	/* Reset the threshold bit */
phungductung	0:8ede47d38d10	1484	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:8ede47d38d10	1485	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:8ede47d38d10	1486
phungductung	0:8ede47d38d10	1487	/* the packing mode management is enabled by the DMA settings according the spi data size */
phungductung	0:8ede47d38d10	1488	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	1489	{
phungductung	0:8ede47d38d10	1490	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:8ede47d38d10	1491	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1492	}
phungductung	0:8ede47d38d10	1493	else
phungductung	0:8ede47d38d10	1494	{
phungductung	0:8ede47d38d10	1495	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:8ede47d38d10	1496	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1497
phungductung	0:8ede47d38d10	1498	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
phungductung	0:8ede47d38d10	1499	{
phungductung	0:8ede47d38d10	1500	if((hspi->TxXferSize & 0x1) == 0x0 )
phungductung	0:8ede47d38d10	1501	{
phungductung	0:8ede47d38d10	1502	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:8ede47d38d10	1503	hspi->TxXferCount = hspi->TxXferCount >> 1;
phungductung	0:8ede47d38d10	1504	}
phungductung	0:8ede47d38d10	1505	else
phungductung	0:8ede47d38d10	1506	{
phungductung	0:8ede47d38d10	1507	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
phungductung	0:8ede47d38d10	1508	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
phungductung	0:8ede47d38d10	1509	}
phungductung	0:8ede47d38d10	1510	}
phungductung	0:8ede47d38d10	1511
phungductung	0:8ede47d38d10	1512	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
phungductung	0:8ede47d38d10	1513	{
phungductung	0:8ede47d38d10	1514	/* set fiforxthreshold according the reception data length: 16bit */
phungductung	0:8ede47d38d10	1515	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	1516
phungductung	0:8ede47d38d10	1517	/* Size must include the CRC length */
phungductung	0:8ede47d38d10	1518	if((hspi->RxXferCount & 0x1) == 0x0 )
phungductung	0:8ede47d38d10	1519	{
phungductung	0:8ede47d38d10	1520	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:8ede47d38d10	1521	hspi->RxXferCount = hspi->RxXferCount >> 1;
phungductung	0:8ede47d38d10	1522	}
phungductung	0:8ede47d38d10	1523	else
phungductung	0:8ede47d38d10	1524	{
phungductung	0:8ede47d38d10	1525	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
phungductung	0:8ede47d38d10	1526	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
phungductung	0:8ede47d38d10	1527	}
phungductung	0:8ede47d38d10	1528	}
phungductung	0:8ede47d38d10	1529	}
phungductung	0:8ede47d38d10	1530
phungductung	0:8ede47d38d10	1531	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
phungductung	0:8ede47d38d10	1532	the reception request (RXNE) */
phungductung	0:8ede47d38d10	1533	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
phungductung	0:8ede47d38d10	1534	{
phungductung	0:8ede47d38d10	1535	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
phungductung	0:8ede47d38d10	1536	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
phungductung	0:8ede47d38d10	1537	}
phungductung	0:8ede47d38d10	1538	else
phungductung	0:8ede47d38d10	1539	{
phungductung	0:8ede47d38d10	1540	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
phungductung	0:8ede47d38d10	1541	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
phungductung	0:8ede47d38d10	1542	}
phungductung	0:8ede47d38d10	1543	/* Set the DMA error callback */
phungductung	0:8ede47d38d10	1544	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
phungductung	0:8ede47d38d10	1545
phungductung	0:8ede47d38d10	1546	/* Enable Rx DMA Request */
phungductung	0:8ede47d38d10	1547	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
phungductung	0:8ede47d38d10	1548
phungductung	0:8ede47d38d10	1549	/* Enable the Rx DMA channel */
phungductung	0:8ede47d38d10	1550	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
phungductung	0:8ede47d38d10	1551
phungductung	0:8ede47d38d10	1552	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
phungductung	0:8ede47d38d10	1553	is performed in DMA reception complete callback */
phungductung	0:8ede47d38d10	1554	hspi->hdmatx->XferHalfCpltCallback = NULL;
phungductung	0:8ede47d38d10	1555	hspi->hdmatx->XferCpltCallback = NULL;
phungductung	0:8ede47d38d10	1556
phungductung	0:8ede47d38d10	1557	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
phungductung	0:8ede47d38d10	1558	{
phungductung	0:8ede47d38d10	1559	/* Set the DMA error callback */
phungductung	0:8ede47d38d10	1560	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
phungductung	0:8ede47d38d10	1561	}
phungductung	0:8ede47d38d10	1562	else
phungductung	0:8ede47d38d10	1563	{
phungductung	0:8ede47d38d10	1564	hspi->hdmatx->XferErrorCallback = NULL;
phungductung	0:8ede47d38d10	1565	}
phungductung	0:8ede47d38d10	1566
phungductung	0:8ede47d38d10	1567	/* Enable the Tx DMA channel */
phungductung	0:8ede47d38d10	1568	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
phungductung	0:8ede47d38d10	1569
phungductung	0:8ede47d38d10	1570	/* Process Unlocked */
phungductung	0:8ede47d38d10	1571	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1572
phungductung	0:8ede47d38d10	1573	/* Check if the SPI is already enabled */
phungductung	0:8ede47d38d10	1574	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
phungductung	0:8ede47d38d10	1575	{
phungductung	0:8ede47d38d10	1576	/* Enable SPI peripheral */
phungductung	0:8ede47d38d10	1577	__HAL_SPI_ENABLE(hspi);
phungductung	0:8ede47d38d10	1578	}
phungductung	0:8ede47d38d10	1579
phungductung	0:8ede47d38d10	1580	/* Enable Tx DMA Request */
phungductung	0:8ede47d38d10	1581	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
phungductung	0:8ede47d38d10	1582
phungductung	0:8ede47d38d10	1583	return HAL_OK;
phungductung	0:8ede47d38d10	1584	}
phungductung	0:8ede47d38d10	1585	else
phungductung	0:8ede47d38d10	1586	{
phungductung	0:8ede47d38d10	1587	return HAL_BUSY;
phungductung	0:8ede47d38d10	1588	}
phungductung	0:8ede47d38d10	1589	}
phungductung	0:8ede47d38d10	1590
phungductung	0:8ede47d38d10	1591	/**
phungductung	0:8ede47d38d10	1592	* @brief Pauses the DMA Transfer.
phungductung	0:8ede47d38d10	1593	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1594	* the configuration information for the specified SPI module.
phungductung	0:8ede47d38d10	1595	* @retval HAL status
phungductung	0:8ede47d38d10	1596	*/
phungductung	0:8ede47d38d10	1597	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1598	{
phungductung	0:8ede47d38d10	1599	/* Process Locked */
phungductung	0:8ede47d38d10	1600	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1601
phungductung	0:8ede47d38d10	1602	/* Disable the SPI DMA Tx & Rx requests */
phungductung	0:8ede47d38d10	1603	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:8ede47d38d10	1604
phungductung	0:8ede47d38d10	1605	/* Process Unlocked */
phungductung	0:8ede47d38d10	1606	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1607
phungductung	0:8ede47d38d10	1608	return HAL_OK;
phungductung	0:8ede47d38d10	1609	}
phungductung	0:8ede47d38d10	1610
phungductung	0:8ede47d38d10	1611	/**
phungductung	0:8ede47d38d10	1612	* @brief Resumes the DMA Transfer.
phungductung	0:8ede47d38d10	1613	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1614	* the configuration information for the specified SPI module.
phungductung	0:8ede47d38d10	1615	* @retval HAL status
phungductung	0:8ede47d38d10	1616	*/
phungductung	0:8ede47d38d10	1617	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1618	{
phungductung	0:8ede47d38d10	1619	/* Process Locked */
phungductung	0:8ede47d38d10	1620	__HAL_LOCK(hspi);
phungductung	0:8ede47d38d10	1621
phungductung	0:8ede47d38d10	1622	/* Enable the SPI DMA Tx & Rx requests */
phungductung	0:8ede47d38d10	1623	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:8ede47d38d10	1624
phungductung	0:8ede47d38d10	1625	/* Process Unlocked */
phungductung	0:8ede47d38d10	1626	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	1627
phungductung	0:8ede47d38d10	1628	return HAL_OK;
phungductung	0:8ede47d38d10	1629	}
phungductung	0:8ede47d38d10	1630
phungductung	0:8ede47d38d10	1631	/**
phungductung	0:8ede47d38d10	1632	* @brief Stops the DMA Transfer.
phungductung	0:8ede47d38d10	1633	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1634	* the configuration information for the specified SPI module.
phungductung	0:8ede47d38d10	1635	* @retval HAL status
phungductung	0:8ede47d38d10	1636	*/
phungductung	0:8ede47d38d10	1637	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1638	{
phungductung	0:8ede47d38d10	1639	/* The Lock is not implemented on this API to allow the user application
phungductung	0:8ede47d38d10	1640	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
phungductung	0:8ede47d38d10	1641	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
phungductung	0:8ede47d38d10	1642	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
phungductung	0:8ede47d38d10	1643	*/
phungductung	0:8ede47d38d10	1644
phungductung	0:8ede47d38d10	1645	/* Abort the SPI DMA tx Stream */
phungductung	0:8ede47d38d10	1646	if(hspi->hdmatx != NULL)
phungductung	0:8ede47d38d10	1647	{
phungductung	0:8ede47d38d10	1648	HAL_DMA_Abort(hspi->hdmatx);
phungductung	0:8ede47d38d10	1649	}
phungductung	0:8ede47d38d10	1650	/* Abort the SPI DMA rx Stream */
phungductung	0:8ede47d38d10	1651	if(hspi->hdmarx != NULL)
phungductung	0:8ede47d38d10	1652	{
phungductung	0:8ede47d38d10	1653	HAL_DMA_Abort(hspi->hdmarx);
phungductung	0:8ede47d38d10	1654	}
phungductung	0:8ede47d38d10	1655
phungductung	0:8ede47d38d10	1656	/* Disable the SPI DMA Tx & Rx requests */
phungductung	0:8ede47d38d10	1657	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:8ede47d38d10	1658	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	1659	return HAL_OK;
phungductung	0:8ede47d38d10	1660	}
phungductung	0:8ede47d38d10	1661
phungductung	0:8ede47d38d10	1662	/**
phungductung	0:8ede47d38d10	1663	* @brief This function handles SPI interrupt request.
phungductung	0:8ede47d38d10	1664	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1665	* the configuration information for the specified SPI module.
phungductung	0:8ede47d38d10	1666	* @retval None
phungductung	0:8ede47d38d10	1667	*/
phungductung	0:8ede47d38d10	1668	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1669	{
phungductung	0:8ede47d38d10	1670	/* SPI in mode Receiver ----------------------------------------------------*/
phungductung	0:8ede47d38d10	1671	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
phungductung	0:8ede47d38d10	1672	(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
phungductung	0:8ede47d38d10	1673	{
phungductung	0:8ede47d38d10	1674	hspi->RxISR(hspi);
phungductung	0:8ede47d38d10	1675	return;
phungductung	0:8ede47d38d10	1676	}
phungductung	0:8ede47d38d10	1677
phungductung	0:8ede47d38d10	1678	/* SPI in mode Transmitter ---------------------------------------------------*/
phungductung	0:8ede47d38d10	1679	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
phungductung	0:8ede47d38d10	1680	{
phungductung	0:8ede47d38d10	1681	hspi->TxISR(hspi);
phungductung	0:8ede47d38d10	1682	return;
phungductung	0:8ede47d38d10	1683	}
phungductung	0:8ede47d38d10	1684
phungductung	0:8ede47d38d10	1685	/* SPI in ERROR Treatment ---------------------------------------------------*/
phungductung	0:8ede47d38d10	1686	if((hspi->Instance->SR & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
phungductung	0:8ede47d38d10	1687	{
phungductung	0:8ede47d38d10	1688	/* SPI Overrun error interrupt occurred -------------------------------------*/
phungductung	0:8ede47d38d10	1689	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
phungductung	0:8ede47d38d10	1690	{
phungductung	0:8ede47d38d10	1691	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
phungductung	0:8ede47d38d10	1692	{
phungductung	0:8ede47d38d10	1693	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
phungductung	0:8ede47d38d10	1694	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:8ede47d38d10	1695	}
phungductung	0:8ede47d38d10	1696	else
phungductung	0:8ede47d38d10	1697	{
phungductung	0:8ede47d38d10	1698	return;
phungductung	0:8ede47d38d10	1699	}
phungductung	0:8ede47d38d10	1700	}
phungductung	0:8ede47d38d10	1701
phungductung	0:8ede47d38d10	1702	/* SPI Mode Fault error interrupt occurred -------------------------------------*/
phungductung	0:8ede47d38d10	1703	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
phungductung	0:8ede47d38d10	1704	{
phungductung	0:8ede47d38d10	1705	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
phungductung	0:8ede47d38d10	1706	__HAL_SPI_CLEAR_MODFFLAG(hspi);
phungductung	0:8ede47d38d10	1707	}
phungductung	0:8ede47d38d10	1708
phungductung	0:8ede47d38d10	1709	/* SPI Frame error interrupt occurred ----------------------------------------*/
phungductung	0:8ede47d38d10	1710	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
phungductung	0:8ede47d38d10	1711	{
phungductung	0:8ede47d38d10	1712	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
phungductung	0:8ede47d38d10	1713	__HAL_SPI_CLEAR_FREFLAG(hspi);
phungductung	0:8ede47d38d10	1714	}
phungductung	0:8ede47d38d10	1715
phungductung	0:8ede47d38d10	1716	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
phungductung	0:8ede47d38d10	1717	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	1718	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	1719
phungductung	0:8ede47d38d10	1720	return;
phungductung	0:8ede47d38d10	1721	}
phungductung	0:8ede47d38d10	1722	}
phungductung	0:8ede47d38d10	1723
phungductung	0:8ede47d38d10	1724	/**
phungductung	0:8ede47d38d10	1725	* @brief Tx Transfer completed callback
phungductung	0:8ede47d38d10	1726	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1727	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1728	* @retval None
phungductung	0:8ede47d38d10	1729	*/
phungductung	0:8ede47d38d10	1730	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1731	{
phungductung	0:8ede47d38d10	1732	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1733	UNUSED(hspi);
phungductung	0:8ede47d38d10	1734
phungductung	0:8ede47d38d10	1735	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1736	the HAL_SPI_TxCpltCallback should be implemented in the user file
phungductung	0:8ede47d38d10	1737	*/
phungductung	0:8ede47d38d10	1738	}
phungductung	0:8ede47d38d10	1739
phungductung	0:8ede47d38d10	1740	/**
phungductung	0:8ede47d38d10	1741	* @brief Rx Transfer completed callbacks
phungductung	0:8ede47d38d10	1742	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1743	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1744	* @retval None
phungductung	0:8ede47d38d10	1745	*/
phungductung	0:8ede47d38d10	1746	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1747	{
phungductung	0:8ede47d38d10	1748	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1749	UNUSED(hspi);
phungductung	0:8ede47d38d10	1750
phungductung	0:8ede47d38d10	1751	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1752	the HAL_SPI_RxCpltCallback should be implemented in the user file
phungductung	0:8ede47d38d10	1753	*/
phungductung	0:8ede47d38d10	1754	}
phungductung	0:8ede47d38d10	1755
phungductung	0:8ede47d38d10	1756	/**
phungductung	0:8ede47d38d10	1757	* @brief Tx and Rx Transfer completed callback
phungductung	0:8ede47d38d10	1758	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1759	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1760	* @retval None
phungductung	0:8ede47d38d10	1761	*/
phungductung	0:8ede47d38d10	1762	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1763	{
phungductung	0:8ede47d38d10	1764	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1765	UNUSED(hspi);
phungductung	0:8ede47d38d10	1766
phungductung	0:8ede47d38d10	1767	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1768	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
phungductung	0:8ede47d38d10	1769	*/
phungductung	0:8ede47d38d10	1770	}
phungductung	0:8ede47d38d10	1771
phungductung	0:8ede47d38d10	1772	/**
phungductung	0:8ede47d38d10	1773	* @brief Tx Half Transfer completed callback
phungductung	0:8ede47d38d10	1774	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1775	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1776	* @retval None
phungductung	0:8ede47d38d10	1777	*/
phungductung	0:8ede47d38d10	1778	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1779	{
phungductung	0:8ede47d38d10	1780	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1781	UNUSED(hspi);
phungductung	0:8ede47d38d10	1782
phungductung	0:8ede47d38d10	1783	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1784	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
phungductung	0:8ede47d38d10	1785	*/
phungductung	0:8ede47d38d10	1786	}
phungductung	0:8ede47d38d10	1787
phungductung	0:8ede47d38d10	1788	/**
phungductung	0:8ede47d38d10	1789	* @brief Rx Half Transfer completed callback
phungductung	0:8ede47d38d10	1790	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1791	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1792	* @retval None
phungductung	0:8ede47d38d10	1793	*/
phungductung	0:8ede47d38d10	1794	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1795	{
phungductung	0:8ede47d38d10	1796	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1797	UNUSED(hspi);
phungductung	0:8ede47d38d10	1798
phungductung	0:8ede47d38d10	1799	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1800	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
phungductung	0:8ede47d38d10	1801	*/
phungductung	0:8ede47d38d10	1802	}
phungductung	0:8ede47d38d10	1803
phungductung	0:8ede47d38d10	1804	/**
phungductung	0:8ede47d38d10	1805	* @brief Tx and Rx Half Transfer callback
phungductung	0:8ede47d38d10	1806	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1807	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1808	* @retval None
phungductung	0:8ede47d38d10	1809	*/
phungductung	0:8ede47d38d10	1810	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1811	{
phungductung	0:8ede47d38d10	1812	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1813	UNUSED(hspi);
phungductung	0:8ede47d38d10	1814
phungductung	0:8ede47d38d10	1815	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1816	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
phungductung	0:8ede47d38d10	1817	*/
phungductung	0:8ede47d38d10	1818	}
phungductung	0:8ede47d38d10	1819
phungductung	0:8ede47d38d10	1820	/**
phungductung	0:8ede47d38d10	1821	* @brief SPI error callback
phungductung	0:8ede47d38d10	1822	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1823	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1824	* @retval None
phungductung	0:8ede47d38d10	1825	*/
phungductung	0:8ede47d38d10	1826	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1827	{
phungductung	0:8ede47d38d10	1828	/* Prevent unused argument(s) compilation warning */
phungductung	0:8ede47d38d10	1829	UNUSED(hspi);
phungductung	0:8ede47d38d10	1830
phungductung	0:8ede47d38d10	1831	/* NOTE : This function should not be modified, when the callback is needed,
phungductung	0:8ede47d38d10	1832	the HAL_SPI_ErrorCallback should be implemented in the user file
phungductung	0:8ede47d38d10	1833	*/
phungductung	0:8ede47d38d10	1834	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
phungductung	0:8ede47d38d10	1835	and user can use HAL_SPI_GetError() API to check the latest error occurred
phungductung	0:8ede47d38d10	1836	*/
phungductung	0:8ede47d38d10	1837	}
phungductung	0:8ede47d38d10	1838
phungductung	0:8ede47d38d10	1839	/**
phungductung	0:8ede47d38d10	1840	* @}
phungductung	0:8ede47d38d10	1841	*/
phungductung	0:8ede47d38d10	1842
phungductung	0:8ede47d38d10	1843	/**
phungductung	0:8ede47d38d10	1844	* @}
phungductung	0:8ede47d38d10	1845	*/
phungductung	0:8ede47d38d10	1846
phungductung	0:8ede47d38d10	1847	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
phungductung	0:8ede47d38d10	1848	* @brief SPI control functions
phungductung	0:8ede47d38d10	1849	*
phungductung	0:8ede47d38d10	1850	@verbatim
phungductung	0:8ede47d38d10	1851	===============================================================================
phungductung	0:8ede47d38d10	1852	##### Peripheral State and Errors functions #####
phungductung	0:8ede47d38d10	1853	===============================================================================
phungductung	0:8ede47d38d10	1854	[..]
phungductung	0:8ede47d38d10	1855	This subsection provides a set of functions allowing to control the SPI.
phungductung	0:8ede47d38d10	1856	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
phungductung	0:8ede47d38d10	1857	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
phungductung	0:8ede47d38d10	1858	@endverbatim
phungductung	0:8ede47d38d10	1859	* @{
phungductung	0:8ede47d38d10	1860	*/
phungductung	0:8ede47d38d10	1861
phungductung	0:8ede47d38d10	1862	/**
phungductung	0:8ede47d38d10	1863	* @brief Return the SPI state
phungductung	0:8ede47d38d10	1864	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1865	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1866	* @retval SPI state
phungductung	0:8ede47d38d10	1867	*/
phungductung	0:8ede47d38d10	1868	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1869	{
phungductung	0:8ede47d38d10	1870	return hspi->State;
phungductung	0:8ede47d38d10	1871	}
phungductung	0:8ede47d38d10	1872
phungductung	0:8ede47d38d10	1873	/**
phungductung	0:8ede47d38d10	1874	* @brief Return the SPI error code
phungductung	0:8ede47d38d10	1875	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1876	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	1877	* @retval SPI error code in bitmap format
phungductung	0:8ede47d38d10	1878	*/
phungductung	0:8ede47d38d10	1879	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	1880	{
phungductung	0:8ede47d38d10	1881	return hspi->ErrorCode;
phungductung	0:8ede47d38d10	1882	}
phungductung	0:8ede47d38d10	1883
phungductung	0:8ede47d38d10	1884	/**
phungductung	0:8ede47d38d10	1885	* @}
phungductung	0:8ede47d38d10	1886	*/
phungductung	0:8ede47d38d10	1887
phungductung	0:8ede47d38d10	1888	/**
phungductung	0:8ede47d38d10	1889	* @}
phungductung	0:8ede47d38d10	1890	*/
phungductung	0:8ede47d38d10	1891
phungductung	0:8ede47d38d10	1892	/** @defgroup SPI_Private_Functions SPI Private Functions
phungductung	0:8ede47d38d10	1893	* @{
phungductung	0:8ede47d38d10	1894	*/
phungductung	0:8ede47d38d10	1895
phungductung	0:8ede47d38d10	1896	/**
phungductung	0:8ede47d38d10	1897	* @brief DMA SPI transmit process complete callback
phungductung	0:8ede47d38d10	1898	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1899	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	1900	* @retval None
phungductung	0:8ede47d38d10	1901	*/
phungductung	0:8ede47d38d10	1902	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	1903	{
phungductung	0:8ede47d38d10	1904	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	1905
phungductung	0:8ede47d38d10	1906	/* DMA Normal Mode */
phungductung	0:8ede47d38d10	1907	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung	0:8ede47d38d10	1908	{
phungductung	0:8ede47d38d10	1909	/* Disable Tx DMA Request */
phungductung	0:8ede47d38d10	1910	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
phungductung	0:8ede47d38d10	1911
phungductung	0:8ede47d38d10	1912	/* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
phungductung	0:8ede47d38d10	1913	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
phungductung	0:8ede47d38d10	1914	{
phungductung	0:8ede47d38d10	1915	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:8ede47d38d10	1916	}
phungductung	0:8ede47d38d10	1917
phungductung	0:8ede47d38d10	1918	hspi->TxXferCount = 0;
phungductung	0:8ede47d38d10	1919	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	1920
phungductung	0:8ede47d38d10	1921	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	1922	{
phungductung	0:8ede47d38d10	1923	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	1924	return;
phungductung	0:8ede47d38d10	1925	}
phungductung	0:8ede47d38d10	1926	}
phungductung	0:8ede47d38d10	1927	HAL_SPI_TxCpltCallback(hspi);
phungductung	0:8ede47d38d10	1928	}
phungductung	0:8ede47d38d10	1929
phungductung	0:8ede47d38d10	1930	/**
phungductung	0:8ede47d38d10	1931	* @brief DMA SPI receive process complete callback
phungductung	0:8ede47d38d10	1932	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	1933	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	1934	* @retval None
phungductung	0:8ede47d38d10	1935	*/
phungductung	0:8ede47d38d10	1936	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	1937	{
phungductung	0:8ede47d38d10	1938	__IO uint16_t tmpreg;
phungductung	0:8ede47d38d10	1939	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	1940
phungductung	0:8ede47d38d10	1941	/* DMA Normal mode */
phungductung	0:8ede47d38d10	1942	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung	0:8ede47d38d10	1943	{
phungductung	0:8ede47d38d10	1944	/* CRC handling */
phungductung	0:8ede47d38d10	1945	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	1946	{
phungductung	0:8ede47d38d10	1947	/* Wait until TXE flag */
phungductung	0:8ede47d38d10	1948	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:8ede47d38d10	1949	{
phungductung	0:8ede47d38d10	1950	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	1951	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	1952	}
phungductung	0:8ede47d38d10	1953	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
phungductung	0:8ede47d38d10	1954	{
phungductung	0:8ede47d38d10	1955	tmpreg = hspi->Instance->DR;
phungductung	0:8ede47d38d10	1956	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	1957	}
phungductung	0:8ede47d38d10	1958	else
phungductung	0:8ede47d38d10	1959	{
phungductung	0:8ede47d38d10	1960	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	1961	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	1962
phungductung	0:8ede47d38d10	1963	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
phungductung	0:8ede47d38d10	1964	{
phungductung	0:8ede47d38d10	1965	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:8ede47d38d10	1966	{
phungductung	0:8ede47d38d10	1967	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	1968	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	1969	}
phungductung	0:8ede47d38d10	1970	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	1971	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	1972	}
phungductung	0:8ede47d38d10	1973	}
phungductung	0:8ede47d38d10	1974	}
phungductung	0:8ede47d38d10	1975
phungductung	0:8ede47d38d10	1976	/* Disable Rx DMA Request */
phungductung	0:8ede47d38d10	1977	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
phungductung	0:8ede47d38d10	1978	/* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
phungductung	0:8ede47d38d10	1979	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
phungductung	0:8ede47d38d10	1980
phungductung	0:8ede47d38d10	1981	/* Check the end of the transaction */
phungductung	0:8ede47d38d10	1982	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
phungductung	0:8ede47d38d10	1983
phungductung	0:8ede47d38d10	1984	hspi->RxXferCount = 0;
phungductung	0:8ede47d38d10	1985	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	1986
phungductung	0:8ede47d38d10	1987	/* Check if CRC error occurred */
phungductung	0:8ede47d38d10	1988	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:8ede47d38d10	1989	{
phungductung	0:8ede47d38d10	1990	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	1991	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:8ede47d38d10	1992	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:8ede47d38d10	1993	}
phungductung	0:8ede47d38d10	1994	else
phungductung	0:8ede47d38d10	1995	{
phungductung	0:8ede47d38d10	1996	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	1997	{
phungductung	0:8ede47d38d10	1998	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:8ede47d38d10	1999	}
phungductung	0:8ede47d38d10	2000	else
phungductung	0:8ede47d38d10	2001	{
phungductung	0:8ede47d38d10	2002	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2003	}
phungductung	0:8ede47d38d10	2004	}
phungductung	0:8ede47d38d10	2005	}
phungductung	0:8ede47d38d10	2006	else
phungductung	0:8ede47d38d10	2007	{
phungductung	0:8ede47d38d10	2008	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:8ede47d38d10	2009	}
phungductung	0:8ede47d38d10	2010	}
phungductung	0:8ede47d38d10	2011
phungductung	0:8ede47d38d10	2012	/**
phungductung	0:8ede47d38d10	2013	* @brief DMA SPI transmit receive process complete callback
phungductung	0:8ede47d38d10	2014	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2015	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	2016	* @retval None
phungductung	0:8ede47d38d10	2017	*/
phungductung	0:8ede47d38d10	2018	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	2019	{
phungductung	0:8ede47d38d10	2020	__IO int16_t tmpreg;
phungductung	0:8ede47d38d10	2021	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	2022
phungductung	0:8ede47d38d10	2023	/* CRC handling */
phungductung	0:8ede47d38d10	2024	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2025	{
phungductung	0:8ede47d38d10	2026	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
phungductung	0:8ede47d38d10	2027	{
phungductung	0:8ede47d38d10	2028	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:8ede47d38d10	2029	{
phungductung	0:8ede47d38d10	2030	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	2031	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	2032	}
phungductung	0:8ede47d38d10	2033	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
phungductung	0:8ede47d38d10	2034	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2035	}
phungductung	0:8ede47d38d10	2036	else
phungductung	0:8ede47d38d10	2037	{
phungductung	0:8ede47d38d10	2038	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
phungductung	0:8ede47d38d10	2039	{
phungductung	0:8ede47d38d10	2040	/* Error on the CRC reception */
phungductung	0:8ede47d38d10	2041	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	2042	}
phungductung	0:8ede47d38d10	2043	tmpreg = hspi->Instance->DR;
phungductung	0:8ede47d38d10	2044	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2045	}
phungductung	0:8ede47d38d10	2046	}
phungductung	0:8ede47d38d10	2047
phungductung	0:8ede47d38d10	2048	/* Check the end of the transaction */
phungductung	0:8ede47d38d10	2049	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
phungductung	0:8ede47d38d10	2050
phungductung	0:8ede47d38d10	2051	/* Disable Tx DMA Request */
phungductung	0:8ede47d38d10	2052	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
phungductung	0:8ede47d38d10	2053
phungductung	0:8ede47d38d10	2054	/* Disable Rx DMA Request */
phungductung	0:8ede47d38d10	2055	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
phungductung	0:8ede47d38d10	2056
phungductung	0:8ede47d38d10	2057	hspi->TxXferCount = 0;
phungductung	0:8ede47d38d10	2058	hspi->RxXferCount = 0;
phungductung	0:8ede47d38d10	2059	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2060
phungductung	0:8ede47d38d10	2061	/* Check if CRC error occurred */
phungductung	0:8ede47d38d10	2062	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:8ede47d38d10	2063	{
phungductung	0:8ede47d38d10	2064	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	2065	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:8ede47d38d10	2066	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2067	}
phungductung	0:8ede47d38d10	2068	else
phungductung	0:8ede47d38d10	2069	{
phungductung	0:8ede47d38d10	2070	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	2071	{
phungductung	0:8ede47d38d10	2072	HAL_SPI_TxRxCpltCallback(hspi);
phungductung	0:8ede47d38d10	2073	}
phungductung	0:8ede47d38d10	2074	else
phungductung	0:8ede47d38d10	2075	{
phungductung	0:8ede47d38d10	2076	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2077	}
phungductung	0:8ede47d38d10	2078	}
phungductung	0:8ede47d38d10	2079	}
phungductung	0:8ede47d38d10	2080
phungductung	0:8ede47d38d10	2081	/**
phungductung	0:8ede47d38d10	2082	* @brief DMA SPI half transmit process complete callback
phungductung	0:8ede47d38d10	2083	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2084	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	2085	* @retval None
phungductung	0:8ede47d38d10	2086	*/
phungductung	0:8ede47d38d10	2087	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	2088	{
phungductung	0:8ede47d38d10	2089	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	2090
phungductung	0:8ede47d38d10	2091	HAL_SPI_TxHalfCpltCallback(hspi);
phungductung	0:8ede47d38d10	2092	}
phungductung	0:8ede47d38d10	2093
phungductung	0:8ede47d38d10	2094	/**
phungductung	0:8ede47d38d10	2095	* @brief DMA SPI half receive process complete callback
phungductung	0:8ede47d38d10	2096	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2097	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	2098	* @retval None
phungductung	0:8ede47d38d10	2099	*/
phungductung	0:8ede47d38d10	2100	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	2101	{
phungductung	0:8ede47d38d10	2102	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	2103
phungductung	0:8ede47d38d10	2104	HAL_SPI_RxHalfCpltCallback(hspi);
phungductung	0:8ede47d38d10	2105	}
phungductung	0:8ede47d38d10	2106
phungductung	0:8ede47d38d10	2107	/**
phungductung	0:8ede47d38d10	2108	* @brief DMA SPI Half transmit receive process complete callback
phungductung	0:8ede47d38d10	2109	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2110	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	2111	* @retval None
phungductung	0:8ede47d38d10	2112	*/
phungductung	0:8ede47d38d10	2113	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	2114	{
phungductung	0:8ede47d38d10	2115	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	2116
phungductung	0:8ede47d38d10	2117	HAL_SPI_TxRxHalfCpltCallback(hspi);
phungductung	0:8ede47d38d10	2118	}
phungductung	0:8ede47d38d10	2119
phungductung	0:8ede47d38d10	2120	/**
phungductung	0:8ede47d38d10	2121	* @brief DMA SPI communication error callback
phungductung	0:8ede47d38d10	2122	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2123	* the configuration information for the specified DMA module.
phungductung	0:8ede47d38d10	2124	* @retval None
phungductung	0:8ede47d38d10	2125	*/
phungductung	0:8ede47d38d10	2126	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
phungductung	0:8ede47d38d10	2127	{
phungductung	0:8ede47d38d10	2128	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
phungductung	0:8ede47d38d10	2129
phungductung	0:8ede47d38d10	2130	/* Stop the disable DMA transfer on SPI side */
phungductung	0:8ede47d38d10	2131	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
phungductung	0:8ede47d38d10	2132
phungductung	0:8ede47d38d10	2133	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
phungductung	0:8ede47d38d10	2134	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2135	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2136	}
phungductung	0:8ede47d38d10	2137
phungductung	0:8ede47d38d10	2138	/**
phungductung	0:8ede47d38d10	2139	* @brief Rx Handler for Transmit and Receive in Interrupt mode
phungductung	0:8ede47d38d10	2140	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2141	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2142	* @retval None
phungductung	0:8ede47d38d10	2143	*/
phungductung	0:8ede47d38d10	2144	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2145	{
phungductung	0:8ede47d38d10	2146	/* Receive data in packing mode */
phungductung	0:8ede47d38d10	2147	if(hspi->RxXferCount > 1)
phungductung	0:8ede47d38d10	2148	{
phungductung	0:8ede47d38d10	2149	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	2150	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	2151	hspi->RxXferCount -= 2;
phungductung	0:8ede47d38d10	2152	if(hspi->RxXferCount == 1)
phungductung	0:8ede47d38d10	2153	{
phungductung	0:8ede47d38d10	2154	/* set fiforxthreshold according the reception data length: 8bit */
phungductung	0:8ede47d38d10	2155	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	2156	}
phungductung	0:8ede47d38d10	2157	}
phungductung	0:8ede47d38d10	2158	/* Receive data in 8 Bit mode */
phungductung	0:8ede47d38d10	2159	else
phungductung	0:8ede47d38d10	2160	{
phungductung	0:8ede47d38d10	2161	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
phungductung	0:8ede47d38d10	2162	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	2163	}
phungductung	0:8ede47d38d10	2164
phungductung	0:8ede47d38d10	2165	/* check end of the reception */
phungductung	0:8ede47d38d10	2166	if(hspi->RxXferCount == 0)
phungductung	0:8ede47d38d10	2167	{
phungductung	0:8ede47d38d10	2168	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2169	{
phungductung	0:8ede47d38d10	2170	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
phungductung	0:8ede47d38d10	2171	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
phungductung	0:8ede47d38d10	2172	return;
phungductung	0:8ede47d38d10	2173	}
phungductung	0:8ede47d38d10	2174
phungductung	0:8ede47d38d10	2175	/* Disable RXNE interrupt */
phungductung	0:8ede47d38d10	2176	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:8ede47d38d10	2177
phungductung	0:8ede47d38d10	2178	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2179	{
phungductung	0:8ede47d38d10	2180	SPI_CloseRxTx_ISR(hspi);
phungductung	0:8ede47d38d10	2181	}
phungductung	0:8ede47d38d10	2182	}
phungductung	0:8ede47d38d10	2183	}
phungductung	0:8ede47d38d10	2184
phungductung	0:8ede47d38d10	2185	/**
phungductung	0:8ede47d38d10	2186	* @brief Rx Handler for Transmit and Receive in Interrupt mode
phungductung	0:8ede47d38d10	2187	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2188	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2189	* @retval None
phungductung	0:8ede47d38d10	2190	*/
phungductung	0:8ede47d38d10	2191	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2192	{
phungductung	0:8ede47d38d10	2193	__IO uint8_t tmpreg;
phungductung	0:8ede47d38d10	2194
phungductung	0:8ede47d38d10	2195	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
phungductung	0:8ede47d38d10	2196	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2197
phungductung	0:8ede47d38d10	2198	hspi->CRCSize--;
phungductung	0:8ede47d38d10	2199
phungductung	0:8ede47d38d10	2200	/* check end of the reception */
phungductung	0:8ede47d38d10	2201	if(hspi->CRCSize == 0)
phungductung	0:8ede47d38d10	2202	{
phungductung	0:8ede47d38d10	2203	/* Disable RXNE interrupt */
phungductung	0:8ede47d38d10	2204	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:8ede47d38d10	2205
phungductung	0:8ede47d38d10	2206	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2207	{
phungductung	0:8ede47d38d10	2208	SPI_CloseRxTx_ISR(hspi);
phungductung	0:8ede47d38d10	2209	}
phungductung	0:8ede47d38d10	2210	}
phungductung	0:8ede47d38d10	2211	}
phungductung	0:8ede47d38d10	2212
phungductung	0:8ede47d38d10	2213	/**
phungductung	0:8ede47d38d10	2214	* @brief Tx Handler for Transmit and Receive in Interrupt mode
phungductung	0:8ede47d38d10	2215	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2216	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2217	* @retval None
phungductung	0:8ede47d38d10	2218	*/
phungductung	0:8ede47d38d10	2219	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2220	{
phungductung	0:8ede47d38d10	2221	/* Transmit data in packing Bit mode */
phungductung	0:8ede47d38d10	2222	if(hspi->TxXferCount >= 2)
phungductung	0:8ede47d38d10	2223	{
phungductung	0:8ede47d38d10	2224	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	2225	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	2226	hspi->TxXferCount -= 2;
phungductung	0:8ede47d38d10	2227	}
phungductung	0:8ede47d38d10	2228	/* Transmit data in 8 Bit mode */
phungductung	0:8ede47d38d10	2229	else
phungductung	0:8ede47d38d10	2230	{
phungductung	0:8ede47d38d10	2231	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
phungductung	0:8ede47d38d10	2232	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	2233	}
phungductung	0:8ede47d38d10	2234
phungductung	0:8ede47d38d10	2235	/* check the end of the transmission */
phungductung	0:8ede47d38d10	2236	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2237	{
phungductung	0:8ede47d38d10	2238	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2239	{
phungductung	0:8ede47d38d10	2240	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	2241	}
phungductung	0:8ede47d38d10	2242	/* Disable TXE interrupt */
phungductung	0:8ede47d38d10	2243	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
phungductung	0:8ede47d38d10	2244
phungductung	0:8ede47d38d10	2245	if(hspi->RxXferCount == 0)
phungductung	0:8ede47d38d10	2246	{
phungductung	0:8ede47d38d10	2247	SPI_CloseRxTx_ISR(hspi);
phungductung	0:8ede47d38d10	2248	}
phungductung	0:8ede47d38d10	2249	}
phungductung	0:8ede47d38d10	2250	}
phungductung	0:8ede47d38d10	2251
phungductung	0:8ede47d38d10	2252	/**
phungductung	0:8ede47d38d10	2253	* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
phungductung	0:8ede47d38d10	2254	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2255	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2256	* @retval None
phungductung	0:8ede47d38d10	2257	*/
phungductung	0:8ede47d38d10	2258	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2259	{
phungductung	0:8ede47d38d10	2260	/* Receive data in 16 Bit mode */
phungductung	0:8ede47d38d10	2261	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	2262	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	2263	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	2264
phungductung	0:8ede47d38d10	2265	if(hspi->RxXferCount == 0)
phungductung	0:8ede47d38d10	2266	{
phungductung	0:8ede47d38d10	2267	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2268	{
phungductung	0:8ede47d38d10	2269	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
phungductung	0:8ede47d38d10	2270	return;
phungductung	0:8ede47d38d10	2271	}
phungductung	0:8ede47d38d10	2272
phungductung	0:8ede47d38d10	2273	/* Disable RXNE interrupt */
phungductung	0:8ede47d38d10	2274	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:8ede47d38d10	2275
phungductung	0:8ede47d38d10	2276	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2277	{
phungductung	0:8ede47d38d10	2278	SPI_CloseRxTx_ISR(hspi);
phungductung	0:8ede47d38d10	2279	}
phungductung	0:8ede47d38d10	2280	}
phungductung	0:8ede47d38d10	2281	}
phungductung	0:8ede47d38d10	2282
phungductung	0:8ede47d38d10	2283	/**
phungductung	0:8ede47d38d10	2284	* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
phungductung	0:8ede47d38d10	2285	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2286	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2287	* @retval None
phungductung	0:8ede47d38d10	2288	*/
phungductung	0:8ede47d38d10	2289	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2290	{
phungductung	0:8ede47d38d10	2291	/* Receive data in 16 Bit mode */
phungductung	0:8ede47d38d10	2292	__IO uint16_t tmpreg = hspi->Instance->DR;
phungductung	0:8ede47d38d10	2293	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2294
phungductung	0:8ede47d38d10	2295	/* Disable RXNE interrupt */
phungductung	0:8ede47d38d10	2296	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
phungductung	0:8ede47d38d10	2297
phungductung	0:8ede47d38d10	2298	SPI_CloseRxTx_ISR(hspi);
phungductung	0:8ede47d38d10	2299	}
phungductung	0:8ede47d38d10	2300
phungductung	0:8ede47d38d10	2301	/**
phungductung	0:8ede47d38d10	2302	* @brief Tx Handler for Transmit and Receive in Interrupt mode
phungductung	0:8ede47d38d10	2303	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2304	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2305	* @retval None
phungductung	0:8ede47d38d10	2306	*/
phungductung	0:8ede47d38d10	2307	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2308	{
phungductung	0:8ede47d38d10	2309	/* Transmit data in 16 Bit mode */
phungductung	0:8ede47d38d10	2310	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	2311	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	2312	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	2313
phungductung	0:8ede47d38d10	2314	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	2315	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2316	{
phungductung	0:8ede47d38d10	2317	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2318	{
phungductung	0:8ede47d38d10	2319	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	2320	}
phungductung	0:8ede47d38d10	2321	/* Disable TXE interrupt */
phungductung	0:8ede47d38d10	2322	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
phungductung	0:8ede47d38d10	2323
phungductung	0:8ede47d38d10	2324	if(hspi->RxXferCount == 0)
phungductung	0:8ede47d38d10	2325	{
phungductung	0:8ede47d38d10	2326	SPI_CloseRxTx_ISR(hspi);
phungductung	0:8ede47d38d10	2327	}
phungductung	0:8ede47d38d10	2328	}
phungductung	0:8ede47d38d10	2329	}
phungductung	0:8ede47d38d10	2330
phungductung	0:8ede47d38d10	2331	/**
phungductung	0:8ede47d38d10	2332	* @brief Manage the CRC receive in Interrupt context
phungductung	0:8ede47d38d10	2333	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2334	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2335	* @retval None
phungductung	0:8ede47d38d10	2336	*/
phungductung	0:8ede47d38d10	2337	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2338	{
phungductung	0:8ede47d38d10	2339	__IO uint8_t tmpreg;
phungductung	0:8ede47d38d10	2340	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
phungductung	0:8ede47d38d10	2341	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2342
phungductung	0:8ede47d38d10	2343	hspi->CRCSize--;
phungductung	0:8ede47d38d10	2344
phungductung	0:8ede47d38d10	2345	if(hspi->CRCSize == 0)
phungductung	0:8ede47d38d10	2346	{
phungductung	0:8ede47d38d10	2347	SPI_CloseRx_ISR(hspi);
phungductung	0:8ede47d38d10	2348	}
phungductung	0:8ede47d38d10	2349	}
phungductung	0:8ede47d38d10	2350
phungductung	0:8ede47d38d10	2351	/**
phungductung	0:8ede47d38d10	2352	* @brief Manage the receive in Interrupt context
phungductung	0:8ede47d38d10	2353	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2354	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2355	* @retval None
phungductung	0:8ede47d38d10	2356	*/
phungductung	0:8ede47d38d10	2357	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2358	{
phungductung	0:8ede47d38d10	2359	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
phungductung	0:8ede47d38d10	2360	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	2361
phungductung	0:8ede47d38d10	2362	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	2363	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:8ede47d38d10	2364	{
phungductung	0:8ede47d38d10	2365	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	2366	}
phungductung	0:8ede47d38d10	2367
phungductung	0:8ede47d38d10	2368	if(hspi->RxXferCount == 0)
phungductung	0:8ede47d38d10	2369	{
phungductung	0:8ede47d38d10	2370	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2371	{
phungductung	0:8ede47d38d10	2372	hspi->RxISR = SPI_RxISR_8BITCRC;
phungductung	0:8ede47d38d10	2373	return;
phungductung	0:8ede47d38d10	2374	}
phungductung	0:8ede47d38d10	2375	SPI_CloseRx_ISR(hspi);
phungductung	0:8ede47d38d10	2376	}
phungductung	0:8ede47d38d10	2377	}
phungductung	0:8ede47d38d10	2378
phungductung	0:8ede47d38d10	2379	/**
phungductung	0:8ede47d38d10	2380	* @brief Manage the CRC 16bit receive in Interrupt context
phungductung	0:8ede47d38d10	2381	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2382	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2383	* @retval None
phungductung	0:8ede47d38d10	2384	*/
phungductung	0:8ede47d38d10	2385	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2386	{
phungductung	0:8ede47d38d10	2387	__IO uint16_t tmpreg;
phungductung	0:8ede47d38d10	2388
phungductung	0:8ede47d38d10	2389	tmpreg = hspi->Instance->DR;
phungductung	0:8ede47d38d10	2390	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2391
phungductung	0:8ede47d38d10	2392	/* Disable RXNE and ERR interrupt */
phungductung	0:8ede47d38d10	2393	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	2394
phungductung	0:8ede47d38d10	2395	SPI_CloseRx_ISR(hspi);
phungductung	0:8ede47d38d10	2396	}
phungductung	0:8ede47d38d10	2397
phungductung	0:8ede47d38d10	2398	/**
phungductung	0:8ede47d38d10	2399	* @brief Manage the 16Bit receive in Interrupt context
phungductung	0:8ede47d38d10	2400	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2401	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2402	* @retval None
phungductung	0:8ede47d38d10	2403	*/
phungductung	0:8ede47d38d10	2404	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2405	{
phungductung	0:8ede47d38d10	2406	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
phungductung	0:8ede47d38d10	2407	hspi->pRxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	2408	hspi->RxXferCount--;
phungductung	0:8ede47d38d10	2409
phungductung	0:8ede47d38d10	2410	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	2411	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
phungductung	0:8ede47d38d10	2412	{
phungductung	0:8ede47d38d10	2413	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	2414	}
phungductung	0:8ede47d38d10	2415
phungductung	0:8ede47d38d10	2416	if(hspi->RxXferCount == 0)
phungductung	0:8ede47d38d10	2417	{
phungductung	0:8ede47d38d10	2418	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2419	{
phungductung	0:8ede47d38d10	2420	hspi->RxISR = SPI_RxISR_16BITCRC;
phungductung	0:8ede47d38d10	2421	return;
phungductung	0:8ede47d38d10	2422	}
phungductung	0:8ede47d38d10	2423	SPI_CloseRx_ISR(hspi);
phungductung	0:8ede47d38d10	2424	}
phungductung	0:8ede47d38d10	2425	}
phungductung	0:8ede47d38d10	2426
phungductung	0:8ede47d38d10	2427	/**
phungductung	0:8ede47d38d10	2428	* @brief Handle the data 8Bit transmit in Interrupt mode
phungductung	0:8ede47d38d10	2429	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2430	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2431	* @retval None
phungductung	0:8ede47d38d10	2432	*/
phungductung	0:8ede47d38d10	2433	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2434	{
phungductung	0:8ede47d38d10	2435	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
phungductung	0:8ede47d38d10	2436	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	2437
phungductung	0:8ede47d38d10	2438	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2439	{
phungductung	0:8ede47d38d10	2440	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2441	{
phungductung	0:8ede47d38d10	2442	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	2443	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	2444	}
phungductung	0:8ede47d38d10	2445	SPI_CloseTx_ISR(hspi);
phungductung	0:8ede47d38d10	2446	}
phungductung	0:8ede47d38d10	2447	}
phungductung	0:8ede47d38d10	2448
phungductung	0:8ede47d38d10	2449	/**
phungductung	0:8ede47d38d10	2450	* @brief Handle the data 16Bit transmit in Interrupt mode
phungductung	0:8ede47d38d10	2451	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2452	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2453	* @retval None
phungductung	0:8ede47d38d10	2454	*/
phungductung	0:8ede47d38d10	2455	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2456	{
phungductung	0:8ede47d38d10	2457	/* Transmit data in 16 Bit mode */
phungductung	0:8ede47d38d10	2458	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
phungductung	0:8ede47d38d10	2459	hspi->pTxBuffPtr += sizeof(uint16_t);
phungductung	0:8ede47d38d10	2460	hspi->TxXferCount--;
phungductung	0:8ede47d38d10	2461
phungductung	0:8ede47d38d10	2462	if(hspi->TxXferCount == 0)
phungductung	0:8ede47d38d10	2463	{
phungductung	0:8ede47d38d10	2464	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2465	{
phungductung	0:8ede47d38d10	2466	/* Enable CRC Transmission */
phungductung	0:8ede47d38d10	2467	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
phungductung	0:8ede47d38d10	2468	}
phungductung	0:8ede47d38d10	2469	SPI_CloseTx_ISR(hspi);
phungductung	0:8ede47d38d10	2470	}
phungductung	0:8ede47d38d10	2471	}
phungductung	0:8ede47d38d10	2472
phungductung	0:8ede47d38d10	2473	/**
phungductung	0:8ede47d38d10	2474	* @brief This function handles SPI Communication Timeout.
phungductung	0:8ede47d38d10	2475	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2476	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2477	* @param Flag : SPI flag to check
phungductung	0:8ede47d38d10	2478	* @param State : flag state to check
phungductung	0:8ede47d38d10	2479	* @param Timeout : Timeout duration
phungductung	0:8ede47d38d10	2480	* @retval HAL status
phungductung	0:8ede47d38d10	2481	*/
phungductung	0:8ede47d38d10	2482	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
phungductung	0:8ede47d38d10	2483	{
phungductung	0:8ede47d38d10	2484	uint32_t tickstart = HAL_GetTick();
phungductung	0:8ede47d38d10	2485
phungductung	0:8ede47d38d10	2486	while((hspi->Instance->SR & Flag) != State)
phungductung	0:8ede47d38d10	2487	{
phungductung	0:8ede47d38d10	2488	if(Timeout != HAL_MAX_DELAY)
phungductung	0:8ede47d38d10	2489	{
phungductung	0:8ede47d38d10	2490	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
phungductung	0:8ede47d38d10	2491	{
phungductung	0:8ede47d38d10	2492	/* Disable the SPI and reset the CRC: the CRC value should be cleared
phungductung	0:8ede47d38d10	2493	on both master and slave sides in order to resynchronize the master
phungductung	0:8ede47d38d10	2494	and slave for their respective CRC calculation */
phungductung	0:8ede47d38d10	2495
phungductung	0:8ede47d38d10	2496	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
phungductung	0:8ede47d38d10	2497	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	2498
phungductung	0:8ede47d38d10	2499	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
phungductung	0:8ede47d38d10	2500	{
phungductung	0:8ede47d38d10	2501	/* Disable SPI peripheral */
phungductung	0:8ede47d38d10	2502	__HAL_SPI_DISABLE(hspi);
phungductung	0:8ede47d38d10	2503	}
phungductung	0:8ede47d38d10	2504
phungductung	0:8ede47d38d10	2505	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	2506	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2507	{
phungductung	0:8ede47d38d10	2508	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	2509	}
phungductung	0:8ede47d38d10	2510
phungductung	0:8ede47d38d10	2511	hspi->State= HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2512
phungductung	0:8ede47d38d10	2513	/* Process Unlocked */
phungductung	0:8ede47d38d10	2514	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	2515
phungductung	0:8ede47d38d10	2516	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2517	}
phungductung	0:8ede47d38d10	2518	}
phungductung	0:8ede47d38d10	2519	}
phungductung	0:8ede47d38d10	2520
phungductung	0:8ede47d38d10	2521	return HAL_OK;
phungductung	0:8ede47d38d10	2522	}
phungductung	0:8ede47d38d10	2523
phungductung	0:8ede47d38d10	2524	/**
phungductung	0:8ede47d38d10	2525	* @brief This function handles SPI Communication Timeout.
phungductung	0:8ede47d38d10	2526	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2527	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2528	* @param Fifo : Fifo to check
phungductung	0:8ede47d38d10	2529	* @param State : Fifo state to check
phungductung	0:8ede47d38d10	2530	* @param Timeout : Timeout duration
phungductung	0:8ede47d38d10	2531	* @retval HAL status
phungductung	0:8ede47d38d10	2532	*/
phungductung	0:8ede47d38d10	2533	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
phungductung	0:8ede47d38d10	2534	{
phungductung	0:8ede47d38d10	2535	__IO uint8_t tmpreg;
phungductung	0:8ede47d38d10	2536	uint32_t tickstart = HAL_GetTick();
phungductung	0:8ede47d38d10	2537
phungductung	0:8ede47d38d10	2538	while((hspi->Instance->SR & Fifo) != State)
phungductung	0:8ede47d38d10	2539	{
phungductung	0:8ede47d38d10	2540	if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
phungductung	0:8ede47d38d10	2541	{
phungductung	0:8ede47d38d10	2542	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
phungductung	0:8ede47d38d10	2543	UNUSED(tmpreg); /* To avoid GCC warning */
phungductung	0:8ede47d38d10	2544	}
phungductung	0:8ede47d38d10	2545
phungductung	0:8ede47d38d10	2546	if(Timeout != HAL_MAX_DELAY)
phungductung	0:8ede47d38d10	2547	{
phungductung	0:8ede47d38d10	2548	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
phungductung	0:8ede47d38d10	2549	{
phungductung	0:8ede47d38d10	2550	/* Disable the SPI and reset the CRC: the CRC value should be cleared
phungductung	0:8ede47d38d10	2551	on both master and slave sides in order to resynchronize the master
phungductung	0:8ede47d38d10	2552	and slave for their respective CRC calculation */
phungductung	0:8ede47d38d10	2553
phungductung	0:8ede47d38d10	2554	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
phungductung	0:8ede47d38d10	2555	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	2556
phungductung	0:8ede47d38d10	2557	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
phungductung	0:8ede47d38d10	2558	{
phungductung	0:8ede47d38d10	2559	/* Disable SPI peripheral */
phungductung	0:8ede47d38d10	2560	__HAL_SPI_DISABLE(hspi);
phungductung	0:8ede47d38d10	2561	}
phungductung	0:8ede47d38d10	2562
phungductung	0:8ede47d38d10	2563	/* Reset CRC Calculation */
phungductung	0:8ede47d38d10	2564	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
phungductung	0:8ede47d38d10	2565	{
phungductung	0:8ede47d38d10	2566	SPI_RESET_CRC(hspi);
phungductung	0:8ede47d38d10	2567	}
phungductung	0:8ede47d38d10	2568
phungductung	0:8ede47d38d10	2569	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2570
phungductung	0:8ede47d38d10	2571	/* Process Unlocked */
phungductung	0:8ede47d38d10	2572	__HAL_UNLOCK(hspi);
phungductung	0:8ede47d38d10	2573
phungductung	0:8ede47d38d10	2574	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2575	}
phungductung	0:8ede47d38d10	2576	}
phungductung	0:8ede47d38d10	2577	}
phungductung	0:8ede47d38d10	2578
phungductung	0:8ede47d38d10	2579	return HAL_OK;
phungductung	0:8ede47d38d10	2580	}
phungductung	0:8ede47d38d10	2581
phungductung	0:8ede47d38d10	2582	/**
phungductung	0:8ede47d38d10	2583	* @brief This function handles the check of the RX transaction complete.
phungductung	0:8ede47d38d10	2584	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2585	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2586	* @param Timeout : Timeout duration
phungductung	0:8ede47d38d10	2587	* @retval None
phungductung	0:8ede47d38d10	2588	*/
phungductung	0:8ede47d38d10	2589	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
phungductung	0:8ede47d38d10	2590	{
phungductung	0:8ede47d38d10	2591	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
phungductung	0:8ede47d38d10	2592	{
phungductung	0:8ede47d38d10	2593	/* Disable SPI peripheral */
phungductung	0:8ede47d38d10	2594	__HAL_SPI_DISABLE(hspi);
phungductung	0:8ede47d38d10	2595	}
phungductung	0:8ede47d38d10	2596	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	2597	{
phungductung	0:8ede47d38d10	2598	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:8ede47d38d10	2599	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2600	}
phungductung	0:8ede47d38d10	2601	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	2602	{
phungductung	0:8ede47d38d10	2603	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:8ede47d38d10	2604	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2605	}
phungductung	0:8ede47d38d10	2606
phungductung	0:8ede47d38d10	2607	return HAL_OK;
phungductung	0:8ede47d38d10	2608	}
phungductung	0:8ede47d38d10	2609
phungductung	0:8ede47d38d10	2610	/**
phungductung	0:8ede47d38d10	2611	* @brief This function handles the check of the RXTX or TX transaction complete.
phungductung	0:8ede47d38d10	2612	* @param hspi: SPI handle
phungductung	0:8ede47d38d10	2613	* @param Timeout : Timeout duration
phungductung	0:8ede47d38d10	2614	*/
phungductung	0:8ede47d38d10	2615	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
phungductung	0:8ede47d38d10	2616	{
phungductung	0:8ede47d38d10	2617	/* Procedure to check the transaction complete */
phungductung	0:8ede47d38d10	2618	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	2619	{
phungductung	0:8ede47d38d10	2620	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:8ede47d38d10	2621	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2622	}
phungductung	0:8ede47d38d10	2623	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	2624	{
phungductung	0:8ede47d38d10	2625	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:8ede47d38d10	2626	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2627	}
phungductung	0:8ede47d38d10	2628	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
phungductung	0:8ede47d38d10	2629	{
phungductung	0:8ede47d38d10	2630	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
phungductung	0:8ede47d38d10	2631	return HAL_TIMEOUT;
phungductung	0:8ede47d38d10	2632	}
phungductung	0:8ede47d38d10	2633	return HAL_OK;
phungductung	0:8ede47d38d10	2634	}
phungductung	0:8ede47d38d10	2635
phungductung	0:8ede47d38d10	2636	/**
phungductung	0:8ede47d38d10	2637	* @brief This function handles the close of the RXTX transaction.
phungductung	0:8ede47d38d10	2638	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2639	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2640	* @retval None
phungductung	0:8ede47d38d10	2641	*/
phungductung	0:8ede47d38d10	2642	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2643	{
phungductung	0:8ede47d38d10	2644	/* Disable ERR interrupt */
phungductung	0:8ede47d38d10	2645	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
phungductung	0:8ede47d38d10	2646
phungductung	0:8ede47d38d10	2647	/* Check if CRC error occurred */
phungductung	0:8ede47d38d10	2648	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:8ede47d38d10	2649	{
phungductung	0:8ede47d38d10	2650	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2651	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	2652	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:8ede47d38d10	2653	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2654	}
phungductung	0:8ede47d38d10	2655	else
phungductung	0:8ede47d38d10	2656	{
phungductung	0:8ede47d38d10	2657	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	2658	{
phungductung	0:8ede47d38d10	2659	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
phungductung	0:8ede47d38d10	2660	{
phungductung	0:8ede47d38d10	2661	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2662	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:8ede47d38d10	2663	}
phungductung	0:8ede47d38d10	2664	else
phungductung	0:8ede47d38d10	2665	{
phungductung	0:8ede47d38d10	2666	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2667	HAL_SPI_TxRxCpltCallback(hspi);
phungductung	0:8ede47d38d10	2668	}
phungductung	0:8ede47d38d10	2669	}
phungductung	0:8ede47d38d10	2670	else
phungductung	0:8ede47d38d10	2671	{
phungductung	0:8ede47d38d10	2672	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2673	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2674	}
phungductung	0:8ede47d38d10	2675	}
phungductung	0:8ede47d38d10	2676	}
phungductung	0:8ede47d38d10	2677
phungductung	0:8ede47d38d10	2678	/**
phungductung	0:8ede47d38d10	2679	* @brief This function handles the close of the RX transaction.
phungductung	0:8ede47d38d10	2680	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2681	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2682	* @retval None
phungductung	0:8ede47d38d10	2683	*/
phungductung	0:8ede47d38d10	2684	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2685	{
phungductung	0:8ede47d38d10	2686	/* Disable RXNE and ERR interrupt */
phungductung	0:8ede47d38d10	2687	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	2688
phungductung	0:8ede47d38d10	2689	/* Check the end of the transaction */
phungductung	0:8ede47d38d10	2690	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
phungductung	0:8ede47d38d10	2691
phungductung	0:8ede47d38d10	2692	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2693
phungductung	0:8ede47d38d10	2694	/* Check if CRC error occurred */
phungductung	0:8ede47d38d10	2695	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
phungductung	0:8ede47d38d10	2696	{
phungductung	0:8ede47d38d10	2697	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
phungductung	0:8ede47d38d10	2698	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
phungductung	0:8ede47d38d10	2699	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2700	}
phungductung	0:8ede47d38d10	2701	else
phungductung	0:8ede47d38d10	2702	{
phungductung	0:8ede47d38d10	2703	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	2704	{
phungductung	0:8ede47d38d10	2705	HAL_SPI_RxCpltCallback(hspi);
phungductung	0:8ede47d38d10	2706	}
phungductung	0:8ede47d38d10	2707	else
phungductung	0:8ede47d38d10	2708	{
phungductung	0:8ede47d38d10	2709	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2710	}
phungductung	0:8ede47d38d10	2711	}
phungductung	0:8ede47d38d10	2712	}
phungductung	0:8ede47d38d10	2713
phungductung	0:8ede47d38d10	2714	/**
phungductung	0:8ede47d38d10	2715	* @brief This function handles the close of the TX transaction.
phungductung	0:8ede47d38d10	2716	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
phungductung	0:8ede47d38d10	2717	* the configuration information for SPI module.
phungductung	0:8ede47d38d10	2718	* @retval None
phungductung	0:8ede47d38d10	2719	*/
phungductung	0:8ede47d38d10	2720	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
phungductung	0:8ede47d38d10	2721	{
phungductung	0:8ede47d38d10	2722	/* Disable TXE and ERR interrupt */
phungductung	0:8ede47d38d10	2723	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
phungductung	0:8ede47d38d10	2724
phungductung	0:8ede47d38d10	2725	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
phungductung	0:8ede47d38d10	2726	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
phungductung	0:8ede47d38d10	2727	{
phungductung	0:8ede47d38d10	2728	__HAL_SPI_CLEAR_OVRFLAG(hspi);
phungductung	0:8ede47d38d10	2729	}
phungductung	0:8ede47d38d10	2730
phungductung	0:8ede47d38d10	2731	hspi->State = HAL_SPI_STATE_READY;
phungductung	0:8ede47d38d10	2732	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
phungductung	0:8ede47d38d10	2733	{
phungductung	0:8ede47d38d10	2734	HAL_SPI_ErrorCallback(hspi);
phungductung	0:8ede47d38d10	2735	}
phungductung	0:8ede47d38d10	2736	else
phungductung	0:8ede47d38d10	2737	{
phungductung	0:8ede47d38d10	2738	HAL_SPI_TxCpltCallback(hspi);
phungductung	0:8ede47d38d10	2739	}
phungductung	0:8ede47d38d10	2740	}
phungductung	0:8ede47d38d10	2741
phungductung	0:8ede47d38d10	2742	/**
phungductung	0:8ede47d38d10	2743	* @}
phungductung	0:8ede47d38d10	2744	*/
phungductung	0:8ede47d38d10	2745
phungductung	0:8ede47d38d10	2746	#endif /* HAL_SPI_MODULE_ENABLED */
phungductung	0:8ede47d38d10	2747	/**
phungductung	0:8ede47d38d10	2748	* @}
phungductung	0:8ede47d38d10	2749	*/
phungductung	0:8ede47d38d10	2750
phungductung	0:8ede47d38d10	2751	/**
phungductung	0:8ede47d38d10	2752	* @}
phungductung	0:8ede47d38d10	2753	*/
phungductung	0:8ede47d38d10	2754
phungductung	0:8ede47d38d10	2755	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	04 Jun 2019
Imports:	17
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	3
Followers:	1

SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:8ede47d38d10, 2019-06-04 (annotated)

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