PHung Tung / DISCO-F746_WAV_PLAYER

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Dependencies:   F746_GUI SD_PlayerSkeleton F746_SAI_IO

SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:37:21 2019 +0000
Revision:
0:8ede47d38d10
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phungductung 0:8ede47d38d10 1 /**
phungductung 0:8ede47d38d10 2 ******************************************************************************
phungductung 0:8ede47d38d10 3 * @file stm32f7xx_hal_rcc_ex.c
phungductung 0:8ede47d38d10 4 * @author MCD Application Team
phungductung 0:8ede47d38d10 5 * @version V1.0.4
phungductung 0:8ede47d38d10 6 * @date 09-December-2015
phungductung 0:8ede47d38d10 7 * @brief Extension RCC HAL module driver.
phungductung 0:8ede47d38d10 8 * This file provides firmware functions to manage the following
phungductung 0:8ede47d38d10 9 * functionalities RCC extension peripheral:
phungductung 0:8ede47d38d10 10 * + Extended Peripheral Control functions
phungductung 0:8ede47d38d10 11 *
phungductung 0:8ede47d38d10 12 ******************************************************************************
phungductung 0:8ede47d38d10 13 * @attention
phungductung 0:8ede47d38d10 14 *
phungductung 0:8ede47d38d10 15 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:8ede47d38d10 16 *
phungductung 0:8ede47d38d10 17 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:8ede47d38d10 18 * are permitted provided that the following conditions are met:
phungductung 0:8ede47d38d10 19 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:8ede47d38d10 20 * this list of conditions and the following disclaimer.
phungductung 0:8ede47d38d10 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:8ede47d38d10 22 * this list of conditions and the following disclaimer in the documentation
phungductung 0:8ede47d38d10 23 * and/or other materials provided with the distribution.
phungductung 0:8ede47d38d10 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:8ede47d38d10 25 * may be used to endorse or promote products derived from this software
phungductung 0:8ede47d38d10 26 * without specific prior written permission.
phungductung 0:8ede47d38d10 27 *
phungductung 0:8ede47d38d10 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:8ede47d38d10 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:8ede47d38d10 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:8ede47d38d10 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:8ede47d38d10 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:8ede47d38d10 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:8ede47d38d10 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:8ede47d38d10 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:8ede47d38d10 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:8ede47d38d10 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:8ede47d38d10 38 *
phungductung 0:8ede47d38d10 39 ******************************************************************************
phungductung 0:8ede47d38d10 40 */
phungductung 0:8ede47d38d10 41
phungductung 0:8ede47d38d10 42 /* Includes ------------------------------------------------------------------*/
phungductung 0:8ede47d38d10 43 #include "stm32f7xx_hal.h"
phungductung 0:8ede47d38d10 44
phungductung 0:8ede47d38d10 45 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:8ede47d38d10 46 * @{
phungductung 0:8ede47d38d10 47 */
phungductung 0:8ede47d38d10 48
phungductung 0:8ede47d38d10 49 /** @defgroup RCCEx RCCEx
phungductung 0:8ede47d38d10 50 * @brief RCCEx HAL module driver
phungductung 0:8ede47d38d10 51 * @{
phungductung 0:8ede47d38d10 52 */
phungductung 0:8ede47d38d10 53
phungductung 0:8ede47d38d10 54 #ifdef HAL_RCC_MODULE_ENABLED
phungductung 0:8ede47d38d10 55
phungductung 0:8ede47d38d10 56 /* Private typedef -----------------------------------------------------------*/
phungductung 0:8ede47d38d10 57 /* Private define ------------------------------------------------------------*/
phungductung 0:8ede47d38d10 58 /** @defgroup RCCEx_Private_Defines RCCEx Private Defines
phungductung 0:8ede47d38d10 59 * @{
phungductung 0:8ede47d38d10 60 */
phungductung 0:8ede47d38d10 61
phungductung 0:8ede47d38d10 62 #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
phungductung 0:8ede47d38d10 63 #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
phungductung 0:8ede47d38d10 64
phungductung 0:8ede47d38d10 65 /**
phungductung 0:8ede47d38d10 66 * @}
phungductung 0:8ede47d38d10 67 */
phungductung 0:8ede47d38d10 68 /* Private macro -------------------------------------------------------------*/
phungductung 0:8ede47d38d10 69 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
phungductung 0:8ede47d38d10 70 * @{
phungductung 0:8ede47d38d10 71 */
phungductung 0:8ede47d38d10 72 /**
phungductung 0:8ede47d38d10 73 * @}
phungductung 0:8ede47d38d10 74 */
phungductung 0:8ede47d38d10 75
phungductung 0:8ede47d38d10 76 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
phungductung 0:8ede47d38d10 77 * @{
phungductung 0:8ede47d38d10 78 */
phungductung 0:8ede47d38d10 79
phungductung 0:8ede47d38d10 80 /**
phungductung 0:8ede47d38d10 81 * @}
phungductung 0:8ede47d38d10 82 */
phungductung 0:8ede47d38d10 83
phungductung 0:8ede47d38d10 84
phungductung 0:8ede47d38d10 85 /* Private variables ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 86 /* Private function prototypes -----------------------------------------------*/
phungductung 0:8ede47d38d10 87 /* Private functions ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 88
phungductung 0:8ede47d38d10 89 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
phungductung 0:8ede47d38d10 90 * @{
phungductung 0:8ede47d38d10 91 */
phungductung 0:8ede47d38d10 92
phungductung 0:8ede47d38d10 93 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
phungductung 0:8ede47d38d10 94 * @brief Extended Peripheral Control functions
phungductung 0:8ede47d38d10 95 *
phungductung 0:8ede47d38d10 96 @verbatim
phungductung 0:8ede47d38d10 97 ===============================================================================
phungductung 0:8ede47d38d10 98 ##### Extended Peripheral Control functions #####
phungductung 0:8ede47d38d10 99 ===============================================================================
phungductung 0:8ede47d38d10 100 [..]
phungductung 0:8ede47d38d10 101 This subsection provides a set of functions allowing to control the RCC Clocks
phungductung 0:8ede47d38d10 102 frequencies.
phungductung 0:8ede47d38d10 103 [..]
phungductung 0:8ede47d38d10 104 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
phungductung 0:8ede47d38d10 105 select the RTC clock source; in this case the Backup domain will be reset in
phungductung 0:8ede47d38d10 106 order to modify the RTC Clock source, as consequence RTC registers (including
phungductung 0:8ede47d38d10 107 the backup registers) and RCC_BDCR register will be set to their reset values.
phungductung 0:8ede47d38d10 108
phungductung 0:8ede47d38d10 109 @endverbatim
phungductung 0:8ede47d38d10 110 * @{
phungductung 0:8ede47d38d10 111 */
phungductung 0:8ede47d38d10 112 /**
phungductung 0:8ede47d38d10 113 * @brief Initializes the RCC extended peripherals clocks according to the specified
phungductung 0:8ede47d38d10 114 * parameters in the RCC_PeriphCLKInitTypeDef.
phungductung 0:8ede47d38d10 115 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
phungductung 0:8ede47d38d10 116 * contains the configuration information for the Extended Peripherals
phungductung 0:8ede47d38d10 117 * clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
phungductung 0:8ede47d38d10 118 *
phungductung 0:8ede47d38d10 119 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
phungductung 0:8ede47d38d10 120 * the RTC clock source; in this case the Backup domain will be reset in
phungductung 0:8ede47d38d10 121 * order to modify the RTC Clock source, as consequence RTC registers (including
phungductung 0:8ede47d38d10 122 * the backup registers) and RCC_BDCR register are set to their reset values.
phungductung 0:8ede47d38d10 123 *
phungductung 0:8ede47d38d10 124 * @retval HAL status
phungductung 0:8ede47d38d10 125 */
phungductung 0:8ede47d38d10 126 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
phungductung 0:8ede47d38d10 127 {
phungductung 0:8ede47d38d10 128 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 129 uint32_t tmpreg0 = 0;
phungductung 0:8ede47d38d10 130 uint32_t tmpreg1 = 0;
phungductung 0:8ede47d38d10 131 uint32_t plli2sused = 0;
phungductung 0:8ede47d38d10 132 uint32_t pllsaiused = 0;
phungductung 0:8ede47d38d10 133
phungductung 0:8ede47d38d10 134 /* Check the parameters */
phungductung 0:8ede47d38d10 135 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
phungductung 0:8ede47d38d10 136
phungductung 0:8ede47d38d10 137 /*----------------------------------- I2S configuration ----------------------------------*/
phungductung 0:8ede47d38d10 138 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
phungductung 0:8ede47d38d10 139 {
phungductung 0:8ede47d38d10 140 /* Check the parameters */
phungductung 0:8ede47d38d10 141 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
phungductung 0:8ede47d38d10 142
phungductung 0:8ede47d38d10 143 /* Configure I2S Clock source */
phungductung 0:8ede47d38d10 144 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
phungductung 0:8ede47d38d10 145
phungductung 0:8ede47d38d10 146 /* Enable the PLLI2S when it's used as clock source for I2S */
phungductung 0:8ede47d38d10 147 if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
phungductung 0:8ede47d38d10 148 {
phungductung 0:8ede47d38d10 149 plli2sused = 1;
phungductung 0:8ede47d38d10 150 }
phungductung 0:8ede47d38d10 151 }
phungductung 0:8ede47d38d10 152
phungductung 0:8ede47d38d10 153 /*------------------------------------ SAI1 configuration --------------------------------------*/
phungductung 0:8ede47d38d10 154 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
phungductung 0:8ede47d38d10 155 {
phungductung 0:8ede47d38d10 156 /* Check the parameters */
phungductung 0:8ede47d38d10 157 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
phungductung 0:8ede47d38d10 158
phungductung 0:8ede47d38d10 159 /* Configure SAI1 Clock source */
phungductung 0:8ede47d38d10 160 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
phungductung 0:8ede47d38d10 161 /* Enable the PLLI2S when it's used as clock source for SAI */
phungductung 0:8ede47d38d10 162 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
phungductung 0:8ede47d38d10 163 {
phungductung 0:8ede47d38d10 164 plli2sused = 1;
phungductung 0:8ede47d38d10 165 }
phungductung 0:8ede47d38d10 166 /* Enable the PLLSAI when it's used as clock source for SAI */
phungductung 0:8ede47d38d10 167 if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
phungductung 0:8ede47d38d10 168 {
phungductung 0:8ede47d38d10 169 pllsaiused = 1;
phungductung 0:8ede47d38d10 170 }
phungductung 0:8ede47d38d10 171 }
phungductung 0:8ede47d38d10 172
phungductung 0:8ede47d38d10 173 /*------------------------------------ SAI2 configuration --------------------------------------*/
phungductung 0:8ede47d38d10 174 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
phungductung 0:8ede47d38d10 175 {
phungductung 0:8ede47d38d10 176 /* Check the parameters */
phungductung 0:8ede47d38d10 177 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
phungductung 0:8ede47d38d10 178
phungductung 0:8ede47d38d10 179 /* Configure SAI2 Clock source */
phungductung 0:8ede47d38d10 180 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
phungductung 0:8ede47d38d10 181
phungductung 0:8ede47d38d10 182 /* Enable the PLLI2S when it's used as clock source for SAI */
phungductung 0:8ede47d38d10 183 if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
phungductung 0:8ede47d38d10 184 {
phungductung 0:8ede47d38d10 185 plli2sused = 1;
phungductung 0:8ede47d38d10 186 }
phungductung 0:8ede47d38d10 187 /* Enable the PLLSAI when it's used as clock source for SAI */
phungductung 0:8ede47d38d10 188 if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
phungductung 0:8ede47d38d10 189 {
phungductung 0:8ede47d38d10 190 pllsaiused = 1;
phungductung 0:8ede47d38d10 191 }
phungductung 0:8ede47d38d10 192 }
phungductung 0:8ede47d38d10 193
phungductung 0:8ede47d38d10 194 /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 195 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
phungductung 0:8ede47d38d10 196 {
phungductung 0:8ede47d38d10 197 plli2sused = 1;
phungductung 0:8ede47d38d10 198 }
phungductung 0:8ede47d38d10 199
phungductung 0:8ede47d38d10 200 /*------------------------------------ RTC configuration --------------------------------------*/
phungductung 0:8ede47d38d10 201 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
phungductung 0:8ede47d38d10 202 {
phungductung 0:8ede47d38d10 203 /* Enable Power Clock*/
phungductung 0:8ede47d38d10 204 __HAL_RCC_PWR_CLK_ENABLE();
phungductung 0:8ede47d38d10 205
phungductung 0:8ede47d38d10 206 /* Enable write access to Backup domain */
phungductung 0:8ede47d38d10 207 PWR->CR1 |= PWR_CR1_DBP;
phungductung 0:8ede47d38d10 208
phungductung 0:8ede47d38d10 209 /* Get Start Tick*/
phungductung 0:8ede47d38d10 210 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 211
phungductung 0:8ede47d38d10 212 /* Wait for Backup domain Write protection disable */
phungductung 0:8ede47d38d10 213 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
phungductung 0:8ede47d38d10 214 {
phungductung 0:8ede47d38d10 215 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 216 {
phungductung 0:8ede47d38d10 217 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 218 }
phungductung 0:8ede47d38d10 219 }
phungductung 0:8ede47d38d10 220 /* Reset the Backup domain only if the RTC Clock source selection is modified */
phungductung 0:8ede47d38d10 221 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
phungductung 0:8ede47d38d10 222 {
phungductung 0:8ede47d38d10 223 /* Store the content of BDCR register before the reset of Backup Domain */
phungductung 0:8ede47d38d10 224 tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
phungductung 0:8ede47d38d10 225
phungductung 0:8ede47d38d10 226 /* RTC Clock selection can be changed only if the Backup Domain is reset */
phungductung 0:8ede47d38d10 227 __HAL_RCC_BACKUPRESET_FORCE();
phungductung 0:8ede47d38d10 228 __HAL_RCC_BACKUPRESET_RELEASE();
phungductung 0:8ede47d38d10 229
phungductung 0:8ede47d38d10 230 /* Restore the Content of BDCR register */
phungductung 0:8ede47d38d10 231 RCC->BDCR = tmpreg0;
phungductung 0:8ede47d38d10 232
phungductung 0:8ede47d38d10 233 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
phungductung 0:8ede47d38d10 234 if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
phungductung 0:8ede47d38d10 235 {
phungductung 0:8ede47d38d10 236 /* Get Start Tick*/
phungductung 0:8ede47d38d10 237 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 238
phungductung 0:8ede47d38d10 239 /* Wait till LSE is ready */
phungductung 0:8ede47d38d10 240 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
phungductung 0:8ede47d38d10 241 {
phungductung 0:8ede47d38d10 242 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 243 {
phungductung 0:8ede47d38d10 244 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 245 }
phungductung 0:8ede47d38d10 246 }
phungductung 0:8ede47d38d10 247 }
phungductung 0:8ede47d38d10 248 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
phungductung 0:8ede47d38d10 249 }
phungductung 0:8ede47d38d10 250 }
phungductung 0:8ede47d38d10 251
phungductung 0:8ede47d38d10 252 /*------------------------------------ TIM configuration --------------------------------------*/
phungductung 0:8ede47d38d10 253 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
phungductung 0:8ede47d38d10 254 {
phungductung 0:8ede47d38d10 255 /* Check the parameters */
phungductung 0:8ede47d38d10 256 assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
phungductung 0:8ede47d38d10 257
phungductung 0:8ede47d38d10 258 /* Configure Timer Prescaler */
phungductung 0:8ede47d38d10 259 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
phungductung 0:8ede47d38d10 260 }
phungductung 0:8ede47d38d10 261
phungductung 0:8ede47d38d10 262 /*-------------------------------------- I2C1 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 263 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
phungductung 0:8ede47d38d10 264 {
phungductung 0:8ede47d38d10 265 /* Check the parameters */
phungductung 0:8ede47d38d10 266 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
phungductung 0:8ede47d38d10 267
phungductung 0:8ede47d38d10 268 /* Configure the I2C1 clock source */
phungductung 0:8ede47d38d10 269 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
phungductung 0:8ede47d38d10 270 }
phungductung 0:8ede47d38d10 271
phungductung 0:8ede47d38d10 272 /*-------------------------------------- I2C2 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 273 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
phungductung 0:8ede47d38d10 274 {
phungductung 0:8ede47d38d10 275 /* Check the parameters */
phungductung 0:8ede47d38d10 276 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
phungductung 0:8ede47d38d10 277
phungductung 0:8ede47d38d10 278 /* Configure the I2C2 clock source */
phungductung 0:8ede47d38d10 279 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
phungductung 0:8ede47d38d10 280 }
phungductung 0:8ede47d38d10 281
phungductung 0:8ede47d38d10 282 /*-------------------------------------- I2C3 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 283 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
phungductung 0:8ede47d38d10 284 {
phungductung 0:8ede47d38d10 285 /* Check the parameters */
phungductung 0:8ede47d38d10 286 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
phungductung 0:8ede47d38d10 287
phungductung 0:8ede47d38d10 288 /* Configure the I2C3 clock source */
phungductung 0:8ede47d38d10 289 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
phungductung 0:8ede47d38d10 290 }
phungductung 0:8ede47d38d10 291
phungductung 0:8ede47d38d10 292 /*-------------------------------------- I2C4 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 293 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
phungductung 0:8ede47d38d10 294 {
phungductung 0:8ede47d38d10 295 /* Check the parameters */
phungductung 0:8ede47d38d10 296 assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
phungductung 0:8ede47d38d10 297
phungductung 0:8ede47d38d10 298 /* Configure the I2C4 clock source */
phungductung 0:8ede47d38d10 299 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
phungductung 0:8ede47d38d10 300 }
phungductung 0:8ede47d38d10 301
phungductung 0:8ede47d38d10 302 /*-------------------------------------- USART1 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 303 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
phungductung 0:8ede47d38d10 304 {
phungductung 0:8ede47d38d10 305 /* Check the parameters */
phungductung 0:8ede47d38d10 306 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
phungductung 0:8ede47d38d10 307
phungductung 0:8ede47d38d10 308 /* Configure the USART1 clock source */
phungductung 0:8ede47d38d10 309 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
phungductung 0:8ede47d38d10 310 }
phungductung 0:8ede47d38d10 311
phungductung 0:8ede47d38d10 312 /*-------------------------------------- USART2 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 313 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
phungductung 0:8ede47d38d10 314 {
phungductung 0:8ede47d38d10 315 /* Check the parameters */
phungductung 0:8ede47d38d10 316 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
phungductung 0:8ede47d38d10 317
phungductung 0:8ede47d38d10 318 /* Configure the USART2 clock source */
phungductung 0:8ede47d38d10 319 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
phungductung 0:8ede47d38d10 320 }
phungductung 0:8ede47d38d10 321
phungductung 0:8ede47d38d10 322 /*-------------------------------------- USART3 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 323 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
phungductung 0:8ede47d38d10 324 {
phungductung 0:8ede47d38d10 325 /* Check the parameters */
phungductung 0:8ede47d38d10 326 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
phungductung 0:8ede47d38d10 327
phungductung 0:8ede47d38d10 328 /* Configure the USART3 clock source */
phungductung 0:8ede47d38d10 329 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
phungductung 0:8ede47d38d10 330 }
phungductung 0:8ede47d38d10 331
phungductung 0:8ede47d38d10 332 /*-------------------------------------- UART4 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 333 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
phungductung 0:8ede47d38d10 334 {
phungductung 0:8ede47d38d10 335 /* Check the parameters */
phungductung 0:8ede47d38d10 336 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
phungductung 0:8ede47d38d10 337
phungductung 0:8ede47d38d10 338 /* Configure the UART4 clock source */
phungductung 0:8ede47d38d10 339 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
phungductung 0:8ede47d38d10 340 }
phungductung 0:8ede47d38d10 341
phungductung 0:8ede47d38d10 342 /*-------------------------------------- UART5 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 343 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
phungductung 0:8ede47d38d10 344 {
phungductung 0:8ede47d38d10 345 /* Check the parameters */
phungductung 0:8ede47d38d10 346 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
phungductung 0:8ede47d38d10 347
phungductung 0:8ede47d38d10 348 /* Configure the UART5 clock source */
phungductung 0:8ede47d38d10 349 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
phungductung 0:8ede47d38d10 350 }
phungductung 0:8ede47d38d10 351
phungductung 0:8ede47d38d10 352 /*-------------------------------------- USART6 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 353 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
phungductung 0:8ede47d38d10 354 {
phungductung 0:8ede47d38d10 355 /* Check the parameters */
phungductung 0:8ede47d38d10 356 assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
phungductung 0:8ede47d38d10 357
phungductung 0:8ede47d38d10 358 /* Configure the USART6 clock source */
phungductung 0:8ede47d38d10 359 __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
phungductung 0:8ede47d38d10 360 }
phungductung 0:8ede47d38d10 361
phungductung 0:8ede47d38d10 362 /*-------------------------------------- UART7 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 363 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
phungductung 0:8ede47d38d10 364 {
phungductung 0:8ede47d38d10 365 /* Check the parameters */
phungductung 0:8ede47d38d10 366 assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
phungductung 0:8ede47d38d10 367
phungductung 0:8ede47d38d10 368 /* Configure the UART7 clock source */
phungductung 0:8ede47d38d10 369 __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
phungductung 0:8ede47d38d10 370 }
phungductung 0:8ede47d38d10 371
phungductung 0:8ede47d38d10 372 /*-------------------------------------- UART8 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 373 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
phungductung 0:8ede47d38d10 374 {
phungductung 0:8ede47d38d10 375 /* Check the parameters */
phungductung 0:8ede47d38d10 376 assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
phungductung 0:8ede47d38d10 377
phungductung 0:8ede47d38d10 378 /* Configure the UART8 clock source */
phungductung 0:8ede47d38d10 379 __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
phungductung 0:8ede47d38d10 380 }
phungductung 0:8ede47d38d10 381
phungductung 0:8ede47d38d10 382 /*--------------------------------------- CEC Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 383 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
phungductung 0:8ede47d38d10 384 {
phungductung 0:8ede47d38d10 385 /* Check the parameters */
phungductung 0:8ede47d38d10 386 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
phungductung 0:8ede47d38d10 387
phungductung 0:8ede47d38d10 388 /* Configure the CEC clock source */
phungductung 0:8ede47d38d10 389 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
phungductung 0:8ede47d38d10 390 }
phungductung 0:8ede47d38d10 391
phungductung 0:8ede47d38d10 392 /*-------------------------------------- CK48 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 393 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
phungductung 0:8ede47d38d10 394 {
phungductung 0:8ede47d38d10 395 /* Check the parameters */
phungductung 0:8ede47d38d10 396 assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
phungductung 0:8ede47d38d10 397
phungductung 0:8ede47d38d10 398 /* Configure the CLK48 source */
phungductung 0:8ede47d38d10 399 __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
phungductung 0:8ede47d38d10 400
phungductung 0:8ede47d38d10 401 /* Enable the PLLSAI when it's used as clock source for CK48 */
phungductung 0:8ede47d38d10 402 if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
phungductung 0:8ede47d38d10 403 {
phungductung 0:8ede47d38d10 404 pllsaiused = 1;
phungductung 0:8ede47d38d10 405 }
phungductung 0:8ede47d38d10 406 }
phungductung 0:8ede47d38d10 407
phungductung 0:8ede47d38d10 408 /*-------------------------------------- LTDC Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 409 #if defined(STM32F756xx) || defined(STM32F746xx)
phungductung 0:8ede47d38d10 410 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
phungductung 0:8ede47d38d10 411 {
phungductung 0:8ede47d38d10 412 pllsaiused = 1;
phungductung 0:8ede47d38d10 413 }
phungductung 0:8ede47d38d10 414 #endif /* STM32F756xx || STM32F746xx */
phungductung 0:8ede47d38d10 415 /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
phungductung 0:8ede47d38d10 416 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
phungductung 0:8ede47d38d10 417 {
phungductung 0:8ede47d38d10 418 /* Check the parameters */
phungductung 0:8ede47d38d10 419 assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
phungductung 0:8ede47d38d10 420
phungductung 0:8ede47d38d10 421 /* Configure the LTPIM1 clock source */
phungductung 0:8ede47d38d10 422 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
phungductung 0:8ede47d38d10 423 }
phungductung 0:8ede47d38d10 424
phungductung 0:8ede47d38d10 425 /*------------------------------------- SDMMC1 Configuration ------------------------------------*/
phungductung 0:8ede47d38d10 426 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
phungductung 0:8ede47d38d10 427 {
phungductung 0:8ede47d38d10 428 /* Check the parameters */
phungductung 0:8ede47d38d10 429 assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
phungductung 0:8ede47d38d10 430
phungductung 0:8ede47d38d10 431 /* Configure the SDMMC1 clock source */
phungductung 0:8ede47d38d10 432 __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
phungductung 0:8ede47d38d10 433 }
phungductung 0:8ede47d38d10 434
phungductung 0:8ede47d38d10 435 /*-------------------------------------- PLLI2S Configuration ---------------------------------*/
phungductung 0:8ede47d38d10 436 /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
phungductung 0:8ede47d38d10 437 if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
phungductung 0:8ede47d38d10 438 {
phungductung 0:8ede47d38d10 439 /* Disable the PLLI2S */
phungductung 0:8ede47d38d10 440 __HAL_RCC_PLLI2S_DISABLE();
phungductung 0:8ede47d38d10 441
phungductung 0:8ede47d38d10 442 /* Get Start Tick*/
phungductung 0:8ede47d38d10 443 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 444
phungductung 0:8ede47d38d10 445 /* Wait till PLLI2S is disabled */
phungductung 0:8ede47d38d10 446 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
phungductung 0:8ede47d38d10 447 {
phungductung 0:8ede47d38d10 448 if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 449 {
phungductung 0:8ede47d38d10 450 /* return in case of Timeout detected */
phungductung 0:8ede47d38d10 451 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 452 }
phungductung 0:8ede47d38d10 453 }
phungductung 0:8ede47d38d10 454
phungductung 0:8ede47d38d10 455 /* check for common PLLI2S Parameters */
phungductung 0:8ede47d38d10 456 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
phungductung 0:8ede47d38d10 457
phungductung 0:8ede47d38d10 458 /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
phungductung 0:8ede47d38d10 459 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
phungductung 0:8ede47d38d10 460 {
phungductung 0:8ede47d38d10 461 /* check for Parameters */
phungductung 0:8ede47d38d10 462 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
phungductung 0:8ede47d38d10 463
phungductung 0:8ede47d38d10 464 /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
phungductung 0:8ede47d38d10 465 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
phungductung 0:8ede47d38d10 466 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
phungductung 0:8ede47d38d10 467 /* Configure the PLLI2S division factors */
phungductung 0:8ede47d38d10 468 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
phungductung 0:8ede47d38d10 469 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
phungductung 0:8ede47d38d10 470 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
phungductung 0:8ede47d38d10 471 }
phungductung 0:8ede47d38d10 472
phungductung 0:8ede47d38d10 473 /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
phungductung 0:8ede47d38d10 474 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
phungductung 0:8ede47d38d10 475 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
phungductung 0:8ede47d38d10 476 {
phungductung 0:8ede47d38d10 477 /* Check for PLLI2S Parameters */
phungductung 0:8ede47d38d10 478 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
phungductung 0:8ede47d38d10 479 /* Check for PLLI2S/DIVQ parameters */
phungductung 0:8ede47d38d10 480 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
phungductung 0:8ede47d38d10 481
phungductung 0:8ede47d38d10 482 /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
phungductung 0:8ede47d38d10 483 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
phungductung 0:8ede47d38d10 484 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
phungductung 0:8ede47d38d10 485 /* Configure the PLLI2S division factors */
phungductung 0:8ede47d38d10 486 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 487 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
phungductung 0:8ede47d38d10 488 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
phungductung 0:8ede47d38d10 489 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
phungductung 0:8ede47d38d10 490
phungductung 0:8ede47d38d10 491 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
phungductung 0:8ede47d38d10 492 __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
phungductung 0:8ede47d38d10 493 }
phungductung 0:8ede47d38d10 494
phungductung 0:8ede47d38d10 495 /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
phungductung 0:8ede47d38d10 496 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
phungductung 0:8ede47d38d10 497 {
phungductung 0:8ede47d38d10 498 /* check for Parameters */
phungductung 0:8ede47d38d10 499 assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
phungductung 0:8ede47d38d10 500
phungductung 0:8ede47d38d10 501 /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
phungductung 0:8ede47d38d10 502 tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
phungductung 0:8ede47d38d10 503 tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
phungductung 0:8ede47d38d10 504 /* Configure the PLLI2S division factors */
phungductung 0:8ede47d38d10 505 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
phungductung 0:8ede47d38d10 506 /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
phungductung 0:8ede47d38d10 507 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
phungductung 0:8ede47d38d10 508 }
phungductung 0:8ede47d38d10 509
phungductung 0:8ede47d38d10 510 /*----------------- In Case of PLLI2S is just selected -----------------*/
phungductung 0:8ede47d38d10 511 if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
phungductung 0:8ede47d38d10 512 {
phungductung 0:8ede47d38d10 513 /* Check for Parameters */
phungductung 0:8ede47d38d10 514 assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
phungductung 0:8ede47d38d10 515 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
phungductung 0:8ede47d38d10 516 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
phungductung 0:8ede47d38d10 517
phungductung 0:8ede47d38d10 518 /* Configure the PLLI2S division factors */
phungductung 0:8ede47d38d10 519 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
phungductung 0:8ede47d38d10 520 /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
phungductung 0:8ede47d38d10 521 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
phungductung 0:8ede47d38d10 522 }
phungductung 0:8ede47d38d10 523
phungductung 0:8ede47d38d10 524 /* Enable the PLLI2S */
phungductung 0:8ede47d38d10 525 __HAL_RCC_PLLI2S_ENABLE();
phungductung 0:8ede47d38d10 526
phungductung 0:8ede47d38d10 527 /* Get Start Tick*/
phungductung 0:8ede47d38d10 528 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 529
phungductung 0:8ede47d38d10 530 /* Wait till PLLI2S is ready */
phungductung 0:8ede47d38d10 531 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
phungductung 0:8ede47d38d10 532 {
phungductung 0:8ede47d38d10 533 if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 534 {
phungductung 0:8ede47d38d10 535 /* return in case of Timeout detected */
phungductung 0:8ede47d38d10 536 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 537 }
phungductung 0:8ede47d38d10 538 }
phungductung 0:8ede47d38d10 539 }
phungductung 0:8ede47d38d10 540
phungductung 0:8ede47d38d10 541 /*-------------------------------------- PLLSAI Configuration ---------------------------------*/
phungductung 0:8ede47d38d10 542 /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
phungductung 0:8ede47d38d10 543 if(pllsaiused == 1)
phungductung 0:8ede47d38d10 544 {
phungductung 0:8ede47d38d10 545 /* Disable PLLSAI Clock */
phungductung 0:8ede47d38d10 546 __HAL_RCC_PLLSAI_DISABLE();
phungductung 0:8ede47d38d10 547
phungductung 0:8ede47d38d10 548 /* Get Start Tick*/
phungductung 0:8ede47d38d10 549 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 550
phungductung 0:8ede47d38d10 551 /* Wait till PLLSAI is disabled */
phungductung 0:8ede47d38d10 552 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
phungductung 0:8ede47d38d10 553 {
phungductung 0:8ede47d38d10 554 if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 555 {
phungductung 0:8ede47d38d10 556 /* return in case of Timeout detected */
phungductung 0:8ede47d38d10 557 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 558 }
phungductung 0:8ede47d38d10 559 }
phungductung 0:8ede47d38d10 560
phungductung 0:8ede47d38d10 561 /* Check the PLLSAI division factors */
phungductung 0:8ede47d38d10 562 assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
phungductung 0:8ede47d38d10 563
phungductung 0:8ede47d38d10 564 /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
phungductung 0:8ede47d38d10 565 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
phungductung 0:8ede47d38d10 566 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
phungductung 0:8ede47d38d10 567 {
phungductung 0:8ede47d38d10 568 /* check for PLLSAIQ Parameter */
phungductung 0:8ede47d38d10 569 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
phungductung 0:8ede47d38d10 570 /* check for PLLSAI/DIVQ Parameter */
phungductung 0:8ede47d38d10 571 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
phungductung 0:8ede47d38d10 572
phungductung 0:8ede47d38d10 573 /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
phungductung 0:8ede47d38d10 574 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
phungductung 0:8ede47d38d10 575 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
phungductung 0:8ede47d38d10 576 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 577 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:8ede47d38d10 578 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
phungductung 0:8ede47d38d10 579 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
phungductung 0:8ede47d38d10 580
phungductung 0:8ede47d38d10 581 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
phungductung 0:8ede47d38d10 582 __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
phungductung 0:8ede47d38d10 583 }
phungductung 0:8ede47d38d10 584
phungductung 0:8ede47d38d10 585 /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
phungductung 0:8ede47d38d10 586 /* In Case of PLLI2S is selected as source clock for CK48 */
phungductung 0:8ede47d38d10 587 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
phungductung 0:8ede47d38d10 588 {
phungductung 0:8ede47d38d10 589 /* check for Parameters */
phungductung 0:8ede47d38d10 590 assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
phungductung 0:8ede47d38d10 591 /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
phungductung 0:8ede47d38d10 592 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
phungductung 0:8ede47d38d10 593 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
phungductung 0:8ede47d38d10 594
phungductung 0:8ede47d38d10 595 /* Configure the PLLSAI division factors */
phungductung 0:8ede47d38d10 596 /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
phungductung 0:8ede47d38d10 597 /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
phungductung 0:8ede47d38d10 598 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
phungductung 0:8ede47d38d10 599 }
phungductung 0:8ede47d38d10 600
phungductung 0:8ede47d38d10 601 #if defined(STM32F756xx) || defined(STM32F746xx)
phungductung 0:8ede47d38d10 602 /*---------------------------- LTDC configuration -------------------------------*/
phungductung 0:8ede47d38d10 603 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
phungductung 0:8ede47d38d10 604 {
phungductung 0:8ede47d38d10 605 assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
phungductung 0:8ede47d38d10 606 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
phungductung 0:8ede47d38d10 607
phungductung 0:8ede47d38d10 608 /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
phungductung 0:8ede47d38d10 609 tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
phungductung 0:8ede47d38d10 610 tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
phungductung 0:8ede47d38d10 611
phungductung 0:8ede47d38d10 612 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 613 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:8ede47d38d10 614 /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
phungductung 0:8ede47d38d10 615 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
phungductung 0:8ede47d38d10 616
phungductung 0:8ede47d38d10 617 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
phungductung 0:8ede47d38d10 618 __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
phungductung 0:8ede47d38d10 619 }
phungductung 0:8ede47d38d10 620 #endif /* STM32F756xx || STM32F746xx */
phungductung 0:8ede47d38d10 621
phungductung 0:8ede47d38d10 622 /* Enable PLLSAI Clock */
phungductung 0:8ede47d38d10 623 __HAL_RCC_PLLSAI_ENABLE();
phungductung 0:8ede47d38d10 624
phungductung 0:8ede47d38d10 625 /* Get Start Tick*/
phungductung 0:8ede47d38d10 626 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 627
phungductung 0:8ede47d38d10 628 /* Wait till PLLSAI is ready */
phungductung 0:8ede47d38d10 629 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
phungductung 0:8ede47d38d10 630 {
phungductung 0:8ede47d38d10 631 if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 632 {
phungductung 0:8ede47d38d10 633 /* return in case of Timeout detected */
phungductung 0:8ede47d38d10 634 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 635 }
phungductung 0:8ede47d38d10 636 }
phungductung 0:8ede47d38d10 637 }
phungductung 0:8ede47d38d10 638 return HAL_OK;
phungductung 0:8ede47d38d10 639 }
phungductung 0:8ede47d38d10 640
phungductung 0:8ede47d38d10 641 /**
phungductung 0:8ede47d38d10 642 * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
phungductung 0:8ede47d38d10 643 * RCC configuration registers.
phungductung 0:8ede47d38d10 644 * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
phungductung 0:8ede47d38d10 645 * @retval None
phungductung 0:8ede47d38d10 646 */
phungductung 0:8ede47d38d10 647 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
phungductung 0:8ede47d38d10 648 {
phungductung 0:8ede47d38d10 649 uint32_t tempreg = 0;
phungductung 0:8ede47d38d10 650
phungductung 0:8ede47d38d10 651 /* Set all possible values for the extended clock type parameter------------*/
phungductung 0:8ede47d38d10 652 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
phungductung 0:8ede47d38d10 653 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
phungductung 0:8ede47d38d10 654 RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
phungductung 0:8ede47d38d10 655 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
phungductung 0:8ede47d38d10 656 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
phungductung 0:8ede47d38d10 657 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
phungductung 0:8ede47d38d10 658 RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
phungductung 0:8ede47d38d10 659 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
phungductung 0:8ede47d38d10 660 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
phungductung 0:8ede47d38d10 661 RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
phungductung 0:8ede47d38d10 662 RCC_PERIPHCLK_CLK48;
phungductung 0:8ede47d38d10 663
phungductung 0:8ede47d38d10 664
phungductung 0:8ede47d38d10 665 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 666 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
phungductung 0:8ede47d38d10 667 PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
phungductung 0:8ede47d38d10 668 PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
phungductung 0:8ede47d38d10 669 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
phungductung 0:8ede47d38d10 670
phungductung 0:8ede47d38d10 671 /* Get the PLLSAI Clock configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 672 PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
phungductung 0:8ede47d38d10 673 PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
phungductung 0:8ede47d38d10 674 PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
phungductung 0:8ede47d38d10 675 PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
phungductung 0:8ede47d38d10 676
phungductung 0:8ede47d38d10 677 /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
phungductung 0:8ede47d38d10 678 PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
phungductung 0:8ede47d38d10 679 PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
phungductung 0:8ede47d38d10 680 PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
phungductung 0:8ede47d38d10 681
phungductung 0:8ede47d38d10 682 /* Get the SAI1 clock configuration ----------------------------------------------*/
phungductung 0:8ede47d38d10 683 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
phungductung 0:8ede47d38d10 684
phungductung 0:8ede47d38d10 685 /* Get the SAI2 clock configuration ----------------------------------------------*/
phungductung 0:8ede47d38d10 686 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
phungductung 0:8ede47d38d10 687
phungductung 0:8ede47d38d10 688 /* Get the I2S clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 689 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE();
phungductung 0:8ede47d38d10 690
phungductung 0:8ede47d38d10 691 /* Get the I2C1 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 692 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
phungductung 0:8ede47d38d10 693
phungductung 0:8ede47d38d10 694 /* Get the I2C2 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 695 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
phungductung 0:8ede47d38d10 696
phungductung 0:8ede47d38d10 697 /* Get the I2C3 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 698 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
phungductung 0:8ede47d38d10 699
phungductung 0:8ede47d38d10 700 /* Get the I2C4 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 701 PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
phungductung 0:8ede47d38d10 702
phungductung 0:8ede47d38d10 703 /* Get the USART1 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 704 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
phungductung 0:8ede47d38d10 705
phungductung 0:8ede47d38d10 706 /* Get the USART2 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 707 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
phungductung 0:8ede47d38d10 708
phungductung 0:8ede47d38d10 709 /* Get the USART3 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 710 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
phungductung 0:8ede47d38d10 711
phungductung 0:8ede47d38d10 712 /* Get the UART4 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 713 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
phungductung 0:8ede47d38d10 714
phungductung 0:8ede47d38d10 715 /* Get the UART5 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 716 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
phungductung 0:8ede47d38d10 717
phungductung 0:8ede47d38d10 718 /* Get the USART6 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 719 PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
phungductung 0:8ede47d38d10 720
phungductung 0:8ede47d38d10 721 /* Get the UART7 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 722 PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE();
phungductung 0:8ede47d38d10 723
phungductung 0:8ede47d38d10 724 /* Get the UART8 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 725 PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE();
phungductung 0:8ede47d38d10 726
phungductung 0:8ede47d38d10 727 /* Get the LPTIM1 clock configuration ------------------------------------------*/
phungductung 0:8ede47d38d10 728 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
phungductung 0:8ede47d38d10 729
phungductung 0:8ede47d38d10 730 /* Get the CEC clock configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 731 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
phungductung 0:8ede47d38d10 732
phungductung 0:8ede47d38d10 733 /* Get the CK48 clock configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 734 PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
phungductung 0:8ede47d38d10 735
phungductung 0:8ede47d38d10 736 /* Get the SDMMC clock configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 737 PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
phungductung 0:8ede47d38d10 738
phungductung 0:8ede47d38d10 739 /* Get the RTC Clock configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 740 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
phungductung 0:8ede47d38d10 741 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
phungductung 0:8ede47d38d10 742
phungductung 0:8ede47d38d10 743 /* Get the TIM Prescaler configuration --------------------------------------------*/
phungductung 0:8ede47d38d10 744 if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET)
phungductung 0:8ede47d38d10 745 {
phungductung 0:8ede47d38d10 746 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
phungductung 0:8ede47d38d10 747 }
phungductung 0:8ede47d38d10 748 else
phungductung 0:8ede47d38d10 749 {
phungductung 0:8ede47d38d10 750 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
phungductung 0:8ede47d38d10 751 }
phungductung 0:8ede47d38d10 752 }
phungductung 0:8ede47d38d10 753
phungductung 0:8ede47d38d10 754 /**
phungductung 0:8ede47d38d10 755 * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
phungductung 0:8ede47d38d10 756 * @note Return 0 if peripheral clock identifier not managed by this API
phungductung 0:8ede47d38d10 757 * @param PeriphClk: Peripheral clock identifier
phungductung 0:8ede47d38d10 758 * This parameter can be one of the following values:
phungductung 0:8ede47d38d10 759 * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
phungductung 0:8ede47d38d10 760 * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
phungductung 0:8ede47d38d10 761 * @retval Frequency in KHz
phungductung 0:8ede47d38d10 762 */
phungductung 0:8ede47d38d10 763 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
phungductung 0:8ede47d38d10 764 {
phungductung 0:8ede47d38d10 765 uint32_t tmpreg = 0;
phungductung 0:8ede47d38d10 766 /* This variable is used to store the SAI clock frequency (value in Hz) */
phungductung 0:8ede47d38d10 767 uint32_t frequency = 0;
phungductung 0:8ede47d38d10 768 /* This variable is used to store the VCO Input (value in Hz) */
phungductung 0:8ede47d38d10 769 uint32_t vcoinput = 0;
phungductung 0:8ede47d38d10 770 /* This variable is used to store the SAI clock source */
phungductung 0:8ede47d38d10 771 uint32_t saiclocksource = 0;
phungductung 0:8ede47d38d10 772
phungductung 0:8ede47d38d10 773 if (PeriphClk == RCC_PERIPHCLK_SAI1)
phungductung 0:8ede47d38d10 774 {
phungductung 0:8ede47d38d10 775 saiclocksource = RCC->DCKCFGR1;
phungductung 0:8ede47d38d10 776 saiclocksource &= RCC_DCKCFGR1_SAI1SEL;
phungductung 0:8ede47d38d10 777 switch (saiclocksource)
phungductung 0:8ede47d38d10 778 {
phungductung 0:8ede47d38d10 779 case 0: /* PLLSAI is the clock source for SAI1 */
phungductung 0:8ede47d38d10 780 {
phungductung 0:8ede47d38d10 781 /* Configure the PLLSAI division factor */
phungductung 0:8ede47d38d10 782 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 783 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:8ede47d38d10 784 {
phungductung 0:8ede47d38d10 785 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:8ede47d38d10 786 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:8ede47d38d10 787 }
phungductung 0:8ede47d38d10 788 else
phungductung 0:8ede47d38d10 789 {
phungductung 0:8ede47d38d10 790 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:8ede47d38d10 791 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:8ede47d38d10 792 }
phungductung 0:8ede47d38d10 793 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:8ede47d38d10 794 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
phungductung 0:8ede47d38d10 795 tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
phungductung 0:8ede47d38d10 796 frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
phungductung 0:8ede47d38d10 797
phungductung 0:8ede47d38d10 798 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
phungductung 0:8ede47d38d10 799 tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
phungductung 0:8ede47d38d10 800 frequency = frequency/(tmpreg);
phungductung 0:8ede47d38d10 801 break;
phungductung 0:8ede47d38d10 802 }
phungductung 0:8ede47d38d10 803 case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */
phungductung 0:8ede47d38d10 804 {
phungductung 0:8ede47d38d10 805 /* Configure the PLLI2S division factor */
phungductung 0:8ede47d38d10 806 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 807 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:8ede47d38d10 808 {
phungductung 0:8ede47d38d10 809 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:8ede47d38d10 810 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:8ede47d38d10 811 }
phungductung 0:8ede47d38d10 812 else
phungductung 0:8ede47d38d10 813 {
phungductung 0:8ede47d38d10 814 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:8ede47d38d10 815 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:8ede47d38d10 816 }
phungductung 0:8ede47d38d10 817
phungductung 0:8ede47d38d10 818 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
phungductung 0:8ede47d38d10 819 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
phungductung 0:8ede47d38d10 820 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
phungductung 0:8ede47d38d10 821 frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
phungductung 0:8ede47d38d10 822
phungductung 0:8ede47d38d10 823 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
phungductung 0:8ede47d38d10 824 tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
phungductung 0:8ede47d38d10 825 frequency = frequency/(tmpreg);
phungductung 0:8ede47d38d10 826 break;
phungductung 0:8ede47d38d10 827 }
phungductung 0:8ede47d38d10 828 case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */
phungductung 0:8ede47d38d10 829 {
phungductung 0:8ede47d38d10 830 frequency = EXTERNAL_CLOCK_VALUE;
phungductung 0:8ede47d38d10 831 break;
phungductung 0:8ede47d38d10 832 }
phungductung 0:8ede47d38d10 833 default :
phungductung 0:8ede47d38d10 834 {
phungductung 0:8ede47d38d10 835 break;
phungductung 0:8ede47d38d10 836 }
phungductung 0:8ede47d38d10 837 }
phungductung 0:8ede47d38d10 838 }
phungductung 0:8ede47d38d10 839
phungductung 0:8ede47d38d10 840 if (PeriphClk == RCC_PERIPHCLK_SAI2)
phungductung 0:8ede47d38d10 841 {
phungductung 0:8ede47d38d10 842 saiclocksource = RCC->DCKCFGR1;
phungductung 0:8ede47d38d10 843 saiclocksource &= RCC_DCKCFGR1_SAI2SEL;
phungductung 0:8ede47d38d10 844 switch (saiclocksource)
phungductung 0:8ede47d38d10 845 {
phungductung 0:8ede47d38d10 846 case 0: /* PLLSAI is the clock source for SAI*/
phungductung 0:8ede47d38d10 847 {
phungductung 0:8ede47d38d10 848 /* Configure the PLLSAI division factor */
phungductung 0:8ede47d38d10 849 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 850 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:8ede47d38d10 851 {
phungductung 0:8ede47d38d10 852 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:8ede47d38d10 853 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:8ede47d38d10 854 }
phungductung 0:8ede47d38d10 855 else
phungductung 0:8ede47d38d10 856 {
phungductung 0:8ede47d38d10 857 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:8ede47d38d10 858 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:8ede47d38d10 859 }
phungductung 0:8ede47d38d10 860 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
phungductung 0:8ede47d38d10 861 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
phungductung 0:8ede47d38d10 862 tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
phungductung 0:8ede47d38d10 863 frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg);
phungductung 0:8ede47d38d10 864
phungductung 0:8ede47d38d10 865 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
phungductung 0:8ede47d38d10 866 tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1);
phungductung 0:8ede47d38d10 867 frequency = frequency/(tmpreg);
phungductung 0:8ede47d38d10 868 break;
phungductung 0:8ede47d38d10 869 }
phungductung 0:8ede47d38d10 870 case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */
phungductung 0:8ede47d38d10 871 {
phungductung 0:8ede47d38d10 872 /* Configure the PLLI2S division factor */
phungductung 0:8ede47d38d10 873 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
phungductung 0:8ede47d38d10 874 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
phungductung 0:8ede47d38d10 875 {
phungductung 0:8ede47d38d10 876 /* In Case the PLL Source is HSI (Internal Clock) */
phungductung 0:8ede47d38d10 877 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
phungductung 0:8ede47d38d10 878 }
phungductung 0:8ede47d38d10 879 else
phungductung 0:8ede47d38d10 880 {
phungductung 0:8ede47d38d10 881 /* In Case the PLL Source is HSE (External Clock) */
phungductung 0:8ede47d38d10 882 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
phungductung 0:8ede47d38d10 883 }
phungductung 0:8ede47d38d10 884
phungductung 0:8ede47d38d10 885 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
phungductung 0:8ede47d38d10 886 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
phungductung 0:8ede47d38d10 887 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
phungductung 0:8ede47d38d10 888 frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
phungductung 0:8ede47d38d10 889
phungductung 0:8ede47d38d10 890 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
phungductung 0:8ede47d38d10 891 tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1);
phungductung 0:8ede47d38d10 892 frequency = frequency/(tmpreg);
phungductung 0:8ede47d38d10 893 break;
phungductung 0:8ede47d38d10 894 }
phungductung 0:8ede47d38d10 895 case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */
phungductung 0:8ede47d38d10 896 {
phungductung 0:8ede47d38d10 897 frequency = EXTERNAL_CLOCK_VALUE;
phungductung 0:8ede47d38d10 898 break;
phungductung 0:8ede47d38d10 899 }
phungductung 0:8ede47d38d10 900 default :
phungductung 0:8ede47d38d10 901 {
phungductung 0:8ede47d38d10 902 break;
phungductung 0:8ede47d38d10 903 }
phungductung 0:8ede47d38d10 904 }
phungductung 0:8ede47d38d10 905 }
phungductung 0:8ede47d38d10 906
phungductung 0:8ede47d38d10 907 return frequency;
phungductung 0:8ede47d38d10 908 }
phungductung 0:8ede47d38d10 909 /**
phungductung 0:8ede47d38d10 910 * @}
phungductung 0:8ede47d38d10 911 */
phungductung 0:8ede47d38d10 912
phungductung 0:8ede47d38d10 913 /**
phungductung 0:8ede47d38d10 914 * @}
phungductung 0:8ede47d38d10 915 */
phungductung 0:8ede47d38d10 916
phungductung 0:8ede47d38d10 917 #endif /* HAL_RCC_MODULE_ENABLED */
phungductung 0:8ede47d38d10 918 /**
phungductung 0:8ede47d38d10 919 * @}
phungductung 0:8ede47d38d10 920 */
phungductung 0:8ede47d38d10 921
phungductung 0:8ede47d38d10 922 /**
phungductung 0:8ede47d38d10 923 * @}
phungductung 0:8ede47d38d10 924 */
phungductung 0:8ede47d38d10 925
phungductung 0:8ede47d38d10 926 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/