PHung Tung / DISCO-F746_WAV_PLAYER

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SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:37:21 2019 +0000
Revision:
0:8ede47d38d10
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phungductung 0:8ede47d38d10 1 /**
phungductung 0:8ede47d38d10 2 ******************************************************************************
phungductung 0:8ede47d38d10 3 * @file stm32f7xx_hal_rcc.c
phungductung 0:8ede47d38d10 4 * @author MCD Application Team
phungductung 0:8ede47d38d10 5 * @version V1.0.4
phungductung 0:8ede47d38d10 6 * @date 09-December-2015
phungductung 0:8ede47d38d10 7 * @brief RCC HAL module driver.
phungductung 0:8ede47d38d10 8 * This file provides firmware functions to manage the following
phungductung 0:8ede47d38d10 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
phungductung 0:8ede47d38d10 10 * + Initialization and de-initialization functions
phungductung 0:8ede47d38d10 11 * + Peripheral Control functions
phungductung 0:8ede47d38d10 12 *
phungductung 0:8ede47d38d10 13 @verbatim
phungductung 0:8ede47d38d10 14 ==============================================================================
phungductung 0:8ede47d38d10 15 ##### RCC specific features #####
phungductung 0:8ede47d38d10 16 ==============================================================================
phungductung 0:8ede47d38d10 17 [..]
phungductung 0:8ede47d38d10 18 After reset the device is running from Internal High Speed oscillator
phungductung 0:8ede47d38d10 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
phungductung 0:8ede47d38d10 20 and I-Cache are disabled, and all peripherals are off except internal
phungductung 0:8ede47d38d10 21 SRAM, Flash and JTAG.
phungductung 0:8ede47d38d10 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
phungductung 0:8ede47d38d10 23 all peripherals mapped on these busses are running at HSI speed.
phungductung 0:8ede47d38d10 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
phungductung 0:8ede47d38d10 25 (+) All GPIOs are in input floating state, except the JTAG pins which
phungductung 0:8ede47d38d10 26 are assigned to be used for debug purpose.
phungductung 0:8ede47d38d10 27
phungductung 0:8ede47d38d10 28 [..]
phungductung 0:8ede47d38d10 29 Once the device started from reset, the user application has to:
phungductung 0:8ede47d38d10 30 (+) Configure the clock source to be used to drive the System clock
phungductung 0:8ede47d38d10 31 (if the application needs higher frequency/performance)
phungductung 0:8ede47d38d10 32 (+) Configure the System clock frequency and Flash settings
phungductung 0:8ede47d38d10 33 (+) Configure the AHB and APB busses prescalers
phungductung 0:8ede47d38d10 34 (+) Enable the clock for the peripheral(s) to be used
phungductung 0:8ede47d38d10 35 (+) Configure the clock source(s) for peripherals which clocks are not
phungductung 0:8ede47d38d10 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
phungductung 0:8ede47d38d10 37
phungductung 0:8ede47d38d10 38 ##### RCC Limitations #####
phungductung 0:8ede47d38d10 39 ==============================================================================
phungductung 0:8ede47d38d10 40 [..]
phungductung 0:8ede47d38d10 41 A delay between an RCC peripheral clock enable and the effective peripheral
phungductung 0:8ede47d38d10 42 enabling should be taken into account in order to manage the peripheral read/write
phungductung 0:8ede47d38d10 43 from/to registers.
phungductung 0:8ede47d38d10 44 (+) This delay depends on the peripheral mapping.
phungductung 0:8ede47d38d10 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
phungductung 0:8ede47d38d10 46 after the clock enable bit is set on the hardware register
phungductung 0:8ede47d38d10 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
phungductung 0:8ede47d38d10 48 after the clock enable bit is set on the hardware register
phungductung 0:8ede47d38d10 49
phungductung 0:8ede47d38d10 50 [..]
phungductung 0:8ede47d38d10 51 Implemented Workaround:
phungductung 0:8ede47d38d10 52 (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
phungductung 0:8ede47d38d10 53 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
phungductung 0:8ede47d38d10 54
phungductung 0:8ede47d38d10 55 @endverbatim
phungductung 0:8ede47d38d10 56 ******************************************************************************
phungductung 0:8ede47d38d10 57 * @attention
phungductung 0:8ede47d38d10 58 *
phungductung 0:8ede47d38d10 59 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:8ede47d38d10 60 *
phungductung 0:8ede47d38d10 61 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:8ede47d38d10 62 * are permitted provided that the following conditions are met:
phungductung 0:8ede47d38d10 63 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:8ede47d38d10 64 * this list of conditions and the following disclaimer.
phungductung 0:8ede47d38d10 65 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:8ede47d38d10 66 * this list of conditions and the following disclaimer in the documentation
phungductung 0:8ede47d38d10 67 * and/or other materials provided with the distribution.
phungductung 0:8ede47d38d10 68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:8ede47d38d10 69 * may be used to endorse or promote products derived from this software
phungductung 0:8ede47d38d10 70 * without specific prior written permission.
phungductung 0:8ede47d38d10 71 *
phungductung 0:8ede47d38d10 72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:8ede47d38d10 73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:8ede47d38d10 74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:8ede47d38d10 75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:8ede47d38d10 76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:8ede47d38d10 77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:8ede47d38d10 78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:8ede47d38d10 79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:8ede47d38d10 80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:8ede47d38d10 81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:8ede47d38d10 82 *
phungductung 0:8ede47d38d10 83 ******************************************************************************
phungductung 0:8ede47d38d10 84 */
phungductung 0:8ede47d38d10 85
phungductung 0:8ede47d38d10 86 /* Includes ------------------------------------------------------------------*/
phungductung 0:8ede47d38d10 87 #include "stm32f7xx_hal.h"
phungductung 0:8ede47d38d10 88
phungductung 0:8ede47d38d10 89 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:8ede47d38d10 90 * @{
phungductung 0:8ede47d38d10 91 */
phungductung 0:8ede47d38d10 92
phungductung 0:8ede47d38d10 93 /** @defgroup RCC RCC
phungductung 0:8ede47d38d10 94 * @brief RCC HAL module driver
phungductung 0:8ede47d38d10 95 * @{
phungductung 0:8ede47d38d10 96 */
phungductung 0:8ede47d38d10 97
phungductung 0:8ede47d38d10 98 #ifdef HAL_RCC_MODULE_ENABLED
phungductung 0:8ede47d38d10 99
phungductung 0:8ede47d38d10 100 /* Private typedef -----------------------------------------------------------*/
phungductung 0:8ede47d38d10 101 /* Private define ------------------------------------------------------------*/
phungductung 0:8ede47d38d10 102 /* Private macro -------------------------------------------------------------*/
phungductung 0:8ede47d38d10 103 /** @defgroup RCC_Private_Macros RCC Private Macros
phungductung 0:8ede47d38d10 104 * @{
phungductung 0:8ede47d38d10 105 */
phungductung 0:8ede47d38d10 106
phungductung 0:8ede47d38d10 107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
phungductung 0:8ede47d38d10 108 #define MCO1_GPIO_PORT GPIOA
phungductung 0:8ede47d38d10 109 #define MCO1_PIN GPIO_PIN_8
phungductung 0:8ede47d38d10 110
phungductung 0:8ede47d38d10 111 #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
phungductung 0:8ede47d38d10 112 #define MCO2_GPIO_PORT GPIOC
phungductung 0:8ede47d38d10 113 #define MCO2_PIN GPIO_PIN_9
phungductung 0:8ede47d38d10 114
phungductung 0:8ede47d38d10 115 /**
phungductung 0:8ede47d38d10 116 * @}
phungductung 0:8ede47d38d10 117 */
phungductung 0:8ede47d38d10 118 /* Private variables ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 119 /** @defgroup RCC_Private_Variables RCC Private Variables
phungductung 0:8ede47d38d10 120 * @{
phungductung 0:8ede47d38d10 121 */
phungductung 0:8ede47d38d10 122 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
phungductung 0:8ede47d38d10 123
phungductung 0:8ede47d38d10 124 /**
phungductung 0:8ede47d38d10 125 * @}
phungductung 0:8ede47d38d10 126 */
phungductung 0:8ede47d38d10 127
phungductung 0:8ede47d38d10 128 /* Private function prototypes -----------------------------------------------*/
phungductung 0:8ede47d38d10 129 /* Exported functions ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 130
phungductung 0:8ede47d38d10 131 /** @defgroup RCC_Exported_Functions RCC Exported Functions
phungductung 0:8ede47d38d10 132 * @{
phungductung 0:8ede47d38d10 133 */
phungductung 0:8ede47d38d10 134
phungductung 0:8ede47d38d10 135 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung 0:8ede47d38d10 136 * @brief Initialization and Configuration functions
phungductung 0:8ede47d38d10 137 *
phungductung 0:8ede47d38d10 138 @verbatim
phungductung 0:8ede47d38d10 139 ===============================================================================
phungductung 0:8ede47d38d10 140 ##### Initialization and de-initialization functions #####
phungductung 0:8ede47d38d10 141 ===============================================================================
phungductung 0:8ede47d38d10 142 [..]
phungductung 0:8ede47d38d10 143 This section provides functions allowing to configure the internal/external oscillators
phungductung 0:8ede47d38d10 144 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
phungductung 0:8ede47d38d10 145 and APB2).
phungductung 0:8ede47d38d10 146
phungductung 0:8ede47d38d10 147 [..] Internal/external clock and PLL configuration
phungductung 0:8ede47d38d10 148 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
phungductung 0:8ede47d38d10 149 the PLL as System clock source.
phungductung 0:8ede47d38d10 150
phungductung 0:8ede47d38d10 151 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
phungductung 0:8ede47d38d10 152 clock source.
phungductung 0:8ede47d38d10 153
phungductung 0:8ede47d38d10 154 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
phungductung 0:8ede47d38d10 155 through the PLL as System clock source. Can be used also as RTC clock source.
phungductung 0:8ede47d38d10 156
phungductung 0:8ede47d38d10 157 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
phungductung 0:8ede47d38d10 158
phungductung 0:8ede47d38d10 159 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
phungductung 0:8ede47d38d10 160 (++) The first output is used to generate the high speed system clock (up to 216 MHz)
phungductung 0:8ede47d38d10 161 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
phungductung 0:8ede47d38d10 162 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
phungductung 0:8ede47d38d10 163
phungductung 0:8ede47d38d10 164 (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
phungductung 0:8ede47d38d10 165 and if a HSE clock failure occurs(HSE used directly or through PLL as System
phungductung 0:8ede47d38d10 166 clock source), the System clock is automatically switched to HSI and an interrupt
phungductung 0:8ede47d38d10 167 is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
phungductung 0:8ede47d38d10 168 (Non-Maskable Interrupt) exception vector.
phungductung 0:8ede47d38d10 169
phungductung 0:8ede47d38d10 170 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
phungductung 0:8ede47d38d10 171 clock (through a configurable prescaler) on PA8 pin.
phungductung 0:8ede47d38d10 172
phungductung 0:8ede47d38d10 173 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
phungductung 0:8ede47d38d10 174 clock (through a configurable prescaler) on PC9 pin.
phungductung 0:8ede47d38d10 175
phungductung 0:8ede47d38d10 176 [..] System, AHB and APB busses clocks configuration
phungductung 0:8ede47d38d10 177 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
phungductung 0:8ede47d38d10 178 HSE and PLL.
phungductung 0:8ede47d38d10 179 The AHB clock (HCLK) is derived from System clock through configurable
phungductung 0:8ede47d38d10 180 prescaler and used to clock the CPU, memory and peripherals mapped
phungductung 0:8ede47d38d10 181 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
phungductung 0:8ede47d38d10 182 from AHB clock through configurable prescalers and used to clock
phungductung 0:8ede47d38d10 183 the peripherals mapped on these busses. You can use
phungductung 0:8ede47d38d10 184 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
phungductung 0:8ede47d38d10 185
phungductung 0:8ede47d38d10 186 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
phungductung 0:8ede47d38d10 187 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
phungductung 0:8ede47d38d10 188 from an external clock mapped on the I2S_CKIN pin.
phungductung 0:8ede47d38d10 189 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
phungductung 0:8ede47d38d10 190 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
phungductung 0:8ede47d38d10 191 from an external clock mapped on the I2S_CKIN pin.
phungductung 0:8ede47d38d10 192 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
phungductung 0:8ede47d38d10 193 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
phungductung 0:8ede47d38d10 194 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
phungductung 0:8ede47d38d10 195 macros to configure this clock.
phungductung 0:8ede47d38d10 196 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
phungductung 0:8ede47d38d10 197 to work correctly, while the SDIO require a frequency equal or lower than
phungductung 0:8ede47d38d10 198 to 48. This clock is derived of the main PLL through PLLQ divider.
phungductung 0:8ede47d38d10 199 (+@) IWDG clock which is always the LSI clock.
phungductung 0:8ede47d38d10 200 @endverbatim
phungductung 0:8ede47d38d10 201 * @{
phungductung 0:8ede47d38d10 202 */
phungductung 0:8ede47d38d10 203
phungductung 0:8ede47d38d10 204 /**
phungductung 0:8ede47d38d10 205 * @brief Resets the RCC clock configuration to the default reset state.
phungductung 0:8ede47d38d10 206 * @note The default reset state of the clock configuration is given below:
phungductung 0:8ede47d38d10 207 * - HSI ON and used as system clock source
phungductung 0:8ede47d38d10 208 * - HSE, PLL and PLLI2S OFF
phungductung 0:8ede47d38d10 209 * - AHB, APB1 and APB2 prescaler set to 1.
phungductung 0:8ede47d38d10 210 * - CSS, MCO1 and MCO2 OFF
phungductung 0:8ede47d38d10 211 * - All interrupts disabled
phungductung 0:8ede47d38d10 212 * @note This function doesn't modify the configuration of the
phungductung 0:8ede47d38d10 213 * - Peripheral clocks
phungductung 0:8ede47d38d10 214 * - LSI, LSE and RTC clocks
phungductung 0:8ede47d38d10 215 * @retval None
phungductung 0:8ede47d38d10 216 */
phungductung 0:8ede47d38d10 217 void HAL_RCC_DeInit(void)
phungductung 0:8ede47d38d10 218 {
phungductung 0:8ede47d38d10 219 /* Set HSION bit */
phungductung 0:8ede47d38d10 220 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
phungductung 0:8ede47d38d10 221
phungductung 0:8ede47d38d10 222 /* Reset CFGR register */
phungductung 0:8ede47d38d10 223 CLEAR_REG(RCC->CFGR);
phungductung 0:8ede47d38d10 224
phungductung 0:8ede47d38d10 225 /* Reset HSEON, CSSON, PLLON, PLLI2S */
phungductung 0:8ede47d38d10 226 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
phungductung 0:8ede47d38d10 227
phungductung 0:8ede47d38d10 228 /* Reset PLLCFGR register */
phungductung 0:8ede47d38d10 229 CLEAR_REG(RCC->PLLCFGR);
phungductung 0:8ede47d38d10 230 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
phungductung 0:8ede47d38d10 231
phungductung 0:8ede47d38d10 232 /* Reset PLLI2SCFGR register */
phungductung 0:8ede47d38d10 233 CLEAR_REG(RCC->PLLI2SCFGR);
phungductung 0:8ede47d38d10 234 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
phungductung 0:8ede47d38d10 235
phungductung 0:8ede47d38d10 236 /* Reset HSEBYP bit */
phungductung 0:8ede47d38d10 237 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
phungductung 0:8ede47d38d10 238
phungductung 0:8ede47d38d10 239 /* Disable all interrupts */
phungductung 0:8ede47d38d10 240 CLEAR_REG(RCC->CIR);
phungductung 0:8ede47d38d10 241 }
phungductung 0:8ede47d38d10 242
phungductung 0:8ede47d38d10 243 /**
phungductung 0:8ede47d38d10 244 * @brief Initializes the RCC Oscillators according to the specified parameters in the
phungductung 0:8ede47d38d10 245 * RCC_OscInitTypeDef.
phungductung 0:8ede47d38d10 246 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
phungductung 0:8ede47d38d10 247 * contains the configuration information for the RCC Oscillators.
phungductung 0:8ede47d38d10 248 * @note The PLL is not disabled when used as system clock.
phungductung 0:8ede47d38d10 249 * @retval HAL status
phungductung 0:8ede47d38d10 250 */
phungductung 0:8ede47d38d10 251 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
phungductung 0:8ede47d38d10 252 {
phungductung 0:8ede47d38d10 253 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 254
phungductung 0:8ede47d38d10 255 /* Check the parameters */
phungductung 0:8ede47d38d10 256 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
phungductung 0:8ede47d38d10 257
phungductung 0:8ede47d38d10 258 /*------------------------------- HSE Configuration ------------------------*/
phungductung 0:8ede47d38d10 259 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
phungductung 0:8ede47d38d10 260 {
phungductung 0:8ede47d38d10 261 /* Check the parameters */
phungductung 0:8ede47d38d10 262 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
phungductung 0:8ede47d38d10 263 /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
phungductung 0:8ede47d38d10 264 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
phungductung 0:8ede47d38d10 265 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
phungductung 0:8ede47d38d10 266 {
phungductung 0:8ede47d38d10 267 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
phungductung 0:8ede47d38d10 268 {
phungductung 0:8ede47d38d10 269 return HAL_ERROR;
phungductung 0:8ede47d38d10 270 }
phungductung 0:8ede47d38d10 271 }
phungductung 0:8ede47d38d10 272 else
phungductung 0:8ede47d38d10 273 {
phungductung 0:8ede47d38d10 274 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
phungductung 0:8ede47d38d10 275 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
phungductung 0:8ede47d38d10 276
phungductung 0:8ede47d38d10 277 /* Get Start Tick*/
phungductung 0:8ede47d38d10 278 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 279
phungductung 0:8ede47d38d10 280 /* Wait till HSE is disabled */
phungductung 0:8ede47d38d10 281 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
phungductung 0:8ede47d38d10 282 {
phungductung 0:8ede47d38d10 283 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 284 {
phungductung 0:8ede47d38d10 285 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 286 }
phungductung 0:8ede47d38d10 287 }
phungductung 0:8ede47d38d10 288
phungductung 0:8ede47d38d10 289 /* Set the new HSE configuration ---------------------------------------*/
phungductung 0:8ede47d38d10 290 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
phungductung 0:8ede47d38d10 291
phungductung 0:8ede47d38d10 292 /* Check the HSE State */
phungductung 0:8ede47d38d10 293 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
phungductung 0:8ede47d38d10 294 {
phungductung 0:8ede47d38d10 295 /* Get Start Tick*/
phungductung 0:8ede47d38d10 296 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 297
phungductung 0:8ede47d38d10 298 /* Wait till HSE is ready */
phungductung 0:8ede47d38d10 299 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
phungductung 0:8ede47d38d10 300 {
phungductung 0:8ede47d38d10 301 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 302 {
phungductung 0:8ede47d38d10 303 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 304 }
phungductung 0:8ede47d38d10 305 }
phungductung 0:8ede47d38d10 306 }
phungductung 0:8ede47d38d10 307 else
phungductung 0:8ede47d38d10 308 {
phungductung 0:8ede47d38d10 309 /* Get Start Tick*/
phungductung 0:8ede47d38d10 310 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 311
phungductung 0:8ede47d38d10 312 /* Wait till HSE is bypassed or disabled */
phungductung 0:8ede47d38d10 313 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
phungductung 0:8ede47d38d10 314 {
phungductung 0:8ede47d38d10 315 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 316 {
phungductung 0:8ede47d38d10 317 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 318 }
phungductung 0:8ede47d38d10 319 }
phungductung 0:8ede47d38d10 320 }
phungductung 0:8ede47d38d10 321 }
phungductung 0:8ede47d38d10 322 }
phungductung 0:8ede47d38d10 323 /*----------------------------- HSI Configuration --------------------------*/
phungductung 0:8ede47d38d10 324 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
phungductung 0:8ede47d38d10 325 {
phungductung 0:8ede47d38d10 326 /* Check the parameters */
phungductung 0:8ede47d38d10 327 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
phungductung 0:8ede47d38d10 328 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
phungductung 0:8ede47d38d10 329
phungductung 0:8ede47d38d10 330 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
phungductung 0:8ede47d38d10 331 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
phungductung 0:8ede47d38d10 332 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
phungductung 0:8ede47d38d10 333 {
phungductung 0:8ede47d38d10 334 /* When HSI is used as system clock it will not disabled */
phungductung 0:8ede47d38d10 335 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
phungductung 0:8ede47d38d10 336 {
phungductung 0:8ede47d38d10 337 return HAL_ERROR;
phungductung 0:8ede47d38d10 338 }
phungductung 0:8ede47d38d10 339 /* Otherwise, just the calibration is allowed */
phungductung 0:8ede47d38d10 340 else
phungductung 0:8ede47d38d10 341 {
phungductung 0:8ede47d38d10 342 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
phungductung 0:8ede47d38d10 343 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
phungductung 0:8ede47d38d10 344 }
phungductung 0:8ede47d38d10 345 }
phungductung 0:8ede47d38d10 346 else
phungductung 0:8ede47d38d10 347 {
phungductung 0:8ede47d38d10 348 /* Check the HSI State */
phungductung 0:8ede47d38d10 349 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
phungductung 0:8ede47d38d10 350 {
phungductung 0:8ede47d38d10 351 /* Enable the Internal High Speed oscillator (HSI). */
phungductung 0:8ede47d38d10 352 __HAL_RCC_HSI_ENABLE();
phungductung 0:8ede47d38d10 353
phungductung 0:8ede47d38d10 354 /* Get Start Tick*/
phungductung 0:8ede47d38d10 355 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 356
phungductung 0:8ede47d38d10 357 /* Wait till HSI is ready */
phungductung 0:8ede47d38d10 358 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
phungductung 0:8ede47d38d10 359 {
phungductung 0:8ede47d38d10 360 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 361 {
phungductung 0:8ede47d38d10 362 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 363 }
phungductung 0:8ede47d38d10 364 }
phungductung 0:8ede47d38d10 365
phungductung 0:8ede47d38d10 366 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
phungductung 0:8ede47d38d10 367 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
phungductung 0:8ede47d38d10 368 }
phungductung 0:8ede47d38d10 369 else
phungductung 0:8ede47d38d10 370 {
phungductung 0:8ede47d38d10 371 /* Disable the Internal High Speed oscillator (HSI). */
phungductung 0:8ede47d38d10 372 __HAL_RCC_HSI_DISABLE();
phungductung 0:8ede47d38d10 373
phungductung 0:8ede47d38d10 374 /* Get Start Tick*/
phungductung 0:8ede47d38d10 375 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 376
phungductung 0:8ede47d38d10 377 /* Wait till HSI is ready */
phungductung 0:8ede47d38d10 378 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
phungductung 0:8ede47d38d10 379 {
phungductung 0:8ede47d38d10 380 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 381 {
phungductung 0:8ede47d38d10 382 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 383 }
phungductung 0:8ede47d38d10 384 }
phungductung 0:8ede47d38d10 385 }
phungductung 0:8ede47d38d10 386 }
phungductung 0:8ede47d38d10 387 }
phungductung 0:8ede47d38d10 388 /*------------------------------ LSI Configuration -------------------------*/
phungductung 0:8ede47d38d10 389 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
phungductung 0:8ede47d38d10 390 {
phungductung 0:8ede47d38d10 391 /* Check the parameters */
phungductung 0:8ede47d38d10 392 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
phungductung 0:8ede47d38d10 393
phungductung 0:8ede47d38d10 394 /* Check the LSI State */
phungductung 0:8ede47d38d10 395 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
phungductung 0:8ede47d38d10 396 {
phungductung 0:8ede47d38d10 397 /* Enable the Internal Low Speed oscillator (LSI). */
phungductung 0:8ede47d38d10 398 __HAL_RCC_LSI_ENABLE();
phungductung 0:8ede47d38d10 399
phungductung 0:8ede47d38d10 400 /* Get Start Tick*/
phungductung 0:8ede47d38d10 401 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 402
phungductung 0:8ede47d38d10 403 /* Wait till LSI is ready */
phungductung 0:8ede47d38d10 404 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
phungductung 0:8ede47d38d10 405 {
phungductung 0:8ede47d38d10 406 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 407 {
phungductung 0:8ede47d38d10 408 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 409 }
phungductung 0:8ede47d38d10 410 }
phungductung 0:8ede47d38d10 411 }
phungductung 0:8ede47d38d10 412 else
phungductung 0:8ede47d38d10 413 {
phungductung 0:8ede47d38d10 414 /* Disable the Internal Low Speed oscillator (LSI). */
phungductung 0:8ede47d38d10 415 __HAL_RCC_LSI_DISABLE();
phungductung 0:8ede47d38d10 416
phungductung 0:8ede47d38d10 417 /* Get Start Tick*/
phungductung 0:8ede47d38d10 418 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 419
phungductung 0:8ede47d38d10 420 /* Wait till LSI is ready */
phungductung 0:8ede47d38d10 421 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
phungductung 0:8ede47d38d10 422 {
phungductung 0:8ede47d38d10 423 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 424 {
phungductung 0:8ede47d38d10 425 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 426 }
phungductung 0:8ede47d38d10 427 }
phungductung 0:8ede47d38d10 428 }
phungductung 0:8ede47d38d10 429 }
phungductung 0:8ede47d38d10 430 /*------------------------------ LSE Configuration -------------------------*/
phungductung 0:8ede47d38d10 431 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
phungductung 0:8ede47d38d10 432 {
phungductung 0:8ede47d38d10 433 /* Check the parameters */
phungductung 0:8ede47d38d10 434 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
phungductung 0:8ede47d38d10 435
phungductung 0:8ede47d38d10 436 /* Enable Power Clock*/
phungductung 0:8ede47d38d10 437 __HAL_RCC_PWR_CLK_ENABLE();
phungductung 0:8ede47d38d10 438
phungductung 0:8ede47d38d10 439 /* Enable write access to Backup domain */
phungductung 0:8ede47d38d10 440 PWR->CR1 |= PWR_CR1_DBP;
phungductung 0:8ede47d38d10 441
phungductung 0:8ede47d38d10 442 /* Wait for Backup domain Write protection disable */
phungductung 0:8ede47d38d10 443 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 444
phungductung 0:8ede47d38d10 445 while((PWR->CR1 & PWR_CR1_DBP) == RESET)
phungductung 0:8ede47d38d10 446 {
phungductung 0:8ede47d38d10 447 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 448 {
phungductung 0:8ede47d38d10 449 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 450 }
phungductung 0:8ede47d38d10 451 }
phungductung 0:8ede47d38d10 452
phungductung 0:8ede47d38d10 453 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
phungductung 0:8ede47d38d10 454 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
phungductung 0:8ede47d38d10 455
phungductung 0:8ede47d38d10 456 /* Get Start Tick*/
phungductung 0:8ede47d38d10 457 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 458
phungductung 0:8ede47d38d10 459 /* Wait till LSE is ready */
phungductung 0:8ede47d38d10 460 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
phungductung 0:8ede47d38d10 461 {
phungductung 0:8ede47d38d10 462 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 463 {
phungductung 0:8ede47d38d10 464 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 465 }
phungductung 0:8ede47d38d10 466 }
phungductung 0:8ede47d38d10 467
phungductung 0:8ede47d38d10 468 /* Set the new LSE configuration -----------------------------------------*/
phungductung 0:8ede47d38d10 469 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
phungductung 0:8ede47d38d10 470 /* Check the LSE State */
phungductung 0:8ede47d38d10 471 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
phungductung 0:8ede47d38d10 472 {
phungductung 0:8ede47d38d10 473 /* Get Start Tick*/
phungductung 0:8ede47d38d10 474 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 475
phungductung 0:8ede47d38d10 476 /* Wait till LSE is ready */
phungductung 0:8ede47d38d10 477 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
phungductung 0:8ede47d38d10 478 {
phungductung 0:8ede47d38d10 479 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 480 {
phungductung 0:8ede47d38d10 481 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 482 }
phungductung 0:8ede47d38d10 483 }
phungductung 0:8ede47d38d10 484 }
phungductung 0:8ede47d38d10 485 else
phungductung 0:8ede47d38d10 486 {
phungductung 0:8ede47d38d10 487 /* Get Start Tick*/
phungductung 0:8ede47d38d10 488 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 489
phungductung 0:8ede47d38d10 490 /* Wait till LSE is ready */
phungductung 0:8ede47d38d10 491 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
phungductung 0:8ede47d38d10 492 {
phungductung 0:8ede47d38d10 493 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 494 {
phungductung 0:8ede47d38d10 495 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 496 }
phungductung 0:8ede47d38d10 497 }
phungductung 0:8ede47d38d10 498 }
phungductung 0:8ede47d38d10 499 }
phungductung 0:8ede47d38d10 500 /*-------------------------------- PLL Configuration -----------------------*/
phungductung 0:8ede47d38d10 501 /* Check the parameters */
phungductung 0:8ede47d38d10 502 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
phungductung 0:8ede47d38d10 503 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
phungductung 0:8ede47d38d10 504 {
phungductung 0:8ede47d38d10 505 /* Check if the PLL is used as system clock or not */
phungductung 0:8ede47d38d10 506 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
phungductung 0:8ede47d38d10 507 {
phungductung 0:8ede47d38d10 508 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
phungductung 0:8ede47d38d10 509 {
phungductung 0:8ede47d38d10 510 /* Check the parameters */
phungductung 0:8ede47d38d10 511 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
phungductung 0:8ede47d38d10 512 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
phungductung 0:8ede47d38d10 513 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
phungductung 0:8ede47d38d10 514 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
phungductung 0:8ede47d38d10 515 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
phungductung 0:8ede47d38d10 516
phungductung 0:8ede47d38d10 517 /* Disable the main PLL. */
phungductung 0:8ede47d38d10 518 __HAL_RCC_PLL_DISABLE();
phungductung 0:8ede47d38d10 519
phungductung 0:8ede47d38d10 520 /* Get Start Tick*/
phungductung 0:8ede47d38d10 521 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 522
phungductung 0:8ede47d38d10 523 /* Wait till PLL is ready */
phungductung 0:8ede47d38d10 524 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
phungductung 0:8ede47d38d10 525 {
phungductung 0:8ede47d38d10 526 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 527 {
phungductung 0:8ede47d38d10 528 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 529 }
phungductung 0:8ede47d38d10 530 }
phungductung 0:8ede47d38d10 531
phungductung 0:8ede47d38d10 532 /* Configure the main PLL clock source, multiplication and division factors. */
phungductung 0:8ede47d38d10 533 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
phungductung 0:8ede47d38d10 534 RCC_OscInitStruct->PLL.PLLM,
phungductung 0:8ede47d38d10 535 RCC_OscInitStruct->PLL.PLLN,
phungductung 0:8ede47d38d10 536 RCC_OscInitStruct->PLL.PLLP,
phungductung 0:8ede47d38d10 537 RCC_OscInitStruct->PLL.PLLQ);
phungductung 0:8ede47d38d10 538 /* Enable the main PLL. */
phungductung 0:8ede47d38d10 539 __HAL_RCC_PLL_ENABLE();
phungductung 0:8ede47d38d10 540
phungductung 0:8ede47d38d10 541 /* Get Start Tick*/
phungductung 0:8ede47d38d10 542 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 543
phungductung 0:8ede47d38d10 544 /* Wait till PLL is ready */
phungductung 0:8ede47d38d10 545 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
phungductung 0:8ede47d38d10 546 {
phungductung 0:8ede47d38d10 547 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 548 {
phungductung 0:8ede47d38d10 549 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 550 }
phungductung 0:8ede47d38d10 551 }
phungductung 0:8ede47d38d10 552 }
phungductung 0:8ede47d38d10 553 else
phungductung 0:8ede47d38d10 554 {
phungductung 0:8ede47d38d10 555 /* Disable the main PLL. */
phungductung 0:8ede47d38d10 556 __HAL_RCC_PLL_DISABLE();
phungductung 0:8ede47d38d10 557
phungductung 0:8ede47d38d10 558 /* Get Start Tick*/
phungductung 0:8ede47d38d10 559 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 560
phungductung 0:8ede47d38d10 561 /* Wait till PLL is ready */
phungductung 0:8ede47d38d10 562 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
phungductung 0:8ede47d38d10 563 {
phungductung 0:8ede47d38d10 564 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 565 {
phungductung 0:8ede47d38d10 566 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 567 }
phungductung 0:8ede47d38d10 568 }
phungductung 0:8ede47d38d10 569 }
phungductung 0:8ede47d38d10 570 }
phungductung 0:8ede47d38d10 571 else
phungductung 0:8ede47d38d10 572 {
phungductung 0:8ede47d38d10 573 return HAL_ERROR;
phungductung 0:8ede47d38d10 574 }
phungductung 0:8ede47d38d10 575 }
phungductung 0:8ede47d38d10 576 return HAL_OK;
phungductung 0:8ede47d38d10 577 }
phungductung 0:8ede47d38d10 578
phungductung 0:8ede47d38d10 579 /**
phungductung 0:8ede47d38d10 580 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
phungductung 0:8ede47d38d10 581 * parameters in the RCC_ClkInitStruct.
phungductung 0:8ede47d38d10 582 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
phungductung 0:8ede47d38d10 583 * contains the configuration information for the RCC peripheral.
phungductung 0:8ede47d38d10 584 * @param FLatency: FLASH Latency, this parameter depend on device selected
phungductung 0:8ede47d38d10 585 *
phungductung 0:8ede47d38d10 586 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
phungductung 0:8ede47d38d10 587 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
phungductung 0:8ede47d38d10 588 *
phungductung 0:8ede47d38d10 589 * @note The HSI is used (enabled by hardware) as system clock source after
phungductung 0:8ede47d38d10 590 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
phungductung 0:8ede47d38d10 591 * of failure of the HSE used directly or indirectly as system clock
phungductung 0:8ede47d38d10 592 * (if the Clock Security System CSS is enabled).
phungductung 0:8ede47d38d10 593 *
phungductung 0:8ede47d38d10 594 * @note A switch from one clock source to another occurs only if the target
phungductung 0:8ede47d38d10 595 * clock source is ready (clock stable after startup delay or PLL locked).
phungductung 0:8ede47d38d10 596 * If a clock source which is not yet ready is selected, the switch will
phungductung 0:8ede47d38d10 597 * occur when the clock source will be ready.
phungductung 0:8ede47d38d10 598 * You can use HAL_RCC_GetClockConfig() function to know which clock is
phungductung 0:8ede47d38d10 599 * currently used as system clock source.
phungductung 0:8ede47d38d10 600 * @note Depending on the device voltage range, the software has to set correctly
phungductung 0:8ede47d38d10 601 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
phungductung 0:8ede47d38d10 602 * (for more details refer to section above "Initialization/de-initialization functions")
phungductung 0:8ede47d38d10 603 * @retval None
phungductung 0:8ede47d38d10 604 */
phungductung 0:8ede47d38d10 605 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
phungductung 0:8ede47d38d10 606 {
phungductung 0:8ede47d38d10 607 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 608
phungductung 0:8ede47d38d10 609 /* Check the parameters */
phungductung 0:8ede47d38d10 610 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
phungductung 0:8ede47d38d10 611 assert_param(IS_FLASH_LATENCY(FLatency));
phungductung 0:8ede47d38d10 612
phungductung 0:8ede47d38d10 613 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
phungductung 0:8ede47d38d10 614 must be correctly programmed according to the frequency of the CPU clock
phungductung 0:8ede47d38d10 615 (HCLK) and the supply voltage of the device. */
phungductung 0:8ede47d38d10 616
phungductung 0:8ede47d38d10 617 /* Increasing the CPU frequency */
phungductung 0:8ede47d38d10 618 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
phungductung 0:8ede47d38d10 619 {
phungductung 0:8ede47d38d10 620 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
phungductung 0:8ede47d38d10 621 __HAL_FLASH_SET_LATENCY(FLatency);
phungductung 0:8ede47d38d10 622
phungductung 0:8ede47d38d10 623 /* Check that the new number of wait states is taken into account to access the Flash
phungductung 0:8ede47d38d10 624 memory by reading the FLASH_ACR register */
phungductung 0:8ede47d38d10 625 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
phungductung 0:8ede47d38d10 626 {
phungductung 0:8ede47d38d10 627 return HAL_ERROR;
phungductung 0:8ede47d38d10 628 }
phungductung 0:8ede47d38d10 629
phungductung 0:8ede47d38d10 630 /*-------------------------- HCLK Configuration --------------------------*/
phungductung 0:8ede47d38d10 631 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
phungductung 0:8ede47d38d10 632 {
phungductung 0:8ede47d38d10 633 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
phungductung 0:8ede47d38d10 634 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
phungductung 0:8ede47d38d10 635 }
phungductung 0:8ede47d38d10 636
phungductung 0:8ede47d38d10 637 /*------------------------- SYSCLK Configuration ---------------------------*/
phungductung 0:8ede47d38d10 638 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
phungductung 0:8ede47d38d10 639 {
phungductung 0:8ede47d38d10 640 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
phungductung 0:8ede47d38d10 641
phungductung 0:8ede47d38d10 642 /* HSE is selected as System Clock Source */
phungductung 0:8ede47d38d10 643 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
phungductung 0:8ede47d38d10 644 {
phungductung 0:8ede47d38d10 645 /* Check the HSE ready flag */
phungductung 0:8ede47d38d10 646 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
phungductung 0:8ede47d38d10 647 {
phungductung 0:8ede47d38d10 648 return HAL_ERROR;
phungductung 0:8ede47d38d10 649 }
phungductung 0:8ede47d38d10 650 }
phungductung 0:8ede47d38d10 651 /* PLL is selected as System Clock Source */
phungductung 0:8ede47d38d10 652 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
phungductung 0:8ede47d38d10 653 {
phungductung 0:8ede47d38d10 654 /* Check the PLL ready flag */
phungductung 0:8ede47d38d10 655 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
phungductung 0:8ede47d38d10 656 {
phungductung 0:8ede47d38d10 657 return HAL_ERROR;
phungductung 0:8ede47d38d10 658 }
phungductung 0:8ede47d38d10 659 }
phungductung 0:8ede47d38d10 660 /* HSI is selected as System Clock Source */
phungductung 0:8ede47d38d10 661 else
phungductung 0:8ede47d38d10 662 {
phungductung 0:8ede47d38d10 663 /* Check the HSI ready flag */
phungductung 0:8ede47d38d10 664 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
phungductung 0:8ede47d38d10 665 {
phungductung 0:8ede47d38d10 666 return HAL_ERROR;
phungductung 0:8ede47d38d10 667 }
phungductung 0:8ede47d38d10 668 }
phungductung 0:8ede47d38d10 669
phungductung 0:8ede47d38d10 670 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
phungductung 0:8ede47d38d10 671 /* Get Start Tick*/
phungductung 0:8ede47d38d10 672 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 673
phungductung 0:8ede47d38d10 674 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
phungductung 0:8ede47d38d10 675 {
phungductung 0:8ede47d38d10 676 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
phungductung 0:8ede47d38d10 677 {
phungductung 0:8ede47d38d10 678 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 679 {
phungductung 0:8ede47d38d10 680 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 681 }
phungductung 0:8ede47d38d10 682 }
phungductung 0:8ede47d38d10 683 }
phungductung 0:8ede47d38d10 684 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
phungductung 0:8ede47d38d10 685 {
phungductung 0:8ede47d38d10 686 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
phungductung 0:8ede47d38d10 687 {
phungductung 0:8ede47d38d10 688 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 689 {
phungductung 0:8ede47d38d10 690 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 691 }
phungductung 0:8ede47d38d10 692 }
phungductung 0:8ede47d38d10 693 }
phungductung 0:8ede47d38d10 694 else
phungductung 0:8ede47d38d10 695 {
phungductung 0:8ede47d38d10 696 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
phungductung 0:8ede47d38d10 697 {
phungductung 0:8ede47d38d10 698 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 699 {
phungductung 0:8ede47d38d10 700 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 701 }
phungductung 0:8ede47d38d10 702 }
phungductung 0:8ede47d38d10 703 }
phungductung 0:8ede47d38d10 704 }
phungductung 0:8ede47d38d10 705 }
phungductung 0:8ede47d38d10 706 /* Decreasing the CPU frequency */
phungductung 0:8ede47d38d10 707 else
phungductung 0:8ede47d38d10 708 {
phungductung 0:8ede47d38d10 709 /*-------------------------- HCLK Configuration --------------------------*/
phungductung 0:8ede47d38d10 710 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
phungductung 0:8ede47d38d10 711 {
phungductung 0:8ede47d38d10 712 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
phungductung 0:8ede47d38d10 713 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
phungductung 0:8ede47d38d10 714 }
phungductung 0:8ede47d38d10 715
phungductung 0:8ede47d38d10 716 /*------------------------- SYSCLK Configuration -------------------------*/
phungductung 0:8ede47d38d10 717 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
phungductung 0:8ede47d38d10 718 {
phungductung 0:8ede47d38d10 719 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
phungductung 0:8ede47d38d10 720
phungductung 0:8ede47d38d10 721 /* HSE is selected as System Clock Source */
phungductung 0:8ede47d38d10 722 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
phungductung 0:8ede47d38d10 723 {
phungductung 0:8ede47d38d10 724 /* Check the HSE ready flag */
phungductung 0:8ede47d38d10 725 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
phungductung 0:8ede47d38d10 726 {
phungductung 0:8ede47d38d10 727 return HAL_ERROR;
phungductung 0:8ede47d38d10 728 }
phungductung 0:8ede47d38d10 729 }
phungductung 0:8ede47d38d10 730 /* PLL is selected as System Clock Source */
phungductung 0:8ede47d38d10 731 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
phungductung 0:8ede47d38d10 732 {
phungductung 0:8ede47d38d10 733 /* Check the PLL ready flag */
phungductung 0:8ede47d38d10 734 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
phungductung 0:8ede47d38d10 735 {
phungductung 0:8ede47d38d10 736 return HAL_ERROR;
phungductung 0:8ede47d38d10 737 }
phungductung 0:8ede47d38d10 738 }
phungductung 0:8ede47d38d10 739 /* HSI is selected as System Clock Source */
phungductung 0:8ede47d38d10 740 else
phungductung 0:8ede47d38d10 741 {
phungductung 0:8ede47d38d10 742 /* Check the HSI ready flag */
phungductung 0:8ede47d38d10 743 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
phungductung 0:8ede47d38d10 744 {
phungductung 0:8ede47d38d10 745 return HAL_ERROR;
phungductung 0:8ede47d38d10 746 }
phungductung 0:8ede47d38d10 747 }
phungductung 0:8ede47d38d10 748 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
phungductung 0:8ede47d38d10 749 /* Get Start Tick*/
phungductung 0:8ede47d38d10 750 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 751
phungductung 0:8ede47d38d10 752 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
phungductung 0:8ede47d38d10 753 {
phungductung 0:8ede47d38d10 754 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
phungductung 0:8ede47d38d10 755 {
phungductung 0:8ede47d38d10 756 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 757 {
phungductung 0:8ede47d38d10 758 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 759 }
phungductung 0:8ede47d38d10 760 }
phungductung 0:8ede47d38d10 761 }
phungductung 0:8ede47d38d10 762 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
phungductung 0:8ede47d38d10 763 {
phungductung 0:8ede47d38d10 764 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
phungductung 0:8ede47d38d10 765 {
phungductung 0:8ede47d38d10 766 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 767 {
phungductung 0:8ede47d38d10 768 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 769 }
phungductung 0:8ede47d38d10 770 }
phungductung 0:8ede47d38d10 771 }
phungductung 0:8ede47d38d10 772 else
phungductung 0:8ede47d38d10 773 {
phungductung 0:8ede47d38d10 774 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
phungductung 0:8ede47d38d10 775 {
phungductung 0:8ede47d38d10 776 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
phungductung 0:8ede47d38d10 777 {
phungductung 0:8ede47d38d10 778 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 779 }
phungductung 0:8ede47d38d10 780 }
phungductung 0:8ede47d38d10 781 }
phungductung 0:8ede47d38d10 782 }
phungductung 0:8ede47d38d10 783
phungductung 0:8ede47d38d10 784 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
phungductung 0:8ede47d38d10 785 __HAL_FLASH_SET_LATENCY(FLatency);
phungductung 0:8ede47d38d10 786
phungductung 0:8ede47d38d10 787 /* Check that the new number of wait states is taken into account to access the Flash
phungductung 0:8ede47d38d10 788 memory by reading the FLASH_ACR register */
phungductung 0:8ede47d38d10 789 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
phungductung 0:8ede47d38d10 790 {
phungductung 0:8ede47d38d10 791 return HAL_ERROR;
phungductung 0:8ede47d38d10 792 }
phungductung 0:8ede47d38d10 793 }
phungductung 0:8ede47d38d10 794
phungductung 0:8ede47d38d10 795 /*-------------------------- PCLK1 Configuration ---------------------------*/
phungductung 0:8ede47d38d10 796 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
phungductung 0:8ede47d38d10 797 {
phungductung 0:8ede47d38d10 798 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
phungductung 0:8ede47d38d10 799 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
phungductung 0:8ede47d38d10 800 }
phungductung 0:8ede47d38d10 801
phungductung 0:8ede47d38d10 802 /*-------------------------- PCLK2 Configuration ---------------------------*/
phungductung 0:8ede47d38d10 803 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
phungductung 0:8ede47d38d10 804 {
phungductung 0:8ede47d38d10 805 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
phungductung 0:8ede47d38d10 806 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
phungductung 0:8ede47d38d10 807 }
phungductung 0:8ede47d38d10 808
phungductung 0:8ede47d38d10 809 /* Configure the source of time base considering new system clocks settings*/
phungductung 0:8ede47d38d10 810 HAL_InitTick (TICK_INT_PRIORITY);
phungductung 0:8ede47d38d10 811
phungductung 0:8ede47d38d10 812 return HAL_OK;
phungductung 0:8ede47d38d10 813 }
phungductung 0:8ede47d38d10 814
phungductung 0:8ede47d38d10 815 /**
phungductung 0:8ede47d38d10 816 * @}
phungductung 0:8ede47d38d10 817 */
phungductung 0:8ede47d38d10 818
phungductung 0:8ede47d38d10 819 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
phungductung 0:8ede47d38d10 820 * @brief RCC clocks control functions
phungductung 0:8ede47d38d10 821 *
phungductung 0:8ede47d38d10 822 @verbatim
phungductung 0:8ede47d38d10 823 ===============================================================================
phungductung 0:8ede47d38d10 824 ##### Peripheral Control functions #####
phungductung 0:8ede47d38d10 825 ===============================================================================
phungductung 0:8ede47d38d10 826 [..]
phungductung 0:8ede47d38d10 827 This subsection provides a set of functions allowing to control the RCC Clocks
phungductung 0:8ede47d38d10 828 frequencies.
phungductung 0:8ede47d38d10 829
phungductung 0:8ede47d38d10 830 @endverbatim
phungductung 0:8ede47d38d10 831 * @{
phungductung 0:8ede47d38d10 832 */
phungductung 0:8ede47d38d10 833
phungductung 0:8ede47d38d10 834 /**
phungductung 0:8ede47d38d10 835 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
phungductung 0:8ede47d38d10 836 * @note PA8/PC9 should be configured in alternate function mode.
phungductung 0:8ede47d38d10 837 * @param RCC_MCOx: specifies the output direction for the clock source.
phungductung 0:8ede47d38d10 838 * This parameter can be one of the following values:
phungductung 0:8ede47d38d10 839 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
phungductung 0:8ede47d38d10 840 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
phungductung 0:8ede47d38d10 841 * @param RCC_MCOSource: specifies the clock source to output.
phungductung 0:8ede47d38d10 842 * This parameter can be one of the following values:
phungductung 0:8ede47d38d10 843 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
phungductung 0:8ede47d38d10 844 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
phungductung 0:8ede47d38d10 845 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
phungductung 0:8ede47d38d10 846 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
phungductung 0:8ede47d38d10 847 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
phungductung 0:8ede47d38d10 848 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
phungductung 0:8ede47d38d10 849 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
phungductung 0:8ede47d38d10 850 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
phungductung 0:8ede47d38d10 851 * @param RCC_MCODiv: specifies the MCOx prescaler.
phungductung 0:8ede47d38d10 852 * This parameter can be one of the following values:
phungductung 0:8ede47d38d10 853 * @arg RCC_MCODIV_1: no division applied to MCOx clock
phungductung 0:8ede47d38d10 854 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
phungductung 0:8ede47d38d10 855 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
phungductung 0:8ede47d38d10 856 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
phungductung 0:8ede47d38d10 857 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
phungductung 0:8ede47d38d10 858 * @retval None
phungductung 0:8ede47d38d10 859 */
phungductung 0:8ede47d38d10 860 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
phungductung 0:8ede47d38d10 861 {
phungductung 0:8ede47d38d10 862 GPIO_InitTypeDef GPIO_InitStruct;
phungductung 0:8ede47d38d10 863 /* Check the parameters */
phungductung 0:8ede47d38d10 864 assert_param(IS_RCC_MCO(RCC_MCOx));
phungductung 0:8ede47d38d10 865 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
phungductung 0:8ede47d38d10 866 /* RCC_MCO1 */
phungductung 0:8ede47d38d10 867 if(RCC_MCOx == RCC_MCO1)
phungductung 0:8ede47d38d10 868 {
phungductung 0:8ede47d38d10 869 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
phungductung 0:8ede47d38d10 870
phungductung 0:8ede47d38d10 871 /* MCO1 Clock Enable */
phungductung 0:8ede47d38d10 872 MCO1_CLK_ENABLE();
phungductung 0:8ede47d38d10 873
phungductung 0:8ede47d38d10 874 /* Configure the MCO1 pin in alternate function mode */
phungductung 0:8ede47d38d10 875 GPIO_InitStruct.Pin = MCO1_PIN;
phungductung 0:8ede47d38d10 876 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
phungductung 0:8ede47d38d10 877 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
phungductung 0:8ede47d38d10 878 GPIO_InitStruct.Pull = GPIO_NOPULL;
phungductung 0:8ede47d38d10 879 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
phungductung 0:8ede47d38d10 880 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
phungductung 0:8ede47d38d10 881
phungductung 0:8ede47d38d10 882 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
phungductung 0:8ede47d38d10 883 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
phungductung 0:8ede47d38d10 884 }
phungductung 0:8ede47d38d10 885 else
phungductung 0:8ede47d38d10 886 {
phungductung 0:8ede47d38d10 887 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
phungductung 0:8ede47d38d10 888
phungductung 0:8ede47d38d10 889 /* MCO2 Clock Enable */
phungductung 0:8ede47d38d10 890 MCO2_CLK_ENABLE();
phungductung 0:8ede47d38d10 891
phungductung 0:8ede47d38d10 892 /* Configure the MCO2 pin in alternate function mode */
phungductung 0:8ede47d38d10 893 GPIO_InitStruct.Pin = MCO2_PIN;
phungductung 0:8ede47d38d10 894 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
phungductung 0:8ede47d38d10 895 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
phungductung 0:8ede47d38d10 896 GPIO_InitStruct.Pull = GPIO_NOPULL;
phungductung 0:8ede47d38d10 897 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
phungductung 0:8ede47d38d10 898 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
phungductung 0:8ede47d38d10 899
phungductung 0:8ede47d38d10 900 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
phungductung 0:8ede47d38d10 901 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
phungductung 0:8ede47d38d10 902 }
phungductung 0:8ede47d38d10 903 }
phungductung 0:8ede47d38d10 904
phungductung 0:8ede47d38d10 905 /**
phungductung 0:8ede47d38d10 906 * @brief Enables the Clock Security System.
phungductung 0:8ede47d38d10 907 * @note If a failure is detected on the HSE oscillator clock, this oscillator
phungductung 0:8ede47d38d10 908 * is automatically disabled and an interrupt is generated to inform the
phungductung 0:8ede47d38d10 909 * software about the failure (Clock Security System Interrupt, CSSI),
phungductung 0:8ede47d38d10 910 * allowing the MCU to perform rescue operations. The CSSI is linked to
phungductung 0:8ede47d38d10 911 * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
phungductung 0:8ede47d38d10 912 * @retval None
phungductung 0:8ede47d38d10 913 */
phungductung 0:8ede47d38d10 914 void HAL_RCC_EnableCSS(void)
phungductung 0:8ede47d38d10 915 {
phungductung 0:8ede47d38d10 916 SET_BIT(RCC->CR, RCC_CR_CSSON);
phungductung 0:8ede47d38d10 917 }
phungductung 0:8ede47d38d10 918
phungductung 0:8ede47d38d10 919 /**
phungductung 0:8ede47d38d10 920 * @brief Disables the Clock Security System.
phungductung 0:8ede47d38d10 921 * @retval None
phungductung 0:8ede47d38d10 922 */
phungductung 0:8ede47d38d10 923 void HAL_RCC_DisableCSS(void)
phungductung 0:8ede47d38d10 924 {
phungductung 0:8ede47d38d10 925 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
phungductung 0:8ede47d38d10 926 }
phungductung 0:8ede47d38d10 927
phungductung 0:8ede47d38d10 928 /**
phungductung 0:8ede47d38d10 929 * @brief Returns the SYSCLK frequency
phungductung 0:8ede47d38d10 930 *
phungductung 0:8ede47d38d10 931 * @note The system frequency computed by this function is not the real
phungductung 0:8ede47d38d10 932 * frequency in the chip. It is calculated based on the predefined
phungductung 0:8ede47d38d10 933 * constant and the selected clock source:
phungductung 0:8ede47d38d10 934 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
phungductung 0:8ede47d38d10 935 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
phungductung 0:8ede47d38d10 936 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
phungductung 0:8ede47d38d10 937 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
phungductung 0:8ede47d38d10 938 * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
phungductung 0:8ede47d38d10 939 * 16 MHz) but the real value may vary depending on the variations
phungductung 0:8ede47d38d10 940 * in voltage and temperature.
phungductung 0:8ede47d38d10 941 * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
phungductung 0:8ede47d38d10 942 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
phungductung 0:8ede47d38d10 943 * frequency of the crystal used. Otherwise, this function may
phungductung 0:8ede47d38d10 944 * have wrong result.
phungductung 0:8ede47d38d10 945 *
phungductung 0:8ede47d38d10 946 * @note The result of this function could be not correct when using fractional
phungductung 0:8ede47d38d10 947 * value for HSE crystal.
phungductung 0:8ede47d38d10 948 *
phungductung 0:8ede47d38d10 949 * @note This function can be used by the user application to compute the
phungductung 0:8ede47d38d10 950 * baudrate for the communication peripherals or configure other parameters.
phungductung 0:8ede47d38d10 951 *
phungductung 0:8ede47d38d10 952 * @note Each time SYSCLK changes, this function must be called to update the
phungductung 0:8ede47d38d10 953 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
phungductung 0:8ede47d38d10 954 *
phungductung 0:8ede47d38d10 955 *
phungductung 0:8ede47d38d10 956 * @retval SYSCLK frequency
phungductung 0:8ede47d38d10 957 */
phungductung 0:8ede47d38d10 958 uint32_t HAL_RCC_GetSysClockFreq(void)
phungductung 0:8ede47d38d10 959 {
phungductung 0:8ede47d38d10 960 uint32_t pllm = 0, pllvco = 0, pllp = 0;
phungductung 0:8ede47d38d10 961 uint32_t sysclockfreq = 0;
phungductung 0:8ede47d38d10 962
phungductung 0:8ede47d38d10 963 /* Get SYSCLK source -------------------------------------------------------*/
phungductung 0:8ede47d38d10 964 switch (RCC->CFGR & RCC_CFGR_SWS)
phungductung 0:8ede47d38d10 965 {
phungductung 0:8ede47d38d10 966 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
phungductung 0:8ede47d38d10 967 {
phungductung 0:8ede47d38d10 968 sysclockfreq = HSI_VALUE;
phungductung 0:8ede47d38d10 969 break;
phungductung 0:8ede47d38d10 970 }
phungductung 0:8ede47d38d10 971 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
phungductung 0:8ede47d38d10 972 {
phungductung 0:8ede47d38d10 973 sysclockfreq = HSE_VALUE;
phungductung 0:8ede47d38d10 974 break;
phungductung 0:8ede47d38d10 975 }
phungductung 0:8ede47d38d10 976 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
phungductung 0:8ede47d38d10 977 {
phungductung 0:8ede47d38d10 978 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
phungductung 0:8ede47d38d10 979 SYSCLK = PLL_VCO / PLLP */
phungductung 0:8ede47d38d10 980 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
phungductung 0:8ede47d38d10 981 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
phungductung 0:8ede47d38d10 982 {
phungductung 0:8ede47d38d10 983 /* HSE used as PLL clock source */
phungductung 0:8ede47d38d10 984 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
phungductung 0:8ede47d38d10 985 }
phungductung 0:8ede47d38d10 986 else
phungductung 0:8ede47d38d10 987 {
phungductung 0:8ede47d38d10 988 /* HSI used as PLL clock source */
phungductung 0:8ede47d38d10 989 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
phungductung 0:8ede47d38d10 990 }
phungductung 0:8ede47d38d10 991 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
phungductung 0:8ede47d38d10 992
phungductung 0:8ede47d38d10 993 sysclockfreq = pllvco/pllp;
phungductung 0:8ede47d38d10 994 break;
phungductung 0:8ede47d38d10 995 }
phungductung 0:8ede47d38d10 996 default:
phungductung 0:8ede47d38d10 997 {
phungductung 0:8ede47d38d10 998 sysclockfreq = HSI_VALUE;
phungductung 0:8ede47d38d10 999 break;
phungductung 0:8ede47d38d10 1000 }
phungductung 0:8ede47d38d10 1001 }
phungductung 0:8ede47d38d10 1002 return sysclockfreq;
phungductung 0:8ede47d38d10 1003 }
phungductung 0:8ede47d38d10 1004
phungductung 0:8ede47d38d10 1005 /**
phungductung 0:8ede47d38d10 1006 * @brief Returns the HCLK frequency
phungductung 0:8ede47d38d10 1007 * @note Each time HCLK changes, this function must be called to update the
phungductung 0:8ede47d38d10 1008 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
phungductung 0:8ede47d38d10 1009 *
phungductung 0:8ede47d38d10 1010 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
phungductung 0:8ede47d38d10 1011 * and updated within this function
phungductung 0:8ede47d38d10 1012 * @retval HCLK frequency
phungductung 0:8ede47d38d10 1013 */
phungductung 0:8ede47d38d10 1014 uint32_t HAL_RCC_GetHCLKFreq(void)
phungductung 0:8ede47d38d10 1015 {
phungductung 0:8ede47d38d10 1016 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
phungductung 0:8ede47d38d10 1017 return SystemCoreClock;
phungductung 0:8ede47d38d10 1018 }
phungductung 0:8ede47d38d10 1019
phungductung 0:8ede47d38d10 1020 /**
phungductung 0:8ede47d38d10 1021 * @brief Returns the PCLK1 frequency
phungductung 0:8ede47d38d10 1022 * @note Each time PCLK1 changes, this function must be called to update the
phungductung 0:8ede47d38d10 1023 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
phungductung 0:8ede47d38d10 1024 * @retval PCLK1 frequency
phungductung 0:8ede47d38d10 1025 */
phungductung 0:8ede47d38d10 1026 uint32_t HAL_RCC_GetPCLK1Freq(void)
phungductung 0:8ede47d38d10 1027 {
phungductung 0:8ede47d38d10 1028 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
phungductung 0:8ede47d38d10 1029 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
phungductung 0:8ede47d38d10 1030 }
phungductung 0:8ede47d38d10 1031
phungductung 0:8ede47d38d10 1032 /**
phungductung 0:8ede47d38d10 1033 * @brief Returns the PCLK2 frequency
phungductung 0:8ede47d38d10 1034 * @note Each time PCLK2 changes, this function must be called to update the
phungductung 0:8ede47d38d10 1035 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
phungductung 0:8ede47d38d10 1036 * @retval PCLK2 frequency
phungductung 0:8ede47d38d10 1037 */
phungductung 0:8ede47d38d10 1038 uint32_t HAL_RCC_GetPCLK2Freq(void)
phungductung 0:8ede47d38d10 1039 {
phungductung 0:8ede47d38d10 1040 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
phungductung 0:8ede47d38d10 1041 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
phungductung 0:8ede47d38d10 1042 }
phungductung 0:8ede47d38d10 1043
phungductung 0:8ede47d38d10 1044 /**
phungductung 0:8ede47d38d10 1045 * @brief Configures the RCC_OscInitStruct according to the internal
phungductung 0:8ede47d38d10 1046 * RCC configuration registers.
phungductung 0:8ede47d38d10 1047 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
phungductung 0:8ede47d38d10 1048 * will be configured.
phungductung 0:8ede47d38d10 1049 * @retval None
phungductung 0:8ede47d38d10 1050 */
phungductung 0:8ede47d38d10 1051 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
phungductung 0:8ede47d38d10 1052 {
phungductung 0:8ede47d38d10 1053 /* Set all possible values for the Oscillator type parameter ---------------*/
phungductung 0:8ede47d38d10 1054 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
phungductung 0:8ede47d38d10 1055
phungductung 0:8ede47d38d10 1056 /* Get the HSE configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 1057 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
phungductung 0:8ede47d38d10 1058 {
phungductung 0:8ede47d38d10 1059 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
phungductung 0:8ede47d38d10 1060 }
phungductung 0:8ede47d38d10 1061 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
phungductung 0:8ede47d38d10 1062 {
phungductung 0:8ede47d38d10 1063 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
phungductung 0:8ede47d38d10 1064 }
phungductung 0:8ede47d38d10 1065 else
phungductung 0:8ede47d38d10 1066 {
phungductung 0:8ede47d38d10 1067 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
phungductung 0:8ede47d38d10 1068 }
phungductung 0:8ede47d38d10 1069
phungductung 0:8ede47d38d10 1070 /* Get the HSI configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 1071 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
phungductung 0:8ede47d38d10 1072 {
phungductung 0:8ede47d38d10 1073 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
phungductung 0:8ede47d38d10 1074 }
phungductung 0:8ede47d38d10 1075 else
phungductung 0:8ede47d38d10 1076 {
phungductung 0:8ede47d38d10 1077 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
phungductung 0:8ede47d38d10 1078 }
phungductung 0:8ede47d38d10 1079
phungductung 0:8ede47d38d10 1080 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
phungductung 0:8ede47d38d10 1081
phungductung 0:8ede47d38d10 1082 /* Get the LSE configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 1083 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
phungductung 0:8ede47d38d10 1084 {
phungductung 0:8ede47d38d10 1085 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
phungductung 0:8ede47d38d10 1086 }
phungductung 0:8ede47d38d10 1087 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
phungductung 0:8ede47d38d10 1088 {
phungductung 0:8ede47d38d10 1089 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
phungductung 0:8ede47d38d10 1090 }
phungductung 0:8ede47d38d10 1091 else
phungductung 0:8ede47d38d10 1092 {
phungductung 0:8ede47d38d10 1093 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
phungductung 0:8ede47d38d10 1094 }
phungductung 0:8ede47d38d10 1095
phungductung 0:8ede47d38d10 1096 /* Get the LSI configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 1097 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
phungductung 0:8ede47d38d10 1098 {
phungductung 0:8ede47d38d10 1099 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
phungductung 0:8ede47d38d10 1100 }
phungductung 0:8ede47d38d10 1101 else
phungductung 0:8ede47d38d10 1102 {
phungductung 0:8ede47d38d10 1103 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
phungductung 0:8ede47d38d10 1104 }
phungductung 0:8ede47d38d10 1105
phungductung 0:8ede47d38d10 1106 /* Get the PLL configuration -----------------------------------------------*/
phungductung 0:8ede47d38d10 1107 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
phungductung 0:8ede47d38d10 1108 {
phungductung 0:8ede47d38d10 1109 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
phungductung 0:8ede47d38d10 1110 }
phungductung 0:8ede47d38d10 1111 else
phungductung 0:8ede47d38d10 1112 {
phungductung 0:8ede47d38d10 1113 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
phungductung 0:8ede47d38d10 1114 }
phungductung 0:8ede47d38d10 1115 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
phungductung 0:8ede47d38d10 1116 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
phungductung 0:8ede47d38d10 1117 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
phungductung 0:8ede47d38d10 1118 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
phungductung 0:8ede47d38d10 1119 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
phungductung 0:8ede47d38d10 1120 }
phungductung 0:8ede47d38d10 1121
phungductung 0:8ede47d38d10 1122 /**
phungductung 0:8ede47d38d10 1123 * @brief Configures the RCC_ClkInitStruct according to the internal
phungductung 0:8ede47d38d10 1124 * RCC configuration registers.
phungductung 0:8ede47d38d10 1125 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
phungductung 0:8ede47d38d10 1126 * will be configured.
phungductung 0:8ede47d38d10 1127 * @param pFLatency: Pointer on the Flash Latency.
phungductung 0:8ede47d38d10 1128 * @retval None
phungductung 0:8ede47d38d10 1129 */
phungductung 0:8ede47d38d10 1130 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
phungductung 0:8ede47d38d10 1131 {
phungductung 0:8ede47d38d10 1132 /* Set all possible values for the Clock type parameter --------------------*/
phungductung 0:8ede47d38d10 1133 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
phungductung 0:8ede47d38d10 1134
phungductung 0:8ede47d38d10 1135 /* Get the SYSCLK configuration --------------------------------------------*/
phungductung 0:8ede47d38d10 1136 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
phungductung 0:8ede47d38d10 1137
phungductung 0:8ede47d38d10 1138 /* Get the HCLK configuration ----------------------------------------------*/
phungductung 0:8ede47d38d10 1139 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
phungductung 0:8ede47d38d10 1140
phungductung 0:8ede47d38d10 1141 /* Get the APB1 configuration ----------------------------------------------*/
phungductung 0:8ede47d38d10 1142 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
phungductung 0:8ede47d38d10 1143
phungductung 0:8ede47d38d10 1144 /* Get the APB2 configuration ----------------------------------------------*/
phungductung 0:8ede47d38d10 1145 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
phungductung 0:8ede47d38d10 1146
phungductung 0:8ede47d38d10 1147 /* Get the Flash Wait State (Latency) configuration ------------------------*/
phungductung 0:8ede47d38d10 1148 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
phungductung 0:8ede47d38d10 1149 }
phungductung 0:8ede47d38d10 1150
phungductung 0:8ede47d38d10 1151 /**
phungductung 0:8ede47d38d10 1152 * @brief This function handles the RCC CSS interrupt request.
phungductung 0:8ede47d38d10 1153 * @note This API should be called under the NMI_Handler().
phungductung 0:8ede47d38d10 1154 * @retval None
phungductung 0:8ede47d38d10 1155 */
phungductung 0:8ede47d38d10 1156 void HAL_RCC_NMI_IRQHandler(void)
phungductung 0:8ede47d38d10 1157 {
phungductung 0:8ede47d38d10 1158 /* Check RCC CSSF flag */
phungductung 0:8ede47d38d10 1159 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
phungductung 0:8ede47d38d10 1160 {
phungductung 0:8ede47d38d10 1161 /* RCC Clock Security System interrupt user callback */
phungductung 0:8ede47d38d10 1162 HAL_RCC_CSSCallback();
phungductung 0:8ede47d38d10 1163
phungductung 0:8ede47d38d10 1164 /* Clear RCC CSS pending bit */
phungductung 0:8ede47d38d10 1165 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
phungductung 0:8ede47d38d10 1166 }
phungductung 0:8ede47d38d10 1167 }
phungductung 0:8ede47d38d10 1168
phungductung 0:8ede47d38d10 1169 /**
phungductung 0:8ede47d38d10 1170 * @brief RCC Clock Security System interrupt callback
phungductung 0:8ede47d38d10 1171 * @retval None
phungductung 0:8ede47d38d10 1172 */
phungductung 0:8ede47d38d10 1173 __weak void HAL_RCC_CSSCallback(void)
phungductung 0:8ede47d38d10 1174 {
phungductung 0:8ede47d38d10 1175 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:8ede47d38d10 1176 the HAL_RCC_CSSCallback could be implemented in the user file
phungductung 0:8ede47d38d10 1177 */
phungductung 0:8ede47d38d10 1178 }
phungductung 0:8ede47d38d10 1179
phungductung 0:8ede47d38d10 1180 /**
phungductung 0:8ede47d38d10 1181 * @}
phungductung 0:8ede47d38d10 1182 */
phungductung 0:8ede47d38d10 1183
phungductung 0:8ede47d38d10 1184 /**
phungductung 0:8ede47d38d10 1185 * @}
phungductung 0:8ede47d38d10 1186 */
phungductung 0:8ede47d38d10 1187
phungductung 0:8ede47d38d10 1188 #endif /* HAL_RCC_MODULE_ENABLED */
phungductung 0:8ede47d38d10 1189 /**
phungductung 0:8ede47d38d10 1190 * @}
phungductung 0:8ede47d38d10 1191 */
phungductung 0:8ede47d38d10 1192
phungductung 0:8ede47d38d10 1193 /**
phungductung 0:8ede47d38d10 1194 * @}
phungductung 0:8ede47d38d10 1195 */
phungductung 0:8ede47d38d10 1196
phungductung 0:8ede47d38d10 1197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/