PHung Tung / DISCO-F746_WAV_PLAYER

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Dependencies:   F746_GUI SD_PlayerSkeleton F746_SAI_IO

SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:37:21 2019 +0000
Revision:
0:8ede47d38d10
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phungductung 0:8ede47d38d10 1 /**
phungductung 0:8ede47d38d10 2 ******************************************************************************
phungductung 0:8ede47d38d10 3 * @file stm32f7xx_hal_nand.c
phungductung 0:8ede47d38d10 4 * @author MCD Application Team
phungductung 0:8ede47d38d10 5 * @version V1.0.4
phungductung 0:8ede47d38d10 6 * @date 09-December-2015
phungductung 0:8ede47d38d10 7 * @brief NAND HAL module driver.
phungductung 0:8ede47d38d10 8 * This file provides a generic firmware to drive NAND memories mounted
phungductung 0:8ede47d38d10 9 * as external device.
phungductung 0:8ede47d38d10 10 *
phungductung 0:8ede47d38d10 11 @verbatim
phungductung 0:8ede47d38d10 12 ==============================================================================
phungductung 0:8ede47d38d10 13 ##### How to use this driver #####
phungductung 0:8ede47d38d10 14 ==============================================================================
phungductung 0:8ede47d38d10 15 [..]
phungductung 0:8ede47d38d10 16 This driver is a generic layered driver which contains a set of APIs used to
phungductung 0:8ede47d38d10 17 control NAND flash memories. It uses the FMC/FSMC layer functions to interface
phungductung 0:8ede47d38d10 18 with NAND devices. This driver is used as follows:
phungductung 0:8ede47d38d10 19
phungductung 0:8ede47d38d10 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
phungductung 0:8ede47d38d10 21 with control and timing parameters for both common and attribute spaces.
phungductung 0:8ede47d38d10 22
phungductung 0:8ede47d38d10 23 (+) Read NAND flash memory maker and device IDs using the function
phungductung 0:8ede47d38d10 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
phungductung 0:8ede47d38d10 25 structure declared by the function caller.
phungductung 0:8ede47d38d10 26
phungductung 0:8ede47d38d10 27 (+) Access NAND flash memory by read/write operations using the functions
phungductung 0:8ede47d38d10 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
phungductung 0:8ede47d38d10 29 to read/write page(s)/spare area(s). These functions use specific device
phungductung 0:8ede47d38d10 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
phungductung 0:8ede47d38d10 31 structure. The read/write address information is contained by the Nand_Address_Typedef
phungductung 0:8ede47d38d10 32 structure passed as parameter.
phungductung 0:8ede47d38d10 33
phungductung 0:8ede47d38d10 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
phungductung 0:8ede47d38d10 35
phungductung 0:8ede47d38d10 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
phungductung 0:8ede47d38d10 37 The erase block address information is contained in the Nand_Address_Typedef
phungductung 0:8ede47d38d10 38 structure passed as parameter.
phungductung 0:8ede47d38d10 39
phungductung 0:8ede47d38d10 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
phungductung 0:8ede47d38d10 41
phungductung 0:8ede47d38d10 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
phungductung 0:8ede47d38d10 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
phungductung 0:8ede47d38d10 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
phungductung 0:8ede47d38d10 45
phungductung 0:8ede47d38d10 46 (+) You can monitor the NAND device HAL state by calling the function
phungductung 0:8ede47d38d10 47 HAL_NAND_GetState()
phungductung 0:8ede47d38d10 48
phungductung 0:8ede47d38d10 49 [..]
phungductung 0:8ede47d38d10 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
phungductung 0:8ede47d38d10 51 If a NAND flash device contains different operations and/or implementations,
phungductung 0:8ede47d38d10 52 it should be implemented separately.
phungductung 0:8ede47d38d10 53
phungductung 0:8ede47d38d10 54 @endverbatim
phungductung 0:8ede47d38d10 55 ******************************************************************************
phungductung 0:8ede47d38d10 56 * @attention
phungductung 0:8ede47d38d10 57 *
phungductung 0:8ede47d38d10 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:8ede47d38d10 59 *
phungductung 0:8ede47d38d10 60 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:8ede47d38d10 61 * are permitted provided that the following conditions are met:
phungductung 0:8ede47d38d10 62 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:8ede47d38d10 63 * this list of conditions and the following disclaimer.
phungductung 0:8ede47d38d10 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:8ede47d38d10 65 * this list of conditions and the following disclaimer in the documentation
phungductung 0:8ede47d38d10 66 * and/or other materials provided with the distribution.
phungductung 0:8ede47d38d10 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:8ede47d38d10 68 * may be used to endorse or promote products derived from this software
phungductung 0:8ede47d38d10 69 * without specific prior written permission.
phungductung 0:8ede47d38d10 70 *
phungductung 0:8ede47d38d10 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:8ede47d38d10 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:8ede47d38d10 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:8ede47d38d10 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:8ede47d38d10 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:8ede47d38d10 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:8ede47d38d10 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:8ede47d38d10 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:8ede47d38d10 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:8ede47d38d10 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:8ede47d38d10 81 *
phungductung 0:8ede47d38d10 82 ******************************************************************************
phungductung 0:8ede47d38d10 83 */
phungductung 0:8ede47d38d10 84
phungductung 0:8ede47d38d10 85 /* Includes ------------------------------------------------------------------*/
phungductung 0:8ede47d38d10 86 #include "stm32f7xx_hal.h"
phungductung 0:8ede47d38d10 87
phungductung 0:8ede47d38d10 88 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:8ede47d38d10 89 * @{
phungductung 0:8ede47d38d10 90 */
phungductung 0:8ede47d38d10 91
phungductung 0:8ede47d38d10 92
phungductung 0:8ede47d38d10 93 #ifdef HAL_NAND_MODULE_ENABLED
phungductung 0:8ede47d38d10 94
phungductung 0:8ede47d38d10 95 /** @defgroup NAND NAND
phungductung 0:8ede47d38d10 96 * @brief NAND HAL module driver
phungductung 0:8ede47d38d10 97 * @{
phungductung 0:8ede47d38d10 98 */
phungductung 0:8ede47d38d10 99
phungductung 0:8ede47d38d10 100 /* Private typedef -----------------------------------------------------------*/
phungductung 0:8ede47d38d10 101 /* Private Constants ------------------------------------------------------------*/
phungductung 0:8ede47d38d10 102 /* Private macro -------------------------------------------------------------*/
phungductung 0:8ede47d38d10 103 /* Private variables ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 104 /* Private function prototypes -----------------------------------------------*/
phungductung 0:8ede47d38d10 105 /* Exported functions ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 106
phungductung 0:8ede47d38d10 107 /** @defgroup NAND_Exported_Functions NAND Exported Functions
phungductung 0:8ede47d38d10 108 * @{
phungductung 0:8ede47d38d10 109 */
phungductung 0:8ede47d38d10 110
phungductung 0:8ede47d38d10 111 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
phungductung 0:8ede47d38d10 112 * @brief Initialization and Configuration functions
phungductung 0:8ede47d38d10 113 *
phungductung 0:8ede47d38d10 114 @verbatim
phungductung 0:8ede47d38d10 115 ==============================================================================
phungductung 0:8ede47d38d10 116 ##### NAND Initialization and de-initialization functions #####
phungductung 0:8ede47d38d10 117 ==============================================================================
phungductung 0:8ede47d38d10 118 [..]
phungductung 0:8ede47d38d10 119 This section provides functions allowing to initialize/de-initialize
phungductung 0:8ede47d38d10 120 the NAND memory
phungductung 0:8ede47d38d10 121
phungductung 0:8ede47d38d10 122 @endverbatim
phungductung 0:8ede47d38d10 123 * @{
phungductung 0:8ede47d38d10 124 */
phungductung 0:8ede47d38d10 125
phungductung 0:8ede47d38d10 126 /**
phungductung 0:8ede47d38d10 127 * @brief Perform NAND memory Initialization sequence
phungductung 0:8ede47d38d10 128 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 129 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 130 * @param ComSpace_Timing: pointer to Common space timing structure
phungductung 0:8ede47d38d10 131 * @param AttSpace_Timing: pointer to Attribute space timing structure
phungductung 0:8ede47d38d10 132 * @retval HAL status
phungductung 0:8ede47d38d10 133 */
phungductung 0:8ede47d38d10 134 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
phungductung 0:8ede47d38d10 135 {
phungductung 0:8ede47d38d10 136 /* Check the NAND handle state */
phungductung 0:8ede47d38d10 137 if(hnand == NULL)
phungductung 0:8ede47d38d10 138 {
phungductung 0:8ede47d38d10 139 return HAL_ERROR;
phungductung 0:8ede47d38d10 140 }
phungductung 0:8ede47d38d10 141
phungductung 0:8ede47d38d10 142 if(hnand->State == HAL_NAND_STATE_RESET)
phungductung 0:8ede47d38d10 143 {
phungductung 0:8ede47d38d10 144 /* Allocate lock resource and initialize it */
phungductung 0:8ede47d38d10 145 hnand->Lock = HAL_UNLOCKED;
phungductung 0:8ede47d38d10 146 /* Initialize the low level hardware (MSP) */
phungductung 0:8ede47d38d10 147 HAL_NAND_MspInit(hnand);
phungductung 0:8ede47d38d10 148 }
phungductung 0:8ede47d38d10 149
phungductung 0:8ede47d38d10 150 /* Initialize NAND control Interface */
phungductung 0:8ede47d38d10 151 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
phungductung 0:8ede47d38d10 152
phungductung 0:8ede47d38d10 153 /* Initialize NAND common space timing Interface */
phungductung 0:8ede47d38d10 154 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
phungductung 0:8ede47d38d10 155
phungductung 0:8ede47d38d10 156 /* Initialize NAND attribute space timing Interface */
phungductung 0:8ede47d38d10 157 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
phungductung 0:8ede47d38d10 158
phungductung 0:8ede47d38d10 159 /* Enable the NAND device */
phungductung 0:8ede47d38d10 160 __FMC_NAND_ENABLE(hnand->Instance);
phungductung 0:8ede47d38d10 161
phungductung 0:8ede47d38d10 162 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 163 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 164
phungductung 0:8ede47d38d10 165 return HAL_OK;
phungductung 0:8ede47d38d10 166 }
phungductung 0:8ede47d38d10 167
phungductung 0:8ede47d38d10 168 /**
phungductung 0:8ede47d38d10 169 * @brief Perform NAND memory De-Initialization sequence
phungductung 0:8ede47d38d10 170 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 171 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 172 * @retval HAL status
phungductung 0:8ede47d38d10 173 */
phungductung 0:8ede47d38d10 174 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 175 {
phungductung 0:8ede47d38d10 176 /* Initialize the low level hardware (MSP) */
phungductung 0:8ede47d38d10 177 HAL_NAND_MspDeInit(hnand);
phungductung 0:8ede47d38d10 178
phungductung 0:8ede47d38d10 179 /* Configure the NAND registers with their reset values */
phungductung 0:8ede47d38d10 180 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
phungductung 0:8ede47d38d10 181
phungductung 0:8ede47d38d10 182 /* Reset the NAND controller state */
phungductung 0:8ede47d38d10 183 hnand->State = HAL_NAND_STATE_RESET;
phungductung 0:8ede47d38d10 184
phungductung 0:8ede47d38d10 185 /* Release Lock */
phungductung 0:8ede47d38d10 186 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 187
phungductung 0:8ede47d38d10 188 return HAL_OK;
phungductung 0:8ede47d38d10 189 }
phungductung 0:8ede47d38d10 190
phungductung 0:8ede47d38d10 191 /**
phungductung 0:8ede47d38d10 192 * @brief NAND MSP Init
phungductung 0:8ede47d38d10 193 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 194 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 195 * @retval None
phungductung 0:8ede47d38d10 196 */
phungductung 0:8ede47d38d10 197 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 198 {
phungductung 0:8ede47d38d10 199 /* Prevent unused argument(s) compilation warning */
phungductung 0:8ede47d38d10 200 UNUSED(hnand);
phungductung 0:8ede47d38d10 201
phungductung 0:8ede47d38d10 202 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:8ede47d38d10 203 the HAL_NAND_MspInit could be implemented in the user file
phungductung 0:8ede47d38d10 204 */
phungductung 0:8ede47d38d10 205 }
phungductung 0:8ede47d38d10 206
phungductung 0:8ede47d38d10 207 /**
phungductung 0:8ede47d38d10 208 * @brief NAND MSP DeInit
phungductung 0:8ede47d38d10 209 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 210 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 211 * @retval None
phungductung 0:8ede47d38d10 212 */
phungductung 0:8ede47d38d10 213 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 214 {
phungductung 0:8ede47d38d10 215 /* Prevent unused argument(s) compilation warning */
phungductung 0:8ede47d38d10 216 UNUSED(hnand);
phungductung 0:8ede47d38d10 217
phungductung 0:8ede47d38d10 218 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:8ede47d38d10 219 the HAL_NAND_MspDeInit could be implemented in the user file
phungductung 0:8ede47d38d10 220 */
phungductung 0:8ede47d38d10 221 }
phungductung 0:8ede47d38d10 222
phungductung 0:8ede47d38d10 223
phungductung 0:8ede47d38d10 224 /**
phungductung 0:8ede47d38d10 225 * @brief This function handles NAND device interrupt request.
phungductung 0:8ede47d38d10 226 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 227 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 228 * @retval HAL status
phungductung 0:8ede47d38d10 229 */
phungductung 0:8ede47d38d10 230 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 231 {
phungductung 0:8ede47d38d10 232 /* Check NAND interrupt Rising edge flag */
phungductung 0:8ede47d38d10 233 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
phungductung 0:8ede47d38d10 234 {
phungductung 0:8ede47d38d10 235 /* NAND interrupt callback*/
phungductung 0:8ede47d38d10 236 HAL_NAND_ITCallback(hnand);
phungductung 0:8ede47d38d10 237
phungductung 0:8ede47d38d10 238 /* Clear NAND interrupt Rising edge pending bit */
phungductung 0:8ede47d38d10 239 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
phungductung 0:8ede47d38d10 240 }
phungductung 0:8ede47d38d10 241
phungductung 0:8ede47d38d10 242 /* Check NAND interrupt Level flag */
phungductung 0:8ede47d38d10 243 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
phungductung 0:8ede47d38d10 244 {
phungductung 0:8ede47d38d10 245 /* NAND interrupt callback*/
phungductung 0:8ede47d38d10 246 HAL_NAND_ITCallback(hnand);
phungductung 0:8ede47d38d10 247
phungductung 0:8ede47d38d10 248 /* Clear NAND interrupt Level pending bit */
phungductung 0:8ede47d38d10 249 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
phungductung 0:8ede47d38d10 250 }
phungductung 0:8ede47d38d10 251
phungductung 0:8ede47d38d10 252 /* Check NAND interrupt Falling edge flag */
phungductung 0:8ede47d38d10 253 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
phungductung 0:8ede47d38d10 254 {
phungductung 0:8ede47d38d10 255 /* NAND interrupt callback*/
phungductung 0:8ede47d38d10 256 HAL_NAND_ITCallback(hnand);
phungductung 0:8ede47d38d10 257
phungductung 0:8ede47d38d10 258 /* Clear NAND interrupt Falling edge pending bit */
phungductung 0:8ede47d38d10 259 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
phungductung 0:8ede47d38d10 260 }
phungductung 0:8ede47d38d10 261
phungductung 0:8ede47d38d10 262 /* Check NAND interrupt FIFO empty flag */
phungductung 0:8ede47d38d10 263 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
phungductung 0:8ede47d38d10 264 {
phungductung 0:8ede47d38d10 265 /* NAND interrupt callback*/
phungductung 0:8ede47d38d10 266 HAL_NAND_ITCallback(hnand);
phungductung 0:8ede47d38d10 267
phungductung 0:8ede47d38d10 268 /* Clear NAND interrupt FIFO empty pending bit */
phungductung 0:8ede47d38d10 269 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
phungductung 0:8ede47d38d10 270 }
phungductung 0:8ede47d38d10 271
phungductung 0:8ede47d38d10 272 }
phungductung 0:8ede47d38d10 273
phungductung 0:8ede47d38d10 274 /**
phungductung 0:8ede47d38d10 275 * @brief NAND interrupt feature callback
phungductung 0:8ede47d38d10 276 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 277 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 278 * @retval None
phungductung 0:8ede47d38d10 279 */
phungductung 0:8ede47d38d10 280 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 281 {
phungductung 0:8ede47d38d10 282 /* Prevent unused argument(s) compilation warning */
phungductung 0:8ede47d38d10 283 UNUSED(hnand);
phungductung 0:8ede47d38d10 284
phungductung 0:8ede47d38d10 285 /* NOTE : This function Should not be modified, when the callback is needed,
phungductung 0:8ede47d38d10 286 the HAL_NAND_ITCallback could be implemented in the user file
phungductung 0:8ede47d38d10 287 */
phungductung 0:8ede47d38d10 288 }
phungductung 0:8ede47d38d10 289
phungductung 0:8ede47d38d10 290 /**
phungductung 0:8ede47d38d10 291 * @}
phungductung 0:8ede47d38d10 292 */
phungductung 0:8ede47d38d10 293
phungductung 0:8ede47d38d10 294 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
phungductung 0:8ede47d38d10 295 * @brief Input Output and memory control functions
phungductung 0:8ede47d38d10 296 *
phungductung 0:8ede47d38d10 297 @verbatim
phungductung 0:8ede47d38d10 298 ==============================================================================
phungductung 0:8ede47d38d10 299 ##### NAND Input and Output functions #####
phungductung 0:8ede47d38d10 300 ==============================================================================
phungductung 0:8ede47d38d10 301 [..]
phungductung 0:8ede47d38d10 302 This section provides functions allowing to use and control the NAND
phungductung 0:8ede47d38d10 303 memory
phungductung 0:8ede47d38d10 304
phungductung 0:8ede47d38d10 305 @endverbatim
phungductung 0:8ede47d38d10 306 * @{
phungductung 0:8ede47d38d10 307 */
phungductung 0:8ede47d38d10 308
phungductung 0:8ede47d38d10 309 /**
phungductung 0:8ede47d38d10 310 * @brief Read the NAND memory electronic signature
phungductung 0:8ede47d38d10 311 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 312 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 313 * @param pNAND_ID: NAND ID structure
phungductung 0:8ede47d38d10 314 * @retval HAL status
phungductung 0:8ede47d38d10 315 */
phungductung 0:8ede47d38d10 316 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
phungductung 0:8ede47d38d10 317 {
phungductung 0:8ede47d38d10 318 __IO uint32_t data = 0;
phungductung 0:8ede47d38d10 319 uint32_t deviceAddress = 0;
phungductung 0:8ede47d38d10 320
phungductung 0:8ede47d38d10 321 /* Process Locked */
phungductung 0:8ede47d38d10 322 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 323
phungductung 0:8ede47d38d10 324 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 325 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 326 {
phungductung 0:8ede47d38d10 327 return HAL_BUSY;
phungductung 0:8ede47d38d10 328 }
phungductung 0:8ede47d38d10 329
phungductung 0:8ede47d38d10 330 /* Identify the device address */
phungductung 0:8ede47d38d10 331 deviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 332
phungductung 0:8ede47d38d10 333 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 334 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 335
phungductung 0:8ede47d38d10 336 /* Send Read ID command sequence */
phungductung 0:8ede47d38d10 337 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
phungductung 0:8ede47d38d10 338 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:8ede47d38d10 339
phungductung 0:8ede47d38d10 340 /* Read the electronic signature from NAND flash */
phungductung 0:8ede47d38d10 341 data = *(__IO uint32_t *)deviceAddress;
phungductung 0:8ede47d38d10 342
phungductung 0:8ede47d38d10 343 /* Return the data read */
phungductung 0:8ede47d38d10 344 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
phungductung 0:8ede47d38d10 345 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
phungductung 0:8ede47d38d10 346 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
phungductung 0:8ede47d38d10 347 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
phungductung 0:8ede47d38d10 348
phungductung 0:8ede47d38d10 349 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 350 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 351
phungductung 0:8ede47d38d10 352 /* Process unlocked */
phungductung 0:8ede47d38d10 353 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 354
phungductung 0:8ede47d38d10 355 return HAL_OK;
phungductung 0:8ede47d38d10 356 }
phungductung 0:8ede47d38d10 357
phungductung 0:8ede47d38d10 358 /**
phungductung 0:8ede47d38d10 359 * @brief NAND memory reset
phungductung 0:8ede47d38d10 360 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 361 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 362 * @retval HAL status
phungductung 0:8ede47d38d10 363 */
phungductung 0:8ede47d38d10 364 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 365 {
phungductung 0:8ede47d38d10 366 uint32_t deviceAddress = 0;
phungductung 0:8ede47d38d10 367
phungductung 0:8ede47d38d10 368 /* Process Locked */
phungductung 0:8ede47d38d10 369 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 370
phungductung 0:8ede47d38d10 371 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 372 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 373 {
phungductung 0:8ede47d38d10 374 return HAL_BUSY;
phungductung 0:8ede47d38d10 375 }
phungductung 0:8ede47d38d10 376
phungductung 0:8ede47d38d10 377 /* Identify the device address */
phungductung 0:8ede47d38d10 378 deviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 379
phungductung 0:8ede47d38d10 380 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 381 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 382
phungductung 0:8ede47d38d10 383 /* Send NAND reset command */
phungductung 0:8ede47d38d10 384 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
phungductung 0:8ede47d38d10 385
phungductung 0:8ede47d38d10 386
phungductung 0:8ede47d38d10 387 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 388 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 389
phungductung 0:8ede47d38d10 390 /* Process unlocked */
phungductung 0:8ede47d38d10 391 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 392
phungductung 0:8ede47d38d10 393 return HAL_OK;
phungductung 0:8ede47d38d10 394
phungductung 0:8ede47d38d10 395 }
phungductung 0:8ede47d38d10 396
phungductung 0:8ede47d38d10 397 /**
phungductung 0:8ede47d38d10 398 * @brief Read Page(s) from NAND memory block
phungductung 0:8ede47d38d10 399 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 400 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 401 * @param pAddress : pointer to NAND address structure
phungductung 0:8ede47d38d10 402 * @param pBuffer : pointer to destination read buffer
phungductung 0:8ede47d38d10 403 * @param NumPageToRead : number of pages to read from block
phungductung 0:8ede47d38d10 404 * @retval HAL status
phungductung 0:8ede47d38d10 405 */
phungductung 0:8ede47d38d10 406 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
phungductung 0:8ede47d38d10 407 {
phungductung 0:8ede47d38d10 408 __IO uint32_t index = 0;
phungductung 0:8ede47d38d10 409 uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
phungductung 0:8ede47d38d10 410
phungductung 0:8ede47d38d10 411 /* Process Locked */
phungductung 0:8ede47d38d10 412 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 413
phungductung 0:8ede47d38d10 414 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 415 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 416 {
phungductung 0:8ede47d38d10 417 return HAL_BUSY;
phungductung 0:8ede47d38d10 418 }
phungductung 0:8ede47d38d10 419
phungductung 0:8ede47d38d10 420 /* Identify the device address */
phungductung 0:8ede47d38d10 421 deviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 422
phungductung 0:8ede47d38d10 423 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 424 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 425
phungductung 0:8ede47d38d10 426 /* NAND raw address calculation */
phungductung 0:8ede47d38d10 427 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:8ede47d38d10 428
phungductung 0:8ede47d38d10 429 /* Page(s) read loop */
phungductung 0:8ede47d38d10 430 while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
phungductung 0:8ede47d38d10 431 {
phungductung 0:8ede47d38d10 432 /* update the buffer size */
phungductung 0:8ede47d38d10 433 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
phungductung 0:8ede47d38d10 434
phungductung 0:8ede47d38d10 435 /* Send read page command sequence */
phungductung 0:8ede47d38d10 436 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
phungductung 0:8ede47d38d10 437
phungductung 0:8ede47d38d10 438 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:8ede47d38d10 439 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 440 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 441 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 442
phungductung 0:8ede47d38d10 443 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:8ede47d38d10 444 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:8ede47d38d10 445 {
phungductung 0:8ede47d38d10 446 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 447 }
phungductung 0:8ede47d38d10 448
phungductung 0:8ede47d38d10 449 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
phungductung 0:8ede47d38d10 450
phungductung 0:8ede47d38d10 451 /* Get Data into Buffer */
phungductung 0:8ede47d38d10 452 for(index = 0; index < size; index++)
phungductung 0:8ede47d38d10 453 {
phungductung 0:8ede47d38d10 454 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
phungductung 0:8ede47d38d10 455 }
phungductung 0:8ede47d38d10 456
phungductung 0:8ede47d38d10 457 /* Increment read pages number */
phungductung 0:8ede47d38d10 458 numPagesRead++;
phungductung 0:8ede47d38d10 459
phungductung 0:8ede47d38d10 460 /* Decrement pages to read */
phungductung 0:8ede47d38d10 461 NumPageToRead--;
phungductung 0:8ede47d38d10 462
phungductung 0:8ede47d38d10 463 /* Increment the NAND address */
phungductung 0:8ede47d38d10 464 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
phungductung 0:8ede47d38d10 465
phungductung 0:8ede47d38d10 466 }
phungductung 0:8ede47d38d10 467
phungductung 0:8ede47d38d10 468 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 469 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 470
phungductung 0:8ede47d38d10 471 /* Process unlocked */
phungductung 0:8ede47d38d10 472 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 473
phungductung 0:8ede47d38d10 474 return HAL_OK;
phungductung 0:8ede47d38d10 475
phungductung 0:8ede47d38d10 476 }
phungductung 0:8ede47d38d10 477
phungductung 0:8ede47d38d10 478 /**
phungductung 0:8ede47d38d10 479 * @brief Write Page(s) to NAND memory block
phungductung 0:8ede47d38d10 480 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 481 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 482 * @param pAddress : pointer to NAND address structure
phungductung 0:8ede47d38d10 483 * @param pBuffer : pointer to source buffer to write
phungductung 0:8ede47d38d10 484 * @param NumPageToWrite : number of pages to write to block
phungductung 0:8ede47d38d10 485 * @retval HAL status
phungductung 0:8ede47d38d10 486 */
phungductung 0:8ede47d38d10 487 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
phungductung 0:8ede47d38d10 488 {
phungductung 0:8ede47d38d10 489 __IO uint32_t index = 0;
phungductung 0:8ede47d38d10 490 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 491 uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
phungductung 0:8ede47d38d10 492
phungductung 0:8ede47d38d10 493 /* Process Locked */
phungductung 0:8ede47d38d10 494 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 495
phungductung 0:8ede47d38d10 496 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 497 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 498 {
phungductung 0:8ede47d38d10 499 return HAL_BUSY;
phungductung 0:8ede47d38d10 500 }
phungductung 0:8ede47d38d10 501
phungductung 0:8ede47d38d10 502 /* Identify the device address */
phungductung 0:8ede47d38d10 503 deviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 504
phungductung 0:8ede47d38d10 505 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 506 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 507
phungductung 0:8ede47d38d10 508 /* NAND raw address calculation */
phungductung 0:8ede47d38d10 509 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:8ede47d38d10 510
phungductung 0:8ede47d38d10 511 /* Page(s) write loop */
phungductung 0:8ede47d38d10 512 while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
phungductung 0:8ede47d38d10 513 {
phungductung 0:8ede47d38d10 514 /* update the buffer size */
phungductung 0:8ede47d38d10 515 size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
phungductung 0:8ede47d38d10 516
phungductung 0:8ede47d38d10 517 /* Send write page command sequence */
phungductung 0:8ede47d38d10 518 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
phungductung 0:8ede47d38d10 519 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
phungductung 0:8ede47d38d10 520
phungductung 0:8ede47d38d10 521 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:8ede47d38d10 522 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 523 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 524 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 525 __DSB();
phungductung 0:8ede47d38d10 526
phungductung 0:8ede47d38d10 527 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:8ede47d38d10 528 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:8ede47d38d10 529 {
phungductung 0:8ede47d38d10 530 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 531 __DSB();
phungductung 0:8ede47d38d10 532 }
phungductung 0:8ede47d38d10 533
phungductung 0:8ede47d38d10 534 /* Write data to memory */
phungductung 0:8ede47d38d10 535 for(index = 0; index < size; index++)
phungductung 0:8ede47d38d10 536 {
phungductung 0:8ede47d38d10 537 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
phungductung 0:8ede47d38d10 538 __DSB();
phungductung 0:8ede47d38d10 539 }
phungductung 0:8ede47d38d10 540
phungductung 0:8ede47d38d10 541 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
phungductung 0:8ede47d38d10 542
phungductung 0:8ede47d38d10 543 /* Read status until NAND is ready */
phungductung 0:8ede47d38d10 544 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
phungductung 0:8ede47d38d10 545 {
phungductung 0:8ede47d38d10 546 /* Get tick */
phungductung 0:8ede47d38d10 547 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 548
phungductung 0:8ede47d38d10 549 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
phungductung 0:8ede47d38d10 550 {
phungductung 0:8ede47d38d10 551 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 552 }
phungductung 0:8ede47d38d10 553 }
phungductung 0:8ede47d38d10 554
phungductung 0:8ede47d38d10 555 /* Increment written pages number */
phungductung 0:8ede47d38d10 556 numPagesWritten++;
phungductung 0:8ede47d38d10 557
phungductung 0:8ede47d38d10 558 /* Decrement pages to write */
phungductung 0:8ede47d38d10 559 NumPageToWrite--;
phungductung 0:8ede47d38d10 560
phungductung 0:8ede47d38d10 561 /* Increment the NAND address */
phungductung 0:8ede47d38d10 562 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
phungductung 0:8ede47d38d10 563 }
phungductung 0:8ede47d38d10 564
phungductung 0:8ede47d38d10 565 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 566 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 567
phungductung 0:8ede47d38d10 568 /* Process unlocked */
phungductung 0:8ede47d38d10 569 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 570
phungductung 0:8ede47d38d10 571 return HAL_OK;
phungductung 0:8ede47d38d10 572 }
phungductung 0:8ede47d38d10 573
phungductung 0:8ede47d38d10 574 /**
phungductung 0:8ede47d38d10 575 * @brief Read Spare area(s) from NAND memory
phungductung 0:8ede47d38d10 576 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 577 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 578 * @param pAddress : pointer to NAND address structure
phungductung 0:8ede47d38d10 579 * @param pBuffer: pointer to source buffer to write
phungductung 0:8ede47d38d10 580 * @param NumSpareAreaToRead: Number of spare area to read
phungductung 0:8ede47d38d10 581 * @retval HAL status
phungductung 0:8ede47d38d10 582 */
phungductung 0:8ede47d38d10 583 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
phungductung 0:8ede47d38d10 584 {
phungductung 0:8ede47d38d10 585 __IO uint32_t index = 0;
phungductung 0:8ede47d38d10 586 uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
phungductung 0:8ede47d38d10 587
phungductung 0:8ede47d38d10 588 /* Process Locked */
phungductung 0:8ede47d38d10 589 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 590
phungductung 0:8ede47d38d10 591 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 592 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 593 {
phungductung 0:8ede47d38d10 594 return HAL_BUSY;
phungductung 0:8ede47d38d10 595 }
phungductung 0:8ede47d38d10 596
phungductung 0:8ede47d38d10 597 /* Identify the device address */
phungductung 0:8ede47d38d10 598 deviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 599
phungductung 0:8ede47d38d10 600 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 601 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 602
phungductung 0:8ede47d38d10 603 /* NAND raw address calculation */
phungductung 0:8ede47d38d10 604 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:8ede47d38d10 605
phungductung 0:8ede47d38d10 606 /* Spare area(s) read loop */
phungductung 0:8ede47d38d10 607 while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
phungductung 0:8ede47d38d10 608 {
phungductung 0:8ede47d38d10 609
phungductung 0:8ede47d38d10 610 /* update the buffer size */
phungductung 0:8ede47d38d10 611 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
phungductung 0:8ede47d38d10 612
phungductung 0:8ede47d38d10 613 /* Send read spare area command sequence */
phungductung 0:8ede47d38d10 614 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
phungductung 0:8ede47d38d10 615
phungductung 0:8ede47d38d10 616 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:8ede47d38d10 617 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 618 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 619 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 620
phungductung 0:8ede47d38d10 621 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:8ede47d38d10 622 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:8ede47d38d10 623 {
phungductung 0:8ede47d38d10 624 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 625 }
phungductung 0:8ede47d38d10 626
phungductung 0:8ede47d38d10 627 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
phungductung 0:8ede47d38d10 628
phungductung 0:8ede47d38d10 629 /* Get Data into Buffer */
phungductung 0:8ede47d38d10 630 for(index = 0; index < size; index++)
phungductung 0:8ede47d38d10 631 {
phungductung 0:8ede47d38d10 632 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
phungductung 0:8ede47d38d10 633 }
phungductung 0:8ede47d38d10 634
phungductung 0:8ede47d38d10 635 /* Increment read spare areas number */
phungductung 0:8ede47d38d10 636 numSpareAreaRead++;
phungductung 0:8ede47d38d10 637
phungductung 0:8ede47d38d10 638 /* Decrement spare areas to read */
phungductung 0:8ede47d38d10 639 NumSpareAreaToRead--;
phungductung 0:8ede47d38d10 640
phungductung 0:8ede47d38d10 641 /* Increment the NAND address */
phungductung 0:8ede47d38d10 642 nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
phungductung 0:8ede47d38d10 643 }
phungductung 0:8ede47d38d10 644
phungductung 0:8ede47d38d10 645 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 646 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 647
phungductung 0:8ede47d38d10 648 /* Process unlocked */
phungductung 0:8ede47d38d10 649 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 650
phungductung 0:8ede47d38d10 651 return HAL_OK;
phungductung 0:8ede47d38d10 652 }
phungductung 0:8ede47d38d10 653
phungductung 0:8ede47d38d10 654 /**
phungductung 0:8ede47d38d10 655 * @brief Write Spare area(s) to NAND memory
phungductung 0:8ede47d38d10 656 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 657 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 658 * @param pAddress : pointer to NAND address structure
phungductung 0:8ede47d38d10 659 * @param pBuffer : pointer to source buffer to write
phungductung 0:8ede47d38d10 660 * @param NumSpareAreaTowrite : number of spare areas to write to block
phungductung 0:8ede47d38d10 661 * @retval HAL status
phungductung 0:8ede47d38d10 662 */
phungductung 0:8ede47d38d10 663 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
phungductung 0:8ede47d38d10 664 {
phungductung 0:8ede47d38d10 665 __IO uint32_t index = 0;
phungductung 0:8ede47d38d10 666 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 667 uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
phungductung 0:8ede47d38d10 668
phungductung 0:8ede47d38d10 669 /* Process Locked */
phungductung 0:8ede47d38d10 670 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 671
phungductung 0:8ede47d38d10 672 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 673 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 674 {
phungductung 0:8ede47d38d10 675 return HAL_BUSY;
phungductung 0:8ede47d38d10 676 }
phungductung 0:8ede47d38d10 677
phungductung 0:8ede47d38d10 678 /* Identify the device address */
phungductung 0:8ede47d38d10 679 deviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 680
phungductung 0:8ede47d38d10 681 /* Update the FMC_NAND controller state */
phungductung 0:8ede47d38d10 682 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 683
phungductung 0:8ede47d38d10 684 /* NAND raw address calculation */
phungductung 0:8ede47d38d10 685 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
phungductung 0:8ede47d38d10 686
phungductung 0:8ede47d38d10 687 /* Spare area(s) write loop */
phungductung 0:8ede47d38d10 688 while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
phungductung 0:8ede47d38d10 689 {
phungductung 0:8ede47d38d10 690 /* update the buffer size */
phungductung 0:8ede47d38d10 691 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
phungductung 0:8ede47d38d10 692
phungductung 0:8ede47d38d10 693 /* Send write Spare area command sequence */
phungductung 0:8ede47d38d10 694 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
phungductung 0:8ede47d38d10 695 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
phungductung 0:8ede47d38d10 696
phungductung 0:8ede47d38d10 697 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
phungductung 0:8ede47d38d10 698 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 699 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 700 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 701 __DSB();
phungductung 0:8ede47d38d10 702 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:8ede47d38d10 703 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:8ede47d38d10 704 {
phungductung 0:8ede47d38d10 705 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
phungductung 0:8ede47d38d10 706 __DSB();
phungductung 0:8ede47d38d10 707 }
phungductung 0:8ede47d38d10 708
phungductung 0:8ede47d38d10 709 /* Write data to memory */
phungductung 0:8ede47d38d10 710 for(index = 0; index < size; index++)
phungductung 0:8ede47d38d10 711 {
phungductung 0:8ede47d38d10 712 *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
phungductung 0:8ede47d38d10 713 __DSB();
phungductung 0:8ede47d38d10 714 }
phungductung 0:8ede47d38d10 715
phungductung 0:8ede47d38d10 716 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
phungductung 0:8ede47d38d10 717 __DSB();
phungductung 0:8ede47d38d10 718
phungductung 0:8ede47d38d10 719 /* Read status until NAND is ready */
phungductung 0:8ede47d38d10 720 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
phungductung 0:8ede47d38d10 721 {
phungductung 0:8ede47d38d10 722 /* Get tick */
phungductung 0:8ede47d38d10 723 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 724
phungductung 0:8ede47d38d10 725 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
phungductung 0:8ede47d38d10 726 {
phungductung 0:8ede47d38d10 727 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 728 }
phungductung 0:8ede47d38d10 729 }
phungductung 0:8ede47d38d10 730
phungductung 0:8ede47d38d10 731 /* Increment written spare areas number */
phungductung 0:8ede47d38d10 732 numSpareAreaWritten++;
phungductung 0:8ede47d38d10 733
phungductung 0:8ede47d38d10 734 /* Decrement spare areas to write */
phungductung 0:8ede47d38d10 735 NumSpareAreaTowrite--;
phungductung 0:8ede47d38d10 736
phungductung 0:8ede47d38d10 737 /* Increment the NAND address */
phungductung 0:8ede47d38d10 738 nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
phungductung 0:8ede47d38d10 739 }
phungductung 0:8ede47d38d10 740
phungductung 0:8ede47d38d10 741 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 742 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 743
phungductung 0:8ede47d38d10 744 /* Process unlocked */
phungductung 0:8ede47d38d10 745 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 746
phungductung 0:8ede47d38d10 747 return HAL_OK;
phungductung 0:8ede47d38d10 748 }
phungductung 0:8ede47d38d10 749
phungductung 0:8ede47d38d10 750 /**
phungductung 0:8ede47d38d10 751 * @brief NAND memory Block erase
phungductung 0:8ede47d38d10 752 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 753 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 754 * @param pAddress : pointer to NAND address structure
phungductung 0:8ede47d38d10 755 * @retval HAL status
phungductung 0:8ede47d38d10 756 */
phungductung 0:8ede47d38d10 757 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
phungductung 0:8ede47d38d10 758 {
phungductung 0:8ede47d38d10 759 uint32_t DeviceAddress = 0;
phungductung 0:8ede47d38d10 760
phungductung 0:8ede47d38d10 761 /* Process Locked */
phungductung 0:8ede47d38d10 762 __HAL_LOCK(hnand);
phungductung 0:8ede47d38d10 763
phungductung 0:8ede47d38d10 764 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 765 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 766 {
phungductung 0:8ede47d38d10 767 return HAL_BUSY;
phungductung 0:8ede47d38d10 768 }
phungductung 0:8ede47d38d10 769
phungductung 0:8ede47d38d10 770 /* Identify the device address */
phungductung 0:8ede47d38d10 771 DeviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 772
phungductung 0:8ede47d38d10 773 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 774 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 775
phungductung 0:8ede47d38d10 776 /* Send Erase block command sequence */
phungductung 0:8ede47d38d10 777 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
phungductung 0:8ede47d38d10 778
phungductung 0:8ede47d38d10 779 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:8ede47d38d10 780 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:8ede47d38d10 781 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:8ede47d38d10 782 __DSB();
phungductung 0:8ede47d38d10 783
phungductung 0:8ede47d38d10 784 /* for 512 and 1 GB devices, 4th cycle is required */
phungductung 0:8ede47d38d10 785 if(hnand->Info.BlockNbr >= 1024)
phungductung 0:8ede47d38d10 786 {
phungductung 0:8ede47d38d10 787 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
phungductung 0:8ede47d38d10 788 __DSB();
phungductung 0:8ede47d38d10 789 }
phungductung 0:8ede47d38d10 790
phungductung 0:8ede47d38d10 791 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
phungductung 0:8ede47d38d10 792 __DSB();
phungductung 0:8ede47d38d10 793
phungductung 0:8ede47d38d10 794 /* Update the NAND controller state */
phungductung 0:8ede47d38d10 795 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 796
phungductung 0:8ede47d38d10 797 /* Process unlocked */
phungductung 0:8ede47d38d10 798 __HAL_UNLOCK(hnand);
phungductung 0:8ede47d38d10 799
phungductung 0:8ede47d38d10 800 return HAL_OK;
phungductung 0:8ede47d38d10 801 }
phungductung 0:8ede47d38d10 802
phungductung 0:8ede47d38d10 803 /**
phungductung 0:8ede47d38d10 804 * @brief NAND memory read status
phungductung 0:8ede47d38d10 805 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 806 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 807 * @retval NAND status
phungductung 0:8ede47d38d10 808 */
phungductung 0:8ede47d38d10 809 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 810 {
phungductung 0:8ede47d38d10 811 uint32_t data = 0;
phungductung 0:8ede47d38d10 812 uint32_t DeviceAddress = 0;
phungductung 0:8ede47d38d10 813
phungductung 0:8ede47d38d10 814 /* Identify the device address */
phungductung 0:8ede47d38d10 815 DeviceAddress = NAND_DEVICE;
phungductung 0:8ede47d38d10 816
phungductung 0:8ede47d38d10 817 /* Send Read status operation command */
phungductung 0:8ede47d38d10 818 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
phungductung 0:8ede47d38d10 819
phungductung 0:8ede47d38d10 820 /* Read status register data */
phungductung 0:8ede47d38d10 821 data = *(__IO uint8_t *)DeviceAddress;
phungductung 0:8ede47d38d10 822
phungductung 0:8ede47d38d10 823 /* Return the status */
phungductung 0:8ede47d38d10 824 if((data & NAND_ERROR) == NAND_ERROR)
phungductung 0:8ede47d38d10 825 {
phungductung 0:8ede47d38d10 826 return NAND_ERROR;
phungductung 0:8ede47d38d10 827 }
phungductung 0:8ede47d38d10 828 else if((data & NAND_READY) == NAND_READY)
phungductung 0:8ede47d38d10 829 {
phungductung 0:8ede47d38d10 830 return NAND_READY;
phungductung 0:8ede47d38d10 831 }
phungductung 0:8ede47d38d10 832
phungductung 0:8ede47d38d10 833 return NAND_BUSY;
phungductung 0:8ede47d38d10 834 }
phungductung 0:8ede47d38d10 835
phungductung 0:8ede47d38d10 836 /**
phungductung 0:8ede47d38d10 837 * @brief Increment the NAND memory address
phungductung 0:8ede47d38d10 838 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 839 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 840 * @param pAddress: pointer to NAND address structure
phungductung 0:8ede47d38d10 841 * @retval The new status of the increment address operation. It can be:
phungductung 0:8ede47d38d10 842 * - NAND_VALID_ADDRESS: When the new address is valid address
phungductung 0:8ede47d38d10 843 * - NAND_INVALID_ADDRESS: When the new address is invalid address
phungductung 0:8ede47d38d10 844 */
phungductung 0:8ede47d38d10 845 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
phungductung 0:8ede47d38d10 846 {
phungductung 0:8ede47d38d10 847 uint32_t status = NAND_VALID_ADDRESS;
phungductung 0:8ede47d38d10 848
phungductung 0:8ede47d38d10 849 /* Increment page address */
phungductung 0:8ede47d38d10 850 pAddress->Page++;
phungductung 0:8ede47d38d10 851
phungductung 0:8ede47d38d10 852 /* Check NAND address is valid */
phungductung 0:8ede47d38d10 853 if(pAddress->Page == hnand->Info.BlockSize)
phungductung 0:8ede47d38d10 854 {
phungductung 0:8ede47d38d10 855 pAddress->Page = 0;
phungductung 0:8ede47d38d10 856 pAddress->Block++;
phungductung 0:8ede47d38d10 857
phungductung 0:8ede47d38d10 858 if(pAddress->Block == hnand->Info.ZoneSize)
phungductung 0:8ede47d38d10 859 {
phungductung 0:8ede47d38d10 860 pAddress->Block = 0;
phungductung 0:8ede47d38d10 861 pAddress->Zone++;
phungductung 0:8ede47d38d10 862
phungductung 0:8ede47d38d10 863 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
phungductung 0:8ede47d38d10 864 {
phungductung 0:8ede47d38d10 865 status = NAND_INVALID_ADDRESS;
phungductung 0:8ede47d38d10 866 }
phungductung 0:8ede47d38d10 867 }
phungductung 0:8ede47d38d10 868 }
phungductung 0:8ede47d38d10 869
phungductung 0:8ede47d38d10 870 return (status);
phungductung 0:8ede47d38d10 871 }
phungductung 0:8ede47d38d10 872 /**
phungductung 0:8ede47d38d10 873 * @}
phungductung 0:8ede47d38d10 874 */
phungductung 0:8ede47d38d10 875
phungductung 0:8ede47d38d10 876 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
phungductung 0:8ede47d38d10 877 * @brief management functions
phungductung 0:8ede47d38d10 878 *
phungductung 0:8ede47d38d10 879 @verbatim
phungductung 0:8ede47d38d10 880 ==============================================================================
phungductung 0:8ede47d38d10 881 ##### NAND Control functions #####
phungductung 0:8ede47d38d10 882 ==============================================================================
phungductung 0:8ede47d38d10 883 [..]
phungductung 0:8ede47d38d10 884 This subsection provides a set of functions allowing to control dynamically
phungductung 0:8ede47d38d10 885 the NAND interface.
phungductung 0:8ede47d38d10 886
phungductung 0:8ede47d38d10 887 @endverbatim
phungductung 0:8ede47d38d10 888 * @{
phungductung 0:8ede47d38d10 889 */
phungductung 0:8ede47d38d10 890
phungductung 0:8ede47d38d10 891
phungductung 0:8ede47d38d10 892 /**
phungductung 0:8ede47d38d10 893 * @brief Enables dynamically NAND ECC feature.
phungductung 0:8ede47d38d10 894 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 895 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 896 * @retval HAL status
phungductung 0:8ede47d38d10 897 */
phungductung 0:8ede47d38d10 898 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 899 {
phungductung 0:8ede47d38d10 900 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 901 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 902 {
phungductung 0:8ede47d38d10 903 return HAL_BUSY;
phungductung 0:8ede47d38d10 904 }
phungductung 0:8ede47d38d10 905
phungductung 0:8ede47d38d10 906 /* Update the NAND state */
phungductung 0:8ede47d38d10 907 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 908
phungductung 0:8ede47d38d10 909 /* Enable ECC feature */
phungductung 0:8ede47d38d10 910 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
phungductung 0:8ede47d38d10 911
phungductung 0:8ede47d38d10 912 /* Update the NAND state */
phungductung 0:8ede47d38d10 913 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 914
phungductung 0:8ede47d38d10 915 return HAL_OK;
phungductung 0:8ede47d38d10 916 }
phungductung 0:8ede47d38d10 917
phungductung 0:8ede47d38d10 918 /**
phungductung 0:8ede47d38d10 919 * @brief Disables dynamically FMC_NAND ECC feature.
phungductung 0:8ede47d38d10 920 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 921 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 922 * @retval HAL status
phungductung 0:8ede47d38d10 923 */
phungductung 0:8ede47d38d10 924 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 925 {
phungductung 0:8ede47d38d10 926 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 927 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 928 {
phungductung 0:8ede47d38d10 929 return HAL_BUSY;
phungductung 0:8ede47d38d10 930 }
phungductung 0:8ede47d38d10 931
phungductung 0:8ede47d38d10 932 /* Update the NAND state */
phungductung 0:8ede47d38d10 933 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 934
phungductung 0:8ede47d38d10 935 /* Disable ECC feature */
phungductung 0:8ede47d38d10 936 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
phungductung 0:8ede47d38d10 937
phungductung 0:8ede47d38d10 938 /* Update the NAND state */
phungductung 0:8ede47d38d10 939 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 940
phungductung 0:8ede47d38d10 941 return HAL_OK;
phungductung 0:8ede47d38d10 942 }
phungductung 0:8ede47d38d10 943
phungductung 0:8ede47d38d10 944 /**
phungductung 0:8ede47d38d10 945 * @brief Disables dynamically NAND ECC feature.
phungductung 0:8ede47d38d10 946 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 947 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 948 * @param ECCval: pointer to ECC value
phungductung 0:8ede47d38d10 949 * @param Timeout: maximum timeout to wait
phungductung 0:8ede47d38d10 950 * @retval HAL status
phungductung 0:8ede47d38d10 951 */
phungductung 0:8ede47d38d10 952 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
phungductung 0:8ede47d38d10 953 {
phungductung 0:8ede47d38d10 954 HAL_StatusTypeDef status = HAL_OK;
phungductung 0:8ede47d38d10 955
phungductung 0:8ede47d38d10 956 /* Check the NAND controller state */
phungductung 0:8ede47d38d10 957 if(hnand->State == HAL_NAND_STATE_BUSY)
phungductung 0:8ede47d38d10 958 {
phungductung 0:8ede47d38d10 959 return HAL_BUSY;
phungductung 0:8ede47d38d10 960 }
phungductung 0:8ede47d38d10 961
phungductung 0:8ede47d38d10 962 /* Update the NAND state */
phungductung 0:8ede47d38d10 963 hnand->State = HAL_NAND_STATE_BUSY;
phungductung 0:8ede47d38d10 964
phungductung 0:8ede47d38d10 965 /* Get NAND ECC value */
phungductung 0:8ede47d38d10 966 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
phungductung 0:8ede47d38d10 967
phungductung 0:8ede47d38d10 968 /* Update the NAND state */
phungductung 0:8ede47d38d10 969 hnand->State = HAL_NAND_STATE_READY;
phungductung 0:8ede47d38d10 970
phungductung 0:8ede47d38d10 971 return status;
phungductung 0:8ede47d38d10 972 }
phungductung 0:8ede47d38d10 973
phungductung 0:8ede47d38d10 974 /**
phungductung 0:8ede47d38d10 975 * @}
phungductung 0:8ede47d38d10 976 */
phungductung 0:8ede47d38d10 977
phungductung 0:8ede47d38d10 978
phungductung 0:8ede47d38d10 979 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
phungductung 0:8ede47d38d10 980 * @brief Peripheral State functions
phungductung 0:8ede47d38d10 981 *
phungductung 0:8ede47d38d10 982 @verbatim
phungductung 0:8ede47d38d10 983 ==============================================================================
phungductung 0:8ede47d38d10 984 ##### NAND State functions #####
phungductung 0:8ede47d38d10 985 ==============================================================================
phungductung 0:8ede47d38d10 986 [..]
phungductung 0:8ede47d38d10 987 This subsection permits to get in run-time the status of the NAND controller
phungductung 0:8ede47d38d10 988 and the data flow.
phungductung 0:8ede47d38d10 989
phungductung 0:8ede47d38d10 990 @endverbatim
phungductung 0:8ede47d38d10 991 * @{
phungductung 0:8ede47d38d10 992 */
phungductung 0:8ede47d38d10 993
phungductung 0:8ede47d38d10 994 /**
phungductung 0:8ede47d38d10 995 * @brief return the NAND state
phungductung 0:8ede47d38d10 996 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 997 * the configuration information for NAND module.
phungductung 0:8ede47d38d10 998 * @retval HAL state
phungductung 0:8ede47d38d10 999 */
phungductung 0:8ede47d38d10 1000 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
phungductung 0:8ede47d38d10 1001 {
phungductung 0:8ede47d38d10 1002 return hnand->State;
phungductung 0:8ede47d38d10 1003 }
phungductung 0:8ede47d38d10 1004
phungductung 0:8ede47d38d10 1005 /**
phungductung 0:8ede47d38d10 1006 * @}
phungductung 0:8ede47d38d10 1007 */
phungductung 0:8ede47d38d10 1008
phungductung 0:8ede47d38d10 1009 /**
phungductung 0:8ede47d38d10 1010 * @}
phungductung 0:8ede47d38d10 1011 */
phungductung 0:8ede47d38d10 1012
phungductung 0:8ede47d38d10 1013 #endif /* HAL_NAND_MODULE_ENABLED */
phungductung 0:8ede47d38d10 1014
phungductung 0:8ede47d38d10 1015 /**
phungductung 0:8ede47d38d10 1016 * @}
phungductung 0:8ede47d38d10 1017 */
phungductung 0:8ede47d38d10 1018
phungductung 0:8ede47d38d10 1019 /**
phungductung 0:8ede47d38d10 1020 * @}
phungductung 0:8ede47d38d10 1021 */
phungductung 0:8ede47d38d10 1022
phungductung 0:8ede47d38d10 1023 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/