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SRC_STM32F7/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c@0:8ede47d38d10, 2019-06-04 (annotated)

Committer:
phungductung
Date:
Tue Jun 04 21:37:21 2019 +0000
Revision:
0:8ede47d38d10
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phungductung 0:8ede47d38d10 1 /**
phungductung 0:8ede47d38d10 2 ******************************************************************************
phungductung 0:8ede47d38d10 3 * @file stm32f7xx_hal_dma.c
phungductung 0:8ede47d38d10 4 * @author MCD Application Team
phungductung 0:8ede47d38d10 5 * @version V1.0.4
phungductung 0:8ede47d38d10 6 * @date 09-December-2015
phungductung 0:8ede47d38d10 7 * @brief DMA HAL module driver.
phungductung 0:8ede47d38d10 8 *
phungductung 0:8ede47d38d10 9 * This file provides firmware functions to manage the following
phungductung 0:8ede47d38d10 10 * functionalities of the Direct Memory Access (DMA) peripheral:
phungductung 0:8ede47d38d10 11 * + Initialization and de-initialization functions
phungductung 0:8ede47d38d10 12 * + IO operation functions
phungductung 0:8ede47d38d10 13 * + Peripheral State and errors functions
phungductung 0:8ede47d38d10 14 @verbatim
phungductung 0:8ede47d38d10 15 ==============================================================================
phungductung 0:8ede47d38d10 16 ##### How to use this driver #####
phungductung 0:8ede47d38d10 17 ==============================================================================
phungductung 0:8ede47d38d10 18 [..]
phungductung 0:8ede47d38d10 19 (#) Enable and configure the peripheral to be connected to the DMA Stream
phungductung 0:8ede47d38d10 20 (except for internal SRAM/FLASH memories: no initialization is
phungductung 0:8ede47d38d10 21 necessary) please refer to Reference manual for connection between peripherals
phungductung 0:8ede47d38d10 22 and DMA requests .
phungductung 0:8ede47d38d10 23
phungductung 0:8ede47d38d10 24 (#) For a given Stream, program the required configuration through the following parameters:
phungductung 0:8ede47d38d10 25 Transfer Direction, Source and Destination data formats,
phungductung 0:8ede47d38d10 26 Circular, Normal or peripheral flow control mode, Stream Priority level,
phungductung 0:8ede47d38d10 27 Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
phungductung 0:8ede47d38d10 28 Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
phungductung 0:8ede47d38d10 29
phungductung 0:8ede47d38d10 30 *** Polling mode IO operation ***
phungductung 0:8ede47d38d10 31 =================================
phungductung 0:8ede47d38d10 32 [..]
phungductung 0:8ede47d38d10 33 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
phungductung 0:8ede47d38d10 34 address and destination address and the Length of data to be transferred
phungductung 0:8ede47d38d10 35 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
phungductung 0:8ede47d38d10 36 case a fixed Timeout can be configured by User depending from his application.
phungductung 0:8ede47d38d10 37
phungductung 0:8ede47d38d10 38 *** Interrupt mode IO operation ***
phungductung 0:8ede47d38d10 39 ===================================
phungductung 0:8ede47d38d10 40 [..]
phungductung 0:8ede47d38d10 41 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
phungductung 0:8ede47d38d10 42 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
phungductung 0:8ede47d38d10 43 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
phungductung 0:8ede47d38d10 44 Source address and destination address and the Length of data to be transferred. In this
phungductung 0:8ede47d38d10 45 case the DMA interrupt is configured
phungductung 0:8ede47d38d10 46 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
phungductung 0:8ede47d38d10 47 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
phungductung 0:8ede47d38d10 48 add his own function by customization of function pointer XferCpltCallback and
phungductung 0:8ede47d38d10 49 XferErrorCallback (i.e a member of DMA handle structure).
phungductung 0:8ede47d38d10 50 [..]
phungductung 0:8ede47d38d10 51 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
phungductung 0:8ede47d38d10 52 detection.
phungductung 0:8ede47d38d10 53
phungductung 0:8ede47d38d10 54 (#) Use HAL_DMA_Abort() function to abort the current transfer
phungductung 0:8ede47d38d10 55
phungductung 0:8ede47d38d10 56 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
phungductung 0:8ede47d38d10 57
phungductung 0:8ede47d38d10 58 -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
phungductung 0:8ede47d38d10 59 possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
phungductung 0:8ede47d38d10 60 Half-Word data size for the peripheral to access its data register and set Word data size
phungductung 0:8ede47d38d10 61 for the Memory to gain in access time. Each two half words will be packed and written in
phungductung 0:8ede47d38d10 62 a single access to a Word in the Memory).
phungductung 0:8ede47d38d10 63
phungductung 0:8ede47d38d10 64 -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
phungductung 0:8ede47d38d10 65 and Destination. In this case the Peripheral Data Size will be applied to both Source
phungductung 0:8ede47d38d10 66 and Destination.
phungductung 0:8ede47d38d10 67
phungductung 0:8ede47d38d10 68 *** DMA HAL driver macros list ***
phungductung 0:8ede47d38d10 69 =============================================
phungductung 0:8ede47d38d10 70 [..]
phungductung 0:8ede47d38d10 71 Below the list of most used macros in DMA HAL driver.
phungductung 0:8ede47d38d10 72
phungductung 0:8ede47d38d10 73 (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
phungductung 0:8ede47d38d10 74 (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
phungductung 0:8ede47d38d10 75 (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level.
phungductung 0:8ede47d38d10 76 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts.
phungductung 0:8ede47d38d10 77 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts.
phungductung 0:8ede47d38d10 78 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
phungductung 0:8ede47d38d10 79
phungductung 0:8ede47d38d10 80 [..]
phungductung 0:8ede47d38d10 81 (@) You can refer to the DMA HAL driver header file for more useful macros
phungductung 0:8ede47d38d10 82
phungductung 0:8ede47d38d10 83 @endverbatim
phungductung 0:8ede47d38d10 84 ******************************************************************************
phungductung 0:8ede47d38d10 85 * @attention
phungductung 0:8ede47d38d10 86 *
phungductung 0:8ede47d38d10 87 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
phungductung 0:8ede47d38d10 88 *
phungductung 0:8ede47d38d10 89 * Redistribution and use in source and binary forms, with or without modification,
phungductung 0:8ede47d38d10 90 * are permitted provided that the following conditions are met:
phungductung 0:8ede47d38d10 91 * 1. Redistributions of source code must retain the above copyright notice,
phungductung 0:8ede47d38d10 92 * this list of conditions and the following disclaimer.
phungductung 0:8ede47d38d10 93 * 2. Redistributions in binary form must reproduce the above copyright notice,
phungductung 0:8ede47d38d10 94 * this list of conditions and the following disclaimer in the documentation
phungductung 0:8ede47d38d10 95 * and/or other materials provided with the distribution.
phungductung 0:8ede47d38d10 96 * 3. Neither the name of STMicroelectronics nor the names of its contributors
phungductung 0:8ede47d38d10 97 * may be used to endorse or promote products derived from this software
phungductung 0:8ede47d38d10 98 * without specific prior written permission.
phungductung 0:8ede47d38d10 99 *
phungductung 0:8ede47d38d10 100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
phungductung 0:8ede47d38d10 101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
phungductung 0:8ede47d38d10 102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
phungductung 0:8ede47d38d10 103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
phungductung 0:8ede47d38d10 104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
phungductung 0:8ede47d38d10 105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
phungductung 0:8ede47d38d10 106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
phungductung 0:8ede47d38d10 107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
phungductung 0:8ede47d38d10 108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
phungductung 0:8ede47d38d10 109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
phungductung 0:8ede47d38d10 110 *
phungductung 0:8ede47d38d10 111 ******************************************************************************
phungductung 0:8ede47d38d10 112 */
phungductung 0:8ede47d38d10 113
phungductung 0:8ede47d38d10 114 /* Includes ------------------------------------------------------------------*/
phungductung 0:8ede47d38d10 115 #include "stm32f7xx_hal.h"
phungductung 0:8ede47d38d10 116
phungductung 0:8ede47d38d10 117 /** @addtogroup STM32F7xx_HAL_Driver
phungductung 0:8ede47d38d10 118 * @{
phungductung 0:8ede47d38d10 119 */
phungductung 0:8ede47d38d10 120
phungductung 0:8ede47d38d10 121 /** @defgroup DMA DMA
phungductung 0:8ede47d38d10 122 * @brief DMA HAL module driver
phungductung 0:8ede47d38d10 123 * @{
phungductung 0:8ede47d38d10 124 */
phungductung 0:8ede47d38d10 125
phungductung 0:8ede47d38d10 126 #ifdef HAL_DMA_MODULE_ENABLED
phungductung 0:8ede47d38d10 127
phungductung 0:8ede47d38d10 128 /* Private types -------------------------------------------------------------*/
phungductung 0:8ede47d38d10 129 typedef struct
phungductung 0:8ede47d38d10 130 {
phungductung 0:8ede47d38d10 131 __IO uint32_t ISR; /*!< DMA interrupt status register */
phungductung 0:8ede47d38d10 132 __IO uint32_t Reserved0;
phungductung 0:8ede47d38d10 133 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
phungductung 0:8ede47d38d10 134 } DMA_Base_Registers;
phungductung 0:8ede47d38d10 135
phungductung 0:8ede47d38d10 136 /* Private variables ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 137 /* Private constants ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 138 /** @addtogroup DMA_Private_Constants
phungductung 0:8ede47d38d10 139 * @{
phungductung 0:8ede47d38d10 140 */
phungductung 0:8ede47d38d10 141 #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
phungductung 0:8ede47d38d10 142 /**
phungductung 0:8ede47d38d10 143 * @}
phungductung 0:8ede47d38d10 144 */
phungductung 0:8ede47d38d10 145 /* Private macros ------------------------------------------------------------*/
phungductung 0:8ede47d38d10 146 /* Private functions ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 147 /** @addtogroup DMA_Private_Functions
phungductung 0:8ede47d38d10 148 * @{
phungductung 0:8ede47d38d10 149 */
phungductung 0:8ede47d38d10 150 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
phungductung 0:8ede47d38d10 151 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
phungductung 0:8ede47d38d10 152
phungductung 0:8ede47d38d10 153 /**
phungductung 0:8ede47d38d10 154 * @brief Sets the DMA Transfer parameter.
phungductung 0:8ede47d38d10 155 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 156 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 157 * @param SrcAddress: The source memory Buffer address
phungductung 0:8ede47d38d10 158 * @param DstAddress: The destination memory Buffer address
phungductung 0:8ede47d38d10 159 * @param DataLength: The length of data to be transferred from source to destination
phungductung 0:8ede47d38d10 160 * @retval HAL status
phungductung 0:8ede47d38d10 161 */
phungductung 0:8ede47d38d10 162 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
phungductung 0:8ede47d38d10 163 {
phungductung 0:8ede47d38d10 164 /* Clear DBM bit */
phungductung 0:8ede47d38d10 165 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
phungductung 0:8ede47d38d10 166
phungductung 0:8ede47d38d10 167 /* Configure DMA Stream data length */
phungductung 0:8ede47d38d10 168 hdma->Instance->NDTR = DataLength;
phungductung 0:8ede47d38d10 169
phungductung 0:8ede47d38d10 170 /* Peripheral to Memory */
phungductung 0:8ede47d38d10 171 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
phungductung 0:8ede47d38d10 172 {
phungductung 0:8ede47d38d10 173 /* Configure DMA Stream destination address */
phungductung 0:8ede47d38d10 174 hdma->Instance->PAR = DstAddress;
phungductung 0:8ede47d38d10 175
phungductung 0:8ede47d38d10 176 /* Configure DMA Stream source address */
phungductung 0:8ede47d38d10 177 hdma->Instance->M0AR = SrcAddress;
phungductung 0:8ede47d38d10 178 }
phungductung 0:8ede47d38d10 179 /* Memory to Peripheral */
phungductung 0:8ede47d38d10 180 else
phungductung 0:8ede47d38d10 181 {
phungductung 0:8ede47d38d10 182 /* Configure DMA Stream source address */
phungductung 0:8ede47d38d10 183 hdma->Instance->PAR = SrcAddress;
phungductung 0:8ede47d38d10 184
phungductung 0:8ede47d38d10 185 /* Configure DMA Stream destination address */
phungductung 0:8ede47d38d10 186 hdma->Instance->M0AR = DstAddress;
phungductung 0:8ede47d38d10 187 }
phungductung 0:8ede47d38d10 188 }
phungductung 0:8ede47d38d10 189
phungductung 0:8ede47d38d10 190 /**
phungductung 0:8ede47d38d10 191 * @}
phungductung 0:8ede47d38d10 192 */
phungductung 0:8ede47d38d10 193
phungductung 0:8ede47d38d10 194 /* Exported functions ---------------------------------------------------------*/
phungductung 0:8ede47d38d10 195 /** @addtogroup DMA_Exported_Functions
phungductung 0:8ede47d38d10 196 * @{
phungductung 0:8ede47d38d10 197 */
phungductung 0:8ede47d38d10 198
phungductung 0:8ede47d38d10 199 /** @addtogroup DMA_Exported_Functions_Group1
phungductung 0:8ede47d38d10 200 *
phungductung 0:8ede47d38d10 201 @verbatim
phungductung 0:8ede47d38d10 202 ===============================================================================
phungductung 0:8ede47d38d10 203 ##### Initialization and de-initialization functions #####
phungductung 0:8ede47d38d10 204 ===============================================================================
phungductung 0:8ede47d38d10 205 [..]
phungductung 0:8ede47d38d10 206 This section provides functions allowing to initialize the DMA Stream source
phungductung 0:8ede47d38d10 207 and destination addresses, incrementation and data sizes, transfer direction,
phungductung 0:8ede47d38d10 208 circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
phungductung 0:8ede47d38d10 209 [..]
phungductung 0:8ede47d38d10 210 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
phungductung 0:8ede47d38d10 211 reference manual.
phungductung 0:8ede47d38d10 212
phungductung 0:8ede47d38d10 213 @endverbatim
phungductung 0:8ede47d38d10 214 * @{
phungductung 0:8ede47d38d10 215 */
phungductung 0:8ede47d38d10 216
phungductung 0:8ede47d38d10 217 /**
phungductung 0:8ede47d38d10 218 * @brief Initializes the DMA according to the specified
phungductung 0:8ede47d38d10 219 * parameters in the DMA_InitTypeDef and create the associated handle.
phungductung 0:8ede47d38d10 220 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 221 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 222 * @retval HAL status
phungductung 0:8ede47d38d10 223 */
phungductung 0:8ede47d38d10 224 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 225 {
phungductung 0:8ede47d38d10 226 uint32_t tmp = 0;
phungductung 0:8ede47d38d10 227
phungductung 0:8ede47d38d10 228 /* Check the DMA peripheral state */
phungductung 0:8ede47d38d10 229 if(hdma == NULL)
phungductung 0:8ede47d38d10 230 {
phungductung 0:8ede47d38d10 231 return HAL_ERROR;
phungductung 0:8ede47d38d10 232 }
phungductung 0:8ede47d38d10 233
phungductung 0:8ede47d38d10 234 /* Check the parameters */
phungductung 0:8ede47d38d10 235 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
phungductung 0:8ede47d38d10 236 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
phungductung 0:8ede47d38d10 237 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
phungductung 0:8ede47d38d10 238 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
phungductung 0:8ede47d38d10 239 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
phungductung 0:8ede47d38d10 240 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
phungductung 0:8ede47d38d10 241 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
phungductung 0:8ede47d38d10 242 assert_param(IS_DMA_MODE(hdma->Init.Mode));
phungductung 0:8ede47d38d10 243 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
phungductung 0:8ede47d38d10 244 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
phungductung 0:8ede47d38d10 245 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
phungductung 0:8ede47d38d10 246 when FIFO mode is enabled */
phungductung 0:8ede47d38d10 247 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
phungductung 0:8ede47d38d10 248 {
phungductung 0:8ede47d38d10 249 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
phungductung 0:8ede47d38d10 250 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
phungductung 0:8ede47d38d10 251 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
phungductung 0:8ede47d38d10 252 }
phungductung 0:8ede47d38d10 253
phungductung 0:8ede47d38d10 254 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 255 hdma->State = HAL_DMA_STATE_BUSY;
phungductung 0:8ede47d38d10 256
phungductung 0:8ede47d38d10 257 /* Get the CR register value */
phungductung 0:8ede47d38d10 258 tmp = hdma->Instance->CR;
phungductung 0:8ede47d38d10 259
phungductung 0:8ede47d38d10 260 /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
phungductung 0:8ede47d38d10 261 tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
phungductung 0:8ede47d38d10 262 DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
phungductung 0:8ede47d38d10 263 DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
phungductung 0:8ede47d38d10 264 DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
phungductung 0:8ede47d38d10 265
phungductung 0:8ede47d38d10 266 /* Prepare the DMA Stream configuration */
phungductung 0:8ede47d38d10 267 tmp |= hdma->Init.Channel | hdma->Init.Direction |
phungductung 0:8ede47d38d10 268 hdma->Init.PeriphInc | hdma->Init.MemInc |
phungductung 0:8ede47d38d10 269 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
phungductung 0:8ede47d38d10 270 hdma->Init.Mode | hdma->Init.Priority;
phungductung 0:8ede47d38d10 271
phungductung 0:8ede47d38d10 272 /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
phungductung 0:8ede47d38d10 273 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
phungductung 0:8ede47d38d10 274 {
phungductung 0:8ede47d38d10 275 /* Get memory burst and peripheral burst */
phungductung 0:8ede47d38d10 276 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
phungductung 0:8ede47d38d10 277 }
phungductung 0:8ede47d38d10 278
phungductung 0:8ede47d38d10 279 /* Write to DMA Stream CR register */
phungductung 0:8ede47d38d10 280 hdma->Instance->CR = tmp;
phungductung 0:8ede47d38d10 281
phungductung 0:8ede47d38d10 282 /* Get the FCR register value */
phungductung 0:8ede47d38d10 283 tmp = hdma->Instance->FCR;
phungductung 0:8ede47d38d10 284
phungductung 0:8ede47d38d10 285 /* Clear Direct mode and FIFO threshold bits */
phungductung 0:8ede47d38d10 286 tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
phungductung 0:8ede47d38d10 287
phungductung 0:8ede47d38d10 288 /* Prepare the DMA Stream FIFO configuration */
phungductung 0:8ede47d38d10 289 tmp |= hdma->Init.FIFOMode;
phungductung 0:8ede47d38d10 290
phungductung 0:8ede47d38d10 291 /* the FIFO threshold is not used when the FIFO mode is disabled */
phungductung 0:8ede47d38d10 292 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
phungductung 0:8ede47d38d10 293 {
phungductung 0:8ede47d38d10 294 /* Get the FIFO threshold */
phungductung 0:8ede47d38d10 295 tmp |= hdma->Init.FIFOThreshold;
phungductung 0:8ede47d38d10 296 }
phungductung 0:8ede47d38d10 297
phungductung 0:8ede47d38d10 298 /* Write to DMA Stream FCR */
phungductung 0:8ede47d38d10 299 hdma->Instance->FCR = tmp;
phungductung 0:8ede47d38d10 300
phungductung 0:8ede47d38d10 301 /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
phungductung 0:8ede47d38d10 302 DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
phungductung 0:8ede47d38d10 303 DMA_CalcBaseAndBitshift(hdma);
phungductung 0:8ede47d38d10 304
phungductung 0:8ede47d38d10 305 /* Initialize the error code */
phungductung 0:8ede47d38d10 306 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
phungductung 0:8ede47d38d10 307
phungductung 0:8ede47d38d10 308 /* Initialize the DMA state */
phungductung 0:8ede47d38d10 309 hdma->State = HAL_DMA_STATE_READY;
phungductung 0:8ede47d38d10 310
phungductung 0:8ede47d38d10 311 return HAL_OK;
phungductung 0:8ede47d38d10 312 }
phungductung 0:8ede47d38d10 313
phungductung 0:8ede47d38d10 314 /**
phungductung 0:8ede47d38d10 315 * @brief DeInitializes the DMA peripheral
phungductung 0:8ede47d38d10 316 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 317 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 318 * @retval HAL status
phungductung 0:8ede47d38d10 319 */
phungductung 0:8ede47d38d10 320 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 321 {
phungductung 0:8ede47d38d10 322 DMA_Base_Registers *regs;
phungductung 0:8ede47d38d10 323
phungductung 0:8ede47d38d10 324 /* Check the DMA peripheral state */
phungductung 0:8ede47d38d10 325 if(hdma == NULL)
phungductung 0:8ede47d38d10 326 {
phungductung 0:8ede47d38d10 327 return HAL_ERROR;
phungductung 0:8ede47d38d10 328 }
phungductung 0:8ede47d38d10 329
phungductung 0:8ede47d38d10 330 /* Check the DMA peripheral state */
phungductung 0:8ede47d38d10 331 if(hdma->State == HAL_DMA_STATE_BUSY)
phungductung 0:8ede47d38d10 332 {
phungductung 0:8ede47d38d10 333 return HAL_ERROR;
phungductung 0:8ede47d38d10 334 }
phungductung 0:8ede47d38d10 335
phungductung 0:8ede47d38d10 336 /* Disable the selected DMA Streamx */
phungductung 0:8ede47d38d10 337 __HAL_DMA_DISABLE(hdma);
phungductung 0:8ede47d38d10 338
phungductung 0:8ede47d38d10 339 /* Reset DMA Streamx control register */
phungductung 0:8ede47d38d10 340 hdma->Instance->CR = 0;
phungductung 0:8ede47d38d10 341
phungductung 0:8ede47d38d10 342 /* Reset DMA Streamx number of data to transfer register */
phungductung 0:8ede47d38d10 343 hdma->Instance->NDTR = 0;
phungductung 0:8ede47d38d10 344
phungductung 0:8ede47d38d10 345 /* Reset DMA Streamx peripheral address register */
phungductung 0:8ede47d38d10 346 hdma->Instance->PAR = 0;
phungductung 0:8ede47d38d10 347
phungductung 0:8ede47d38d10 348 /* Reset DMA Streamx memory 0 address register */
phungductung 0:8ede47d38d10 349 hdma->Instance->M0AR = 0;
phungductung 0:8ede47d38d10 350
phungductung 0:8ede47d38d10 351 /* Reset DMA Streamx memory 1 address register */
phungductung 0:8ede47d38d10 352 hdma->Instance->M1AR = 0;
phungductung 0:8ede47d38d10 353
phungductung 0:8ede47d38d10 354 /* Reset DMA Streamx FIFO control register */
phungductung 0:8ede47d38d10 355 hdma->Instance->FCR = (uint32_t)0x00000021;
phungductung 0:8ede47d38d10 356
phungductung 0:8ede47d38d10 357 /* Get DMA steam Base Address */
phungductung 0:8ede47d38d10 358 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
phungductung 0:8ede47d38d10 359
phungductung 0:8ede47d38d10 360 /* Clear all interrupt flags at correct offset within the register */
phungductung 0:8ede47d38d10 361 regs->IFCR = 0x3F << hdma->StreamIndex;
phungductung 0:8ede47d38d10 362
phungductung 0:8ede47d38d10 363 /* Initialize the error code */
phungductung 0:8ede47d38d10 364 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
phungductung 0:8ede47d38d10 365
phungductung 0:8ede47d38d10 366 /* Initialize the DMA state */
phungductung 0:8ede47d38d10 367 hdma->State = HAL_DMA_STATE_RESET;
phungductung 0:8ede47d38d10 368
phungductung 0:8ede47d38d10 369 /* Release Lock */
phungductung 0:8ede47d38d10 370 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 371
phungductung 0:8ede47d38d10 372 return HAL_OK;
phungductung 0:8ede47d38d10 373 }
phungductung 0:8ede47d38d10 374
phungductung 0:8ede47d38d10 375 /**
phungductung 0:8ede47d38d10 376 * @}
phungductung 0:8ede47d38d10 377 */
phungductung 0:8ede47d38d10 378
phungductung 0:8ede47d38d10 379 /** @addtogroup DMA_Exported_Functions_Group2
phungductung 0:8ede47d38d10 380 *
phungductung 0:8ede47d38d10 381 @verbatim
phungductung 0:8ede47d38d10 382 ===============================================================================
phungductung 0:8ede47d38d10 383 ##### IO operation functions #####
phungductung 0:8ede47d38d10 384 ===============================================================================
phungductung 0:8ede47d38d10 385 [..] This section provides functions allowing to:
phungductung 0:8ede47d38d10 386 (+) Configure the source, destination address and data length and Start DMA transfer
phungductung 0:8ede47d38d10 387 (+) Configure the source, destination address and data length and
phungductung 0:8ede47d38d10 388 Start DMA transfer with interrupt
phungductung 0:8ede47d38d10 389 (+) Abort DMA transfer
phungductung 0:8ede47d38d10 390 (+) Poll for transfer complete
phungductung 0:8ede47d38d10 391 (+) Handle DMA interrupt request
phungductung 0:8ede47d38d10 392
phungductung 0:8ede47d38d10 393 @endverbatim
phungductung 0:8ede47d38d10 394 * @{
phungductung 0:8ede47d38d10 395 */
phungductung 0:8ede47d38d10 396
phungductung 0:8ede47d38d10 397 /**
phungductung 0:8ede47d38d10 398 * @brief Starts the DMA Transfer.
phungductung 0:8ede47d38d10 399 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 400 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 401 * @param SrcAddress: The source memory Buffer address
phungductung 0:8ede47d38d10 402 * @param DstAddress: The destination memory Buffer address
phungductung 0:8ede47d38d10 403 * @param DataLength: The length of data to be transferred from source to destination
phungductung 0:8ede47d38d10 404 * @retval HAL status
phungductung 0:8ede47d38d10 405 */
phungductung 0:8ede47d38d10 406 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
phungductung 0:8ede47d38d10 407 {
phungductung 0:8ede47d38d10 408 /* Process locked */
phungductung 0:8ede47d38d10 409 __HAL_LOCK(hdma);
phungductung 0:8ede47d38d10 410
phungductung 0:8ede47d38d10 411 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 412 hdma->State = HAL_DMA_STATE_BUSY;
phungductung 0:8ede47d38d10 413
phungductung 0:8ede47d38d10 414 /* Check the parameters */
phungductung 0:8ede47d38d10 415 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
phungductung 0:8ede47d38d10 416
phungductung 0:8ede47d38d10 417 /* Disable the peripheral */
phungductung 0:8ede47d38d10 418 __HAL_DMA_DISABLE(hdma);
phungductung 0:8ede47d38d10 419
phungductung 0:8ede47d38d10 420 /* Configure the source, destination address and the data length */
phungductung 0:8ede47d38d10 421 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
phungductung 0:8ede47d38d10 422
phungductung 0:8ede47d38d10 423 /* Enable the Peripheral */
phungductung 0:8ede47d38d10 424 __HAL_DMA_ENABLE(hdma);
phungductung 0:8ede47d38d10 425
phungductung 0:8ede47d38d10 426 return HAL_OK;
phungductung 0:8ede47d38d10 427 }
phungductung 0:8ede47d38d10 428
phungductung 0:8ede47d38d10 429 /**
phungductung 0:8ede47d38d10 430 * @brief Start the DMA Transfer with interrupt enabled.
phungductung 0:8ede47d38d10 431 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 432 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 433 * @param SrcAddress: The source memory Buffer address
phungductung 0:8ede47d38d10 434 * @param DstAddress: The destination memory Buffer address
phungductung 0:8ede47d38d10 435 * @param DataLength: The length of data to be transferred from source to destination
phungductung 0:8ede47d38d10 436 * @retval HAL status
phungductung 0:8ede47d38d10 437 */
phungductung 0:8ede47d38d10 438 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
phungductung 0:8ede47d38d10 439 {
phungductung 0:8ede47d38d10 440 /* Process locked */
phungductung 0:8ede47d38d10 441 __HAL_LOCK(hdma);
phungductung 0:8ede47d38d10 442
phungductung 0:8ede47d38d10 443 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 444 hdma->State = HAL_DMA_STATE_BUSY;
phungductung 0:8ede47d38d10 445
phungductung 0:8ede47d38d10 446 /* Check the parameters */
phungductung 0:8ede47d38d10 447 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
phungductung 0:8ede47d38d10 448
phungductung 0:8ede47d38d10 449 /* Disable the peripheral */
phungductung 0:8ede47d38d10 450 __HAL_DMA_DISABLE(hdma);
phungductung 0:8ede47d38d10 451
phungductung 0:8ede47d38d10 452 /* Configure the source, destination address and the data length */
phungductung 0:8ede47d38d10 453 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
phungductung 0:8ede47d38d10 454
phungductung 0:8ede47d38d10 455 /* Enable all interrupts */
phungductung 0:8ede47d38d10 456 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_HT | DMA_IT_TE | DMA_IT_DME;
phungductung 0:8ede47d38d10 457 hdma->Instance->FCR |= DMA_IT_FE;
phungductung 0:8ede47d38d10 458
phungductung 0:8ede47d38d10 459 /* Enable the Peripheral */
phungductung 0:8ede47d38d10 460 __HAL_DMA_ENABLE(hdma);
phungductung 0:8ede47d38d10 461
phungductung 0:8ede47d38d10 462 return HAL_OK;
phungductung 0:8ede47d38d10 463 }
phungductung 0:8ede47d38d10 464
phungductung 0:8ede47d38d10 465 /**
phungductung 0:8ede47d38d10 466 * @brief Aborts the DMA Transfer.
phungductung 0:8ede47d38d10 467 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 468 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 469 *
phungductung 0:8ede47d38d10 470 * @note After disabling a DMA Stream, a check for wait until the DMA Stream is
phungductung 0:8ede47d38d10 471 * effectively disabled is added. If a Stream is disabled
phungductung 0:8ede47d38d10 472 * while a data transfer is ongoing, the current data will be transferred
phungductung 0:8ede47d38d10 473 * and the Stream will be effectively disabled only after the transfer of
phungductung 0:8ede47d38d10 474 * this single data is finished.
phungductung 0:8ede47d38d10 475 * @retval HAL status
phungductung 0:8ede47d38d10 476 */
phungductung 0:8ede47d38d10 477 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 478 {
phungductung 0:8ede47d38d10 479 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 480
phungductung 0:8ede47d38d10 481 /* Disable the stream */
phungductung 0:8ede47d38d10 482 __HAL_DMA_DISABLE(hdma);
phungductung 0:8ede47d38d10 483
phungductung 0:8ede47d38d10 484 /* Get tick */
phungductung 0:8ede47d38d10 485 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 486
phungductung 0:8ede47d38d10 487 /* Check if the DMA Stream is effectively disabled */
phungductung 0:8ede47d38d10 488 while((hdma->Instance->CR & DMA_SxCR_EN) != 0)
phungductung 0:8ede47d38d10 489 {
phungductung 0:8ede47d38d10 490 /* Check for the Timeout */
phungductung 0:8ede47d38d10 491 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
phungductung 0:8ede47d38d10 492 {
phungductung 0:8ede47d38d10 493 /* Update error code */
phungductung 0:8ede47d38d10 494 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
phungductung 0:8ede47d38d10 495
phungductung 0:8ede47d38d10 496 /* Process Unlocked */
phungductung 0:8ede47d38d10 497 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 498
phungductung 0:8ede47d38d10 499 /* Change the DMA state */
phungductung 0:8ede47d38d10 500 hdma->State = HAL_DMA_STATE_TIMEOUT;
phungductung 0:8ede47d38d10 501
phungductung 0:8ede47d38d10 502 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 503 }
phungductung 0:8ede47d38d10 504 }
phungductung 0:8ede47d38d10 505 /* Process Unlocked */
phungductung 0:8ede47d38d10 506 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 507
phungductung 0:8ede47d38d10 508 /* Change the DMA state*/
phungductung 0:8ede47d38d10 509 hdma->State = HAL_DMA_STATE_READY;
phungductung 0:8ede47d38d10 510
phungductung 0:8ede47d38d10 511 return HAL_OK;
phungductung 0:8ede47d38d10 512 }
phungductung 0:8ede47d38d10 513
phungductung 0:8ede47d38d10 514 /**
phungductung 0:8ede47d38d10 515 * @brief Polling for transfer complete.
phungductung 0:8ede47d38d10 516 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 517 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 518 * @param CompleteLevel: Specifies the DMA level complete.
phungductung 0:8ede47d38d10 519 * @param Timeout: Timeout duration.
phungductung 0:8ede47d38d10 520 * @retval HAL status
phungductung 0:8ede47d38d10 521 */
phungductung 0:8ede47d38d10 522 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
phungductung 0:8ede47d38d10 523 {
phungductung 0:8ede47d38d10 524 uint32_t temp, tmp, tmp1, tmp2;
phungductung 0:8ede47d38d10 525 uint32_t tickstart = 0;
phungductung 0:8ede47d38d10 526
phungductung 0:8ede47d38d10 527 /* calculate DMA base and stream number */
phungductung 0:8ede47d38d10 528 DMA_Base_Registers *regs;
phungductung 0:8ede47d38d10 529
phungductung 0:8ede47d38d10 530 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
phungductung 0:8ede47d38d10 531
phungductung 0:8ede47d38d10 532 /* Get the level transfer complete flag */
phungductung 0:8ede47d38d10 533 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
phungductung 0:8ede47d38d10 534 {
phungductung 0:8ede47d38d10 535 /* Transfer Complete flag */
phungductung 0:8ede47d38d10 536 temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 537 }
phungductung 0:8ede47d38d10 538 else
phungductung 0:8ede47d38d10 539 {
phungductung 0:8ede47d38d10 540 /* Half Transfer Complete flag */
phungductung 0:8ede47d38d10 541 temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 542 }
phungductung 0:8ede47d38d10 543
phungductung 0:8ede47d38d10 544 /* Get tick */
phungductung 0:8ede47d38d10 545 tickstart = HAL_GetTick();
phungductung 0:8ede47d38d10 546
phungductung 0:8ede47d38d10 547 while((regs->ISR & temp) == RESET)
phungductung 0:8ede47d38d10 548 {
phungductung 0:8ede47d38d10 549 tmp = regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex);
phungductung 0:8ede47d38d10 550 tmp1 = regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex);
phungductung 0:8ede47d38d10 551 tmp2 = regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex);
phungductung 0:8ede47d38d10 552 if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET))
phungductung 0:8ede47d38d10 553 {
phungductung 0:8ede47d38d10 554 if(tmp != RESET)
phungductung 0:8ede47d38d10 555 {
phungductung 0:8ede47d38d10 556 /* Update error code */
phungductung 0:8ede47d38d10 557 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
phungductung 0:8ede47d38d10 558
phungductung 0:8ede47d38d10 559 /* Clear the transfer error flag */
phungductung 0:8ede47d38d10 560 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 561 }
phungductung 0:8ede47d38d10 562 if(tmp1 != RESET)
phungductung 0:8ede47d38d10 563 {
phungductung 0:8ede47d38d10 564 /* Update error code */
phungductung 0:8ede47d38d10 565 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
phungductung 0:8ede47d38d10 566
phungductung 0:8ede47d38d10 567 /* Clear the FIFO error flag */
phungductung 0:8ede47d38d10 568 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 569 }
phungductung 0:8ede47d38d10 570 if(tmp2 != RESET)
phungductung 0:8ede47d38d10 571 {
phungductung 0:8ede47d38d10 572 /* Update error code */
phungductung 0:8ede47d38d10 573 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
phungductung 0:8ede47d38d10 574
phungductung 0:8ede47d38d10 575 /* Clear the Direct Mode error flag */
phungductung 0:8ede47d38d10 576 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 577 }
phungductung 0:8ede47d38d10 578 /* Change the DMA state */
phungductung 0:8ede47d38d10 579 hdma->State= HAL_DMA_STATE_ERROR;
phungductung 0:8ede47d38d10 580
phungductung 0:8ede47d38d10 581 /* Process Unlocked */
phungductung 0:8ede47d38d10 582 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 583
phungductung 0:8ede47d38d10 584 return HAL_ERROR;
phungductung 0:8ede47d38d10 585 }
phungductung 0:8ede47d38d10 586 /* Check for the Timeout */
phungductung 0:8ede47d38d10 587 if(Timeout != HAL_MAX_DELAY)
phungductung 0:8ede47d38d10 588 {
phungductung 0:8ede47d38d10 589 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
phungductung 0:8ede47d38d10 590 {
phungductung 0:8ede47d38d10 591 /* Update error code */
phungductung 0:8ede47d38d10 592 hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
phungductung 0:8ede47d38d10 593
phungductung 0:8ede47d38d10 594 /* Change the DMA state */
phungductung 0:8ede47d38d10 595 hdma->State = HAL_DMA_STATE_TIMEOUT;
phungductung 0:8ede47d38d10 596
phungductung 0:8ede47d38d10 597 /* Process Unlocked */
phungductung 0:8ede47d38d10 598 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 599
phungductung 0:8ede47d38d10 600 return HAL_TIMEOUT;
phungductung 0:8ede47d38d10 601 }
phungductung 0:8ede47d38d10 602 }
phungductung 0:8ede47d38d10 603 }
phungductung 0:8ede47d38d10 604
phungductung 0:8ede47d38d10 605 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
phungductung 0:8ede47d38d10 606 {
phungductung 0:8ede47d38d10 607 /* Clear the half transfer and transfer complete flags */
phungductung 0:8ede47d38d10 608 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
phungductung 0:8ede47d38d10 609
phungductung 0:8ede47d38d10 610 /* Multi_Buffering mode enabled */
phungductung 0:8ede47d38d10 611 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:8ede47d38d10 612 {
phungductung 0:8ede47d38d10 613 /* Current memory buffer used is Memory 0 */
phungductung 0:8ede47d38d10 614 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:8ede47d38d10 615 {
phungductung 0:8ede47d38d10 616 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 617 hdma->State = HAL_DMA_STATE_READY_MEM0;
phungductung 0:8ede47d38d10 618 }
phungductung 0:8ede47d38d10 619 /* Current memory buffer used is Memory 1 */
phungductung 0:8ede47d38d10 620 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:8ede47d38d10 621 {
phungductung 0:8ede47d38d10 622 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 623 hdma->State = HAL_DMA_STATE_READY_MEM1;
phungductung 0:8ede47d38d10 624 }
phungductung 0:8ede47d38d10 625 }
phungductung 0:8ede47d38d10 626 else
phungductung 0:8ede47d38d10 627 {
phungductung 0:8ede47d38d10 628 /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers
phungductung 0:8ede47d38d10 629 are complete) */
phungductung 0:8ede47d38d10 630 hdma->State = HAL_DMA_STATE_READY_MEM0;
phungductung 0:8ede47d38d10 631 }
phungductung 0:8ede47d38d10 632 /* Process Unlocked */
phungductung 0:8ede47d38d10 633 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 634 }
phungductung 0:8ede47d38d10 635 else
phungductung 0:8ede47d38d10 636 {
phungductung 0:8ede47d38d10 637 /* Clear the half transfer complete flag */
phungductung 0:8ede47d38d10 638 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 639
phungductung 0:8ede47d38d10 640 /* Multi_Buffering mode enabled */
phungductung 0:8ede47d38d10 641 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:8ede47d38d10 642 {
phungductung 0:8ede47d38d10 643 /* Current memory buffer used is Memory 0 */
phungductung 0:8ede47d38d10 644 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:8ede47d38d10 645 {
phungductung 0:8ede47d38d10 646 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 647 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:8ede47d38d10 648 }
phungductung 0:8ede47d38d10 649 /* Current memory buffer used is Memory 1 */
phungductung 0:8ede47d38d10 650 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:8ede47d38d10 651 {
phungductung 0:8ede47d38d10 652 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 653 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
phungductung 0:8ede47d38d10 654 }
phungductung 0:8ede47d38d10 655 }
phungductung 0:8ede47d38d10 656 else
phungductung 0:8ede47d38d10 657 {
phungductung 0:8ede47d38d10 658 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 659 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:8ede47d38d10 660 }
phungductung 0:8ede47d38d10 661 }
phungductung 0:8ede47d38d10 662 return HAL_OK;
phungductung 0:8ede47d38d10 663 }
phungductung 0:8ede47d38d10 664
phungductung 0:8ede47d38d10 665 /**
phungductung 0:8ede47d38d10 666 * @brief Handles DMA interrupt request.
phungductung 0:8ede47d38d10 667 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 668 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 669 * @retval None
phungductung 0:8ede47d38d10 670 */
phungductung 0:8ede47d38d10 671 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 672 {
phungductung 0:8ede47d38d10 673 /* calculate DMA base and stream number */
phungductung 0:8ede47d38d10 674 DMA_Base_Registers *regs;
phungductung 0:8ede47d38d10 675
phungductung 0:8ede47d38d10 676 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
phungductung 0:8ede47d38d10 677
phungductung 0:8ede47d38d10 678 /* Transfer Error Interrupt management ***************************************/
phungductung 0:8ede47d38d10 679 if ((regs->ISR & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:8ede47d38d10 680 {
phungductung 0:8ede47d38d10 681 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
phungductung 0:8ede47d38d10 682 {
phungductung 0:8ede47d38d10 683 /* Disable the transfer error interrupt */
phungductung 0:8ede47d38d10 684 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
phungductung 0:8ede47d38d10 685
phungductung 0:8ede47d38d10 686 /* Clear the transfer error flag */
phungductung 0:8ede47d38d10 687 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 688
phungductung 0:8ede47d38d10 689 /* Update error code */
phungductung 0:8ede47d38d10 690 hdma->ErrorCode |= HAL_DMA_ERROR_TE;
phungductung 0:8ede47d38d10 691
phungductung 0:8ede47d38d10 692 /* Change the DMA state */
phungductung 0:8ede47d38d10 693 hdma->State = HAL_DMA_STATE_ERROR;
phungductung 0:8ede47d38d10 694
phungductung 0:8ede47d38d10 695 /* Process Unlocked */
phungductung 0:8ede47d38d10 696 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 697
phungductung 0:8ede47d38d10 698 if(hdma->XferErrorCallback != NULL)
phungductung 0:8ede47d38d10 699 {
phungductung 0:8ede47d38d10 700 /* Transfer error callback */
phungductung 0:8ede47d38d10 701 hdma->XferErrorCallback(hdma);
phungductung 0:8ede47d38d10 702 }
phungductung 0:8ede47d38d10 703 }
phungductung 0:8ede47d38d10 704 }
phungductung 0:8ede47d38d10 705 /* FIFO Error Interrupt management ******************************************/
phungductung 0:8ede47d38d10 706 if ((regs->ISR & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:8ede47d38d10 707 {
phungductung 0:8ede47d38d10 708 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
phungductung 0:8ede47d38d10 709 {
phungductung 0:8ede47d38d10 710 /* Disable the FIFO Error interrupt */
phungductung 0:8ede47d38d10 711 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_FE);
phungductung 0:8ede47d38d10 712
phungductung 0:8ede47d38d10 713 /* Clear the FIFO error flag */
phungductung 0:8ede47d38d10 714 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 715
phungductung 0:8ede47d38d10 716 /* Update error code */
phungductung 0:8ede47d38d10 717 hdma->ErrorCode |= HAL_DMA_ERROR_FE;
phungductung 0:8ede47d38d10 718
phungductung 0:8ede47d38d10 719 /* Change the DMA state */
phungductung 0:8ede47d38d10 720 hdma->State = HAL_DMA_STATE_ERROR;
phungductung 0:8ede47d38d10 721
phungductung 0:8ede47d38d10 722 /* Process Unlocked */
phungductung 0:8ede47d38d10 723 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 724
phungductung 0:8ede47d38d10 725 if(hdma->XferErrorCallback != NULL)
phungductung 0:8ede47d38d10 726 {
phungductung 0:8ede47d38d10 727 /* Transfer error callback */
phungductung 0:8ede47d38d10 728 hdma->XferErrorCallback(hdma);
phungductung 0:8ede47d38d10 729 }
phungductung 0:8ede47d38d10 730 }
phungductung 0:8ede47d38d10 731 }
phungductung 0:8ede47d38d10 732 /* Direct Mode Error Interrupt management ***********************************/
phungductung 0:8ede47d38d10 733 if ((regs->ISR & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:8ede47d38d10 734 {
phungductung 0:8ede47d38d10 735 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
phungductung 0:8ede47d38d10 736 {
phungductung 0:8ede47d38d10 737 /* Disable the direct mode Error interrupt */
phungductung 0:8ede47d38d10 738 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_DME);
phungductung 0:8ede47d38d10 739
phungductung 0:8ede47d38d10 740 /* Clear the direct mode error flag */
phungductung 0:8ede47d38d10 741 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 742
phungductung 0:8ede47d38d10 743 /* Update error code */
phungductung 0:8ede47d38d10 744 hdma->ErrorCode |= HAL_DMA_ERROR_DME;
phungductung 0:8ede47d38d10 745
phungductung 0:8ede47d38d10 746 /* Change the DMA state */
phungductung 0:8ede47d38d10 747 hdma->State = HAL_DMA_STATE_ERROR;
phungductung 0:8ede47d38d10 748
phungductung 0:8ede47d38d10 749 /* Process Unlocked */
phungductung 0:8ede47d38d10 750 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 751
phungductung 0:8ede47d38d10 752 if(hdma->XferErrorCallback != NULL)
phungductung 0:8ede47d38d10 753 {
phungductung 0:8ede47d38d10 754 /* Transfer error callback */
phungductung 0:8ede47d38d10 755 hdma->XferErrorCallback(hdma);
phungductung 0:8ede47d38d10 756 }
phungductung 0:8ede47d38d10 757 }
phungductung 0:8ede47d38d10 758 }
phungductung 0:8ede47d38d10 759 /* Half Transfer Complete Interrupt management ******************************/
phungductung 0:8ede47d38d10 760 if ((regs->ISR & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:8ede47d38d10 761 {
phungductung 0:8ede47d38d10 762 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
phungductung 0:8ede47d38d10 763 {
phungductung 0:8ede47d38d10 764 /* Multi_Buffering mode enabled */
phungductung 0:8ede47d38d10 765 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:8ede47d38d10 766 {
phungductung 0:8ede47d38d10 767 /* Clear the half transfer complete flag */
phungductung 0:8ede47d38d10 768 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 769
phungductung 0:8ede47d38d10 770 /* Current memory buffer used is Memory 0 */
phungductung 0:8ede47d38d10 771 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:8ede47d38d10 772 {
phungductung 0:8ede47d38d10 773 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 774 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:8ede47d38d10 775 }
phungductung 0:8ede47d38d10 776 /* Current memory buffer used is Memory 1 */
phungductung 0:8ede47d38d10 777 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:8ede47d38d10 778 {
phungductung 0:8ede47d38d10 779 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 780 hdma->State = HAL_DMA_STATE_READY_HALF_MEM1;
phungductung 0:8ede47d38d10 781 }
phungductung 0:8ede47d38d10 782 }
phungductung 0:8ede47d38d10 783 else
phungductung 0:8ede47d38d10 784 {
phungductung 0:8ede47d38d10 785 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
phungductung 0:8ede47d38d10 786 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung 0:8ede47d38d10 787 {
phungductung 0:8ede47d38d10 788 /* Disable the half transfer interrupt */
phungductung 0:8ede47d38d10 789 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
phungductung 0:8ede47d38d10 790 }
phungductung 0:8ede47d38d10 791 /* Clear the half transfer complete flag */
phungductung 0:8ede47d38d10 792 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 793
phungductung 0:8ede47d38d10 794 /* Change DMA peripheral state */
phungductung 0:8ede47d38d10 795 hdma->State = HAL_DMA_STATE_READY_HALF_MEM0;
phungductung 0:8ede47d38d10 796 }
phungductung 0:8ede47d38d10 797
phungductung 0:8ede47d38d10 798 if(hdma->XferHalfCpltCallback != NULL)
phungductung 0:8ede47d38d10 799 {
phungductung 0:8ede47d38d10 800 /* Half transfer callback */
phungductung 0:8ede47d38d10 801 hdma->XferHalfCpltCallback(hdma);
phungductung 0:8ede47d38d10 802 }
phungductung 0:8ede47d38d10 803 }
phungductung 0:8ede47d38d10 804 }
phungductung 0:8ede47d38d10 805 /* Transfer Complete Interrupt management ***********************************/
phungductung 0:8ede47d38d10 806 if ((regs->ISR & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
phungductung 0:8ede47d38d10 807 {
phungductung 0:8ede47d38d10 808 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
phungductung 0:8ede47d38d10 809 {
phungductung 0:8ede47d38d10 810 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0)
phungductung 0:8ede47d38d10 811 {
phungductung 0:8ede47d38d10 812 /* Clear the transfer complete flag */
phungductung 0:8ede47d38d10 813 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 814
phungductung 0:8ede47d38d10 815 /* Current memory buffer used is Memory 1 */
phungductung 0:8ede47d38d10 816 if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
phungductung 0:8ede47d38d10 817 {
phungductung 0:8ede47d38d10 818 if(hdma->XferM1CpltCallback != NULL)
phungductung 0:8ede47d38d10 819 {
phungductung 0:8ede47d38d10 820 /* Transfer complete Callback for memory1 */
phungductung 0:8ede47d38d10 821 hdma->XferM1CpltCallback(hdma);
phungductung 0:8ede47d38d10 822 }
phungductung 0:8ede47d38d10 823 }
phungductung 0:8ede47d38d10 824 /* Current memory buffer used is Memory 0 */
phungductung 0:8ede47d38d10 825 else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
phungductung 0:8ede47d38d10 826 {
phungductung 0:8ede47d38d10 827 if(hdma->XferCpltCallback != NULL)
phungductung 0:8ede47d38d10 828 {
phungductung 0:8ede47d38d10 829 /* Transfer complete Callback for memory0 */
phungductung 0:8ede47d38d10 830 hdma->XferCpltCallback(hdma);
phungductung 0:8ede47d38d10 831 }
phungductung 0:8ede47d38d10 832 }
phungductung 0:8ede47d38d10 833 }
phungductung 0:8ede47d38d10 834 /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
phungductung 0:8ede47d38d10 835 else
phungductung 0:8ede47d38d10 836 {
phungductung 0:8ede47d38d10 837 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
phungductung 0:8ede47d38d10 838 {
phungductung 0:8ede47d38d10 839 /* Disable the transfer complete interrupt */
phungductung 0:8ede47d38d10 840 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
phungductung 0:8ede47d38d10 841 }
phungductung 0:8ede47d38d10 842 /* Clear the transfer complete flag */
phungductung 0:8ede47d38d10 843 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
phungductung 0:8ede47d38d10 844
phungductung 0:8ede47d38d10 845 /* Update error code */
phungductung 0:8ede47d38d10 846 hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
phungductung 0:8ede47d38d10 847
phungductung 0:8ede47d38d10 848 /* Change the DMA state */
phungductung 0:8ede47d38d10 849 hdma->State = HAL_DMA_STATE_READY_MEM0;
phungductung 0:8ede47d38d10 850
phungductung 0:8ede47d38d10 851 /* Process Unlocked */
phungductung 0:8ede47d38d10 852 __HAL_UNLOCK(hdma);
phungductung 0:8ede47d38d10 853
phungductung 0:8ede47d38d10 854 if(hdma->XferCpltCallback != NULL)
phungductung 0:8ede47d38d10 855 {
phungductung 0:8ede47d38d10 856 /* Transfer complete callback */
phungductung 0:8ede47d38d10 857 hdma->XferCpltCallback(hdma);
phungductung 0:8ede47d38d10 858 }
phungductung 0:8ede47d38d10 859 }
phungductung 0:8ede47d38d10 860 }
phungductung 0:8ede47d38d10 861 }
phungductung 0:8ede47d38d10 862 }
phungductung 0:8ede47d38d10 863
phungductung 0:8ede47d38d10 864
phungductung 0:8ede47d38d10 865 /**
phungductung 0:8ede47d38d10 866 * @}
phungductung 0:8ede47d38d10 867 */
phungductung 0:8ede47d38d10 868
phungductung 0:8ede47d38d10 869 /** @addtogroup DMA_Exported_Functions_Group3
phungductung 0:8ede47d38d10 870 *
phungductung 0:8ede47d38d10 871 @verbatim
phungductung 0:8ede47d38d10 872 ===============================================================================
phungductung 0:8ede47d38d10 873 ##### State and Errors functions #####
phungductung 0:8ede47d38d10 874 ===============================================================================
phungductung 0:8ede47d38d10 875 [..]
phungductung 0:8ede47d38d10 876 This subsection provides functions allowing to
phungductung 0:8ede47d38d10 877 (+) Check the DMA state
phungductung 0:8ede47d38d10 878 (+) Get error code
phungductung 0:8ede47d38d10 879
phungductung 0:8ede47d38d10 880 @endverbatim
phungductung 0:8ede47d38d10 881 * @{
phungductung 0:8ede47d38d10 882 */
phungductung 0:8ede47d38d10 883
phungductung 0:8ede47d38d10 884 /**
phungductung 0:8ede47d38d10 885 * @brief Returns the DMA state.
phungductung 0:8ede47d38d10 886 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 887 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 888 * @retval HAL state
phungductung 0:8ede47d38d10 889 */
phungductung 0:8ede47d38d10 890 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 891 {
phungductung 0:8ede47d38d10 892 return hdma->State;
phungductung 0:8ede47d38d10 893 }
phungductung 0:8ede47d38d10 894
phungductung 0:8ede47d38d10 895 /**
phungductung 0:8ede47d38d10 896 * @brief Return the DMA error code
phungductung 0:8ede47d38d10 897 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 898 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 899 * @retval DMA Error Code
phungductung 0:8ede47d38d10 900 */
phungductung 0:8ede47d38d10 901 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 902 {
phungductung 0:8ede47d38d10 903 return hdma->ErrorCode;
phungductung 0:8ede47d38d10 904 }
phungductung 0:8ede47d38d10 905
phungductung 0:8ede47d38d10 906 /**
phungductung 0:8ede47d38d10 907 * @}
phungductung 0:8ede47d38d10 908 */
phungductung 0:8ede47d38d10 909
phungductung 0:8ede47d38d10 910 /**
phungductung 0:8ede47d38d10 911 * @brief Returns the DMA Stream base address depending on stream number
phungductung 0:8ede47d38d10 912 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
phungductung 0:8ede47d38d10 913 * the configuration information for the specified DMA Stream.
phungductung 0:8ede47d38d10 914 * @retval Stream base address
phungductung 0:8ede47d38d10 915 */
phungductung 0:8ede47d38d10 916 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
phungductung 0:8ede47d38d10 917 {
phungductung 0:8ede47d38d10 918 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFF) - 16) / 24;
phungductung 0:8ede47d38d10 919
phungductung 0:8ede47d38d10 920 /* lookup table for necessary bitshift of flags within status registers */
phungductung 0:8ede47d38d10 921 static const uint8_t flagBitshiftOffset[8] = {0, 6, 16, 22, 0, 6, 16, 22};
phungductung 0:8ede47d38d10 922 hdma->StreamIndex = flagBitshiftOffset[stream_number];
phungductung 0:8ede47d38d10 923
phungductung 0:8ede47d38d10 924 if (stream_number > 3)
phungductung 0:8ede47d38d10 925 {
phungductung 0:8ede47d38d10 926 /* return pointer to HISR and HIFCR */
phungductung 0:8ede47d38d10 927 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FF)) + 4);
phungductung 0:8ede47d38d10 928 }
phungductung 0:8ede47d38d10 929 else
phungductung 0:8ede47d38d10 930 {
phungductung 0:8ede47d38d10 931 /* return pointer to LISR and LIFCR */
phungductung 0:8ede47d38d10 932 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FF));
phungductung 0:8ede47d38d10 933 }
phungductung 0:8ede47d38d10 934
phungductung 0:8ede47d38d10 935 return hdma->StreamBaseAddress;
phungductung 0:8ede47d38d10 936 }
phungductung 0:8ede47d38d10 937 /**
phungductung 0:8ede47d38d10 938 * @}
phungductung 0:8ede47d38d10 939 */
phungductung 0:8ede47d38d10 940
phungductung 0:8ede47d38d10 941 #endif /* HAL_DMA_MODULE_ENABLED */
phungductung 0:8ede47d38d10 942 /**
phungductung 0:8ede47d38d10 943 * @}
phungductung 0:8ede47d38d10 944 */
phungductung 0:8ede47d38d10 945
phungductung 0:8ede47d38d10 946 /**
phungductung 0:8ede47d38d10 947 * @}
phungductung 0:8ede47d38d10 948 */
phungductung 0:8ede47d38d10 949
phungductung 0:8ede47d38d10 950 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/