Patrick Clary / Radio

Specialized interface code for the nRF24L01P wireless transceiver.

Dependents:   WalkingRobot PcRadioBridge FzeroXcontroller WalkingRobot ... more

nRF24L01P_defs.h@4:7953b5fa8aae, 2013-01-17 (annotated)

Committer:
pclary
Date:
Thu Jan 17 18:33:18 2013 +0000
Revision:
4:7953b5fa8aae
Parent:
0:fb0cf6209cd3 
Removed unnecessary 1ms pause in receive interrupt.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pclary 0:fb0cf6209cd3 1 // SPI frequency
pclary 0:fb0cf6209cd3 2 #define SPI_FREQUENCY 2000000
pclary 0:fb0cf6209cd3 3
pclary 0:fb0cf6209cd3 4 // SPI commands
pclary 0:fb0cf6209cd3 5 #define R_REGISTER 0x00
pclary 0:fb0cf6209cd3 6 #define W_REGISTER 0x20
pclary 0:fb0cf6209cd3 7 #define R_RX_PAYLOAD 0x61
pclary 0:fb0cf6209cd3 8 #define W_TX_PAYLOAD 0xa0
pclary 0:fb0cf6209cd3 9 #define FLUSH_TX 0xe1
pclary 0:fb0cf6209cd3 10 #define FLUSH_RX 0xe2
pclary 0:fb0cf6209cd3 11 #define REUSE_TX_PL 0xe3
pclary 0:fb0cf6209cd3 12 #define R_RX_PL_WID 0x60
pclary 0:fb0cf6209cd3 13 #define W_ACK_PAYLOAD 0xa8
pclary 0:fb0cf6209cd3 14 #define W_TX_PAYLOAD_NOACK 0xb0
pclary 0:fb0cf6209cd3 15 #define NOP 0xff
pclary 0:fb0cf6209cd3 16
pclary 0:fb0cf6209cd3 17 // Address masks
pclary 0:fb0cf6209cd3 18 #define REGISTER_ADDRESS_MASK 0x1f
pclary 0:fb0cf6209cd3 19 #define PIPE_MASK 0x07
pclary 0:fb0cf6209cd3 20
pclary 0:fb0cf6209cd3 21 // Register addresses
pclary 0:fb0cf6209cd3 22 #define CONFIG 0x00
pclary 0:fb0cf6209cd3 23 #define EN_AA 0x01
pclary 0:fb0cf6209cd3 24 #define EN_RXADDR 0x02
pclary 0:fb0cf6209cd3 25 #define SETUP_AW 0x03
pclary 0:fb0cf6209cd3 26 #define SETUP_RETR 0x04
pclary 0:fb0cf6209cd3 27 #define RF_CH 0x05
pclary 0:fb0cf6209cd3 28 #define RF_SETUP 0x06
pclary 0:fb0cf6209cd3 29 #define STATUS 0x07
pclary 0:fb0cf6209cd3 30 #define OBSERVE_TX 0x08
pclary 0:fb0cf6209cd3 31 #define RPD 0x09
pclary 0:fb0cf6209cd3 32 #define RX_ADDR_P0 0x0a
pclary 0:fb0cf6209cd3 33 #define RX_ADDR_P1 0x0b
pclary 0:fb0cf6209cd3 34 #define RX_ADDR_P2 0x0c
pclary 0:fb0cf6209cd3 35 #define RX_ADDR_P3 0x0d
pclary 0:fb0cf6209cd3 36 #define RX_ADDR_P4 0x0e
pclary 0:fb0cf6209cd3 37 #define RX_ADDR_P5 0x0f
pclary 0:fb0cf6209cd3 38 #define TX_ADDR 0x10
pclary 0:fb0cf6209cd3 39 #define RX_PW_P0 0x11
pclary 0:fb0cf6209cd3 40 #define RX_PW_P1 0x12
pclary 0:fb0cf6209cd3 41 #define RX_PW_P2 0x13
pclary 0:fb0cf6209cd3 42 #define RX_PW_P3 0x14
pclary 0:fb0cf6209cd3 43 #define RX_PW_P4 0x15
pclary 0:fb0cf6209cd3 44 #define RX_PW_P5 0x16
pclary 0:fb0cf6209cd3 45 #define FIFO_STATUS 0x17
pclary 0:fb0cf6209cd3 46 #define DYNPD 0x1c
pclary 0:fb0cf6209cd3 47 #define FEATURE 0x1d
pclary 0:fb0cf6209cd3 48
pclary 0:fb0cf6209cd3 49 // CONFIG bits
pclary 0:fb0cf6209cd3 50 #define CONFIG_MASK_RX_DR (1<<6)
pclary 0:fb0cf6209cd3 51 #define CONFIG_MASK_TX_DS (1<<5)
pclary 0:fb0cf6209cd3 52 #define CONFIG_MASK_MAX_RT (1<<4)
pclary 0:fb0cf6209cd3 53 #define CONFIG_EN_CRC (1<<3)
pclary 0:fb0cf6209cd3 54 #define CONFIG_CRC0 (1<<2)
pclary 0:fb0cf6209cd3 55 #define CONFIG_PWR_UP (1<<1)
pclary 0:fb0cf6209cd3 56 #define CONFIG_PRIM_RX (1<<0)
pclary 0:fb0cf6209cd3 57
pclary 0:fb0cf6209cd3 58 // EN_AA bits
pclary 0:fb0cf6209cd3 59 #define ENAA_P5 (1<<5)
pclary 0:fb0cf6209cd3 60 #define ENAA_P4 (1<<4)
pclary 0:fb0cf6209cd3 61 #define ENAA_P3 (1<<3)
pclary 0:fb0cf6209cd3 62 #define ENAA_P2 (1<<2)
pclary 0:fb0cf6209cd3 63 #define ENAA_P1 (1<<1)
pclary 0:fb0cf6209cd3 64 #define ENAA_P0 (1<<0)
pclary 0:fb0cf6209cd3 65
pclary 0:fb0cf6209cd3 66 // EN_RXADDR bits
pclary 0:fb0cf6209cd3 67 #define ERX_P5 (1<<5)
pclary 0:fb0cf6209cd3 68 #define ERX_P4 (1<<4)
pclary 0:fb0cf6209cd3 69 #define ERX_P3 (1<<3)
pclary 0:fb0cf6209cd3 70 #define ERX_P2 (1<<2)
pclary 0:fb0cf6209cd3 71 #define ERX_P1 (1<<1)
pclary 0:fb0cf6209cd3 72 #define ERX_P0 (1<<0)
pclary 0:fb0cf6209cd3 73
pclary 0:fb0cf6209cd3 74 // SETUP_AW values
pclary 0:fb0cf6209cd3 75 #define SETUP_AW_3BYTES 0x01
pclary 0:fb0cf6209cd3 76 #define SETUP_AW_4BYTES 0x02
pclary 0:fb0cf6209cd3 77 #define SETUP_AW_5BYTES 0x03
pclary 0:fb0cf6209cd3 78
pclary 0:fb0cf6209cd3 79 // RF_SETUP bits
pclary 0:fb0cf6209cd3 80 #define RF_SETUP_CONT_WAVE (1<<7)
pclary 0:fb0cf6209cd3 81 #define RF_SETUP_RF_DR_LOW (1<<5)
pclary 0:fb0cf6209cd3 82 #define RF_SETUP_PLL_LOCK (1<<4)
pclary 0:fb0cf6209cd3 83 #define RF_SETUP_RF_DR_HIGH (1<<3)
pclary 0:fb0cf6209cd3 84 #define RF_SETUP_RF_PWR_18 (0x0<<1)
pclary 0:fb0cf6209cd3 85 #define RF_SETUP_RF_PWR_12 (0x1<<1)
pclary 0:fb0cf6209cd3 86 #define RF_SETUP_RF_PWR_6 (0x2<<1)
pclary 0:fb0cf6209cd3 87 #define RF_SETUP_RF_PWR_0 (0x3<<1)
pclary 0:fb0cf6209cd3 88
pclary 0:fb0cf6209cd3 89 // STATUS bits
pclary 0:fb0cf6209cd3 90 #define STATUS_RX_DR (1<<6)
pclary 0:fb0cf6209cd3 91 #define STATUS_TX_DS (1<<5)
pclary 0:fb0cf6209cd3 92 #define STATUS_MAX_RT (1<<4)
pclary 0:fb0cf6209cd3 93 #define STATUS_RN_P_MASK (0x7<<1)
pclary 0:fb0cf6209cd3 94 #define STATUS_RN_P_NO_P0 (0x0<<1)
pclary 0:fb0cf6209cd3 95 #define STATUS_RN_P_NO_P1 (0x1<<1)
pclary 0:fb0cf6209cd3 96 #define STATUS_RN_P_NO_P2 (0x2<<1)
pclary 0:fb0cf6209cd3 97 #define STATUS_RN_P_NO_P3 (0x3<<1)
pclary 0:fb0cf6209cd3 98 #define STATUS_RN_P_NO_P4 (0x4<<1)
pclary 0:fb0cf6209cd3 99 #define STATUS_RN_P_NO_P5 (0x5<<1)
pclary 0:fb0cf6209cd3 100 #define STATUS_RN_P_NO_EMPTY (0x7<<1)
pclary 0:fb0cf6209cd3 101 #define STATUS_TX_FULL (1<<0)
pclary 0:fb0cf6209cd3 102
pclary 0:fb0cf6209cd3 103 // FIFO_STATUS bits
pclary 0:fb0cf6209cd3 104 #define FIFO_STATUS_TX_REUSE (1<<6)
pclary 0:fb0cf6209cd3 105 #define FIFO_STATUS_TX_FULL (1<<5)
pclary 0:fb0cf6209cd3 106 #define FIFO_STATUS_TX_EMPTY (1<<4)
pclary 0:fb0cf6209cd3 107 #define FIFO_STATUS_RX_FULL (1<<1)
pclary 0:fb0cf6209cd3 108 #define FIFO_STATUS_RX_EMPTY (1<<0)
pclary 0:fb0cf6209cd3 109
pclary 0:fb0cf6209cd3 110 // DYNPD bits
pclary 0:fb0cf6209cd3 111 #define DPL_P5 (1<<5)
pclary 0:fb0cf6209cd3 112 #define DPL_P4 (1<<4)
pclary 0:fb0cf6209cd3 113 #define DPL_P3 (1<<3)
pclary 0:fb0cf6209cd3 114 #define DPL_P2 (1<<2)
pclary 0:fb0cf6209cd3 115 #define DPL_P1 (1<<1)
pclary 0:fb0cf6209cd3 116 #define DPL_P0 (1<<0)
pclary 0:fb0cf6209cd3 117
pclary 0:fb0cf6209cd3 118 // FEATURE bits
pclary 0:fb0cf6209cd3 119 #define FEATURE_EN_DPL (1<<2)
pclary 0:fb0cf6209cd3 120 #define FEATURE_EN_ACK_PAY (1<<1)
pclary 0:fb0cf6209cd3 121 #define FEATURE_EN_DYN_ACK (1<<0)
pclary 0:fb0cf6209cd3 122
pclary 0:fb0cf6209cd3 123 // Timing
pclary 0:fb0cf6209cd3 124 #define TIMING_Tpd2stby 4500
pclary 0:fb0cf6209cd3 125 #define TIMING_Tstby2a 130
pclary 0:fb0cf6209cd3 126 #define TIMING_Thce 10
pclary 0:fb0cf6209cd3 127 #define TIMING_Tpece2csn 4
pclary 0:fb0cf6209cd3 128 #define TIMING_Tpor 100000
pclary 0:fb0cf6209cd3 129 #define TIMING_Toa 41
pclary 0:fb0cf6209cd3 130 #define TIMING_Tirq 6
pclary 0:fb0cf6209cd3 131
pclary 0:fb0cf6209cd3 132 // Channel used
pclary 0:fb0cf6209cd3 133 #define RF_CHANNEL 56
pclary 0:fb0cf6209cd3 134
pclary 0:fb0cf6209cd3 135 // Addresses
pclary 0:fb0cf6209cd3 136 #define ROBOT_ADDRESS_1 0x07
pclary 0:fb0cf6209cd3 137 #define ROBOT_ADDRESS_2 0x00
pclary 0:fb0cf6209cd3 138 #define ROBOT_ADDRESS_3 0x00
pclary 0:fb0cf6209cd3 139 #define CTRL_BASE_ADDRESS_1 0xa4
pclary 0:fb0cf6209cd3 140 #define CTRL_BASE_ADDRESS_2 0x01
pclary 0:fb0cf6209cd3 141 #define CTRL_BASE_ADDRESS_3 0x00