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Dependencies: ChaNFSSD EthernetNetIf I2CLEDDisp Agentbed ChaNFSUSB ILinterpreter mbed BMP085 WeatherMeters ConfigFile ChaNFS I2CLCD

PowerControl/PowerControl/EthernetPowerControl.cpp@8:bed0b81794ba, 2012-03-16 (annotated)

Committer:: okini3939
Date:: Fri Mar 16 15:26:46 2012 +0000
Revision:: 8:bed0b81794ba

Who changed what in which revision?

User	Revision	Line number	New contents of line
okini3939	8:bed0b81794ba	1	#include "EthernetPowerControl.h"
okini3939	8:bed0b81794ba	2
okini3939	8:bed0b81794ba	3	static void write_PHY (unsigned int PhyReg, unsigned short Value) {
okini3939	8:bed0b81794ba	4	/* Write a data 'Value' to PHY register 'PhyReg'. */
okini3939	8:bed0b81794ba	5	unsigned int tout;
okini3939	8:bed0b81794ba	6	/* Hardware MII Management for LPC176x devices. */
okini3939	8:bed0b81794ba	7	LPC_EMAC->MADR = DP83848C_DEF_ADR \| PhyReg;
okini3939	8:bed0b81794ba	8	LPC_EMAC->MWTD = Value;
okini3939	8:bed0b81794ba	9
okini3939	8:bed0b81794ba	10	/* Wait utill operation completed */
okini3939	8:bed0b81794ba	11	for (tout = 0; tout < MII_WR_TOUT; tout++) {
okini3939	8:bed0b81794ba	12	if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
okini3939	8:bed0b81794ba	13	break;
okini3939	8:bed0b81794ba	14	}
okini3939	8:bed0b81794ba	15	}
okini3939	8:bed0b81794ba	16	}
okini3939	8:bed0b81794ba	17
okini3939	8:bed0b81794ba	18	static unsigned short read_PHY (unsigned int PhyReg) {
okini3939	8:bed0b81794ba	19	/* Read a PHY register 'PhyReg'. */
okini3939	8:bed0b81794ba	20	unsigned int tout, val;
okini3939	8:bed0b81794ba	21
okini3939	8:bed0b81794ba	22	LPC_EMAC->MADR = DP83848C_DEF_ADR \| PhyReg;
okini3939	8:bed0b81794ba	23	LPC_EMAC->MCMD = MCMD_READ;
okini3939	8:bed0b81794ba	24
okini3939	8:bed0b81794ba	25	/* Wait until operation completed */
okini3939	8:bed0b81794ba	26	for (tout = 0; tout < MII_RD_TOUT; tout++) {
okini3939	8:bed0b81794ba	27	if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
okini3939	8:bed0b81794ba	28	break;
okini3939	8:bed0b81794ba	29	}
okini3939	8:bed0b81794ba	30	}
okini3939	8:bed0b81794ba	31	LPC_EMAC->MCMD = 0;
okini3939	8:bed0b81794ba	32	val = LPC_EMAC->MRDD;
okini3939	8:bed0b81794ba	33
okini3939	8:bed0b81794ba	34	return (val);
okini3939	8:bed0b81794ba	35	}
okini3939	8:bed0b81794ba	36
okini3939	8:bed0b81794ba	37	void EMAC_Init()
okini3939	8:bed0b81794ba	38	{
okini3939	8:bed0b81794ba	39	unsigned int tout,regv;
okini3939	8:bed0b81794ba	40	/* Power Up the EMAC controller. */
okini3939	8:bed0b81794ba	41	Peripheral_PowerUp(LPC1768_PCONP_PCENET);
okini3939	8:bed0b81794ba	42
okini3939	8:bed0b81794ba	43	LPC_PINCON->PINSEL2 = 0x50150105;
okini3939	8:bed0b81794ba	44	LPC_PINCON->PINSEL3 &= ~0x0000000F;
okini3939	8:bed0b81794ba	45	LPC_PINCON->PINSEL3 \|= 0x00000005;
okini3939	8:bed0b81794ba	46
okini3939	8:bed0b81794ba	47	/* Reset all EMAC internal modules. */
okini3939	8:bed0b81794ba	48	LPC_EMAC->MAC1 = MAC1_RES_TX \| MAC1_RES_MCS_TX \| MAC1_RES_RX \| MAC1_RES_MCS_RX \|
okini3939	8:bed0b81794ba	49	MAC1_SIM_RES \| MAC1_SOFT_RES;
okini3939	8:bed0b81794ba	50	LPC_EMAC->Command = CR_REG_RES \| CR_TX_RES \| CR_RX_RES;
okini3939	8:bed0b81794ba	51
okini3939	8:bed0b81794ba	52	/* A short delay after reset. */
okini3939	8:bed0b81794ba	53	for (tout = 100; tout; tout--);
okini3939	8:bed0b81794ba	54
okini3939	8:bed0b81794ba	55	/* Initialize MAC control registers. */
okini3939	8:bed0b81794ba	56	LPC_EMAC->MAC1 = MAC1_PASS_ALL;
okini3939	8:bed0b81794ba	57	LPC_EMAC->MAC2 = MAC2_CRC_EN \| MAC2_PAD_EN;
okini3939	8:bed0b81794ba	58	LPC_EMAC->MAXF = ETH_MAX_FLEN;
okini3939	8:bed0b81794ba	59	LPC_EMAC->CLRT = CLRT_DEF;
okini3939	8:bed0b81794ba	60	LPC_EMAC->IPGR = IPGR_DEF;
okini3939	8:bed0b81794ba	61
okini3939	8:bed0b81794ba	62	/* Enable Reduced MII interface. */
okini3939	8:bed0b81794ba	63	LPC_EMAC->Command = CR_RMII \| CR_PASS_RUNT_FRM;
okini3939	8:bed0b81794ba	64
okini3939	8:bed0b81794ba	65	/* Reset Reduced MII Logic. */
okini3939	8:bed0b81794ba	66	LPC_EMAC->SUPP = SUPP_RES_RMII;
okini3939	8:bed0b81794ba	67	for (tout = 100; tout; tout--);
okini3939	8:bed0b81794ba	68	LPC_EMAC->SUPP = 0;
okini3939	8:bed0b81794ba	69
okini3939	8:bed0b81794ba	70	/* Put the DP83848C in reset mode */
okini3939	8:bed0b81794ba	71	write_PHY (PHY_REG_BMCR, 0x8000);
okini3939	8:bed0b81794ba	72
okini3939	8:bed0b81794ba	73	/* Wait for hardware reset to end. */
okini3939	8:bed0b81794ba	74	for (tout = 0; tout < 0x100000; tout++) {
okini3939	8:bed0b81794ba	75	regv = read_PHY (PHY_REG_BMCR);
okini3939	8:bed0b81794ba	76	if (!(regv & 0x8000)) {
okini3939	8:bed0b81794ba	77	/* Reset complete */
okini3939	8:bed0b81794ba	78	break;
okini3939	8:bed0b81794ba	79	}
okini3939	8:bed0b81794ba	80	}
okini3939	8:bed0b81794ba	81	}
okini3939	8:bed0b81794ba	82
okini3939	8:bed0b81794ba	83
okini3939	8:bed0b81794ba	84	void PHY_PowerDown()
okini3939	8:bed0b81794ba	85	{
okini3939	8:bed0b81794ba	86	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939	8:bed0b81794ba	87	EMAC_Init(); //init EMAC if it is not already init'd
okini3939	8:bed0b81794ba	88
okini3939	8:bed0b81794ba	89	unsigned int regv;
okini3939	8:bed0b81794ba	90	regv = read_PHY(PHY_REG_BMCR);
okini3939	8:bed0b81794ba	91	write_PHY(PHY_REG_BMCR, regv \| (1 << PHY_REG_BMCR_POWERDOWN));
okini3939	8:bed0b81794ba	92	regv = read_PHY(PHY_REG_BMCR);
okini3939	8:bed0b81794ba	93
okini3939	8:bed0b81794ba	94	//shouldn't need the EMAC now.
okini3939	8:bed0b81794ba	95	Peripheral_PowerDown(LPC1768_PCONP_PCENET);
okini3939	8:bed0b81794ba	96
okini3939	8:bed0b81794ba	97	//and turn off the PHY OSC
okini3939	8:bed0b81794ba	98	LPC_GPIO1->FIODIR \|= 0x8000000;
okini3939	8:bed0b81794ba	99	LPC_GPIO1->FIOCLR = 0x8000000;
okini3939	8:bed0b81794ba	100	}
okini3939	8:bed0b81794ba	101
okini3939	8:bed0b81794ba	102	void PHY_PowerUp()
okini3939	8:bed0b81794ba	103	{
okini3939	8:bed0b81794ba	104	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939	8:bed0b81794ba	105	EMAC_Init(); //init EMAC if it is not already init'd
okini3939	8:bed0b81794ba	106
okini3939	8:bed0b81794ba	107	LPC_GPIO1->FIODIR \|= 0x8000000;
okini3939	8:bed0b81794ba	108	LPC_GPIO1->FIOSET = 0x8000000;
okini3939	8:bed0b81794ba	109
okini3939	8:bed0b81794ba	110	//wait for osc to be stable
okini3939	8:bed0b81794ba	111	wait_ms(200);
okini3939	8:bed0b81794ba	112
okini3939	8:bed0b81794ba	113	unsigned int regv;
okini3939	8:bed0b81794ba	114	regv = read_PHY(PHY_REG_BMCR);
okini3939	8:bed0b81794ba	115	write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
okini3939	8:bed0b81794ba	116	regv = read_PHY(PHY_REG_BMCR);
okini3939	8:bed0b81794ba	117	}
okini3939	8:bed0b81794ba	118
okini3939	8:bed0b81794ba	119	void PHY_EnergyDetect_Enable()
okini3939	8:bed0b81794ba	120	{
okini3939	8:bed0b81794ba	121	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939	8:bed0b81794ba	122	EMAC_Init(); //init EMAC if it is not already init'd
okini3939	8:bed0b81794ba	123
okini3939	8:bed0b81794ba	124	unsigned int regv;
okini3939	8:bed0b81794ba	125	regv = read_PHY(PHY_REG_EDCR);
okini3939	8:bed0b81794ba	126	write_PHY(PHY_REG_BMCR, regv \| (1 << PHY_REG_EDCR_ENABLE));
okini3939	8:bed0b81794ba	127	regv = read_PHY(PHY_REG_EDCR);
okini3939	8:bed0b81794ba	128	}
okini3939	8:bed0b81794ba	129
okini3939	8:bed0b81794ba	130	void PHY_EnergyDetect_Disable()
okini3939	8:bed0b81794ba	131	{
okini3939	8:bed0b81794ba	132	if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
okini3939	8:bed0b81794ba	133	EMAC_Init(); //init EMAC if it is not already init'd
okini3939	8:bed0b81794ba	134	unsigned int regv;
okini3939	8:bed0b81794ba	135	regv = read_PHY(PHY_REG_EDCR);
okini3939	8:bed0b81794ba	136	write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
okini3939	8:bed0b81794ba	137	regv = read_PHY(PHY_REG_EDCR);
okini3939	8:bed0b81794ba	138	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	04 Jul 2011
Imports:	120
Forks:	0
Commits:	9
Dependents:	0
Dependencies:	12
Followers:	8

PowerControl/PowerControl/EthernetPowerControl.cpp@8:bed0b81794ba, 2012-03-16 (annotated)

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