SPI RAM 23LC1024 (Microchip) with DMA

Dependencies:   mbed

Fork of SPIRAM_23LC1024 by Suga koubou

Committer:
okini3939
Date:
Wed Dec 05 07:56:09 2012 +0000
Revision:
2:a3e0f7f37ac9
DMX

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okini3939 2:a3e0f7f37ac9 1 /*
okini3939 2:a3e0f7f37ac9 2 Copyright (c) 2011 Andy Kirkham
okini3939 2:a3e0f7f37ac9 3
okini3939 2:a3e0f7f37ac9 4 Permission is hereby granted, free of charge, to any person obtaining a copy
okini3939 2:a3e0f7f37ac9 5 of this software and associated documentation files (the "Software"), to deal
okini3939 2:a3e0f7f37ac9 6 in the Software without restriction, including without limitation the rights
okini3939 2:a3e0f7f37ac9 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
okini3939 2:a3e0f7f37ac9 8 copies of the Software, and to permit persons to whom the Software is
okini3939 2:a3e0f7f37ac9 9 furnished to do so, subject to the following conditions:
okini3939 2:a3e0f7f37ac9 10
okini3939 2:a3e0f7f37ac9 11 The above copyright notice and this permission notice shall be included in
okini3939 2:a3e0f7f37ac9 12 all copies or substantial portions of the Software.
okini3939 2:a3e0f7f37ac9 13
okini3939 2:a3e0f7f37ac9 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
okini3939 2:a3e0f7f37ac9 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
okini3939 2:a3e0f7f37ac9 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
okini3939 2:a3e0f7f37ac9 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
okini3939 2:a3e0f7f37ac9 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
okini3939 2:a3e0f7f37ac9 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
okini3939 2:a3e0f7f37ac9 20 THE SOFTWARE.
okini3939 2:a3e0f7f37ac9 21 */
okini3939 2:a3e0f7f37ac9 22
okini3939 2:a3e0f7f37ac9 23 #ifndef IOMACROS_H
okini3939 2:a3e0f7f37ac9 24 #define IOMACROS_H
okini3939 2:a3e0f7f37ac9 25
okini3939 2:a3e0f7f37ac9 26 #ifndef __LPC17xx_H__
okini3939 2:a3e0f7f37ac9 27 #include "LPC17xx.h"
okini3939 2:a3e0f7f37ac9 28 #endif
okini3939 2:a3e0f7f37ac9 29
okini3939 2:a3e0f7f37ac9 30 #define PIN_PULLUP 0UL
okini3939 2:a3e0f7f37ac9 31 #define PIN_REPEAT 1UL
okini3939 2:a3e0f7f37ac9 32 #define PIN_NONE 2UL
okini3939 2:a3e0f7f37ac9 33 #define PIN_PULLDOWN 3UL
okini3939 2:a3e0f7f37ac9 34
okini3939 2:a3e0f7f37ac9 35 /* p5 is P0.9 */
okini3939 2:a3e0f7f37ac9 36 #define p5_SEL_MASK ~(3UL << 18)
okini3939 2:a3e0f7f37ac9 37 #define p5_SET_MASK (1UL << 9)
okini3939 2:a3e0f7f37ac9 38 #define p5_CLR_MASK ~(p5_SET_MASK)
okini3939 2:a3e0f7f37ac9 39 #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK
okini3939 2:a3e0f7f37ac9 40 #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK;
okini3939 2:a3e0f7f37ac9 41 #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK
okini3939 2:a3e0f7f37ac9 42 #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK
okini3939 2:a3e0f7f37ac9 43 #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK)
okini3939 2:a3e0f7f37ac9 44 #define p5_IS_CLR !(p5_IS_SET)
okini3939 2:a3e0f7f37ac9 45 #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18)
okini3939 2:a3e0f7f37ac9 46
okini3939 2:a3e0f7f37ac9 47 /* p6 is P0.8 */
okini3939 2:a3e0f7f37ac9 48 #define p6_SEL_MASK ~(3UL << 16)
okini3939 2:a3e0f7f37ac9 49 #define p6_SET_MASK (1UL << 8)
okini3939 2:a3e0f7f37ac9 50 #define p6_CLR_MASK ~(p6_SET_MASK)
okini3939 2:a3e0f7f37ac9 51 #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK
okini3939 2:a3e0f7f37ac9 52 #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK;
okini3939 2:a3e0f7f37ac9 53 #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK
okini3939 2:a3e0f7f37ac9 54 #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK
okini3939 2:a3e0f7f37ac9 55 #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK)
okini3939 2:a3e0f7f37ac9 56 #define p6_IS_CLR !(p6_IS_SET)
okini3939 2:a3e0f7f37ac9 57 #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16)
okini3939 2:a3e0f7f37ac9 58
okini3939 2:a3e0f7f37ac9 59 /* p7 is P0.7 */
okini3939 2:a3e0f7f37ac9 60 #define p7_SEL_MASK ~(3UL << 14)
okini3939 2:a3e0f7f37ac9 61 #define p7_SET_MASK (1UL << 7)
okini3939 2:a3e0f7f37ac9 62 #define p7_CLR_MASK ~(p7_SET_MASK)
okini3939 2:a3e0f7f37ac9 63 #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK
okini3939 2:a3e0f7f37ac9 64 #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK;
okini3939 2:a3e0f7f37ac9 65 #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK
okini3939 2:a3e0f7f37ac9 66 #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK
okini3939 2:a3e0f7f37ac9 67 #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK)
okini3939 2:a3e0f7f37ac9 68 #define p7_IS_CLR !(p7_IS_SET)
okini3939 2:a3e0f7f37ac9 69 #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14)
okini3939 2:a3e0f7f37ac9 70
okini3939 2:a3e0f7f37ac9 71 /* p8 is P0.6 */
okini3939 2:a3e0f7f37ac9 72 #define p8_SEL_MASK ~(3UL << 12)
okini3939 2:a3e0f7f37ac9 73 #define p8_SET_MASK (1UL << 6)
okini3939 2:a3e0f7f37ac9 74 #define p8_CLR_MASK ~(p8_SET_MASK)
okini3939 2:a3e0f7f37ac9 75 #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK
okini3939 2:a3e0f7f37ac9 76 #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK;
okini3939 2:a3e0f7f37ac9 77 #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK
okini3939 2:a3e0f7f37ac9 78 #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK
okini3939 2:a3e0f7f37ac9 79 #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK)
okini3939 2:a3e0f7f37ac9 80 #define p8_IS_CLR !(p8_IS_SET)
okini3939 2:a3e0f7f37ac9 81 #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12)
okini3939 2:a3e0f7f37ac9 82
okini3939 2:a3e0f7f37ac9 83 /* p9 is P0.0 */
okini3939 2:a3e0f7f37ac9 84 #define p9_SEL_MASK ~(3UL << 0)
okini3939 2:a3e0f7f37ac9 85 #define p9_SET_MASK (1UL << 0)
okini3939 2:a3e0f7f37ac9 86 #define p9_CLR_MASK ~(p9_SET_MASK)
okini3939 2:a3e0f7f37ac9 87 #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK
okini3939 2:a3e0f7f37ac9 88 #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK;
okini3939 2:a3e0f7f37ac9 89 #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK
okini3939 2:a3e0f7f37ac9 90 #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK
okini3939 2:a3e0f7f37ac9 91 #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK)
okini3939 2:a3e0f7f37ac9 92 #define p9_IS_CLR !(p9_IS_SET)
okini3939 2:a3e0f7f37ac9 93 #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0)
okini3939 2:a3e0f7f37ac9 94
okini3939 2:a3e0f7f37ac9 95 /* p10 is P0.1 */
okini3939 2:a3e0f7f37ac9 96 #define p10_SEL_MASK ~(3UL << 2)
okini3939 2:a3e0f7f37ac9 97 #define p10_SET_MASK (1UL << 1)
okini3939 2:a3e0f7f37ac9 98 #define p10_CLR_MASK ~(p10_SET_MASK)
okini3939 2:a3e0f7f37ac9 99 #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK
okini3939 2:a3e0f7f37ac9 100 #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK;
okini3939 2:a3e0f7f37ac9 101 #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK
okini3939 2:a3e0f7f37ac9 102 #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK
okini3939 2:a3e0f7f37ac9 103 #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK)
okini3939 2:a3e0f7f37ac9 104 #define p10_IS_CLR !(p10_IS_SET)
okini3939 2:a3e0f7f37ac9 105 #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2)
okini3939 2:a3e0f7f37ac9 106
okini3939 2:a3e0f7f37ac9 107 /* p11 is P0.18 */
okini3939 2:a3e0f7f37ac9 108 #define p11_SEL_MASK ~(3UL << 4)
okini3939 2:a3e0f7f37ac9 109 #define p11_SET_MASK (1UL << 18)
okini3939 2:a3e0f7f37ac9 110 #define p11_CLR_MASK ~(p11_SET_MASK)
okini3939 2:a3e0f7f37ac9 111 #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK
okini3939 2:a3e0f7f37ac9 112 #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK;
okini3939 2:a3e0f7f37ac9 113 #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK
okini3939 2:a3e0f7f37ac9 114 #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK
okini3939 2:a3e0f7f37ac9 115 #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK)
okini3939 2:a3e0f7f37ac9 116 #define p11_IS_CLR !(p11_IS_SET)
okini3939 2:a3e0f7f37ac9 117 #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4)
okini3939 2:a3e0f7f37ac9 118
okini3939 2:a3e0f7f37ac9 119 /* p12 is P0.17 */
okini3939 2:a3e0f7f37ac9 120 #define p12_SEL_MASK ~(3UL << 2)
okini3939 2:a3e0f7f37ac9 121 #define p12_SET_MASK (1UL << 17)
okini3939 2:a3e0f7f37ac9 122 #define p12_CLR_MASK ~(p12_SET_MASK)
okini3939 2:a3e0f7f37ac9 123 #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK
okini3939 2:a3e0f7f37ac9 124 #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK;
okini3939 2:a3e0f7f37ac9 125 #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK
okini3939 2:a3e0f7f37ac9 126 #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK
okini3939 2:a3e0f7f37ac9 127 #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK)
okini3939 2:a3e0f7f37ac9 128 #define p12_IS_CLR !(p12_IS_SET)
okini3939 2:a3e0f7f37ac9 129 #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2)
okini3939 2:a3e0f7f37ac9 130
okini3939 2:a3e0f7f37ac9 131 /* p13 is P0.15 */
okini3939 2:a3e0f7f37ac9 132 #define p13_SEL_MASK ~(3UL << 30)
okini3939 2:a3e0f7f37ac9 133 #define p13_SET_MASK (1UL << 15)
okini3939 2:a3e0f7f37ac9 134 #define p13_CLR_MASK ~(p13_SET_MASK)
okini3939 2:a3e0f7f37ac9 135 #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK
okini3939 2:a3e0f7f37ac9 136 #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK;
okini3939 2:a3e0f7f37ac9 137 #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK
okini3939 2:a3e0f7f37ac9 138 #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK
okini3939 2:a3e0f7f37ac9 139 #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK)
okini3939 2:a3e0f7f37ac9 140 #define p13_IS_CLR !(p13_IS_SET)
okini3939 2:a3e0f7f37ac9 141 #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30)
okini3939 2:a3e0f7f37ac9 142
okini3939 2:a3e0f7f37ac9 143 /* p14 is P0.16 */
okini3939 2:a3e0f7f37ac9 144 #define p14_SEL_MASK ~(3UL << 0)
okini3939 2:a3e0f7f37ac9 145 #define p14_SET_MASK (1UL << 16)
okini3939 2:a3e0f7f37ac9 146 #define p14_CLR_MASK ~(p14_SET_MASK)
okini3939 2:a3e0f7f37ac9 147 #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK
okini3939 2:a3e0f7f37ac9 148 #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK;
okini3939 2:a3e0f7f37ac9 149 #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK
okini3939 2:a3e0f7f37ac9 150 #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK
okini3939 2:a3e0f7f37ac9 151 #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK)
okini3939 2:a3e0f7f37ac9 152 #define p14_IS_CLR !(p14_IS_SET)
okini3939 2:a3e0f7f37ac9 153 #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0)
okini3939 2:a3e0f7f37ac9 154
okini3939 2:a3e0f7f37ac9 155 /* p15 is P0.23 */
okini3939 2:a3e0f7f37ac9 156 #define p15_SEL_MASK ~(3UL << 14)
okini3939 2:a3e0f7f37ac9 157 #define p15_SET_MASK (1UL << 23)
okini3939 2:a3e0f7f37ac9 158 #define p15_CLR_MASK ~(p15_SET_MASK)
okini3939 2:a3e0f7f37ac9 159 #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK
okini3939 2:a3e0f7f37ac9 160 #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK;
okini3939 2:a3e0f7f37ac9 161 #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK
okini3939 2:a3e0f7f37ac9 162 #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK
okini3939 2:a3e0f7f37ac9 163 #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK)
okini3939 2:a3e0f7f37ac9 164 #define p15_IS_CLR !(p15_IS_SET)
okini3939 2:a3e0f7f37ac9 165 #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14)
okini3939 2:a3e0f7f37ac9 166
okini3939 2:a3e0f7f37ac9 167 /* p16 is P0.24 */
okini3939 2:a3e0f7f37ac9 168 #define p16_SEL_MASK ~(3UL << 16)
okini3939 2:a3e0f7f37ac9 169 #define p16_SET_MASK (1UL << 24)
okini3939 2:a3e0f7f37ac9 170 #define p16_CLR_MASK ~(p16_SET_MASK)
okini3939 2:a3e0f7f37ac9 171 #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK
okini3939 2:a3e0f7f37ac9 172 #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK;
okini3939 2:a3e0f7f37ac9 173 #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK
okini3939 2:a3e0f7f37ac9 174 #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK
okini3939 2:a3e0f7f37ac9 175 #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK)
okini3939 2:a3e0f7f37ac9 176 #define p16_IS_CLR !(p16_IS_SET)
okini3939 2:a3e0f7f37ac9 177 #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16)
okini3939 2:a3e0f7f37ac9 178
okini3939 2:a3e0f7f37ac9 179 /* p17 is P0.25 */
okini3939 2:a3e0f7f37ac9 180 #define p17_SEL_MASK ~(3UL << 18)
okini3939 2:a3e0f7f37ac9 181 #define p17_SET_MASK (1UL << 25)
okini3939 2:a3e0f7f37ac9 182 #define p17_CLR_MASK ~(p17_SET_MASK)
okini3939 2:a3e0f7f37ac9 183 #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK
okini3939 2:a3e0f7f37ac9 184 #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK;
okini3939 2:a3e0f7f37ac9 185 #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK
okini3939 2:a3e0f7f37ac9 186 #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK
okini3939 2:a3e0f7f37ac9 187 #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK)
okini3939 2:a3e0f7f37ac9 188 #define p17_IS_CLR !(p17_IS_SET)
okini3939 2:a3e0f7f37ac9 189 #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18)
okini3939 2:a3e0f7f37ac9 190
okini3939 2:a3e0f7f37ac9 191 /* p18 is P0.26 */
okini3939 2:a3e0f7f37ac9 192 #define p18_SEL_MASK ~(3UL << 20)
okini3939 2:a3e0f7f37ac9 193 #define p18_SET_MASK (1UL << 26)
okini3939 2:a3e0f7f37ac9 194 #define p18_CLR_MASK ~(p18_SET_MASK)
okini3939 2:a3e0f7f37ac9 195 #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK
okini3939 2:a3e0f7f37ac9 196 #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK;
okini3939 2:a3e0f7f37ac9 197 #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK
okini3939 2:a3e0f7f37ac9 198 #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK
okini3939 2:a3e0f7f37ac9 199 #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK)
okini3939 2:a3e0f7f37ac9 200 #define p18_IS_CLR !(p18_IS_SET)
okini3939 2:a3e0f7f37ac9 201 #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20)
okini3939 2:a3e0f7f37ac9 202
okini3939 2:a3e0f7f37ac9 203 /* p19 is P1.30 */
okini3939 2:a3e0f7f37ac9 204 #define p19_SEL_MASK ~(3UL << 28)
okini3939 2:a3e0f7f37ac9 205 #define p19_SET_MASK (1UL << 30)
okini3939 2:a3e0f7f37ac9 206 #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK
okini3939 2:a3e0f7f37ac9 207 #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK;
okini3939 2:a3e0f7f37ac9 208 #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK
okini3939 2:a3e0f7f37ac9 209 #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK
okini3939 2:a3e0f7f37ac9 210 #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK)
okini3939 2:a3e0f7f37ac9 211 #define p19_IS_CLR !(p19_IS_SET)
okini3939 2:a3e0f7f37ac9 212 #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28)
okini3939 2:a3e0f7f37ac9 213
okini3939 2:a3e0f7f37ac9 214 /* p20 is P1.31 */
okini3939 2:a3e0f7f37ac9 215 #define p20_SEL_MASK ~(3UL << 30)
okini3939 2:a3e0f7f37ac9 216 #define p20_SET_MASK (1UL << 31)
okini3939 2:a3e0f7f37ac9 217 #define p20_CLR_MASK ~(p20_SET_MASK)
okini3939 2:a3e0f7f37ac9 218 #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK
okini3939 2:a3e0f7f37ac9 219 #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK;
okini3939 2:a3e0f7f37ac9 220 #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK
okini3939 2:a3e0f7f37ac9 221 #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK
okini3939 2:a3e0f7f37ac9 222 #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK)
okini3939 2:a3e0f7f37ac9 223 #define p20_IS_CLR !(p20_IS_SET)
okini3939 2:a3e0f7f37ac9 224 #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30)
okini3939 2:a3e0f7f37ac9 225
okini3939 2:a3e0f7f37ac9 226 /* p21 is P2.5 */
okini3939 2:a3e0f7f37ac9 227 #define p21_SEL_MASK ~(3UL << 10)
okini3939 2:a3e0f7f37ac9 228 #define p21_SET_MASK (1UL << 5)
okini3939 2:a3e0f7f37ac9 229 #define p21_CLR_MASK ~(p21_SET_MASK)
okini3939 2:a3e0f7f37ac9 230 #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK
okini3939 2:a3e0f7f37ac9 231 #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK;
okini3939 2:a3e0f7f37ac9 232 #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK
okini3939 2:a3e0f7f37ac9 233 #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK
okini3939 2:a3e0f7f37ac9 234 #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK)
okini3939 2:a3e0f7f37ac9 235 #define p21_IS_CLR !(p21_IS_SET)
okini3939 2:a3e0f7f37ac9 236 #define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET
okini3939 2:a3e0f7f37ac9 237 #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10)
okini3939 2:a3e0f7f37ac9 238
okini3939 2:a3e0f7f37ac9 239 /* p22 is P2.4 */
okini3939 2:a3e0f7f37ac9 240 #define p22_SEL_MASK ~(3UL << 8)
okini3939 2:a3e0f7f37ac9 241 #define p22_SET_MASK (1UL << 4)
okini3939 2:a3e0f7f37ac9 242 #define p22_CLR_MASK ~(p22_SET_MASK)
okini3939 2:a3e0f7f37ac9 243 #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK
okini3939 2:a3e0f7f37ac9 244 #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK;
okini3939 2:a3e0f7f37ac9 245 #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK
okini3939 2:a3e0f7f37ac9 246 #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK
okini3939 2:a3e0f7f37ac9 247 #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK)
okini3939 2:a3e0f7f37ac9 248 #define p22_IS_CLR !(p22_IS_SET)
okini3939 2:a3e0f7f37ac9 249 #define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET
okini3939 2:a3e0f7f37ac9 250 #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8)
okini3939 2:a3e0f7f37ac9 251
okini3939 2:a3e0f7f37ac9 252 /* p23 is P2.3 */
okini3939 2:a3e0f7f37ac9 253 #define p23_SEL_MASK ~(3UL << 6)
okini3939 2:a3e0f7f37ac9 254 #define p23_SET_MASK (1UL << 3)
okini3939 2:a3e0f7f37ac9 255 #define p23_CLR_MASK ~(p23_SET_MASK)
okini3939 2:a3e0f7f37ac9 256 #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK
okini3939 2:a3e0f7f37ac9 257 #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK;
okini3939 2:a3e0f7f37ac9 258 #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK
okini3939 2:a3e0f7f37ac9 259 #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK
okini3939 2:a3e0f7f37ac9 260 #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK)
okini3939 2:a3e0f7f37ac9 261 #define p23_IS_CLR !(p23_IS_SET)
okini3939 2:a3e0f7f37ac9 262 #define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET
okini3939 2:a3e0f7f37ac9 263 #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6)
okini3939 2:a3e0f7f37ac9 264
okini3939 2:a3e0f7f37ac9 265 /* p24 is P2.2 */
okini3939 2:a3e0f7f37ac9 266 #define p24_SEL_MASK ~(3UL << 4)
okini3939 2:a3e0f7f37ac9 267 #define p24_SET_MASK (1UL << 2)
okini3939 2:a3e0f7f37ac9 268 #define p24_CLR_MASK ~(p24_SET_MASK)
okini3939 2:a3e0f7f37ac9 269 #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK
okini3939 2:a3e0f7f37ac9 270 #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK;
okini3939 2:a3e0f7f37ac9 271 #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK
okini3939 2:a3e0f7f37ac9 272 #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK
okini3939 2:a3e0f7f37ac9 273 #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK)
okini3939 2:a3e0f7f37ac9 274 #define p24_IS_CLR !(p24_IS_SET)
okini3939 2:a3e0f7f37ac9 275 #define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET
okini3939 2:a3e0f7f37ac9 276 #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4)
okini3939 2:a3e0f7f37ac9 277
okini3939 2:a3e0f7f37ac9 278 /* p25 is P2.1 */
okini3939 2:a3e0f7f37ac9 279 #define p25_SEL_MASK ~(3UL << 2)
okini3939 2:a3e0f7f37ac9 280 #define p25_SET_MASK (1UL << 1)
okini3939 2:a3e0f7f37ac9 281 #define p25_CLR_MASK ~(p25_SET_MASK)
okini3939 2:a3e0f7f37ac9 282 #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK
okini3939 2:a3e0f7f37ac9 283 #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK;
okini3939 2:a3e0f7f37ac9 284 #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK
okini3939 2:a3e0f7f37ac9 285 #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK
okini3939 2:a3e0f7f37ac9 286 #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK)
okini3939 2:a3e0f7f37ac9 287 #define p25_IS_CLR !(p25_IS_SET)
okini3939 2:a3e0f7f37ac9 288 #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2)
okini3939 2:a3e0f7f37ac9 289
okini3939 2:a3e0f7f37ac9 290 /* p26 is P2.0 */
okini3939 2:a3e0f7f37ac9 291 #define p26_SEL_MASK ~(3UL << 0)
okini3939 2:a3e0f7f37ac9 292 #define p26_SET_MASK (1UL << 0)
okini3939 2:a3e0f7f37ac9 293 #define p26_CLR_MASK ~(p26_SET_MASK)
okini3939 2:a3e0f7f37ac9 294 #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK
okini3939 2:a3e0f7f37ac9 295 #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK;
okini3939 2:a3e0f7f37ac9 296 #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK
okini3939 2:a3e0f7f37ac9 297 #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK
okini3939 2:a3e0f7f37ac9 298 #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK)
okini3939 2:a3e0f7f37ac9 299 #define p26_IS_CLR !(p26_IS_SET)
okini3939 2:a3e0f7f37ac9 300 #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0)
okini3939 2:a3e0f7f37ac9 301
okini3939 2:a3e0f7f37ac9 302 /* p27 is P0.11 */
okini3939 2:a3e0f7f37ac9 303 #define p27_SEL_MASK ~(3UL << 22)
okini3939 2:a3e0f7f37ac9 304 #define p27_SET_MASK (1UL << 11)
okini3939 2:a3e0f7f37ac9 305 #define p27_CLR_MASK ~(p27_SET_MASK)
okini3939 2:a3e0f7f37ac9 306 #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK
okini3939 2:a3e0f7f37ac9 307 #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK;
okini3939 2:a3e0f7f37ac9 308 #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK
okini3939 2:a3e0f7f37ac9 309 #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK
okini3939 2:a3e0f7f37ac9 310 #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK)
okini3939 2:a3e0f7f37ac9 311 #define p27_IS_CLR !(p27_IS_SET)
okini3939 2:a3e0f7f37ac9 312 #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22)
okini3939 2:a3e0f7f37ac9 313
okini3939 2:a3e0f7f37ac9 314 /* p28 is P0.10 */
okini3939 2:a3e0f7f37ac9 315 #define p28_SEL_MASK ~(3UL << 20)
okini3939 2:a3e0f7f37ac9 316 #define p28_SET_MASK (1UL << 10)
okini3939 2:a3e0f7f37ac9 317 #define p28_CLR_MASK ~(p28_SET_MASK)
okini3939 2:a3e0f7f37ac9 318 #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK
okini3939 2:a3e0f7f37ac9 319 #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK;
okini3939 2:a3e0f7f37ac9 320 #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK
okini3939 2:a3e0f7f37ac9 321 #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK
okini3939 2:a3e0f7f37ac9 322 #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK)
okini3939 2:a3e0f7f37ac9 323 #define p28_IS_CLR !(p28_IS_SET)
okini3939 2:a3e0f7f37ac9 324 #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20)
okini3939 2:a3e0f7f37ac9 325
okini3939 2:a3e0f7f37ac9 326 /* p29 is P0.5 */
okini3939 2:a3e0f7f37ac9 327 #define p29_SEL_MASK ~(3UL << 10)
okini3939 2:a3e0f7f37ac9 328 #define p29_SET_MASK (1UL << 5)
okini3939 2:a3e0f7f37ac9 329 #define p29_CLR_MASK ~(p29_SET_MASK)
okini3939 2:a3e0f7f37ac9 330 #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK
okini3939 2:a3e0f7f37ac9 331 #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK;
okini3939 2:a3e0f7f37ac9 332 #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK
okini3939 2:a3e0f7f37ac9 333 #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK
okini3939 2:a3e0f7f37ac9 334 #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK)
okini3939 2:a3e0f7f37ac9 335 #define p29_IS_CLR !(p29_IS_SET)
okini3939 2:a3e0f7f37ac9 336 #define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET
okini3939 2:a3e0f7f37ac9 337 #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10)
okini3939 2:a3e0f7f37ac9 338
okini3939 2:a3e0f7f37ac9 339 /* p30 is P0.4 */
okini3939 2:a3e0f7f37ac9 340 #define p30_SEL_MASK ~(3UL << 8)
okini3939 2:a3e0f7f37ac9 341 #define p30_SET_MASK (1UL << 4)
okini3939 2:a3e0f7f37ac9 342 #define p30_CLR_MASK ~(p30_SET_MASK)
okini3939 2:a3e0f7f37ac9 343 #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK
okini3939 2:a3e0f7f37ac9 344 #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK;
okini3939 2:a3e0f7f37ac9 345 #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK
okini3939 2:a3e0f7f37ac9 346 #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK
okini3939 2:a3e0f7f37ac9 347 #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK)
okini3939 2:a3e0f7f37ac9 348 #define p30_IS_CLR !(p30_IS_SET)
okini3939 2:a3e0f7f37ac9 349 #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8)
okini3939 2:a3e0f7f37ac9 350
okini3939 2:a3e0f7f37ac9 351 /* The following definitions are for the four Mbed LEDs.
okini3939 2:a3e0f7f37ac9 352 LED1 = P1.18
okini3939 2:a3e0f7f37ac9 353 LED2 = P1.20
okini3939 2:a3e0f7f37ac9 354 LED3 = P1.21
okini3939 2:a3e0f7f37ac9 355 LED4 = P1.23 */
okini3939 2:a3e0f7f37ac9 356
okini3939 2:a3e0f7f37ac9 357 #define P1_18_SEL_MASK ~(3UL << 4)
okini3939 2:a3e0f7f37ac9 358 #define P1_18_SET_MASK (1UL << 18)
okini3939 2:a3e0f7f37ac9 359 #define P1_18_CLR_MASK ~(P1_18_SET_MASK)
okini3939 2:a3e0f7f37ac9 360 #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK
okini3939 2:a3e0f7f37ac9 361 #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK;
okini3939 2:a3e0f7f37ac9 362 #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK
okini3939 2:a3e0f7f37ac9 363 #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK
okini3939 2:a3e0f7f37ac9 364 #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK)
okini3939 2:a3e0f7f37ac9 365 #define P1_18_IS_CLR !(P1_18_IS_SET)
okini3939 2:a3e0f7f37ac9 366 #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT
okini3939 2:a3e0f7f37ac9 367 #define LED1_ON P1_18_SET
okini3939 2:a3e0f7f37ac9 368 #define LED1_OFF P1_18_CLR
okini3939 2:a3e0f7f37ac9 369 #define LED1_IS_ON P1_18_IS_SET
okini3939 2:a3e0f7f37ac9 370 #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON
okini3939 2:a3e0f7f37ac9 371
okini3939 2:a3e0f7f37ac9 372 #define P1_20_SEL_MASK ~(3UL << 8)
okini3939 2:a3e0f7f37ac9 373 #define P1_20_SET_MASK (1UL << 20)
okini3939 2:a3e0f7f37ac9 374 #define P1_20_CLR_MASK ~(P1_20_SET_MASK)
okini3939 2:a3e0f7f37ac9 375 #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK
okini3939 2:a3e0f7f37ac9 376 #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK;
okini3939 2:a3e0f7f37ac9 377 #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK
okini3939 2:a3e0f7f37ac9 378 #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK
okini3939 2:a3e0f7f37ac9 379 #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK)
okini3939 2:a3e0f7f37ac9 380 #define P1_20_IS_CLR !(P1_20_IS_SET)
okini3939 2:a3e0f7f37ac9 381 #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT
okini3939 2:a3e0f7f37ac9 382 #define LED2_ON P1_20_SET
okini3939 2:a3e0f7f37ac9 383 #define LED2_OFF P1_20_CLR
okini3939 2:a3e0f7f37ac9 384 #define LED2_IS_ON P1_20_IS_SET
okini3939 2:a3e0f7f37ac9 385 #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON
okini3939 2:a3e0f7f37ac9 386
okini3939 2:a3e0f7f37ac9 387 #define P1_21_SEL_MASK ~(3UL << 10)
okini3939 2:a3e0f7f37ac9 388 #define P1_21_SET_MASK (1UL << 21)
okini3939 2:a3e0f7f37ac9 389 #define P1_21_CLR_MASK ~(P1_21_SET_MASK)
okini3939 2:a3e0f7f37ac9 390 #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK
okini3939 2:a3e0f7f37ac9 391 #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK;
okini3939 2:a3e0f7f37ac9 392 #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK
okini3939 2:a3e0f7f37ac9 393 #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK
okini3939 2:a3e0f7f37ac9 394 #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK)
okini3939 2:a3e0f7f37ac9 395 #define P1_21_IS_CLR !(P1_21_IS_SET)
okini3939 2:a3e0f7f37ac9 396 #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT
okini3939 2:a3e0f7f37ac9 397 #define LED3_ON P1_21_SET
okini3939 2:a3e0f7f37ac9 398 #define LED3_OFF P1_21_CLR
okini3939 2:a3e0f7f37ac9 399 #define LED3_IS_ON P1_21_IS_SET
okini3939 2:a3e0f7f37ac9 400 #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON
okini3939 2:a3e0f7f37ac9 401
okini3939 2:a3e0f7f37ac9 402 #define P1_23_SEL_MASK ~(3UL << 14)
okini3939 2:a3e0f7f37ac9 403 #define P1_23_SET_MASK (1UL << 23)
okini3939 2:a3e0f7f37ac9 404 #define P1_23_CLR_MASK ~(P1_23_SET_MASK)
okini3939 2:a3e0f7f37ac9 405 #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK
okini3939 2:a3e0f7f37ac9 406 #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK;
okini3939 2:a3e0f7f37ac9 407 #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK
okini3939 2:a3e0f7f37ac9 408 #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK
okini3939 2:a3e0f7f37ac9 409 #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK)
okini3939 2:a3e0f7f37ac9 410 #define P1_23_IS_CLR !(P1_23_IS_SET)
okini3939 2:a3e0f7f37ac9 411 #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT
okini3939 2:a3e0f7f37ac9 412 #define LED4_ON P1_23_SET
okini3939 2:a3e0f7f37ac9 413 #define LED4_OFF P1_23_CLR
okini3939 2:a3e0f7f37ac9 414 #define LED4_IS_ON P1_23_IS_SET
okini3939 2:a3e0f7f37ac9 415 #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON
okini3939 2:a3e0f7f37ac9 416
okini3939 2:a3e0f7f37ac9 417 #endif
okini3939 2:a3e0f7f37ac9 418