Suga koubou / IAP

supported LPC11U35

Fork of IAP by Tedd OKANO

IAP.cpp@7:c8bf974ecb33, 2015-03-10 (annotated)

Committer:
okano
Date:
Tue Mar 10 04:19:23 2015 +0000
Revision:
7:c8bf974ecb33
Parent:
6:f794a51897b8
Parent:
4:cee1a2a734c9 
merged with pull requests

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okano 0:ada7fb504504 1 /** IAP : internal Flash memory access library
okano 0:ada7fb504504 2 *
okano 2:17f3464672c1 3 * The internal Flash memory access is described in the LPC1768 and LPC11U24 usermanual.
okano 0:ada7fb504504 4 * http://www.nxp.com/documents/user_manual/UM10360.pdf
okano 0:ada7fb504504 5 * http://www.nxp.com/documents/user_manual/UM10462.pdf
okano 0:ada7fb504504 6 *
okano 0:ada7fb504504 7 * LPC1768 --
okano 0:ada7fb504504 8 * Chapter 2: "LPC17xx Memory map"
okano 0:ada7fb504504 9 * Chapter 32: "LPC17xx Flash memory interface and programming"
okano 0:ada7fb504504 10 * refering Rev. 01 - 4 January 2010
okano 2:17f3464672c1 11 *
okano 0:ada7fb504504 12 * LPC11U24 --
okano 0:ada7fb504504 13 * Chapter 2: "LPC11Uxx Memory mapping"
okano 0:ada7fb504504 14 * Chapter 20: "LPC11Uxx Flash programming firmware"
okano 0:ada7fb504504 15 * refering Rev. 03 - 16 July 2012
okano 2:17f3464672c1 16 *
okano 0:ada7fb504504 17 * Released under the MIT License: http://mbed.org/license/mit
okano 0:ada7fb504504 18 *
okano 0:ada7fb504504 19 * revision 1.0 09-Mar-2010 1st release
okano 0:ada7fb504504 20 * revision 1.1 12-Mar-2010 chaged: to make possible to reserve flash area for user
okano 0:ada7fb504504 21 * it can be set by USER_FLASH_AREA_START and USER_FLASH_AREA_SIZE in IAP.h
okano 1:ff906ad52cf9 22 * revision 2.0 26-Nov-2012 LPC11U24 code added
okano 1:ff906ad52cf9 23 * revision 2.1 26-Nov-2012 EEPROM access code imported from Suga koubou san's (http://mbed.org/users/okini3939/) library
okano 1:ff906ad52cf9 24 * http://mbed.org/users/okini3939/code/M0_EEPROM_test/
okano 4:cee1a2a734c9 25 * revision 3.0 09-Jan-2015 LPC812 and LPC824 support added
okano 4:cee1a2a734c9 26 * revision 3.1 13-Jan-2015 LPC1114 support added
okano 4:cee1a2a734c9 27 * revision 3.1.1 16-Jan-2015 Target MCU name changed for better compatibility across the platforms
okano 0:ada7fb504504 28 */
okano 0:ada7fb504504 29
okano 0:ada7fb504504 30 #include "mbed.h"
okano 0:ada7fb504504 31 #include "IAP.h"
okano 0:ada7fb504504 32
okano 0:ada7fb504504 33 #define USER_FLASH_AREA_START_STR( x ) STR( x )
okano 0:ada7fb504504 34 #define STR( x ) #x
okano 0:ada7fb504504 35
okano 0:ada7fb504504 36 unsigned char user_area[ USER_FLASH_AREA_SIZE ] __attribute__((section( ".ARM.__at_" USER_FLASH_AREA_START_STR( USER_FLASH_AREA_START ) ), zero_init));
okano 0:ada7fb504504 37
okano 0:ada7fb504504 38 /*
okano 0:ada7fb504504 39 * Reserve of flash area is explained by Igor. Please refer next URL
okano 0:ada7fb504504 40 * http://mbed.org/users/okano/notebook/iap-in-application-programming-internal-flash-eras/?page=1#comment-271
okano 0:ada7fb504504 41 */
okano 2:17f3464672c1 42
okano 0:ada7fb504504 43 //unsigned char user_area[ size ] __attribute__((section(".ARM.__at_0x78000"), zero_init));
okano 0:ada7fb504504 44
okano 0:ada7fb504504 45 /*
okano 0:ada7fb504504 46 * IAP command codes
okano 0:ada7fb504504 47 * Table 589. "IAP Command Summary", Chapter 8. "IAP commands", usermanual
okano 0:ada7fb504504 48 */
okano 0:ada7fb504504 49
okano 2:17f3464672c1 50 enum command_code {
okano 2:17f3464672c1 51 IAPCommand_Prepare_sector_for_write_operation = 50,
okano 2:17f3464672c1 52 IAPCommand_Copy_RAM_to_Flash,
okano 2:17f3464672c1 53 IAPCommand_Erase_sector,
okano 2:17f3464672c1 54 IAPCommand_Blank_check_sector,
okano 2:17f3464672c1 55 IAPCommand_Read_part_ID,
okano 2:17f3464672c1 56 IAPCommand_Read_Boot_Code_version,
okano 2:17f3464672c1 57 IAPCommand_Compare,
okano 2:17f3464672c1 58 IAPCommand_Reinvoke_ISP,
okano 2:17f3464672c1 59 IAPCommand_Read_device_serial_number,
okano 4:cee1a2a734c9 60 #if defined(TARGET_LPC11UXX)
okano 2:17f3464672c1 61 IAPCommand_EEPROM_Write = 61,
okano 2:17f3464672c1 62 IAPCommand_EEPROM_Read,
okano 4:cee1a2a734c9 63 #elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X)
okano 2:17f3464672c1 64 IAPCommand_Erase_page = 59,
okano 1:ff906ad52cf9 65 #endif
okano 2:17f3464672c1 66 };
okano 0:ada7fb504504 67
jaerts 5:7484398d50ea 68 int IAP::reinvoke_isp( void ) {
jaerts 5:7484398d50ea 69 __disable_irq();
jaerts 5:7484398d50ea 70
jaerts 5:7484398d50ea 71 IAP_command[ 0 ] = IAPCommand_Reinvoke_ISP;
jaerts 5:7484398d50ea 72
jaerts 5:7484398d50ea 73 iap_entry( IAP_command, IAP_result );
jaerts 5:7484398d50ea 74
jaerts 5:7484398d50ea 75 return ( (int)IAP_result[ 0 ] );
jaerts 5:7484398d50ea 76 }
jaerts 5:7484398d50ea 77
okano 0:ada7fb504504 78 /** Read part identification number
okano 0:ada7fb504504 79 *
okano 0:ada7fb504504 80 * @return device ID
okano 0:ada7fb504504 81 * @see read_serial()
okano 0:ada7fb504504 82 */
okano 2:17f3464672c1 83 int IAP::read_ID( void )
okano 2:17f3464672c1 84 {
okano 2:17f3464672c1 85 IAP_command[ 0 ] = IAPCommand_Read_part_ID;
okano 0:ada7fb504504 86
okano 0:ada7fb504504 87 iap_entry( IAP_command, IAP_result );
okano 2:17f3464672c1 88
okano 0:ada7fb504504 89 // return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 90 return ( (int)IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
okano 0:ada7fb504504 91 }
okano 0:ada7fb504504 92
sam_grove 6:f794a51897b8 93 int *IAP::read_serial( void ) {
okano 2:17f3464672c1 94 IAP_command[ 0 ] = IAPCommand_Read_device_serial_number;
okano 0:ada7fb504504 95
okano 2:17f3464672c1 96 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 97
okano 0:ada7fb504504 98 // return ( (int)IAP_result[ 0 ] );
sam_grove 6:f794a51897b8 99 return ( (int *)&IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
okano 0:ada7fb504504 100 }
okano 0:ada7fb504504 101
okano 2:17f3464672c1 102 int IAP::blank_check( int start, int end )
okano 2:17f3464672c1 103 {
okano 0:ada7fb504504 104 IAP_command[ 0 ] = IAPCommand_Blank_check_sector;
okano 0:ada7fb504504 105 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 0:ada7fb504504 106 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number)
okano 0:ada7fb504504 107
okano 0:ada7fb504504 108 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 109
okano 0:ada7fb504504 110 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 111 }
okano 0:ada7fb504504 112
okano 2:17f3464672c1 113 int IAP::erase( int start, int end )
okano 2:17f3464672c1 114 {
okano 0:ada7fb504504 115 IAP_command[ 0 ] = IAPCommand_Erase_sector;
okano 0:ada7fb504504 116 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 0:ada7fb504504 117 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number)
okano 0:ada7fb504504 118 IAP_command[ 3 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz
okano 0:ada7fb504504 119
okano 0:ada7fb504504 120 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 121
okano 0:ada7fb504504 122 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 123 }
okano 0:ada7fb504504 124
okano 2:17f3464672c1 125 int IAP::prepare( int start, int end )
okano 2:17f3464672c1 126 {
okano 0:ada7fb504504 127 IAP_command[ 0 ] = IAPCommand_Prepare_sector_for_write_operation;
okano 0:ada7fb504504 128 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 0:ada7fb504504 129 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number).
okano 2:17f3464672c1 130
okano 0:ada7fb504504 131 iap_entry( IAP_command, IAP_result );
okano 2:17f3464672c1 132
okano 0:ada7fb504504 133 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 134 }
okano 0:ada7fb504504 135
okano 2:17f3464672c1 136 int IAP::write( char *source_addr, char *target_addr, int size )
okano 2:17f3464672c1 137 {
okano 0:ada7fb504504 138 IAP_command[ 0 ] = IAPCommand_Copy_RAM_to_Flash;
okano 0:ada7fb504504 139 IAP_command[ 1 ] = (unsigned int)target_addr; // Destination flash address where data bytes are to be written. This address should be a 256 byte boundary.
okano 0:ada7fb504504 140 IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary.
okano 0:ada7fb504504 141 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 0:ada7fb504504 142 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
okano 0:ada7fb504504 143
okano 0:ada7fb504504 144 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 145
okano 0:ada7fb504504 146 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 147 }
okano 0:ada7fb504504 148
okano 2:17f3464672c1 149 int IAP::compare( char *source_addr, char *target_addr, int size )
okano 2:17f3464672c1 150 {
okano 0:ada7fb504504 151 IAP_command[ 0 ] = IAPCommand_Compare;
okano 0:ada7fb504504 152 IAP_command[ 1 ] = (unsigned int)target_addr; // Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 153 IAP_command[ 2 ] = (unsigned int)source_addr; // Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 154 IAP_command[ 3 ] = size; // Number of bytes to be compared; should be a multiple of 4.
okano 0:ada7fb504504 155
okano 0:ada7fb504504 156 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 157
okano 0:ada7fb504504 158 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 159 }
okano 0:ada7fb504504 160
okano 2:17f3464672c1 161 int IAP::read_BootVer(void)
okano 2:17f3464672c1 162 {
okano 0:ada7fb504504 163 IAP_command[0] = IAPCommand_Read_Boot_Code_version;
okano 0:ada7fb504504 164 IAP_result[1] = 0; // not sure if in high or low bits.
okano 0:ada7fb504504 165 iap_entry(IAP_command, IAP_result);
okano 0:ada7fb504504 166 return ((int)IAP_result[1]);
okano 0:ada7fb504504 167 }
okano 0:ada7fb504504 168
okano 0:ada7fb504504 169 char * IAP::reserved_flash_area_start( void )
okano 0:ada7fb504504 170 {
okano 0:ada7fb504504 171 return ( (char *)USER_FLASH_AREA_START );
okano 0:ada7fb504504 172 }
okano 0:ada7fb504504 173
okano 0:ada7fb504504 174 int IAP::reserved_flash_area_size( void )
okano 0:ada7fb504504 175 {
okano 0:ada7fb504504 176 return ( USER_FLASH_AREA_SIZE );
okano 0:ada7fb504504 177 }
okano 0:ada7fb504504 178
okano 4:cee1a2a734c9 179 #if defined(TARGET_LPC11UXX)
okano 2:17f3464672c1 180
okano 2:17f3464672c1 181 int IAP::write_eeprom( char *source_addr, char *target_addr, int size )
okano 2:17f3464672c1 182 {
okano 1:ff906ad52cf9 183 IAP_command[ 0 ] = IAPCommand_EEPROM_Write;
okano 1:ff906ad52cf9 184 IAP_command[ 1 ] = (unsigned int)target_addr; // Destination EEPROM address where data bytes are to be written. This address should be a 256 byte boundary.
okano 1:ff906ad52cf9 185 IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary.
okano 1:ff906ad52cf9 186 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 1:ff906ad52cf9 187 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
okano 2:17f3464672c1 188
okano 1:ff906ad52cf9 189 iap_entry( IAP_command, IAP_result );
okano 2:17f3464672c1 190
okano 1:ff906ad52cf9 191 return ( (int)IAP_result[ 0 ] );
okano 1:ff906ad52cf9 192 }
okano 2:17f3464672c1 193
okano 2:17f3464672c1 194 int IAP::read_eeprom( char *source_addr, char *target_addr, int size )
okano 2:17f3464672c1 195 {
okano 1:ff906ad52cf9 196 IAP_command[ 0 ] = IAPCommand_EEPROM_Read;
okano 1:ff906ad52cf9 197 IAP_command[ 1 ] = (unsigned int)source_addr; // Source EEPROM address from which data bytes are to be read. This address should be a word boundary.
okano 1:ff906ad52cf9 198 IAP_command[ 2 ] = (unsigned int)target_addr; // Destination RAM address where data bytes are to be written. This address should be a 256 byte boundary.
okano 1:ff906ad52cf9 199 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 1:ff906ad52cf9 200 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
okano 2:17f3464672c1 201
okano 1:ff906ad52cf9 202 iap_entry( IAP_command, IAP_result );
okano 2:17f3464672c1 203
okano 1:ff906ad52cf9 204 return ( (int)IAP_result[ 0 ] );
okano 1:ff906ad52cf9 205 }
okano 2:17f3464672c1 206
okano 4:cee1a2a734c9 207 #elif defined(TARGET_LPC81X) || defined(TARGET_LPC82X)
okano 2:17f3464672c1 208
okano 2:17f3464672c1 209 int IAP::erase_page( int start, int end )
okano 2:17f3464672c1 210 {
okano 2:17f3464672c1 211 IAP_command[ 0 ] = IAPCommand_Erase_page;
okano 2:17f3464672c1 212 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 2:17f3464672c1 213 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number)
okano 2:17f3464672c1 214 IAP_command[ 3 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz
okano 2:17f3464672c1 215
okano 2:17f3464672c1 216 iap_entry( IAP_command, IAP_result );
okano 2:17f3464672c1 217
okano 2:17f3464672c1 218 return ( (int)IAP_result[ 0 ] );
okano 2:17f3464672c1 219 }
okano 2:17f3464672c1 220
okano 1:ff906ad52cf9 221 #endif