Bryan and Naved Debub monitor

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Show/hide line numbers ADC_input.cpp Source File

ADC_input.cpp

00001 /**----------------------------------------------------------------------------
00002  *
00003  *            \file frequency_detector.cpp
00004 --                                                                           --
00005 --              ECEN 5803 Mastering Embedded System Architecture             --
00006 --                  Project 1 Module 4                                       --
00007 --                Microcontroller Firmware                                   --
00008 --                      frequency_detector.cpp                                           --
00009 --                                                                           --
00010 -------------------------------------------------------------------------------
00011 --
00012 --  Designed for:  University of Colorado at Boulder
00013 --                
00014 --                
00015 --  Designed by:  Tim Scherr
00016 --  Revised by:  Naved Maududi and Bryan Cisneros 
00017 -- 
00018 -- Version: 2.1
00019 -- Date of current revision:  2017-09-25   
00020 -- Target Microcontroller: Freescale MKL25ZVMT4 
00021 -- Tools used:  ARM mbed compiler
00022 --              ARM mbed SDK
00023 --              Freescale FRDM-KL25Z Freedom Board
00024 --               
00025 --               
00026    Functional Description:  
00027    This file contains code that takes in quasi-sine wave ADC inputs from the flow meter
00028      From the ADC inputs, it calculates the frequency of that sine wave. The frequency is 
00029      important in determining the flow rate and velocity for the flowmeter that are outputed
00030      to the display. 
00031 -- 
00032 --      Copyright (c) 2015 Tim Scherr  All rights reserved.
00033 */
00034 
00035 
00036 #include "shared.h" 
00037 
00038 
00039 PinName const ch0 = PTB0;  // channel 0 (PTB0) to A/D pin VREFL
00040 PinName const ch1 = PTB1; // channel 1 (PTB1) to J10_4 a virtual vortex frequency input,
00041 PinName const ch2 = PTB2; // channel 2 (PTB2) to an actual internal TempSensor
00042     
00043 #define ADC0_CFG1 (ADC0->CFG1)
00044 #define ADC0_CFG2 (ADC0->CFG2)
00045 #define ADC0_SC1A (ADC0->SC1[0]) // ADC0 to SC1A
00046 #define ADC0_SC3 (ADC0->SC3)
00047 #define SIM_SCGC6 (SIM->SCGC6)
00048 #define CHANNEL_0               (0U)
00049 #define CHANNEL_1               (1U)
00050 #define CHANNEL_2               (2U)
00051 
00052 AnalogIn Vref_low(ch0);
00053 
00054 AnalogIn vortex_frequency(ch1);
00055 
00056 AnalogIn TempSensor(ch2);
00057 
00058 
00059 void adc_calibration(void){
00060     
00061         // Enable clocks
00062     SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;   // ADC 0 clock
00063 
00064     // Configure ADC
00065     ADC0_CFG1 = 0; // Reset register
00066     
00067 
00068                  
00069     ADC0_CFG1 |= (ADC_CFG1_MODE(0)|   // 8 bit mode
00070                  ADC_CFG1_ADICLK(0)|   // Input Bus Clock for calibration
00071                  ADC_CFG1_ADIV(3));  // Long time sample configuration
00072                  
00073    ADC0_CFG1 = 0 & ADC_CFG1_ADLPC_MASK; // normal power configuration
00074    ADC0_CFG1 = 1 & ADC_CFG1_ADLSMP_MASK; // Long time sample configuration
00075 
00076     
00077   ADC0_CFG2 = 0 & ADC_CFG2_ADHSC_MASK; // 1 High-speed conversion sequence, 0 for normal coversion, zero as sampling is 10 usec, bus clock is good enought
00078   ADC0_CFG2 =  0 & ADC_CFG2_ADLSTS_MASK;     // Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
00079   ADC0_CFG2 =   0 & ADC_CFG2_ADACKEN_MASK;     // Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. low power configuration
00080     
00081 
00082 
00083     ADC0_SC3 = 1 & ADC_SC3_AVGE_MASK; // 1 High-speed conversion sequence, for calibration
00084     ADC0_SC3  = 3 & ADC_SC3_AVGS_MASK;      // Average of 32 samples, for calibration purposes
00085     ADC0_SC3 = 1 & ADC_SC3_CAL_MASK; // set to 1 for calibration of the ADC prior to completing conversions
00086     
00087   uint16_t PG_calibration = 0; //Initialize or clear a 16-bit variable in RAM.
00088     uint16_t MG_calibration = 0; //Initialize or clear a 16-bit variable in RAM.
00089     
00090     PG_calibration = (ADC0->CLP0)+(ADC0->CLP1)+(ADC0->CLP2)+(ADC0->CLP3)+(ADC0->CLP4)+(ADC0->CLPS); // Add the plus-side calibration results to the variable
00091     PG_calibration = PG_calibration/2; // Divide the variable by two
00092     PG_calibration = (PG_calibration & 0xFF00); //Set the MSB of the variable.
00093     ADC0->PG = (ADC0->CLP0)+PG_calibration; //Store the value in the plus-side gain calibration register PG.
00094     
00095     MG_calibration = (ADC0->CLM0)+(ADC0->CLM1)+(ADC0->CLM2)+(ADC0->CLM3)+(ADC0->CLM4)+(ADC0->CLMS); // Add the minus-side calibration results to the variable
00096     MG_calibration = MG_calibration/2; //Divide the variable by two
00097     MG_calibration = (MG_calibration & 0xFF00); //Set the MSB of the variable.
00098     ADC0->MG = (ADC0->CLM0)+MG_calibration; //Store the value in the plus-side gain calibration register MG.
00099     // END OF CALIBRATION
00100 }
00101 
00102 
00103 
00104 
00105 void read_ADC(uint8_t channel)
00106 {
00107     if (channel==CHANNEL_0){
00108         // Enable clocks
00109     SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;   // ADC 0 clock
00110 
00111     // Configure ADC
00112     ADC0_CFG1 = 0; // Reset register
00113 
00114     ADC0_CFG1 |= (ADC_CFG1_MODE(0)|   // 8 bit mode
00115                   ADC_CFG1_ADICLK(0)|   // Input Bus Clock (20-25 MHz out of reset (FEI mode))
00116                   ADC_CFG1_ADIV(0)); // Clock divide by 1
00117     ADC0_CFG1 = 0 & ADC_CFG1_ADLPC_MASK;   // normal power configuration
00118     ADC0_CFG1  = 1 & ADC_CFG1_ADLSMP_MASK;  // Long time sample configuration
00119     
00120    ADC0_CFG2 = 0 & ADC_CFG2_ADHSC_MASK; // 1 High-speed conversion sequence, 0 for normal coversion, zero as sampling is 10 usec, bus clock is good enought
00121    ADC0_CFG2 = 0 & ADC_CFG2_ADLSTS_MASK;     // Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
00122    ADC0_CFG2 = 0 & ADC_CFG2_ADACKEN_MASK;     // Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. low power configuration
00123     
00124 
00125   ADC0_SC3 = 0 & ADC_SC3_ADCO_MASK; // set to 1 for continuious conversion, 0 for only 1 set of conversions
00126   
00127   ADC0_SC1A = 13 & ADC_SC1_ADCH_MASK; // ADC0_SE8 that is connected to PTB0
00128   ADC0_SC1A = 0& ADC_SC1_DIFF_MASK; //0 Single-ended conversions and input channels are selected.
00129                              
00130     Vrefl = (Vref_low.read_u16());
00131         
00132     } else if (channel==CHANNEL_1){
00133         
00134         // Enable clocks
00135     SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;   // ADC 0 clock
00136 
00137     // Configure ADC
00138     ADC0_CFG1 = 0; // Reset register
00139     
00140    ADC0_CFG1 |= (ADC_CFG1_MODE(3)|   // 8 bit mode
00141                   ADC_CFG1_ADICLK(0)|   // Input Bus Clock (20-25 MHz out of reset (FEI mode))
00142                   ADC_CFG1_ADIV(0)); // Clock divide by 1
00143     ADC0_CFG1 = 0 & ADC_CFG1_ADLPC_MASK;   // normal power configuration
00144     ADC0_CFG1  = 1 & ADC_CFG1_ADLSMP_MASK;  // Long time sample configuration
00145 
00146     
00147    ADC0_CFG2 = 0 & ADC_CFG2_ADHSC_MASK; // 1 High-speed conversion sequence, 0 for normal coversion, zero as sampling is 10 usec, bus clock is good enought
00148    ADC0_CFG2 = 0 & ADC_CFG2_ADLSTS_MASK;     // Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
00149    ADC0_CFG2 = 0 & ADC_CFG2_ADACKEN_MASK;     // Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. low power configuration
00150     
00151 
00152   ADC0_SC3 = 1 & ADC_SC3_ADCO_MASK; // set to 1 for continuious conversion, 0 for only 1 set of conversions
00153 
00154   ADC0_SC1A = 14 & ADC_SC1_ADCH_MASK; // ADC0_SE9 that is connected to PTB1
00155   ADC0_SC1A = 0 & ADC_SC1_DIFF_MASK; //0 Single-ended conversions and input channels are selected.
00156                               
00157     ADC_vortex_frequency_input = (vortex_frequency.read_u16());
00158         
00159     } else 
00160     {
00161         // Enable clocks
00162     SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;   // ADC 0 clock
00163 
00164     // Configure ADC
00165     ADC0_CFG1 = 0; // Reset register
00166     
00167    ADC0_CFG1 |= (ADC_CFG1_MODE(3)|   // 8 bit mode
00168                   ADC_CFG1_ADICLK(0)|   // Input Bus Clock (20-25 MHz out of reset (FEI mode))
00169                   ADC_CFG1_ADIV(0)); // Clock divide by 1
00170     ADC0_CFG1 = 0 & ADC_CFG1_ADLPC_MASK;   // normal power configuration
00171     ADC0_CFG1  = 1 & ADC_CFG1_ADLSMP_MASK;  // Long time sample configuration
00172 
00173     
00174    ADC0_CFG2 = 0 & ADC_CFG2_ADHSC_MASK; // 1 High-speed conversion sequence, 0 for normal coversion, zero as sampling is 10 usec, bus clock is good enought
00175    ADC0_CFG2 = 0 & ADC_CFG2_ADLSTS_MASK;     // Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
00176    ADC0_CFG2 = 0 & ADC_CFG2_ADACKEN_MASK;     // Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. low power configuration
00177     
00178 
00179   ADC0_SC3 = 1 & ADC_SC3_ADCO_MASK; // set to 1 for continuious conversion, 0 for only 1 set of conversions
00180 
00181   ADC0_SC1A = 26 & ADC_SC1_ADCH_MASK; // temperature sensor (reading in value from internal sensor) V
00182   ADC0_SC1A = 0 & ADC_SC1_DIFF_MASK; //0 Single-ended conversions and input channels are selected.
00183                       
00184     Vtemp =  (TempSensor.read_u16());
00185     }
00186 
00187     
00188 }
00189 
00190