test
Dependencies: ad5422_arduino mbed LT1446 ADS1248-1 LM35-1 Flash FT813 PGA280_ADS1259
PerifConfig.h@1:5d28312892aa, 2020-06-22 (annotated)
- Committer:
- vitlog
- Date:
- Mon Jun 22 10:06:00 2020 +0000
- Revision:
- 1:5d28312892aa
- Child:
- 3:d4b106bf3a32
22.06.2020
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
vitlog | 1:5d28312892aa | 1 | #ifndef PERIFCONFIG_H |
vitlog | 1:5d28312892aa | 2 | #define PERIFCONFIG_H |
vitlog | 1:5d28312892aa | 3 | /*Это перенос с языка Си для PIC32 максимально безболезненно*/ |
vitlog | 1:5d28312892aa | 4 | #include "mbed.h" |
vitlog | 1:5d28312892aa | 5 | |
vitlog | 1:5d28312892aa | 6 | #ifdef __cplusplus |
vitlog | 1:5d28312892aa | 7 | extern "C" { |
vitlog | 1:5d28312892aa | 8 | #endif |
vitlog | 1:5d28312892aa | 9 | |
vitlog | 1:5d28312892aa | 10 | /*Моё начало*/ |
vitlog | 1:5d28312892aa | 11 | #define SYS_FREQ (180000000L) |
vitlog | 1:5d28312892aa | 12 | /*настройки для UART1*/ |
vitlog | 1:5d28312892aa | 13 | #define BAUD 115200 //бодрейт |
vitlog | 1:5d28312892aa | 14 | #define MYUBRG SYS_FREQ/16/BAUD-1 |
vitlog | 1:5d28312892aa | 15 | /*Конец*/ |
vitlog | 1:5d28312892aa | 16 | |
vitlog | 1:5d28312892aa | 17 | /*Переименование выводов SPI*/ |
vitlog | 1:5d28312892aa | 18 | #define MOSI1 mosi1 //MOSI настройка вывода SPI1 на выход (на всякий случай) |
vitlog | 1:5d28312892aa | 19 | #define MISO1 miso2 //MISO |
vitlog | 1:5d28312892aa | 20 | #define SCK1 sck1 //SCK |
vitlog | 1:5d28312892aa | 21 | /*Конец*/ |
vitlog | 1:5d28312892aa | 22 | |
vitlog | 1:5d28312892aa | 23 | /*Период таймера*/ |
vitlog | 1:5d28312892aa | 24 | #define PER 0.04 //с |
vitlog | 1:5d28312892aa | 25 | #define PERREG SYS_FREQ/8*PER-1 //25 fps |
vitlog | 1:5d28312892aa | 26 | #define PER2 0.00001 //10 мкс |
vitlog | 1:5d28312892aa | 27 | #define PERREG2 SYS_FREQ/8*PER2-1 // fps |
vitlog | 1:5d28312892aa | 28 | /*Конец*/ |
vitlog | 1:5d28312892aa | 29 | |
vitlog | 1:5d28312892aa | 30 | #ifndef CS |
vitlog | 1:5d28312892aa | 31 | #define CS Cs //чипселект |
vitlog | 1:5d28312892aa | 32 | #endif |
vitlog | 1:5d28312892aa | 33 | |
vitlog | 1:5d28312892aa | 34 | #define EN1 En1 //включить что-то |
vitlog | 1:5d28312892aa | 35 | |
vitlog | 1:5d28312892aa | 36 | #define ADR0 Adr0 |
vitlog | 1:5d28312892aa | 37 | #define ADR1 Adr1 |
vitlog | 1:5d28312892aa | 38 | #define ADR2 Adr2 |
vitlog | 1:5d28312892aa | 39 | |
vitlog | 1:5d28312892aa | 40 | #define RESET Reset |
vitlog | 1:5d28312892aa | 41 | #define CRDYA CrdyA //сигнал готовности с АЦП/ЦАП |
vitlog | 1:5d28312892aa | 42 | |
vitlog | 1:5d28312892aa | 43 | #define ADS1259_RESET Reset |
vitlog | 1:5d28312892aa | 44 | #define ADS1259_RDYA CrdyA |
vitlog | 1:5d28312892aa | 45 | #define MUX_AN10_IZM_RRG1 2 |
vitlog | 1:5d28312892aa | 46 | #define MUX_AN10_KLAPAN_RRG1 3 |
vitlog | 1:5d28312892aa | 47 | |
vitlog | 1:5d28312892aa | 48 | #define ADC_CH0 0 |
vitlog | 1:5d28312892aa | 49 | #define ADC_CH1 |
vitlog | 1:5d28312892aa | 50 | #define ADC_CH2 |
vitlog | 1:5d28312892aa | 51 | |
vitlog | 1:5d28312892aa | 52 | #define PGA280_TED 4 |
vitlog | 1:5d28312892aa | 53 | #define PGA280_RRG1 5 |
vitlog | 1:5d28312892aa | 54 | /*конец*/ |
vitlog | 1:5d28312892aa | 55 | |
vitlog | 1:5d28312892aa | 56 | /*Переопределение имени пинов*/ |
vitlog | 1:5d28312892aa | 57 | extern DigitalOut Cs,En1,Adr0,Adr1,Adr2,Reset,SCK,MOSI; |
vitlog | 1:5d28312892aa | 58 | extern DigitalIn CrdyA,MISO; |
vitlog | 1:5d28312892aa | 59 | /*Конец*/ |
vitlog | 1:5d28312892aa | 60 | extern SPI TED2; |
vitlog | 1:5d28312892aa | 61 | extern Serial UART; |
vitlog | 1:5d28312892aa | 62 | |
vitlog | 1:5d28312892aa | 63 | typedef union { |
vitlog | 1:5d28312892aa | 64 | struct { |
vitlog | 1:5d28312892aa | 65 | uint8_t |
vitlog | 1:5d28312892aa | 66 | adr0:1, |
vitlog | 1:5d28312892aa | 67 | adr1:1, |
vitlog | 1:5d28312892aa | 68 | adr2:1, |
vitlog | 1:5d28312892aa | 69 | :5; |
vitlog | 1:5d28312892aa | 70 | }; |
vitlog | 1:5d28312892aa | 71 | struct { |
vitlog | 1:5d28312892aa | 72 | uint8_t adr:3; |
vitlog | 1:5d28312892aa | 73 | uint8_t :5; |
vitlog | 1:5d28312892aa | 74 | }; |
vitlog | 1:5d28312892aa | 75 | } adress_t; |
vitlog | 1:5d28312892aa | 76 | extern adress_t adress; |
vitlog | 1:5d28312892aa | 77 | |
vitlog | 1:5d28312892aa | 78 | |
vitlog | 1:5d28312892aa | 79 | extern unsigned int counter; |
vitlog | 1:5d28312892aa | 80 | extern unsigned char str[32]; |
vitlog | 1:5d28312892aa | 81 | extern unsigned char in; //счетчик буфера прерываний |
vitlog | 1:5d28312892aa | 82 | //RING_buffer_t buf_1; //буфер данных |
vitlog | 1:5d28312892aa | 83 | |
vitlog | 1:5d28312892aa | 84 | |
vitlog | 1:5d28312892aa | 85 | |
vitlog | 1:5d28312892aa | 86 | void GPIO_Init(void); |
vitlog | 1:5d28312892aa | 87 | void UART_Init(void); |
vitlog | 1:5d28312892aa | 88 | void UART1_Transmit(unsigned char data); |
vitlog | 1:5d28312892aa | 89 | void UDebugTransmit(unsigned char cData); |
vitlog | 1:5d28312892aa | 90 | void DebugString (unsigned char *sData, unsigned char sz); |
vitlog | 1:5d28312892aa | 91 | void UART_gets(char maxcount); |
vitlog | 1:5d28312892aa | 92 | void SPI1_MasterInitMode(char mode); |
vitlog | 1:5d28312892aa | 93 | void SPI1_SlaveInit(void); |
vitlog | 1:5d28312892aa | 94 | void SPI1MasterTransmitString(unsigned char *sData,unsigned int sz); //передать строку размером sz |
vitlog | 1:5d28312892aa | 95 | unsigned char SPI1MasterTransferByte(unsigned char cData);//отправить и считать байт |
vitlog | 1:5d28312892aa | 96 | unsigned char SPI1MasterReadByte(void); |
vitlog | 1:5d28312892aa | 97 | void TIMER32bit_Init(void); |
vitlog | 1:5d28312892aa | 98 | |
vitlog | 1:5d28312892aa | 99 | namespace std{}; |
vitlog | 1:5d28312892aa | 100 | using namespace std; |
vitlog | 1:5d28312892aa | 101 | |
vitlog | 1:5d28312892aa | 102 | #ifdef __cplusplus |
vitlog | 1:5d28312892aa | 103 | } |
vitlog | 1:5d28312892aa | 104 | #endif |
vitlog | 1:5d28312892aa | 105 | |
vitlog | 1:5d28312892aa | 106 | #endif /* PERIFCONFIG_H */ |