nguyen nam / Mbed 2 deprecated BSP-DISCO_F746NG

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Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.c@8:56384bddaba5, 2017-02-23 (annotated)

Committer:
Jerome Coutant
Date:
Thu Feb 23 14:14:09 2017 +0100
Revision:
8:56384bddaba5
Parent:
6:e1d9da7fe856 
STM32Cube_FW_F7_V1.6.0 BSP_DISCO_F746NG

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 6:e1d9da7fe856 1 /**
bcostm 6:e1d9da7fe856 2 ******************************************************************************
bcostm 6:e1d9da7fe856 3 * @file stm32746g_discovery_sdram.c
bcostm 6:e1d9da7fe856 4 * @author MCD Application Team
Jerome Coutant 8:56384bddaba5 5 * @version V2.0.0
Jerome Coutant 8:56384bddaba5 6 * @date 30-December-2016
bcostm 6:e1d9da7fe856 7 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
bcostm 6:e1d9da7fe856 8 * device mounted on STM32746G-Discovery board.
bcostm 6:e1d9da7fe856 9 @verbatim
bcostm 6:e1d9da7fe856 10 1. How To use this driver:
bcostm 6:e1d9da7fe856 11 --------------------------
bcostm 6:e1d9da7fe856 12 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
bcostm 6:e1d9da7fe856 13 on STM32746G-Discovery board.
bcostm 6:e1d9da7fe856 14 - This driver does not need a specific component driver for the SDRAM device
bcostm 6:e1d9da7fe856 15 to be included with.
bcostm 6:e1d9da7fe856 16
bcostm 6:e1d9da7fe856 17 2. Driver description:
bcostm 6:e1d9da7fe856 18 ---------------------
bcostm 6:e1d9da7fe856 19 + Initialization steps:
bcostm 6:e1d9da7fe856 20 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
bcostm 6:e1d9da7fe856 21 function includes the MSP layer hardware resources initialization and the
bcostm 6:e1d9da7fe856 22 FMC controller configuration to interface with the external SDRAM memory.
bcostm 6:e1d9da7fe856 23 o It contains the SDRAM initialization sequence to program the SDRAM external
bcostm 6:e1d9da7fe856 24 device using the function BSP_SDRAM_Initialization_sequence(). Note that this
bcostm 6:e1d9da7fe856 25 sequence is standard for all SDRAM devices, but can include some differences
bcostm 6:e1d9da7fe856 26 from a device to another. If it is the case, the right sequence should be
bcostm 6:e1d9da7fe856 27 implemented separately.
bcostm 6:e1d9da7fe856 28
bcostm 6:e1d9da7fe856 29 + SDRAM read/write operations
bcostm 6:e1d9da7fe856 30 o SDRAM external memory can be accessed with read/write operations once it is
bcostm 6:e1d9da7fe856 31 initialized.
bcostm 6:e1d9da7fe856 32 Read/write operation can be performed with AHB access using the functions
bcostm 6:e1d9da7fe856 33 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
bcostm 6:e1d9da7fe856 34 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
bcostm 6:e1d9da7fe856 35 o The AHB access is performed with 32-bit width transaction, the DMA transfer
bcostm 6:e1d9da7fe856 36 configuration is fixed at single (no burst) word transfer (see the
bcostm 6:e1d9da7fe856 37 SDRAM_MspInit() static function).
bcostm 6:e1d9da7fe856 38 o User can implement his own functions for read/write access with his desired
bcostm 6:e1d9da7fe856 39 configurations.
bcostm 6:e1d9da7fe856 40 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
bcostm 6:e1d9da7fe856 41 is called in IRQ handler file, to serve the generated interrupt once the DMA
bcostm 6:e1d9da7fe856 42 transfer is complete.
bcostm 6:e1d9da7fe856 43 o You can send a command to the SDRAM device in runtime using the function
bcostm 6:e1d9da7fe856 44 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
bcostm 6:e1d9da7fe856 45 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
bcostm 6:e1d9da7fe856 46
bcostm 6:e1d9da7fe856 47 @endverbatim
bcostm 6:e1d9da7fe856 48 ******************************************************************************
bcostm 6:e1d9da7fe856 49 * @attention
bcostm 6:e1d9da7fe856 50 *
bcostm 6:e1d9da7fe856 51 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bcostm 6:e1d9da7fe856 52 *
bcostm 6:e1d9da7fe856 53 * Redistribution and use in source and binary forms, with or without modification,
bcostm 6:e1d9da7fe856 54 * are permitted provided that the following conditions are met:
bcostm 6:e1d9da7fe856 55 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 6:e1d9da7fe856 56 * this list of conditions and the following disclaimer.
bcostm 6:e1d9da7fe856 57 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 6:e1d9da7fe856 58 * this list of conditions and the following disclaimer in the documentation
bcostm 6:e1d9da7fe856 59 * and/or other materials provided with the distribution.
bcostm 6:e1d9da7fe856 60 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 6:e1d9da7fe856 61 * may be used to endorse or promote products derived from this software
bcostm 6:e1d9da7fe856 62 * without specific prior written permission.
bcostm 6:e1d9da7fe856 63 *
bcostm 6:e1d9da7fe856 64 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 6:e1d9da7fe856 65 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 6:e1d9da7fe856 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 6:e1d9da7fe856 67 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 6:e1d9da7fe856 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 6:e1d9da7fe856 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 6:e1d9da7fe856 70 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 6:e1d9da7fe856 71 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 6:e1d9da7fe856 72 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 6:e1d9da7fe856 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 6:e1d9da7fe856 74 *
bcostm 6:e1d9da7fe856 75 ******************************************************************************
bcostm 6:e1d9da7fe856 76 */
bcostm 6:e1d9da7fe856 77
bcostm 6:e1d9da7fe856 78 /* Includes ------------------------------------------------------------------*/
bcostm 6:e1d9da7fe856 79 #include "stm32746g_discovery_sdram.h"
bcostm 6:e1d9da7fe856 80
bcostm 6:e1d9da7fe856 81 void wait_ms(int ms); // MBED to replace HAL_Delay function
bcostm 6:e1d9da7fe856 82
bcostm 6:e1d9da7fe856 83 /** @addtogroup BSP
bcostm 6:e1d9da7fe856 84 * @{
bcostm 6:e1d9da7fe856 85 */
bcostm 6:e1d9da7fe856 86
bcostm 6:e1d9da7fe856 87 /** @addtogroup STM32746G_DISCOVERY
bcostm 6:e1d9da7fe856 88 * @{
bcostm 6:e1d9da7fe856 89 */
bcostm 6:e1d9da7fe856 90
bcostm 6:e1d9da7fe856 91 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
bcostm 6:e1d9da7fe856 92 * @{
bcostm 6:e1d9da7fe856 93 */
bcostm 6:e1d9da7fe856 94
bcostm 6:e1d9da7fe856 95 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
bcostm 6:e1d9da7fe856 96 * @{
bcostm 6:e1d9da7fe856 97 */
bcostm 6:e1d9da7fe856 98 /**
bcostm 6:e1d9da7fe856 99 * @}
bcostm 6:e1d9da7fe856 100 */
bcostm 6:e1d9da7fe856 101
bcostm 6:e1d9da7fe856 102 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
bcostm 6:e1d9da7fe856 103 * @{
bcostm 6:e1d9da7fe856 104 */
bcostm 6:e1d9da7fe856 105 /**
bcostm 6:e1d9da7fe856 106 * @}
bcostm 6:e1d9da7fe856 107 */
bcostm 6:e1d9da7fe856 108
bcostm 6:e1d9da7fe856 109 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
bcostm 6:e1d9da7fe856 110 * @{
bcostm 6:e1d9da7fe856 111 */
bcostm 6:e1d9da7fe856 112 /**
bcostm 6:e1d9da7fe856 113 * @}
bcostm 6:e1d9da7fe856 114 */
bcostm 6:e1d9da7fe856 115
bcostm 6:e1d9da7fe856 116 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
bcostm 6:e1d9da7fe856 117 * @{
bcostm 6:e1d9da7fe856 118 */
bcostm 6:e1d9da7fe856 119 SDRAM_HandleTypeDef sdramHandle;
bcostm 6:e1d9da7fe856 120 static FMC_SDRAM_TimingTypeDef Timing;
bcostm 6:e1d9da7fe856 121 static FMC_SDRAM_CommandTypeDef Command;
bcostm 6:e1d9da7fe856 122 /**
bcostm 6:e1d9da7fe856 123 * @}
bcostm 6:e1d9da7fe856 124 */
bcostm 6:e1d9da7fe856 125
bcostm 6:e1d9da7fe856 126 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
bcostm 6:e1d9da7fe856 127 * @{
bcostm 6:e1d9da7fe856 128 */
bcostm 6:e1d9da7fe856 129 /**
bcostm 6:e1d9da7fe856 130 * @}
bcostm 6:e1d9da7fe856 131 */
bcostm 6:e1d9da7fe856 132
bcostm 6:e1d9da7fe856 133 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
bcostm 6:e1d9da7fe856 134 * @{
bcostm 6:e1d9da7fe856 135 */
bcostm 6:e1d9da7fe856 136
bcostm 6:e1d9da7fe856 137 /**
bcostm 6:e1d9da7fe856 138 * @brief Initializes the SDRAM device.
bcostm 6:e1d9da7fe856 139 * @retval SDRAM status
bcostm 6:e1d9da7fe856 140 */
bcostm 6:e1d9da7fe856 141 uint8_t BSP_SDRAM_Init(void)
bcostm 6:e1d9da7fe856 142 {
bcostm 6:e1d9da7fe856 143 static uint8_t sdramstatus = SDRAM_ERROR;
bcostm 6:e1d9da7fe856 144 /* SDRAM device configuration */
bcostm 6:e1d9da7fe856 145 sdramHandle.Instance = FMC_SDRAM_DEVICE;
bcostm 6:e1d9da7fe856 146
bcostm 6:e1d9da7fe856 147 /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
bcostm 6:e1d9da7fe856 148 Timing.LoadToActiveDelay = 2;
bcostm 6:e1d9da7fe856 149 Timing.ExitSelfRefreshDelay = 7;
bcostm 6:e1d9da7fe856 150 Timing.SelfRefreshTime = 4;
bcostm 6:e1d9da7fe856 151 Timing.RowCycleDelay = 7;
bcostm 6:e1d9da7fe856 152 Timing.WriteRecoveryTime = 2;
bcostm 6:e1d9da7fe856 153 Timing.RPDelay = 2;
bcostm 6:e1d9da7fe856 154 Timing.RCDDelay = 2;
bcostm 6:e1d9da7fe856 155
bcostm 6:e1d9da7fe856 156 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
bcostm 6:e1d9da7fe856 157 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
bcostm 6:e1d9da7fe856 158 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
bcostm 6:e1d9da7fe856 159 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
bcostm 6:e1d9da7fe856 160 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
bcostm 6:e1d9da7fe856 161 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
bcostm 6:e1d9da7fe856 162 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
bcostm 6:e1d9da7fe856 163 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
bcostm 6:e1d9da7fe856 164 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
bcostm 6:e1d9da7fe856 165 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
bcostm 6:e1d9da7fe856 166
bcostm 6:e1d9da7fe856 167 /* SDRAM controller initialization */
bcostm 6:e1d9da7fe856 168
bcostm 6:e1d9da7fe856 169 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
bcostm 6:e1d9da7fe856 170
bcostm 6:e1d9da7fe856 171 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
bcostm 6:e1d9da7fe856 172 {
bcostm 6:e1d9da7fe856 173 sdramstatus = SDRAM_ERROR;
bcostm 6:e1d9da7fe856 174 }
bcostm 6:e1d9da7fe856 175 else
bcostm 6:e1d9da7fe856 176 {
bcostm 6:e1d9da7fe856 177 sdramstatus = SDRAM_OK;
bcostm 6:e1d9da7fe856 178 }
bcostm 6:e1d9da7fe856 179
bcostm 6:e1d9da7fe856 180 /* SDRAM initialization sequence */
bcostm 6:e1d9da7fe856 181 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
bcostm 6:e1d9da7fe856 182
bcostm 6:e1d9da7fe856 183 return sdramstatus;
bcostm 6:e1d9da7fe856 184 }
bcostm 6:e1d9da7fe856 185
bcostm 6:e1d9da7fe856 186 /**
bcostm 6:e1d9da7fe856 187 * @brief DeInitializes the SDRAM device.
bcostm 6:e1d9da7fe856 188 * @retval SDRAM status
bcostm 6:e1d9da7fe856 189 */
bcostm 6:e1d9da7fe856 190 uint8_t BSP_SDRAM_DeInit(void)
bcostm 6:e1d9da7fe856 191 {
bcostm 6:e1d9da7fe856 192 static uint8_t sdramstatus = SDRAM_ERROR;
bcostm 6:e1d9da7fe856 193 /* SDRAM device de-initialization */
bcostm 6:e1d9da7fe856 194 sdramHandle.Instance = FMC_SDRAM_DEVICE;
bcostm 6:e1d9da7fe856 195
bcostm 6:e1d9da7fe856 196 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
bcostm 6:e1d9da7fe856 197 {
bcostm 6:e1d9da7fe856 198 sdramstatus = SDRAM_ERROR;
bcostm 6:e1d9da7fe856 199 }
bcostm 6:e1d9da7fe856 200 else
bcostm 6:e1d9da7fe856 201 {
bcostm 6:e1d9da7fe856 202 sdramstatus = SDRAM_OK;
bcostm 6:e1d9da7fe856 203 }
bcostm 6:e1d9da7fe856 204
bcostm 6:e1d9da7fe856 205 /* SDRAM controller de-initialization */
bcostm 6:e1d9da7fe856 206 BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
bcostm 6:e1d9da7fe856 207
bcostm 6:e1d9da7fe856 208 return sdramstatus;
bcostm 6:e1d9da7fe856 209 }
bcostm 6:e1d9da7fe856 210
bcostm 6:e1d9da7fe856 211 /**
bcostm 6:e1d9da7fe856 212 * @brief Programs the SDRAM device.
bcostm 6:e1d9da7fe856 213 * @param RefreshCount: SDRAM refresh counter value
bcostm 6:e1d9da7fe856 214 * @retval None
bcostm 6:e1d9da7fe856 215 */
bcostm 6:e1d9da7fe856 216 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
bcostm 6:e1d9da7fe856 217 {
bcostm 6:e1d9da7fe856 218 __IO uint32_t tmpmrd = 0;
bcostm 6:e1d9da7fe856 219
bcostm 6:e1d9da7fe856 220 /* Step 1: Configure a clock configuration enable command */
bcostm 6:e1d9da7fe856 221 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
bcostm 6:e1d9da7fe856 222 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 6:e1d9da7fe856 223 Command.AutoRefreshNumber = 1;
bcostm 6:e1d9da7fe856 224 Command.ModeRegisterDefinition = 0;
bcostm 6:e1d9da7fe856 225
bcostm 6:e1d9da7fe856 226 /* Send the command */
bcostm 6:e1d9da7fe856 227 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 6:e1d9da7fe856 228
bcostm 6:e1d9da7fe856 229 /* Step 2: Insert 100 us minimum delay */
bcostm 6:e1d9da7fe856 230 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
bcostm 6:e1d9da7fe856 231 //HAL_Delay(1); // MBED
bcostm 6:e1d9da7fe856 232 wait_ms(1); // MBED
bcostm 6:e1d9da7fe856 233
bcostm 6:e1d9da7fe856 234 /* Step 3: Configure a PALL (precharge all) command */
bcostm 6:e1d9da7fe856 235 Command.CommandMode = FMC_SDRAM_CMD_PALL;
bcostm 6:e1d9da7fe856 236 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 6:e1d9da7fe856 237 Command.AutoRefreshNumber = 1;
bcostm 6:e1d9da7fe856 238 Command.ModeRegisterDefinition = 0;
bcostm 6:e1d9da7fe856 239
bcostm 6:e1d9da7fe856 240 /* Send the command */
bcostm 6:e1d9da7fe856 241 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 6:e1d9da7fe856 242
bcostm 6:e1d9da7fe856 243 /* Step 4: Configure an Auto Refresh command */
bcostm 6:e1d9da7fe856 244 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
bcostm 6:e1d9da7fe856 245 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 6:e1d9da7fe856 246 Command.AutoRefreshNumber = 8;
bcostm 6:e1d9da7fe856 247 Command.ModeRegisterDefinition = 0;
bcostm 6:e1d9da7fe856 248
bcostm 6:e1d9da7fe856 249 /* Send the command */
bcostm 6:e1d9da7fe856 250 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 6:e1d9da7fe856 251
bcostm 6:e1d9da7fe856 252 /* Step 5: Program the external memory mode register */
bcostm 6:e1d9da7fe856 253 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
bcostm 6:e1d9da7fe856 254 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
bcostm 6:e1d9da7fe856 255 SDRAM_MODEREG_CAS_LATENCY_2 |\
bcostm 6:e1d9da7fe856 256 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
bcostm 6:e1d9da7fe856 257 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
bcostm 6:e1d9da7fe856 258
bcostm 6:e1d9da7fe856 259 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
bcostm 6:e1d9da7fe856 260 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 6:e1d9da7fe856 261 Command.AutoRefreshNumber = 1;
bcostm 6:e1d9da7fe856 262 Command.ModeRegisterDefinition = tmpmrd;
bcostm 6:e1d9da7fe856 263
bcostm 6:e1d9da7fe856 264 /* Send the command */
bcostm 6:e1d9da7fe856 265 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 6:e1d9da7fe856 266
bcostm 6:e1d9da7fe856 267 /* Step 6: Set the refresh rate counter */
bcostm 6:e1d9da7fe856 268 /* Set the device refresh rate */
bcostm 6:e1d9da7fe856 269 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
bcostm 6:e1d9da7fe856 270 }
bcostm 6:e1d9da7fe856 271
bcostm 6:e1d9da7fe856 272 /**
bcostm 6:e1d9da7fe856 273 * @brief Reads an amount of data from the SDRAM memory in polling mode.
bcostm 6:e1d9da7fe856 274 * @param uwStartAddress: Read start address
bcostm 6:e1d9da7fe856 275 * @param pData: Pointer to data to be read
bcostm 6:e1d9da7fe856 276 * @param uwDataSize: Size of read data from the memory
bcostm 6:e1d9da7fe856 277 * @retval SDRAM status
bcostm 6:e1d9da7fe856 278 */
bcostm 6:e1d9da7fe856 279 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 6:e1d9da7fe856 280 {
bcostm 6:e1d9da7fe856 281 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 6:e1d9da7fe856 282 {
bcostm 6:e1d9da7fe856 283 return SDRAM_ERROR;
bcostm 6:e1d9da7fe856 284 }
bcostm 6:e1d9da7fe856 285 else
bcostm 6:e1d9da7fe856 286 {
bcostm 6:e1d9da7fe856 287 return SDRAM_OK;
bcostm 6:e1d9da7fe856 288 }
bcostm 6:e1d9da7fe856 289 }
bcostm 6:e1d9da7fe856 290
bcostm 6:e1d9da7fe856 291 /**
bcostm 6:e1d9da7fe856 292 * @brief Reads an amount of data from the SDRAM memory in DMA mode.
bcostm 6:e1d9da7fe856 293 * @param uwStartAddress: Read start address
bcostm 6:e1d9da7fe856 294 * @param pData: Pointer to data to be read
bcostm 6:e1d9da7fe856 295 * @param uwDataSize: Size of read data from the memory
bcostm 6:e1d9da7fe856 296 * @retval SDRAM status
bcostm 6:e1d9da7fe856 297 */
bcostm 6:e1d9da7fe856 298 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 6:e1d9da7fe856 299 {
bcostm 6:e1d9da7fe856 300 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 6:e1d9da7fe856 301 {
bcostm 6:e1d9da7fe856 302 return SDRAM_ERROR;
bcostm 6:e1d9da7fe856 303 }
bcostm 6:e1d9da7fe856 304 else
bcostm 6:e1d9da7fe856 305 {
bcostm 6:e1d9da7fe856 306 return SDRAM_OK;
bcostm 6:e1d9da7fe856 307 }
bcostm 6:e1d9da7fe856 308 }
bcostm 6:e1d9da7fe856 309
bcostm 6:e1d9da7fe856 310 /**
bcostm 6:e1d9da7fe856 311 * @brief Writes an amount of data to the SDRAM memory in polling mode.
bcostm 6:e1d9da7fe856 312 * @param uwStartAddress: Write start address
bcostm 6:e1d9da7fe856 313 * @param pData: Pointer to data to be written
bcostm 6:e1d9da7fe856 314 * @param uwDataSize: Size of written data from the memory
bcostm 6:e1d9da7fe856 315 * @retval SDRAM status
bcostm 6:e1d9da7fe856 316 */
bcostm 6:e1d9da7fe856 317 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 6:e1d9da7fe856 318 {
bcostm 6:e1d9da7fe856 319 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 6:e1d9da7fe856 320 {
bcostm 6:e1d9da7fe856 321 return SDRAM_ERROR;
bcostm 6:e1d9da7fe856 322 }
bcostm 6:e1d9da7fe856 323 else
bcostm 6:e1d9da7fe856 324 {
bcostm 6:e1d9da7fe856 325 return SDRAM_OK;
bcostm 6:e1d9da7fe856 326 }
bcostm 6:e1d9da7fe856 327 }
bcostm 6:e1d9da7fe856 328
bcostm 6:e1d9da7fe856 329 /**
bcostm 6:e1d9da7fe856 330 * @brief Writes an amount of data to the SDRAM memory in DMA mode.
bcostm 6:e1d9da7fe856 331 * @param uwStartAddress: Write start address
bcostm 6:e1d9da7fe856 332 * @param pData: Pointer to data to be written
bcostm 6:e1d9da7fe856 333 * @param uwDataSize: Size of written data from the memory
bcostm 6:e1d9da7fe856 334 * @retval SDRAM status
bcostm 6:e1d9da7fe856 335 */
bcostm 6:e1d9da7fe856 336 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 6:e1d9da7fe856 337 {
bcostm 6:e1d9da7fe856 338 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 6:e1d9da7fe856 339 {
bcostm 6:e1d9da7fe856 340 return SDRAM_ERROR;
bcostm 6:e1d9da7fe856 341 }
bcostm 6:e1d9da7fe856 342 else
bcostm 6:e1d9da7fe856 343 {
bcostm 6:e1d9da7fe856 344 return SDRAM_OK;
bcostm 6:e1d9da7fe856 345 }
bcostm 6:e1d9da7fe856 346 }
bcostm 6:e1d9da7fe856 347
bcostm 6:e1d9da7fe856 348 /**
bcostm 6:e1d9da7fe856 349 * @brief Sends command to the SDRAM bank.
bcostm 6:e1d9da7fe856 350 * @param SdramCmd: Pointer to SDRAM command structure
bcostm 6:e1d9da7fe856 351 * @retval SDRAM status
bcostm 6:e1d9da7fe856 352 */
bcostm 6:e1d9da7fe856 353 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
bcostm 6:e1d9da7fe856 354 {
bcostm 6:e1d9da7fe856 355 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
bcostm 6:e1d9da7fe856 356 {
bcostm 6:e1d9da7fe856 357 return SDRAM_ERROR;
bcostm 6:e1d9da7fe856 358 }
bcostm 6:e1d9da7fe856 359 else
bcostm 6:e1d9da7fe856 360 {
bcostm 6:e1d9da7fe856 361 return SDRAM_OK;
bcostm 6:e1d9da7fe856 362 }
bcostm 6:e1d9da7fe856 363 }
bcostm 6:e1d9da7fe856 364
bcostm 6:e1d9da7fe856 365 /**
bcostm 6:e1d9da7fe856 366 * @brief Initializes SDRAM MSP.
bcostm 6:e1d9da7fe856 367 * @param hsdram: SDRAM handle
bcostm 6:e1d9da7fe856 368 * @param Params
bcostm 6:e1d9da7fe856 369 * @retval None
bcostm 6:e1d9da7fe856 370 */
bcostm 6:e1d9da7fe856 371 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
bcostm 6:e1d9da7fe856 372 {
bcostm 6:e1d9da7fe856 373 static DMA_HandleTypeDef dma_handle;
bcostm 6:e1d9da7fe856 374 GPIO_InitTypeDef gpio_init_structure;
bcostm 6:e1d9da7fe856 375
bcostm 6:e1d9da7fe856 376 /* Enable FMC clock */
bcostm 6:e1d9da7fe856 377 __HAL_RCC_FMC_CLK_ENABLE();
bcostm 6:e1d9da7fe856 378
bcostm 6:e1d9da7fe856 379 /* Enable chosen DMAx clock */
bcostm 6:e1d9da7fe856 380 __DMAx_CLK_ENABLE();
bcostm 6:e1d9da7fe856 381
bcostm 6:e1d9da7fe856 382 /* Enable GPIOs clock */
bcostm 6:e1d9da7fe856 383 __HAL_RCC_GPIOC_CLK_ENABLE();
bcostm 6:e1d9da7fe856 384 __HAL_RCC_GPIOD_CLK_ENABLE();
bcostm 6:e1d9da7fe856 385 __HAL_RCC_GPIOE_CLK_ENABLE();
bcostm 6:e1d9da7fe856 386 __HAL_RCC_GPIOF_CLK_ENABLE();
bcostm 6:e1d9da7fe856 387 __HAL_RCC_GPIOG_CLK_ENABLE();
bcostm 6:e1d9da7fe856 388 __HAL_RCC_GPIOH_CLK_ENABLE();
bcostm 6:e1d9da7fe856 389
bcostm 6:e1d9da7fe856 390 /* Common GPIO configuration */
bcostm 6:e1d9da7fe856 391 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
bcostm 6:e1d9da7fe856 392 gpio_init_structure.Pull = GPIO_PULLUP;
bcostm 6:e1d9da7fe856 393 gpio_init_structure.Speed = GPIO_SPEED_FAST;
bcostm 6:e1d9da7fe856 394 gpio_init_structure.Alternate = GPIO_AF12_FMC;
bcostm 6:e1d9da7fe856 395
bcostm 6:e1d9da7fe856 396 /* GPIOC configuration */
bcostm 6:e1d9da7fe856 397 gpio_init_structure.Pin = GPIO_PIN_3;
bcostm 6:e1d9da7fe856 398 HAL_GPIO_Init(GPIOC, &gpio_init_structure);
bcostm 6:e1d9da7fe856 399
bcostm 6:e1d9da7fe856 400 /* GPIOD configuration */
bcostm 6:e1d9da7fe856 401 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
bcostm 6:e1d9da7fe856 402 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
bcostm 6:e1d9da7fe856 403 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
bcostm 6:e1d9da7fe856 404
bcostm 6:e1d9da7fe856 405 /* GPIOE configuration */
bcostm 6:e1d9da7fe856 406 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
bcostm 6:e1d9da7fe856 407 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
bcostm 6:e1d9da7fe856 408 GPIO_PIN_15;
bcostm 6:e1d9da7fe856 409 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
bcostm 6:e1d9da7fe856 410
bcostm 6:e1d9da7fe856 411 /* GPIOF configuration */
bcostm 6:e1d9da7fe856 412 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
bcostm 6:e1d9da7fe856 413 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
bcostm 6:e1d9da7fe856 414 GPIO_PIN_15;
bcostm 6:e1d9da7fe856 415 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
bcostm 6:e1d9da7fe856 416
bcostm 6:e1d9da7fe856 417 /* GPIOG configuration */
bcostm 6:e1d9da7fe856 418 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
bcostm 6:e1d9da7fe856 419 GPIO_PIN_15;
bcostm 6:e1d9da7fe856 420 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
bcostm 6:e1d9da7fe856 421
bcostm 6:e1d9da7fe856 422 /* GPIOH configuration */
bcostm 6:e1d9da7fe856 423 gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
bcostm 6:e1d9da7fe856 424 HAL_GPIO_Init(GPIOH, &gpio_init_structure);
bcostm 6:e1d9da7fe856 425
bcostm 6:e1d9da7fe856 426 /* Configure common DMA parameters */
bcostm 6:e1d9da7fe856 427 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
bcostm 6:e1d9da7fe856 428 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
bcostm 6:e1d9da7fe856 429 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
bcostm 6:e1d9da7fe856 430 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
bcostm 6:e1d9da7fe856 431 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
bcostm 6:e1d9da7fe856 432 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
bcostm 6:e1d9da7fe856 433 dma_handle.Init.Mode = DMA_NORMAL;
bcostm 6:e1d9da7fe856 434 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
bcostm 6:e1d9da7fe856 435 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
bcostm 6:e1d9da7fe856 436 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
bcostm 6:e1d9da7fe856 437 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
bcostm 6:e1d9da7fe856 438 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
bcostm 6:e1d9da7fe856 439
bcostm 6:e1d9da7fe856 440 dma_handle.Instance = SDRAM_DMAx_STREAM;
bcostm 6:e1d9da7fe856 441
bcostm 6:e1d9da7fe856 442 /* Associate the DMA handle */
bcostm 6:e1d9da7fe856 443 __HAL_LINKDMA(hsdram, hdma, dma_handle);
bcostm 6:e1d9da7fe856 444
bcostm 6:e1d9da7fe856 445 /* Deinitialize the stream for new transfer */
bcostm 6:e1d9da7fe856 446 HAL_DMA_DeInit(&dma_handle);
bcostm 6:e1d9da7fe856 447
bcostm 6:e1d9da7fe856 448 /* Configure the DMA stream */
bcostm 6:e1d9da7fe856 449 HAL_DMA_Init(&dma_handle);
bcostm 6:e1d9da7fe856 450
bcostm 6:e1d9da7fe856 451 /* NVIC configuration for DMA transfer complete interrupt */
bcostm 6:e1d9da7fe856 452 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
bcostm 6:e1d9da7fe856 453 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
bcostm 6:e1d9da7fe856 454 }
bcostm 6:e1d9da7fe856 455
bcostm 6:e1d9da7fe856 456 /**
bcostm 6:e1d9da7fe856 457 * @brief DeInitializes SDRAM MSP.
bcostm 6:e1d9da7fe856 458 * @param hsdram: SDRAM handle
bcostm 6:e1d9da7fe856 459 * @param Params
bcostm 6:e1d9da7fe856 460 * @retval None
bcostm 6:e1d9da7fe856 461 */
bcostm 6:e1d9da7fe856 462 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
bcostm 6:e1d9da7fe856 463 {
bcostm 6:e1d9da7fe856 464 static DMA_HandleTypeDef dma_handle;
bcostm 6:e1d9da7fe856 465
bcostm 6:e1d9da7fe856 466 /* Disable NVIC configuration for DMA interrupt */
bcostm 6:e1d9da7fe856 467 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
bcostm 6:e1d9da7fe856 468
bcostm 6:e1d9da7fe856 469 /* Deinitialize the stream for new transfer */
bcostm 6:e1d9da7fe856 470 dma_handle.Instance = SDRAM_DMAx_STREAM;
bcostm 6:e1d9da7fe856 471 HAL_DMA_DeInit(&dma_handle);
bcostm 6:e1d9da7fe856 472
bcostm 6:e1d9da7fe856 473 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
bcostm 6:e1d9da7fe856 474 by surcharging this __weak function */
bcostm 6:e1d9da7fe856 475 }
bcostm 6:e1d9da7fe856 476
bcostm 6:e1d9da7fe856 477 /**
bcostm 6:e1d9da7fe856 478 * @}
bcostm 6:e1d9da7fe856 479 */
bcostm 6:e1d9da7fe856 480
bcostm 6:e1d9da7fe856 481 /**
bcostm 6:e1d9da7fe856 482 * @}
bcostm 6:e1d9da7fe856 483 */
bcostm 6:e1d9da7fe856 484
bcostm 6:e1d9da7fe856 485 /**
bcostm 6:e1d9da7fe856 486 * @}
bcostm 6:e1d9da7fe856 487 */
bcostm 6:e1d9da7fe856 488
bcostm 6:e1d9da7fe856 489 /**
bcostm 6:e1d9da7fe856 490 * @}
bcostm 6:e1d9da7fe856 491 */
bcostm 6:e1d9da7fe856 492
bcostm 6:e1d9da7fe856 493 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/