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Diff: Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h
- Revision:
- 6:e1d9da7fe856
- Child:
- 8:56384bddaba5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/Drivers/BSP/STM32746G-Discovery/stm32746g_discovery_sdram.h Thu Nov 10 09:57:11 2016 +0100
@@ -0,0 +1,164 @@
+/**
+ ******************************************************************************
+ * @file stm32746g_discovery_sdram.h
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 02-June-2016
+ * @brief This file contains the common defines and functions prototypes for
+ * the stm32746g_discovery_sdram.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32746G_DISCOVERY_SDRAM_H
+#define __STM32746G_DISCOVERY_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup STM32746G_DISCOVERY
+ * @{
+ */
+
+/** @addtogroup STM32746G_DISCOVERY_SDRAM
+ * @{
+ */
+
+/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
+ * @{
+ */
+
+/**
+ * @brief SDRAM status structure definition
+ */
+#define SDRAM_OK ((uint8_t)0x00)
+#define SDRAM_ERROR ((uint8_t)0x01)
+
+/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
+ * @{
+ */
+#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
+#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
+
+/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
+#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
+
+#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
+/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
+
+#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
+
+#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
+
+/* DMA definitions for SDRAM DMA transfer */
+#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
+#define SDRAM_DMAx_STREAM DMA2_Stream0
+#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
+#define BSP_SDRAM_DMA_IRQHandler DMA2_Stream0_IRQHandler
+/**
+ * @}
+ */
+
+/**
+ * @brief FMC SDRAM Mode definition register defines
+ */
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+/**
+ * @}
+ */
+
+/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
+ * @{
+ */
+uint8_t BSP_SDRAM_Init(void);
+uint8_t BSP_SDRAM_DeInit(void);
+void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
+uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
+uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
+
+/* These functions can be modified in case the current settings (e.g. DMA stream)
+ need to be changed for specific application needs */
+void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
+void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32746G_DISCOVERY_SDRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/