XRange SX1272Lib
Dependents: XRangePingPong XRange-LoRaWAN-lmic-app lora-transceiver
Fork of SX1276Lib by
SX1272 LoRa RF module https://www.netblocks.eu/xrange-sx1272-lora-datasheet/
Driver for the SX1272 RF Transceiver.
sx1272/sx1272-hal.cpp@18:0d1c09259f20, 2016-01-07 (annotated)
- Committer:
- netblocks
- Date:
- Thu Jan 07 08:14:20 2016 +0000
- Revision:
- 18:0d1c09259f20
- Parent:
- 17:a5c9fd1a1ea6
Sets RX/TX packet length 256 bytes.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
GregCr | 0:e6ceb13d2d05 | 1 | /* |
GregCr | 0:e6ceb13d2d05 | 2 | / _____) _ | | |
GregCr | 0:e6ceb13d2d05 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
GregCr | 0:e6ceb13d2d05 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
GregCr | 0:e6ceb13d2d05 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
GregCr | 0:e6ceb13d2d05 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
GregCr | 8:0fe3e0e8007b | 7 | ( C )2014 Semtech |
GregCr | 0:e6ceb13d2d05 | 8 | |
GregCr | 0:e6ceb13d2d05 | 9 | Description: - |
GregCr | 0:e6ceb13d2d05 | 10 | |
GregCr | 0:e6ceb13d2d05 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
GregCr | 0:e6ceb13d2d05 | 12 | |
netblocks | 17:a5c9fd1a1ea6 | 13 | Maintainers: www.netblocks.eu |
netblocks | 17:a5c9fd1a1ea6 | 14 | SX1272 LoRa RF module : http://www.netblocks.eu/xrange-sx1272-lora-datasheet/ |
netblocks | 17:a5c9fd1a1ea6 | 15 | |
GregCr | 0:e6ceb13d2d05 | 16 | */ |
netblocks | 17:a5c9fd1a1ea6 | 17 | #include "sx1272-hal.h" |
GregCr | 0:e6ceb13d2d05 | 18 | |
netblocks | 17:a5c9fd1a1ea6 | 19 | const RadioRegisters_t XRange::RadioRegsInit[] = |
GregCr | 0:e6ceb13d2d05 | 20 | { |
GregCr | 0:e6ceb13d2d05 | 21 | { MODEM_FSK , REG_LNA , 0x23 }, |
GregCr | 0:e6ceb13d2d05 | 22 | { MODEM_FSK , REG_RXCONFIG , 0x1E }, |
GregCr | 0:e6ceb13d2d05 | 23 | { MODEM_FSK , REG_RSSICONFIG , 0xD2 }, |
GregCr | 0:e6ceb13d2d05 | 24 | { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA }, |
GregCr | 0:e6ceb13d2d05 | 25 | { MODEM_FSK , REG_OSC , 0x07 }, |
GregCr | 0:e6ceb13d2d05 | 26 | { MODEM_FSK , REG_SYNCCONFIG , 0x12 }, |
GregCr | 0:e6ceb13d2d05 | 27 | { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 }, |
GregCr | 0:e6ceb13d2d05 | 28 | { MODEM_FSK , REG_SYNCVALUE2 , 0x94 }, |
GregCr | 0:e6ceb13d2d05 | 29 | { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 }, |
mluis | 15:04374b1c33fa | 30 | { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 }, |
GregCr | 0:e6ceb13d2d05 | 31 | { MODEM_FSK , REG_FIFOTHRESH , 0x8F }, |
GregCr | 0:e6ceb13d2d05 | 32 | { MODEM_FSK , REG_IMAGECAL , 0x02 }, |
GregCr | 0:e6ceb13d2d05 | 33 | { MODEM_FSK , REG_DIOMAPPING1 , 0x00 }, |
GregCr | 0:e6ceb13d2d05 | 34 | { MODEM_FSK , REG_DIOMAPPING2 , 0x30 }, |
netblocks | 18:0d1c09259f20 | 35 | //Sets 256 Bytes for RX TX packets |
netblocks | 18:0d1c09259f20 | 36 | { MODEM_LORA, REG_LR_FIFOTXBASEADDR, 0x00 }, |
netblocks | 18:0d1c09259f20 | 37 | { MODEM_LORA, REG_LR_FIFORXBASEADDR, 0x00 }, |
netblocks | 18:0d1c09259f20 | 38 | |
GregCr | 0:e6ceb13d2d05 | 39 | }; |
GregCr | 0:e6ceb13d2d05 | 40 | |
netblocks | 17:a5c9fd1a1ea6 | 41 | |
netblocks | 17:a5c9fd1a1ea6 | 42 | XRange::XRange( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ), |
GregCr | 12:aa5b3bf7fdf4 | 43 | void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool ChannelActivityDetected ), |
GregCr | 0:e6ceb13d2d05 | 44 | PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, |
GregCr | 0:e6ceb13d2d05 | 45 | PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5, |
GregCr | 0:e6ceb13d2d05 | 46 | PinName antSwitch ) |
netblocks | 17:a5c9fd1a1ea6 | 47 | : SX1272( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5), |
netblocks | 17:a5c9fd1a1ea6 | 48 | antSwitch( antSwitch ) |
GregCr | 0:e6ceb13d2d05 | 49 | { |
GregCr | 0:e6ceb13d2d05 | 50 | Reset( ); |
netblocks | 17:a5c9fd1a1ea6 | 51 | |
GregCr | 0:e6ceb13d2d05 | 52 | IoInit( ); |
GregCr | 0:e6ceb13d2d05 | 53 | |
GregCr | 0:e6ceb13d2d05 | 54 | SetOpMode( RF_OPMODE_SLEEP ); |
GregCr | 0:e6ceb13d2d05 | 55 | |
GregCr | 0:e6ceb13d2d05 | 56 | IoIrqInit( dioIrq ); |
GregCr | 0:e6ceb13d2d05 | 57 | |
GregCr | 0:e6ceb13d2d05 | 58 | RadioRegistersInit( ); |
GregCr | 0:e6ceb13d2d05 | 59 | |
GregCr | 0:e6ceb13d2d05 | 60 | SetModem( MODEM_FSK ); |
GregCr | 0:e6ceb13d2d05 | 61 | |
GregCr | 0:e6ceb13d2d05 | 62 | this->settings.State = IDLE ; |
GregCr | 0:e6ceb13d2d05 | 63 | } |
GregCr | 0:e6ceb13d2d05 | 64 | |
netblocks | 17:a5c9fd1a1ea6 | 65 | XRange::XRange( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ), |
GregCr | 12:aa5b3bf7fdf4 | 66 | void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool ChannelActivityDetected ) ) |
netblocks | 17:a5c9fd1a1ea6 | 67 | : SX1272( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone, |
netblocks | 17:a5c9fd1a1ea6 | 68 | PB_15 /*MOSI*/, PB_14 /*MISO*/, PB_13 /*SCLK*/, PB_12 /*NSS*/, PB_2 /*RESET*/, |
netblocks | 17:a5c9fd1a1ea6 | 69 | PA_10 /*DIO0*/, PA_9 /*DIO1*/, PC_13 /*DIO2*/, PB_0 /*DIO3*/, PB_1 /*DIO4*/,PB_10 /*DIO5*/ ), |
netblocks | 17:a5c9fd1a1ea6 | 70 | antSwitch( PB_11 ) |
GregCr | 0:e6ceb13d2d05 | 71 | { |
GregCr | 0:e6ceb13d2d05 | 72 | Reset( ); |
netblocks | 17:a5c9fd1a1ea6 | 73 | |
GregCr | 0:e6ceb13d2d05 | 74 | IoInit( ); |
GregCr | 0:e6ceb13d2d05 | 75 | |
GregCr | 0:e6ceb13d2d05 | 76 | SetOpMode( RF_OPMODE_SLEEP ); |
GregCr | 0:e6ceb13d2d05 | 77 | IoIrqInit( dioIrq ); |
GregCr | 0:e6ceb13d2d05 | 78 | |
GregCr | 0:e6ceb13d2d05 | 79 | RadioRegistersInit( ); |
GregCr | 0:e6ceb13d2d05 | 80 | |
GregCr | 0:e6ceb13d2d05 | 81 | SetModem( MODEM_FSK ); |
GregCr | 0:e6ceb13d2d05 | 82 | |
GregCr | 0:e6ceb13d2d05 | 83 | this->settings.State = IDLE ; |
GregCr | 0:e6ceb13d2d05 | 84 | } |
GregCr | 0:e6ceb13d2d05 | 85 | |
GregCr | 0:e6ceb13d2d05 | 86 | |
netblocks | 17:a5c9fd1a1ea6 | 87 | void XRange::IoInit( void ) |
GregCr | 0:e6ceb13d2d05 | 88 | { |
GregCr | 0:e6ceb13d2d05 | 89 | AntSwInit( ); |
GregCr | 0:e6ceb13d2d05 | 90 | SpiInit( ); |
GregCr | 0:e6ceb13d2d05 | 91 | } |
GregCr | 0:e6ceb13d2d05 | 92 | |
netblocks | 17:a5c9fd1a1ea6 | 93 | void XRange::RadioRegistersInit( ){ |
GregCr | 0:e6ceb13d2d05 | 94 | uint8_t i = 0; |
GregCr | 0:e6ceb13d2d05 | 95 | for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ ) |
GregCr | 0:e6ceb13d2d05 | 96 | { |
GregCr | 0:e6ceb13d2d05 | 97 | SetModem( RadioRegsInit[i].Modem ); |
GregCr | 0:e6ceb13d2d05 | 98 | Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); |
GregCr | 0:e6ceb13d2d05 | 99 | } |
GregCr | 0:e6ceb13d2d05 | 100 | } |
GregCr | 0:e6ceb13d2d05 | 101 | |
netblocks | 17:a5c9fd1a1ea6 | 102 | void XRange::SpiInit( void ) |
GregCr | 0:e6ceb13d2d05 | 103 | { |
GregCr | 0:e6ceb13d2d05 | 104 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 105 | spi.format( 8,0 ); |
GregCr | 0:e6ceb13d2d05 | 106 | uint32_t frequencyToSet = 8000000; |
netblocks | 17:a5c9fd1a1ea6 | 107 | spi.frequency( frequencyToSet ); |
GregCr | 0:e6ceb13d2d05 | 108 | wait(0.1); |
GregCr | 0:e6ceb13d2d05 | 109 | } |
GregCr | 0:e6ceb13d2d05 | 110 | |
netblocks | 17:a5c9fd1a1ea6 | 111 | void XRange::IoIrqInit( DioIrqHandler *irqHandlers ) |
GregCr | 0:e6ceb13d2d05 | 112 | { |
netblocks | 17:a5c9fd1a1ea6 | 113 | dio0.mode(PullDown); |
netblocks | 17:a5c9fd1a1ea6 | 114 | dio1.mode(PullDown); |
netblocks | 17:a5c9fd1a1ea6 | 115 | dio2.mode(PullDown); |
netblocks | 17:a5c9fd1a1ea6 | 116 | dio3.mode(PullDown); |
netblocks | 17:a5c9fd1a1ea6 | 117 | dio4.mode(PullDown); |
netblocks | 17:a5c9fd1a1ea6 | 118 | dio0.rise( this, static_cast< TriggerXRange > ( irqHandlers[0] ) ); |
netblocks | 17:a5c9fd1a1ea6 | 119 | dio1.rise( this, static_cast< TriggerXRange > ( irqHandlers[1] ) ); |
netblocks | 17:a5c9fd1a1ea6 | 120 | dio2.rise( this, static_cast< TriggerXRange > ( irqHandlers[2] ) ); |
netblocks | 17:a5c9fd1a1ea6 | 121 | dio3.rise( this, static_cast< TriggerXRange > ( irqHandlers[3] ) ); |
netblocks | 17:a5c9fd1a1ea6 | 122 | dio4.rise( this, static_cast< TriggerXRange > ( irqHandlers[4] ) ); |
GregCr | 0:e6ceb13d2d05 | 123 | } |
GregCr | 0:e6ceb13d2d05 | 124 | |
netblocks | 17:a5c9fd1a1ea6 | 125 | void XRange::IoDeInit( void ) |
GregCr | 0:e6ceb13d2d05 | 126 | { |
GregCr | 0:e6ceb13d2d05 | 127 | //nothing |
GregCr | 0:e6ceb13d2d05 | 128 | } |
GregCr | 0:e6ceb13d2d05 | 129 | |
netblocks | 17:a5c9fd1a1ea6 | 130 | uint8_t XRange::GetPaSelect( uint32_t channel ) |
GregCr | 0:e6ceb13d2d05 | 131 | { |
netblocks | 17:a5c9fd1a1ea6 | 132 | return RF_PACONFIG_PASELECT_PABOOST; |
GregCr | 0:e6ceb13d2d05 | 133 | } |
GregCr | 0:e6ceb13d2d05 | 134 | |
netblocks | 17:a5c9fd1a1ea6 | 135 | void XRange::SetAntSwLowPower( bool status ) |
GregCr | 0:e6ceb13d2d05 | 136 | { |
GregCr | 0:e6ceb13d2d05 | 137 | if( isRadioActive != status ) |
GregCr | 0:e6ceb13d2d05 | 138 | { |
GregCr | 0:e6ceb13d2d05 | 139 | isRadioActive = status; |
GregCr | 0:e6ceb13d2d05 | 140 | |
GregCr | 0:e6ceb13d2d05 | 141 | if( status == false ) |
GregCr | 0:e6ceb13d2d05 | 142 | { |
GregCr | 0:e6ceb13d2d05 | 143 | AntSwInit( ); |
GregCr | 0:e6ceb13d2d05 | 144 | } |
GregCr | 0:e6ceb13d2d05 | 145 | else |
GregCr | 0:e6ceb13d2d05 | 146 | { |
GregCr | 0:e6ceb13d2d05 | 147 | AntSwDeInit( ); |
GregCr | 0:e6ceb13d2d05 | 148 | } |
GregCr | 0:e6ceb13d2d05 | 149 | } |
GregCr | 0:e6ceb13d2d05 | 150 | } |
GregCr | 0:e6ceb13d2d05 | 151 | |
netblocks | 17:a5c9fd1a1ea6 | 152 | void XRange::AntSwInit( void ) |
GregCr | 0:e6ceb13d2d05 | 153 | { |
GregCr | 0:e6ceb13d2d05 | 154 | antSwitch = 0; |
GregCr | 0:e6ceb13d2d05 | 155 | } |
GregCr | 0:e6ceb13d2d05 | 156 | |
netblocks | 17:a5c9fd1a1ea6 | 157 | void XRange::AntSwDeInit( void ) |
GregCr | 0:e6ceb13d2d05 | 158 | { |
GregCr | 0:e6ceb13d2d05 | 159 | antSwitch = 0; |
GregCr | 0:e6ceb13d2d05 | 160 | } |
GregCr | 0:e6ceb13d2d05 | 161 | |
netblocks | 17:a5c9fd1a1ea6 | 162 | void XRange::SetAntSw( uint8_t rxTx ) |
GregCr | 0:e6ceb13d2d05 | 163 | { |
GregCr | 0:e6ceb13d2d05 | 164 | if( this->rxTx == rxTx ) |
GregCr | 0:e6ceb13d2d05 | 165 | { |
GregCr | 0:e6ceb13d2d05 | 166 | //no need to go further |
GregCr | 0:e6ceb13d2d05 | 167 | return; |
GregCr | 0:e6ceb13d2d05 | 168 | } |
GregCr | 0:e6ceb13d2d05 | 169 | |
GregCr | 0:e6ceb13d2d05 | 170 | this->rxTx = rxTx; |
GregCr | 0:e6ceb13d2d05 | 171 | |
GregCr | 0:e6ceb13d2d05 | 172 | if( rxTx != 0 ) |
GregCr | 0:e6ceb13d2d05 | 173 | { |
GregCr | 0:e6ceb13d2d05 | 174 | antSwitch = 1; |
GregCr | 0:e6ceb13d2d05 | 175 | } |
GregCr | 0:e6ceb13d2d05 | 176 | else |
GregCr | 0:e6ceb13d2d05 | 177 | { |
GregCr | 0:e6ceb13d2d05 | 178 | antSwitch = 0; |
GregCr | 0:e6ceb13d2d05 | 179 | } |
GregCr | 0:e6ceb13d2d05 | 180 | } |
GregCr | 0:e6ceb13d2d05 | 181 | |
netblocks | 17:a5c9fd1a1ea6 | 182 | bool XRange::CheckRfFrequency( uint32_t frequency ) |
GregCr | 0:e6ceb13d2d05 | 183 | { |
GregCr | 0:e6ceb13d2d05 | 184 | //TODO: Implement check, currently all frequencies are supported |
GregCr | 0:e6ceb13d2d05 | 185 | return true; |
GregCr | 0:e6ceb13d2d05 | 186 | } |
GregCr | 0:e6ceb13d2d05 | 187 | |
GregCr | 0:e6ceb13d2d05 | 188 | |
netblocks | 17:a5c9fd1a1ea6 | 189 | void XRange::Reset( void ) |
GregCr | 0:e6ceb13d2d05 | 190 | { |
GregCr | 4:f0ce52e94d3f | 191 | reset.output(); |
netblocks | 17:a5c9fd1a1ea6 | 192 | reset = 1; |
GregCr | 0:e6ceb13d2d05 | 193 | wait_ms( 1 ); |
GregCr | 4:f0ce52e94d3f | 194 | reset.input(); |
GregCr | 0:e6ceb13d2d05 | 195 | wait_ms( 6 ); |
GregCr | 0:e6ceb13d2d05 | 196 | } |
GregCr | 0:e6ceb13d2d05 | 197 | |
netblocks | 17:a5c9fd1a1ea6 | 198 | void XRange::Write( uint8_t addr, uint8_t data ) |
GregCr | 0:e6ceb13d2d05 | 199 | { |
GregCr | 0:e6ceb13d2d05 | 200 | Write( addr, &data, 1 ); |
GregCr | 0:e6ceb13d2d05 | 201 | } |
GregCr | 0:e6ceb13d2d05 | 202 | |
netblocks | 17:a5c9fd1a1ea6 | 203 | uint8_t XRange::Read( uint8_t addr ) |
GregCr | 0:e6ceb13d2d05 | 204 | { |
GregCr | 0:e6ceb13d2d05 | 205 | uint8_t data; |
GregCr | 0:e6ceb13d2d05 | 206 | Read( addr, &data, 1 ); |
GregCr | 0:e6ceb13d2d05 | 207 | return data; |
GregCr | 0:e6ceb13d2d05 | 208 | } |
GregCr | 0:e6ceb13d2d05 | 209 | |
netblocks | 17:a5c9fd1a1ea6 | 210 | void XRange::Write( uint8_t addr, uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 211 | { |
GregCr | 0:e6ceb13d2d05 | 212 | uint8_t i; |
GregCr | 0:e6ceb13d2d05 | 213 | |
GregCr | 0:e6ceb13d2d05 | 214 | nss = 0; |
GregCr | 0:e6ceb13d2d05 | 215 | spi.write( addr | 0x80 ); |
GregCr | 0:e6ceb13d2d05 | 216 | for( i = 0; i < size; i++ ) |
GregCr | 0:e6ceb13d2d05 | 217 | { |
GregCr | 0:e6ceb13d2d05 | 218 | spi.write( buffer[i] ); |
GregCr | 0:e6ceb13d2d05 | 219 | } |
GregCr | 0:e6ceb13d2d05 | 220 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 221 | } |
GregCr | 0:e6ceb13d2d05 | 222 | |
netblocks | 17:a5c9fd1a1ea6 | 223 | void XRange::Read( uint8_t addr, uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 224 | { |
GregCr | 0:e6ceb13d2d05 | 225 | uint8_t i; |
GregCr | 0:e6ceb13d2d05 | 226 | |
GregCr | 0:e6ceb13d2d05 | 227 | nss = 0; |
GregCr | 0:e6ceb13d2d05 | 228 | spi.write( addr & 0x7F ); |
GregCr | 0:e6ceb13d2d05 | 229 | for( i = 0; i < size; i++ ) |
GregCr | 0:e6ceb13d2d05 | 230 | { |
GregCr | 0:e6ceb13d2d05 | 231 | buffer[i] = spi.write( 0 ); |
GregCr | 0:e6ceb13d2d05 | 232 | } |
GregCr | 0:e6ceb13d2d05 | 233 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 234 | } |
GregCr | 0:e6ceb13d2d05 | 235 | |
netblocks | 17:a5c9fd1a1ea6 | 236 | void XRange::WriteFifo( uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 237 | { |
GregCr | 0:e6ceb13d2d05 | 238 | Write( 0, buffer, size ); |
GregCr | 0:e6ceb13d2d05 | 239 | } |
GregCr | 0:e6ceb13d2d05 | 240 | |
netblocks | 17:a5c9fd1a1ea6 | 241 | void XRange::ReadFifo( uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 242 | { |
GregCr | 0:e6ceb13d2d05 | 243 | Read( 0, buffer, size ); |
GregCr | 0:e6ceb13d2d05 | 244 | } |