HelloWorld_IKS01A1 - Simple "hello world" style program for X-NUCLEO-I…

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mattia griotti / Mbed 2 deprecated HelloWorld_IKS01A1

Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial

Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed

stm32f4xx_usart.c@8:1c6281289d67, 2015-11-15 (annotated)

Committer:: n0tform3
Date:: Sun Nov 15 09:00:40 2015 +0000
Revision:: 8:1c6281289d67

test with led

Who changed what in which revision?

User	Revision	Line number	New contents of line
n0tform3	8:1c6281289d67	1	/**
n0tform3	8:1c6281289d67	2	******************************************************************************
n0tform3	8:1c6281289d67	3	* @file stm32f4xx_usart.c
n0tform3	8:1c6281289d67	4	* @author MCD Application Team
n0tform3	8:1c6281289d67	5	* @version V1.0.0
n0tform3	8:1c6281289d67	6	* @date 30-September-2011
n0tform3	8:1c6281289d67	7	* @brief This file provides firmware functions to manage the following
n0tform3	8:1c6281289d67	8	* functionalities of the Universal synchronous asynchronous receiver
n0tform3	8:1c6281289d67	9	* transmitter (USART):
n0tform3	8:1c6281289d67	10	* - Initialization and Configuration
n0tform3	8:1c6281289d67	11	* - Data transfers
n0tform3	8:1c6281289d67	12	* - Multi-Processor Communication
n0tform3	8:1c6281289d67	13	* - LIN mode
n0tform3	8:1c6281289d67	14	* - Half-duplex mode
n0tform3	8:1c6281289d67	15	* - Smartcard mode
n0tform3	8:1c6281289d67	16	* - IrDA mode
n0tform3	8:1c6281289d67	17	* - DMA transfers management
n0tform3	8:1c6281289d67	18	* - Interrupts and flags management
n0tform3	8:1c6281289d67	19	*
n0tform3	8:1c6281289d67	20	* @verbatim
n0tform3	8:1c6281289d67	21	*
n0tform3	8:1c6281289d67	22	* ===================================================================
n0tform3	8:1c6281289d67	23	* How to use this driver
n0tform3	8:1c6281289d67	24	* ===================================================================
n0tform3	8:1c6281289d67	25	* 1. Enable peripheral clock using the follwoing functions
n0tform3	8:1c6281289d67	26	* RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6
n0tform3	8:1c6281289d67	27	* RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5.
n0tform3	8:1c6281289d67	28	*
n0tform3	8:1c6281289d67	29	* 2. According to the USART mode, enable the GPIO clocks using
n0tform3	8:1c6281289d67	30	* RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS,
n0tform3	8:1c6281289d67	31	* or/and SCLK).
n0tform3	8:1c6281289d67	32	*
n0tform3	8:1c6281289d67	33	* 3. Peripheral's alternate function:
n0tform3	8:1c6281289d67	34	* - Connect the pin to the desired peripherals' Alternate
n0tform3	8:1c6281289d67	35	* Function (AF) using GPIO_PinAFConfig() function
n0tform3	8:1c6281289d67	36	* - Configure the desired pin in alternate function by:
n0tform3	8:1c6281289d67	37	* GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
n0tform3	8:1c6281289d67	38	* - Select the type, pull-up/pull-down and output speed via
n0tform3	8:1c6281289d67	39	* GPIO_PuPd, GPIO_OType and GPIO_Speed members
n0tform3	8:1c6281289d67	40	* - Call GPIO_Init() function
n0tform3	8:1c6281289d67	41	*
n0tform3	8:1c6281289d67	42	* 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
n0tform3	8:1c6281289d67	43	* flow control and Mode(Receiver/Transmitter) using the USART_Init()
n0tform3	8:1c6281289d67	44	* function.
n0tform3	8:1c6281289d67	45	*
n0tform3	8:1c6281289d67	46	* 5. For synchronous mode, enable the clock and program the polarity,
n0tform3	8:1c6281289d67	47	* phase and last bit using the USART_ClockInit() function.
n0tform3	8:1c6281289d67	48	*
n0tform3	8:1c6281289d67	49	* 5. Enable the NVIC and the corresponding interrupt using the function
n0tform3	8:1c6281289d67	50	* USART_ITConfig() if you need to use interrupt mode.
n0tform3	8:1c6281289d67	51	*
n0tform3	8:1c6281289d67	52	* 6. When using the DMA mode
n0tform3	8:1c6281289d67	53	* - Configure the DMA using DMA_Init() function
n0tform3	8:1c6281289d67	54	* - Active the needed channel Request using USART_DMACmd() function
n0tform3	8:1c6281289d67	55	*
n0tform3	8:1c6281289d67	56	* 7. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	57	*
n0tform3	8:1c6281289d67	58	* 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode.
n0tform3	8:1c6281289d67	59	*
n0tform3	8:1c6281289d67	60	* Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
n0tform3	8:1c6281289d67	61	* for more details
n0tform3	8:1c6281289d67	62	*
n0tform3	8:1c6281289d67	63	* In order to reach higher communication baudrates, it is possible to
n0tform3	8:1c6281289d67	64	* enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
n0tform3	8:1c6281289d67	65	* This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
n0tform3	8:1c6281289d67	66	* and before calling the function USART_Init().
n0tform3	8:1c6281289d67	67	*
n0tform3	8:1c6281289d67	68	* @endverbatim
n0tform3	8:1c6281289d67	69	*
n0tform3	8:1c6281289d67	70	******************************************************************************
n0tform3	8:1c6281289d67	71	* @attention
n0tform3	8:1c6281289d67	72	*
n0tform3	8:1c6281289d67	73	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
n0tform3	8:1c6281289d67	74	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
n0tform3	8:1c6281289d67	75	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
n0tform3	8:1c6281289d67	76	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
n0tform3	8:1c6281289d67	77	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
n0tform3	8:1c6281289d67	78	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
n0tform3	8:1c6281289d67	79	*
n0tform3	8:1c6281289d67	80	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
n0tform3	8:1c6281289d67	81	******************************************************************************
n0tform3	8:1c6281289d67	82	*/
n0tform3	8:1c6281289d67	83
n0tform3	8:1c6281289d67	84	/* Includes ------------------------------------------------------------------*/
n0tform3	8:1c6281289d67	85	#include "stm32f4xx_usart.h"
n0tform3	8:1c6281289d67	86	#include "stm32f4xx_rcc.h"
n0tform3	8:1c6281289d67	87
n0tform3	8:1c6281289d67	88	/** @addtogroup STM32F4xx_StdPeriph_Driver
n0tform3	8:1c6281289d67	89	* @{
n0tform3	8:1c6281289d67	90	*/
n0tform3	8:1c6281289d67	91
n0tform3	8:1c6281289d67	92	/** @defgroup USART
n0tform3	8:1c6281289d67	93	* @brief USART driver modules
n0tform3	8:1c6281289d67	94	* @{
n0tform3	8:1c6281289d67	95	*/
n0tform3	8:1c6281289d67	96
n0tform3	8:1c6281289d67	97	/* Private typedef -----------------------------------------------------------*/
n0tform3	8:1c6281289d67	98	/* Private define ------------------------------------------------------------*/
n0tform3	8:1c6281289d67	99
n0tform3	8:1c6281289d67	100	/!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) /
n0tform3	8:1c6281289d67	101	#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M \| USART_CR1_PCE \| \
n0tform3	8:1c6281289d67	102	USART_CR1_PS \| USART_CR1_TE \| \
n0tform3	8:1c6281289d67	103	USART_CR1_RE))
n0tform3	8:1c6281289d67	104
n0tform3	8:1c6281289d67	105	/!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) /
n0tform3	8:1c6281289d67	106	#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN \| USART_CR2_CPOL \| \
n0tform3	8:1c6281289d67	107	USART_CR2_CPHA \| USART_CR2_LBCL))
n0tform3	8:1c6281289d67	108
n0tform3	8:1c6281289d67	109	/!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) /
n0tform3	8:1c6281289d67	110	#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE \| USART_CR3_CTSE))
n0tform3	8:1c6281289d67	111
n0tform3	8:1c6281289d67	112	/!< USART Interrupts mask /
n0tform3	8:1c6281289d67	113	#define IT_MASK ((uint16_t)0x001F)
n0tform3	8:1c6281289d67	114
n0tform3	8:1c6281289d67	115	/* Private macro -------------------------------------------------------------*/
n0tform3	8:1c6281289d67	116	/* Private variables ---------------------------------------------------------*/
n0tform3	8:1c6281289d67	117	/* Private function prototypes -----------------------------------------------*/
n0tform3	8:1c6281289d67	118	/* Private functions ---------------------------------------------------------*/
n0tform3	8:1c6281289d67	119
n0tform3	8:1c6281289d67	120	/** @defgroup USART_Private_Functions
n0tform3	8:1c6281289d67	121	* @{
n0tform3	8:1c6281289d67	122	*/
n0tform3	8:1c6281289d67	123
n0tform3	8:1c6281289d67	124	/** @defgroup USART_Group1 Initialization and Configuration functions
n0tform3	8:1c6281289d67	125	* @brief Initialization and Configuration functions
n0tform3	8:1c6281289d67	126	*
n0tform3	8:1c6281289d67	127	@verbatim
n0tform3	8:1c6281289d67	128	===============================================================================
n0tform3	8:1c6281289d67	129	Initialization and Configuration functions
n0tform3	8:1c6281289d67	130	===============================================================================
n0tform3	8:1c6281289d67	131
n0tform3	8:1c6281289d67	132	This subsection provides a set of functions allowing to initialize the USART
n0tform3	8:1c6281289d67	133	in asynchronous and in synchronous modes.
n0tform3	8:1c6281289d67	134	- For the asynchronous mode only these parameters can be configured:
n0tform3	8:1c6281289d67	135	- Baud Rate
n0tform3	8:1c6281289d67	136	- Word Length
n0tform3	8:1c6281289d67	137	- Stop Bit
n0tform3	8:1c6281289d67	138	- Parity: If the parity is enabled, then the MSB bit of the data written
n0tform3	8:1c6281289d67	139	in the data register is transmitted but is changed by the parity bit.
n0tform3	8:1c6281289d67	140	Depending on the frame length defined by the M bit (8-bits or 9-bits),
n0tform3	8:1c6281289d67	141	the possible USART frame formats are as listed in the following table:
n0tform3	8:1c6281289d67	142	+-------------------------------------------------------------+
n0tform3	8:1c6281289d67	143	\| M bit \| PCE bit \| USART frame \|
n0tform3	8:1c6281289d67	144	\|---------------------\|---------------------------------------\|
n0tform3	8:1c6281289d67	145	\| 0 \| 0 \| \| SB \| 8 bit data \| STB \| \|
n0tform3	8:1c6281289d67	146	\|---------\|-----------\|---------------------------------------\|
n0tform3	8:1c6281289d67	147	\| 0 \| 1 \| \| SB \| 7 bit data \| PB \| STB \| \|
n0tform3	8:1c6281289d67	148	\|---------\|-----------\|---------------------------------------\|
n0tform3	8:1c6281289d67	149	\| 1 \| 0 \| \| SB \| 9 bit data \| STB \| \|
n0tform3	8:1c6281289d67	150	\|---------\|-----------\|---------------------------------------\|
n0tform3	8:1c6281289d67	151	\| 1 \| 1 \| \| SB \| 8 bit data \| PB \| STB \| \|
n0tform3	8:1c6281289d67	152	+-------------------------------------------------------------+
n0tform3	8:1c6281289d67	153	- Hardware flow control
n0tform3	8:1c6281289d67	154	- Receiver/transmitter modes
n0tform3	8:1c6281289d67	155
n0tform3	8:1c6281289d67	156	The USART_Init() function follows the USART asynchronous configuration procedure
n0tform3	8:1c6281289d67	157	(details for the procedure are available in reference manual (RM0090)).
n0tform3	8:1c6281289d67	158
n0tform3	8:1c6281289d67	159	- For the synchronous mode in addition to the asynchronous mode parameters these
n0tform3	8:1c6281289d67	160	parameters should be also configured:
n0tform3	8:1c6281289d67	161	- USART Clock Enabled
n0tform3	8:1c6281289d67	162	- USART polarity
n0tform3	8:1c6281289d67	163	- USART phase
n0tform3	8:1c6281289d67	164	- USART LastBit
n0tform3	8:1c6281289d67	165
n0tform3	8:1c6281289d67	166	These parameters can be configured using the USART_ClockInit() function.
n0tform3	8:1c6281289d67	167
n0tform3	8:1c6281289d67	168	@endverbatim
n0tform3	8:1c6281289d67	169	* @{
n0tform3	8:1c6281289d67	170	*/
n0tform3	8:1c6281289d67	171
n0tform3	8:1c6281289d67	172	/**
n0tform3	8:1c6281289d67	173	* @brief Deinitializes the USARTx peripheral registers to their default reset values.
n0tform3	8:1c6281289d67	174	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	175	* UART peripheral.
n0tform3	8:1c6281289d67	176	* @retval None
n0tform3	8:1c6281289d67	177	*/
n0tform3	8:1c6281289d67	178	void USART_DeInit(USART_TypeDef* USARTx)
n0tform3	8:1c6281289d67	179	{
n0tform3	8:1c6281289d67	180	/* Check the parameters */
n0tform3	8:1c6281289d67	181	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	182
n0tform3	8:1c6281289d67	183	if (USARTx == USART1)
n0tform3	8:1c6281289d67	184	{
n0tform3	8:1c6281289d67	185	RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
n0tform3	8:1c6281289d67	186	RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
n0tform3	8:1c6281289d67	187	}
n0tform3	8:1c6281289d67	188	else if (USARTx == USART2)
n0tform3	8:1c6281289d67	189	{
n0tform3	8:1c6281289d67	190	RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
n0tform3	8:1c6281289d67	191	RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
n0tform3	8:1c6281289d67	192	}
n0tform3	8:1c6281289d67	193	else if (USARTx == USART3)
n0tform3	8:1c6281289d67	194	{
n0tform3	8:1c6281289d67	195	RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
n0tform3	8:1c6281289d67	196	RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
n0tform3	8:1c6281289d67	197	}
n0tform3	8:1c6281289d67	198	else if (USARTx == UART4)
n0tform3	8:1c6281289d67	199	{
n0tform3	8:1c6281289d67	200	RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
n0tform3	8:1c6281289d67	201	RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
n0tform3	8:1c6281289d67	202	}
n0tform3	8:1c6281289d67	203	else if (USARTx == UART5)
n0tform3	8:1c6281289d67	204	{
n0tform3	8:1c6281289d67	205	RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
n0tform3	8:1c6281289d67	206	RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
n0tform3	8:1c6281289d67	207	}
n0tform3	8:1c6281289d67	208	else
n0tform3	8:1c6281289d67	209	{
n0tform3	8:1c6281289d67	210	if (USARTx == USART6)
n0tform3	8:1c6281289d67	211	{
n0tform3	8:1c6281289d67	212	RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
n0tform3	8:1c6281289d67	213	RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
n0tform3	8:1c6281289d67	214	}
n0tform3	8:1c6281289d67	215	}
n0tform3	8:1c6281289d67	216	}
n0tform3	8:1c6281289d67	217
n0tform3	8:1c6281289d67	218	/**
n0tform3	8:1c6281289d67	219	* @brief Initializes the USARTx peripheral according to the specified
n0tform3	8:1c6281289d67	220	* parameters in the USART_InitStruct .
n0tform3	8:1c6281289d67	221	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	222	* UART peripheral.
n0tform3	8:1c6281289d67	223	* @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
n0tform3	8:1c6281289d67	224	* the configuration information for the specified USART peripheral.
n0tform3	8:1c6281289d67	225	* @retval None
n0tform3	8:1c6281289d67	226	*/
n0tform3	8:1c6281289d67	227	void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
n0tform3	8:1c6281289d67	228	{
n0tform3	8:1c6281289d67	229	uint32_t tmpreg = 0x00, apbclock = 0x00;
n0tform3	8:1c6281289d67	230	uint32_t integerdivider = 0x00;
n0tform3	8:1c6281289d67	231	uint32_t fractionaldivider = 0x00;
n0tform3	8:1c6281289d67	232	RCC_ClocksTypeDef RCC_ClocksStatus;
n0tform3	8:1c6281289d67	233
n0tform3	8:1c6281289d67	234	/* Check the parameters */
n0tform3	8:1c6281289d67	235	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	236	assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
n0tform3	8:1c6281289d67	237	assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
n0tform3	8:1c6281289d67	238	assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
n0tform3	8:1c6281289d67	239	assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
n0tform3	8:1c6281289d67	240	assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
n0tform3	8:1c6281289d67	241	assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
n0tform3	8:1c6281289d67	242
n0tform3	8:1c6281289d67	243	/* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
n0tform3	8:1c6281289d67	244	if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
n0tform3	8:1c6281289d67	245	{
n0tform3	8:1c6281289d67	246	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	247	}
n0tform3	8:1c6281289d67	248
n0tform3	8:1c6281289d67	249	/---------------------------- USART CR2 Configuration -----------------------/
n0tform3	8:1c6281289d67	250	tmpreg = USARTx->CR2;
n0tform3	8:1c6281289d67	251
n0tform3	8:1c6281289d67	252	/* Clear STOP[13:12] bits */
n0tform3	8:1c6281289d67	253	tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
n0tform3	8:1c6281289d67	254
n0tform3	8:1c6281289d67	255	/* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
n0tform3	8:1c6281289d67	256	Set STOP[13:12] bits according to USART_StopBits value */
n0tform3	8:1c6281289d67	257	tmpreg \|= (uint32_t)USART_InitStruct->USART_StopBits;
n0tform3	8:1c6281289d67	258
n0tform3	8:1c6281289d67	259	/* Write to USART CR2 */
n0tform3	8:1c6281289d67	260	USARTx->CR2 = (uint16_t)tmpreg;
n0tform3	8:1c6281289d67	261
n0tform3	8:1c6281289d67	262	/---------------------------- USART CR1 Configuration -----------------------/
n0tform3	8:1c6281289d67	263	tmpreg = USARTx->CR1;
n0tform3	8:1c6281289d67	264
n0tform3	8:1c6281289d67	265	/* Clear M, PCE, PS, TE and RE bits */
n0tform3	8:1c6281289d67	266	tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
n0tform3	8:1c6281289d67	267
n0tform3	8:1c6281289d67	268	/* Configure the USART Word Length, Parity and mode:
n0tform3	8:1c6281289d67	269	Set the M bits according to USART_WordLength value
n0tform3	8:1c6281289d67	270	Set PCE and PS bits according to USART_Parity value
n0tform3	8:1c6281289d67	271	Set TE and RE bits according to USART_Mode value */
n0tform3	8:1c6281289d67	272	tmpreg \|= (uint32_t)USART_InitStruct->USART_WordLength \| USART_InitStruct->USART_Parity \|
n0tform3	8:1c6281289d67	273	USART_InitStruct->USART_Mode;
n0tform3	8:1c6281289d67	274
n0tform3	8:1c6281289d67	275	/* Write to USART CR1 */
n0tform3	8:1c6281289d67	276	USARTx->CR1 = (uint16_t)tmpreg;
n0tform3	8:1c6281289d67	277
n0tform3	8:1c6281289d67	278	/---------------------------- USART CR3 Configuration -----------------------/
n0tform3	8:1c6281289d67	279	tmpreg = USARTx->CR3;
n0tform3	8:1c6281289d67	280
n0tform3	8:1c6281289d67	281	/* Clear CTSE and RTSE bits */
n0tform3	8:1c6281289d67	282	tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
n0tform3	8:1c6281289d67	283
n0tform3	8:1c6281289d67	284	/* Configure the USART HFC :
n0tform3	8:1c6281289d67	285	Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
n0tform3	8:1c6281289d67	286	tmpreg \|= USART_InitStruct->USART_HardwareFlowControl;
n0tform3	8:1c6281289d67	287
n0tform3	8:1c6281289d67	288	/* Write to USART CR3 */
n0tform3	8:1c6281289d67	289	USARTx->CR3 = (uint16_t)tmpreg;
n0tform3	8:1c6281289d67	290
n0tform3	8:1c6281289d67	291	/---------------------------- USART BRR Configuration -----------------------/
n0tform3	8:1c6281289d67	292	/* Configure the USART Baud Rate */
n0tform3	8:1c6281289d67	293	RCC_GetClocksFreq(&RCC_ClocksStatus);
n0tform3	8:1c6281289d67	294
n0tform3	8:1c6281289d67	295	if ((USARTx == USART1) \|\| (USARTx == USART6))
n0tform3	8:1c6281289d67	296	{
n0tform3	8:1c6281289d67	297	apbclock = RCC_ClocksStatus.PCLK2_Frequency;
n0tform3	8:1c6281289d67	298	}
n0tform3	8:1c6281289d67	299	else
n0tform3	8:1c6281289d67	300	{
n0tform3	8:1c6281289d67	301	apbclock = RCC_ClocksStatus.PCLK1_Frequency;
n0tform3	8:1c6281289d67	302	}
n0tform3	8:1c6281289d67	303
n0tform3	8:1c6281289d67	304	/* Determine the integer part */
n0tform3	8:1c6281289d67	305	if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
n0tform3	8:1c6281289d67	306	{
n0tform3	8:1c6281289d67	307	/* Integer part computing in case Oversampling mode is 8 Samples */
n0tform3	8:1c6281289d67	308	integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
n0tform3	8:1c6281289d67	309	}
n0tform3	8:1c6281289d67	310	else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
n0tform3	8:1c6281289d67	311	{
n0tform3	8:1c6281289d67	312	/* Integer part computing in case Oversampling mode is 16 Samples */
n0tform3	8:1c6281289d67	313	integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
n0tform3	8:1c6281289d67	314	}
n0tform3	8:1c6281289d67	315	tmpreg = (integerdivider / 100) << 4;
n0tform3	8:1c6281289d67	316
n0tform3	8:1c6281289d67	317	/* Determine the fractional part */
n0tform3	8:1c6281289d67	318	fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
n0tform3	8:1c6281289d67	319
n0tform3	8:1c6281289d67	320	/* Implement the fractional part in the register */
n0tform3	8:1c6281289d67	321	if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
n0tform3	8:1c6281289d67	322	{
n0tform3	8:1c6281289d67	323	tmpreg \|= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
n0tform3	8:1c6281289d67	324	}
n0tform3	8:1c6281289d67	325	else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
n0tform3	8:1c6281289d67	326	{
n0tform3	8:1c6281289d67	327	tmpreg \|= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
n0tform3	8:1c6281289d67	328	}
n0tform3	8:1c6281289d67	329
n0tform3	8:1c6281289d67	330	/* Write to USART BRR register */
n0tform3	8:1c6281289d67	331	USARTx->BRR = (uint16_t)tmpreg;
n0tform3	8:1c6281289d67	332	}
n0tform3	8:1c6281289d67	333
n0tform3	8:1c6281289d67	334	/**
n0tform3	8:1c6281289d67	335	* @brief Fills each USART_InitStruct member with its default value.
n0tform3	8:1c6281289d67	336	* @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will
n0tform3	8:1c6281289d67	337	* be initialized.
n0tform3	8:1c6281289d67	338	* @retval None
n0tform3	8:1c6281289d67	339	*/
n0tform3	8:1c6281289d67	340	void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
n0tform3	8:1c6281289d67	341	{
n0tform3	8:1c6281289d67	342	/* USART_InitStruct members default value */
n0tform3	8:1c6281289d67	343	USART_InitStruct->USART_BaudRate = 9600;
n0tform3	8:1c6281289d67	344	USART_InitStruct->USART_WordLength = USART_WordLength_8b;
n0tform3	8:1c6281289d67	345	USART_InitStruct->USART_StopBits = USART_StopBits_1;
n0tform3	8:1c6281289d67	346	USART_InitStruct->USART_Parity = USART_Parity_No ;
n0tform3	8:1c6281289d67	347	USART_InitStruct->USART_Mode = USART_Mode_Rx \| USART_Mode_Tx;
n0tform3	8:1c6281289d67	348	USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
n0tform3	8:1c6281289d67	349	}
n0tform3	8:1c6281289d67	350
n0tform3	8:1c6281289d67	351	/**
n0tform3	8:1c6281289d67	352	* @brief Initializes the USARTx peripheral Clock according to the
n0tform3	8:1c6281289d67	353	* specified parameters in the USART_ClockInitStruct .
n0tform3	8:1c6281289d67	354	* @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
n0tform3	8:1c6281289d67	355	* @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
n0tform3	8:1c6281289d67	356	* contains the configuration information for the specified USART peripheral.
n0tform3	8:1c6281289d67	357	* @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
n0tform3	8:1c6281289d67	358	* @retval None
n0tform3	8:1c6281289d67	359	*/
n0tform3	8:1c6281289d67	360	void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
n0tform3	8:1c6281289d67	361	{
n0tform3	8:1c6281289d67	362	uint32_t tmpreg = 0x00;
n0tform3	8:1c6281289d67	363	/* Check the parameters */
n0tform3	8:1c6281289d67	364	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	365	assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
n0tform3	8:1c6281289d67	366	assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
n0tform3	8:1c6281289d67	367	assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
n0tform3	8:1c6281289d67	368	assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
n0tform3	8:1c6281289d67	369
n0tform3	8:1c6281289d67	370	/---------------------------- USART CR2 Configuration -----------------------/
n0tform3	8:1c6281289d67	371	tmpreg = USARTx->CR2;
n0tform3	8:1c6281289d67	372	/* Clear CLKEN, CPOL, CPHA and LBCL bits */
n0tform3	8:1c6281289d67	373	tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
n0tform3	8:1c6281289d67	374	/* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
n0tform3	8:1c6281289d67	375	/* Set CLKEN bit according to USART_Clock value */
n0tform3	8:1c6281289d67	376	/* Set CPOL bit according to USART_CPOL value */
n0tform3	8:1c6281289d67	377	/* Set CPHA bit according to USART_CPHA value */
n0tform3	8:1c6281289d67	378	/* Set LBCL bit according to USART_LastBit value */
n0tform3	8:1c6281289d67	379	tmpreg \|= (uint32_t)USART_ClockInitStruct->USART_Clock \| USART_ClockInitStruct->USART_CPOL \|
n0tform3	8:1c6281289d67	380	USART_ClockInitStruct->USART_CPHA \| USART_ClockInitStruct->USART_LastBit;
n0tform3	8:1c6281289d67	381	/* Write to USART CR2 */
n0tform3	8:1c6281289d67	382	USARTx->CR2 = (uint16_t)tmpreg;
n0tform3	8:1c6281289d67	383	}
n0tform3	8:1c6281289d67	384
n0tform3	8:1c6281289d67	385	/**
n0tform3	8:1c6281289d67	386	* @brief Fills each USART_ClockInitStruct member with its default value.
n0tform3	8:1c6281289d67	387	* @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
n0tform3	8:1c6281289d67	388	* which will be initialized.
n0tform3	8:1c6281289d67	389	* @retval None
n0tform3	8:1c6281289d67	390	*/
n0tform3	8:1c6281289d67	391	void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
n0tform3	8:1c6281289d67	392	{
n0tform3	8:1c6281289d67	393	/* USART_ClockInitStruct members default value */
n0tform3	8:1c6281289d67	394	USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
n0tform3	8:1c6281289d67	395	USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
n0tform3	8:1c6281289d67	396	USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
n0tform3	8:1c6281289d67	397	USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
n0tform3	8:1c6281289d67	398	}
n0tform3	8:1c6281289d67	399
n0tform3	8:1c6281289d67	400	/**
n0tform3	8:1c6281289d67	401	* @brief Enables or disables the specified USART peripheral.
n0tform3	8:1c6281289d67	402	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	403	* UART peripheral.
n0tform3	8:1c6281289d67	404	* @param NewState: new state of the USARTx peripheral.
n0tform3	8:1c6281289d67	405	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	406	* @retval None
n0tform3	8:1c6281289d67	407	*/
n0tform3	8:1c6281289d67	408	void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	409	{
n0tform3	8:1c6281289d67	410	/* Check the parameters */
n0tform3	8:1c6281289d67	411	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	412	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	413
n0tform3	8:1c6281289d67	414	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	415	{
n0tform3	8:1c6281289d67	416	/* Enable the selected USART by setting the UE bit in the CR1 register */
n0tform3	8:1c6281289d67	417	USARTx->CR1 \|= USART_CR1_UE;
n0tform3	8:1c6281289d67	418	}
n0tform3	8:1c6281289d67	419	else
n0tform3	8:1c6281289d67	420	{
n0tform3	8:1c6281289d67	421	/* Disable the selected USART by clearing the UE bit in the CR1 register */
n0tform3	8:1c6281289d67	422	USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
n0tform3	8:1c6281289d67	423	}
n0tform3	8:1c6281289d67	424	}
n0tform3	8:1c6281289d67	425
n0tform3	8:1c6281289d67	426	/**
n0tform3	8:1c6281289d67	427	* @brief Sets the system clock prescaler.
n0tform3	8:1c6281289d67	428	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	429	* UART peripheral.
n0tform3	8:1c6281289d67	430	* @param USART_Prescaler: specifies the prescaler clock.
n0tform3	8:1c6281289d67	431	* @note The function is used for IrDA mode with UART4 and UART5.
n0tform3	8:1c6281289d67	432	* @retval None
n0tform3	8:1c6281289d67	433	*/
n0tform3	8:1c6281289d67	434	void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
n0tform3	8:1c6281289d67	435	{
n0tform3	8:1c6281289d67	436	/* Check the parameters */
n0tform3	8:1c6281289d67	437	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	438
n0tform3	8:1c6281289d67	439	/* Clear the USART prescaler */
n0tform3	8:1c6281289d67	440	USARTx->GTPR &= USART_GTPR_GT;
n0tform3	8:1c6281289d67	441	/* Set the USART prescaler */
n0tform3	8:1c6281289d67	442	USARTx->GTPR \|= USART_Prescaler;
n0tform3	8:1c6281289d67	443	}
n0tform3	8:1c6281289d67	444
n0tform3	8:1c6281289d67	445	/**
n0tform3	8:1c6281289d67	446	* @brief Enables or disables the USART's 8x oversampling mode.
n0tform3	8:1c6281289d67	447	* @note This function has to be called before calling USART_Init() function
n0tform3	8:1c6281289d67	448	* in order to have correct baudrate Divider value.
n0tform3	8:1c6281289d67	449	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	450	* UART peripheral.
n0tform3	8:1c6281289d67	451	* @param NewState: new state of the USART 8x oversampling mode.
n0tform3	8:1c6281289d67	452	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	453	* @retval None
n0tform3	8:1c6281289d67	454	*/
n0tform3	8:1c6281289d67	455	void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	456	{
n0tform3	8:1c6281289d67	457	/* Check the parameters */
n0tform3	8:1c6281289d67	458	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	459	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	460
n0tform3	8:1c6281289d67	461	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	462	{
n0tform3	8:1c6281289d67	463	/* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
n0tform3	8:1c6281289d67	464	USARTx->CR1 \|= USART_CR1_OVER8;
n0tform3	8:1c6281289d67	465	}
n0tform3	8:1c6281289d67	466	else
n0tform3	8:1c6281289d67	467	{
n0tform3	8:1c6281289d67	468	/* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
n0tform3	8:1c6281289d67	469	USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
n0tform3	8:1c6281289d67	470	}
n0tform3	8:1c6281289d67	471	}
n0tform3	8:1c6281289d67	472
n0tform3	8:1c6281289d67	473	/**
n0tform3	8:1c6281289d67	474	* @brief Enables or disables the USART's one bit sampling method.
n0tform3	8:1c6281289d67	475	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	476	* UART peripheral.
n0tform3	8:1c6281289d67	477	* @param NewState: new state of the USART one bit sampling method.
n0tform3	8:1c6281289d67	478	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	479	* @retval None
n0tform3	8:1c6281289d67	480	*/
n0tform3	8:1c6281289d67	481	void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	482	{
n0tform3	8:1c6281289d67	483	/* Check the parameters */
n0tform3	8:1c6281289d67	484	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	485	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	486
n0tform3	8:1c6281289d67	487	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	488	{
n0tform3	8:1c6281289d67	489	/* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
n0tform3	8:1c6281289d67	490	USARTx->CR3 \|= USART_CR3_ONEBIT;
n0tform3	8:1c6281289d67	491	}
n0tform3	8:1c6281289d67	492	else
n0tform3	8:1c6281289d67	493	{
n0tform3	8:1c6281289d67	494	/* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
n0tform3	8:1c6281289d67	495	USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
n0tform3	8:1c6281289d67	496	}
n0tform3	8:1c6281289d67	497	}
n0tform3	8:1c6281289d67	498
n0tform3	8:1c6281289d67	499	/**
n0tform3	8:1c6281289d67	500	* @}
n0tform3	8:1c6281289d67	501	*/
n0tform3	8:1c6281289d67	502
n0tform3	8:1c6281289d67	503	/** @defgroup USART_Group2 Data transfers functions
n0tform3	8:1c6281289d67	504	* @brief Data transfers functions
n0tform3	8:1c6281289d67	505	*
n0tform3	8:1c6281289d67	506	@verbatim
n0tform3	8:1c6281289d67	507	===============================================================================
n0tform3	8:1c6281289d67	508	Data transfers functions
n0tform3	8:1c6281289d67	509	===============================================================================
n0tform3	8:1c6281289d67	510
n0tform3	8:1c6281289d67	511	This subsection provides a set of functions allowing to manage the USART data
n0tform3	8:1c6281289d67	512	transfers.
n0tform3	8:1c6281289d67	513
n0tform3	8:1c6281289d67	514	During an USART reception, data shifts in least significant bit first through
n0tform3	8:1c6281289d67	515	the RX pin. In this mode, the USART_DR register consists of a buffer (RDR)
n0tform3	8:1c6281289d67	516	between the internal bus and the received shift register.
n0tform3	8:1c6281289d67	517
n0tform3	8:1c6281289d67	518	When a transmission is taking place, a write instruction to the USART_DR register
n0tform3	8:1c6281289d67	519	stores the data in the TDR register and which is copied in the shift register
n0tform3	8:1c6281289d67	520	at the end of the current transmission.
n0tform3	8:1c6281289d67	521
n0tform3	8:1c6281289d67	522	The read access of the USART_DR register can be done using the USART_ReceiveData()
n0tform3	8:1c6281289d67	523	function and returns the RDR buffered value. Whereas a write access to the USART_DR
n0tform3	8:1c6281289d67	524	can be done using USART_SendData() function and stores the written data into
n0tform3	8:1c6281289d67	525	TDR buffer.
n0tform3	8:1c6281289d67	526
n0tform3	8:1c6281289d67	527	@endverbatim
n0tform3	8:1c6281289d67	528	* @{
n0tform3	8:1c6281289d67	529	*/
n0tform3	8:1c6281289d67	530
n0tform3	8:1c6281289d67	531	/**
n0tform3	8:1c6281289d67	532	* @brief Transmits single data through the USARTx peripheral.
n0tform3	8:1c6281289d67	533	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	534	* UART peripheral.
n0tform3	8:1c6281289d67	535	* @param Data: the data to transmit.
n0tform3	8:1c6281289d67	536	* @retval None
n0tform3	8:1c6281289d67	537	*/
n0tform3	8:1c6281289d67	538	void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
n0tform3	8:1c6281289d67	539	{
n0tform3	8:1c6281289d67	540	/* Check the parameters */
n0tform3	8:1c6281289d67	541	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	542	assert_param(IS_USART_DATA(Data));
n0tform3	8:1c6281289d67	543
n0tform3	8:1c6281289d67	544	/* Transmit Data */
n0tform3	8:1c6281289d67	545	USARTx->DR = (Data & (uint16_t)0x01FF);
n0tform3	8:1c6281289d67	546	}
n0tform3	8:1c6281289d67	547
n0tform3	8:1c6281289d67	548	/**
n0tform3	8:1c6281289d67	549	* @brief Returns the most recent received data by the USARTx peripheral.
n0tform3	8:1c6281289d67	550	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	551	* UART peripheral.
n0tform3	8:1c6281289d67	552	* @retval The received data.
n0tform3	8:1c6281289d67	553	*/
n0tform3	8:1c6281289d67	554	uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
n0tform3	8:1c6281289d67	555	{
n0tform3	8:1c6281289d67	556	/* Check the parameters */
n0tform3	8:1c6281289d67	557	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	558
n0tform3	8:1c6281289d67	559	/* Receive Data */
n0tform3	8:1c6281289d67	560	return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
n0tform3	8:1c6281289d67	561	}
n0tform3	8:1c6281289d67	562
n0tform3	8:1c6281289d67	563	/**
n0tform3	8:1c6281289d67	564	* @}
n0tform3	8:1c6281289d67	565	*/
n0tform3	8:1c6281289d67	566
n0tform3	8:1c6281289d67	567	/** @defgroup USART_Group3 MultiProcessor Communication functions
n0tform3	8:1c6281289d67	568	* @brief Multi-Processor Communication functions
n0tform3	8:1c6281289d67	569	*
n0tform3	8:1c6281289d67	570	@verbatim
n0tform3	8:1c6281289d67	571	===============================================================================
n0tform3	8:1c6281289d67	572	Multi-Processor Communication functions
n0tform3	8:1c6281289d67	573	===============================================================================
n0tform3	8:1c6281289d67	574
n0tform3	8:1c6281289d67	575	This subsection provides a set of functions allowing to manage the USART
n0tform3	8:1c6281289d67	576	multiprocessor communication.
n0tform3	8:1c6281289d67	577
n0tform3	8:1c6281289d67	578	For instance one of the USARTs can be the master, its TX output is connected to
n0tform3	8:1c6281289d67	579	the RX input of the other USART. The others are slaves, their respective TX outputs
n0tform3	8:1c6281289d67	580	are logically ANDed together and connected to the RX input of the master.
n0tform3	8:1c6281289d67	581
n0tform3	8:1c6281289d67	582	USART multiprocessor communication is possible through the following procedure:
n0tform3	8:1c6281289d67	583	1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter
n0tform3	8:1c6281289d67	584	or Mode receiver and hardware flow control values using the USART_Init()
n0tform3	8:1c6281289d67	585	function.
n0tform3	8:1c6281289d67	586	2. Configures the USART address using the USART_SetAddress() function.
n0tform3	8:1c6281289d67	587	3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
n0tform3	8:1c6281289d67	588	using USART_WakeUpConfig() function only for the slaves.
n0tform3	8:1c6281289d67	589	4. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	590	5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
n0tform3	8:1c6281289d67	591
n0tform3	8:1c6281289d67	592	The USART Slave exit from mute mode when receive the wake up condition.
n0tform3	8:1c6281289d67	593
n0tform3	8:1c6281289d67	594	@endverbatim
n0tform3	8:1c6281289d67	595	* @{
n0tform3	8:1c6281289d67	596	*/
n0tform3	8:1c6281289d67	597
n0tform3	8:1c6281289d67	598	/**
n0tform3	8:1c6281289d67	599	* @brief Sets the address of the USART node.
n0tform3	8:1c6281289d67	600	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	601	* UART peripheral.
n0tform3	8:1c6281289d67	602	* @param USART_Address: Indicates the address of the USART node.
n0tform3	8:1c6281289d67	603	* @retval None
n0tform3	8:1c6281289d67	604	*/
n0tform3	8:1c6281289d67	605	void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
n0tform3	8:1c6281289d67	606	{
n0tform3	8:1c6281289d67	607	/* Check the parameters */
n0tform3	8:1c6281289d67	608	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	609	assert_param(IS_USART_ADDRESS(USART_Address));
n0tform3	8:1c6281289d67	610
n0tform3	8:1c6281289d67	611	/* Clear the USART address */
n0tform3	8:1c6281289d67	612	USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
n0tform3	8:1c6281289d67	613	/* Set the USART address node */
n0tform3	8:1c6281289d67	614	USARTx->CR2 \|= USART_Address;
n0tform3	8:1c6281289d67	615	}
n0tform3	8:1c6281289d67	616
n0tform3	8:1c6281289d67	617	/**
n0tform3	8:1c6281289d67	618	* @brief Determines if the USART is in mute mode or not.
n0tform3	8:1c6281289d67	619	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	620	* UART peripheral.
n0tform3	8:1c6281289d67	621	* @param NewState: new state of the USART mute mode.
n0tform3	8:1c6281289d67	622	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	623	* @retval None
n0tform3	8:1c6281289d67	624	*/
n0tform3	8:1c6281289d67	625	void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	626	{
n0tform3	8:1c6281289d67	627	/* Check the parameters */
n0tform3	8:1c6281289d67	628	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	629	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	630
n0tform3	8:1c6281289d67	631	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	632	{
n0tform3	8:1c6281289d67	633	/* Enable the USART mute mode by setting the RWU bit in the CR1 register */
n0tform3	8:1c6281289d67	634	USARTx->CR1 \|= USART_CR1_RWU;
n0tform3	8:1c6281289d67	635	}
n0tform3	8:1c6281289d67	636	else
n0tform3	8:1c6281289d67	637	{
n0tform3	8:1c6281289d67	638	/* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
n0tform3	8:1c6281289d67	639	USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
n0tform3	8:1c6281289d67	640	}
n0tform3	8:1c6281289d67	641	}
n0tform3	8:1c6281289d67	642	/**
n0tform3	8:1c6281289d67	643	* @brief Selects the USART WakeUp method.
n0tform3	8:1c6281289d67	644	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	645	* UART peripheral.
n0tform3	8:1c6281289d67	646	* @param USART_WakeUp: specifies the USART wakeup method.
n0tform3	8:1c6281289d67	647	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	648	* @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
n0tform3	8:1c6281289d67	649	* @arg USART_WakeUp_AddressMark: WakeUp by an address mark
n0tform3	8:1c6281289d67	650	* @retval None
n0tform3	8:1c6281289d67	651	*/
n0tform3	8:1c6281289d67	652	void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
n0tform3	8:1c6281289d67	653	{
n0tform3	8:1c6281289d67	654	/* Check the parameters */
n0tform3	8:1c6281289d67	655	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	656	assert_param(IS_USART_WAKEUP(USART_WakeUp));
n0tform3	8:1c6281289d67	657
n0tform3	8:1c6281289d67	658	USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
n0tform3	8:1c6281289d67	659	USARTx->CR1 \|= USART_WakeUp;
n0tform3	8:1c6281289d67	660	}
n0tform3	8:1c6281289d67	661
n0tform3	8:1c6281289d67	662	/**
n0tform3	8:1c6281289d67	663	* @}
n0tform3	8:1c6281289d67	664	*/
n0tform3	8:1c6281289d67	665
n0tform3	8:1c6281289d67	666	/** @defgroup USART_Group4 LIN mode functions
n0tform3	8:1c6281289d67	667	* @brief LIN mode functions
n0tform3	8:1c6281289d67	668	*
n0tform3	8:1c6281289d67	669	@verbatim
n0tform3	8:1c6281289d67	670	===============================================================================
n0tform3	8:1c6281289d67	671	LIN mode functions
n0tform3	8:1c6281289d67	672	===============================================================================
n0tform3	8:1c6281289d67	673
n0tform3	8:1c6281289d67	674	This subsection provides a set of functions allowing to manage the USART LIN
n0tform3	8:1c6281289d67	675	Mode communication.
n0tform3	8:1c6281289d67	676
n0tform3	8:1c6281289d67	677	In LIN mode, 8-bit data format with 1 stop bit is required in accordance with
n0tform3	8:1c6281289d67	678	the LIN standard.
n0tform3	8:1c6281289d67	679
n0tform3	8:1c6281289d67	680	Only this LIN Feature is supported by the USART IP:
n0tform3	8:1c6281289d67	681	- LIN Master Synchronous Break send capability and LIN slave break detection
n0tform3	8:1c6281289d67	682	capability : 13-bit break generation and 10/11 bit break detection
n0tform3	8:1c6281289d67	683
n0tform3	8:1c6281289d67	684
n0tform3	8:1c6281289d67	685	USART LIN Master transmitter communication is possible through the following procedure:
n0tform3	8:1c6281289d67	686	1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
n0tform3	8:1c6281289d67	687	Mode transmitter or Mode receiver and hardware flow control values using
n0tform3	8:1c6281289d67	688	the USART_Init() function.
n0tform3	8:1c6281289d67	689	2. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	690	3. Enable the LIN mode using the USART_LINCmd() function.
n0tform3	8:1c6281289d67	691	4. Send the break character using USART_SendBreak() function.
n0tform3	8:1c6281289d67	692
n0tform3	8:1c6281289d67	693	USART LIN Master receiver communication is possible through the following procedure:
n0tform3	8:1c6281289d67	694	1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
n0tform3	8:1c6281289d67	695	Mode transmitter or Mode receiver and hardware flow control values using
n0tform3	8:1c6281289d67	696	the USART_Init() function.
n0tform3	8:1c6281289d67	697	2. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	698	3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()
n0tform3	8:1c6281289d67	699	function.
n0tform3	8:1c6281289d67	700	4. Enable the LIN mode using the USART_LINCmd() function.
n0tform3	8:1c6281289d67	701
n0tform3	8:1c6281289d67	702
n0tform3	8:1c6281289d67	703	@note In LIN mode, the following bits must be kept cleared:
n0tform3	8:1c6281289d67	704	- CLKEN in the USART_CR2 register,
n0tform3	8:1c6281289d67	705	- STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
n0tform3	8:1c6281289d67	706
n0tform3	8:1c6281289d67	707	@endverbatim
n0tform3	8:1c6281289d67	708	* @{
n0tform3	8:1c6281289d67	709	*/
n0tform3	8:1c6281289d67	710
n0tform3	8:1c6281289d67	711	/**
n0tform3	8:1c6281289d67	712	* @brief Sets the USART LIN Break detection length.
n0tform3	8:1c6281289d67	713	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	714	* UART peripheral.
n0tform3	8:1c6281289d67	715	* @param USART_LINBreakDetectLength: specifies the LIN break detection length.
n0tform3	8:1c6281289d67	716	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	717	* @arg USART_LINBreakDetectLength_10b: 10-bit break detection
n0tform3	8:1c6281289d67	718	* @arg USART_LINBreakDetectLength_11b: 11-bit break detection
n0tform3	8:1c6281289d67	719	* @retval None
n0tform3	8:1c6281289d67	720	*/
n0tform3	8:1c6281289d67	721	void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
n0tform3	8:1c6281289d67	722	{
n0tform3	8:1c6281289d67	723	/* Check the parameters */
n0tform3	8:1c6281289d67	724	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	725	assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
n0tform3	8:1c6281289d67	726
n0tform3	8:1c6281289d67	727	USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
n0tform3	8:1c6281289d67	728	USARTx->CR2 \|= USART_LINBreakDetectLength;
n0tform3	8:1c6281289d67	729	}
n0tform3	8:1c6281289d67	730
n0tform3	8:1c6281289d67	731	/**
n0tform3	8:1c6281289d67	732	* @brief Enables or disables the USART's LIN mode.
n0tform3	8:1c6281289d67	733	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	734	* UART peripheral.
n0tform3	8:1c6281289d67	735	* @param NewState: new state of the USART LIN mode.
n0tform3	8:1c6281289d67	736	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	737	* @retval None
n0tform3	8:1c6281289d67	738	*/
n0tform3	8:1c6281289d67	739	void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	740	{
n0tform3	8:1c6281289d67	741	/* Check the parameters */
n0tform3	8:1c6281289d67	742	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	743	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	744
n0tform3	8:1c6281289d67	745	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	746	{
n0tform3	8:1c6281289d67	747	/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
n0tform3	8:1c6281289d67	748	USARTx->CR2 \|= USART_CR2_LINEN;
n0tform3	8:1c6281289d67	749	}
n0tform3	8:1c6281289d67	750	else
n0tform3	8:1c6281289d67	751	{
n0tform3	8:1c6281289d67	752	/* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
n0tform3	8:1c6281289d67	753	USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
n0tform3	8:1c6281289d67	754	}
n0tform3	8:1c6281289d67	755	}
n0tform3	8:1c6281289d67	756
n0tform3	8:1c6281289d67	757	/**
n0tform3	8:1c6281289d67	758	* @brief Transmits break characters.
n0tform3	8:1c6281289d67	759	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	760	* UART peripheral.
n0tform3	8:1c6281289d67	761	* @retval None
n0tform3	8:1c6281289d67	762	*/
n0tform3	8:1c6281289d67	763	void USART_SendBreak(USART_TypeDef* USARTx)
n0tform3	8:1c6281289d67	764	{
n0tform3	8:1c6281289d67	765	/* Check the parameters */
n0tform3	8:1c6281289d67	766	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	767
n0tform3	8:1c6281289d67	768	/* Send break characters */
n0tform3	8:1c6281289d67	769	USARTx->CR1 \|= USART_CR1_SBK;
n0tform3	8:1c6281289d67	770	}
n0tform3	8:1c6281289d67	771
n0tform3	8:1c6281289d67	772	/**
n0tform3	8:1c6281289d67	773	* @}
n0tform3	8:1c6281289d67	774	*/
n0tform3	8:1c6281289d67	775
n0tform3	8:1c6281289d67	776	/** @defgroup USART_Group5 Halfduplex mode function
n0tform3	8:1c6281289d67	777	* @brief Half-duplex mode function
n0tform3	8:1c6281289d67	778	*
n0tform3	8:1c6281289d67	779	@verbatim
n0tform3	8:1c6281289d67	780	===============================================================================
n0tform3	8:1c6281289d67	781	Half-duplex mode function
n0tform3	8:1c6281289d67	782	===============================================================================
n0tform3	8:1c6281289d67	783
n0tform3	8:1c6281289d67	784	This subsection provides a set of functions allowing to manage the USART
n0tform3	8:1c6281289d67	785	Half-duplex communication.
n0tform3	8:1c6281289d67	786
n0tform3	8:1c6281289d67	787	The USART can be configured to follow a single-wire half-duplex protocol where
n0tform3	8:1c6281289d67	788	the TX and RX lines are internally connected.
n0tform3	8:1c6281289d67	789
n0tform3	8:1c6281289d67	790	USART Half duplex communication is possible through the following procedure:
n0tform3	8:1c6281289d67	791	1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
n0tform3	8:1c6281289d67	792	or Mode receiver and hardware flow control values using the USART_Init()
n0tform3	8:1c6281289d67	793	function.
n0tform3	8:1c6281289d67	794	2. Configures the USART address using the USART_SetAddress() function.
n0tform3	8:1c6281289d67	795	3. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	796	4. Enable the half duplex mode using USART_HalfDuplexCmd() function.
n0tform3	8:1c6281289d67	797
n0tform3	8:1c6281289d67	798
n0tform3	8:1c6281289d67	799	@note The RX pin is no longer used
n0tform3	8:1c6281289d67	800	@note In Half-duplex mode the following bits must be kept cleared:
n0tform3	8:1c6281289d67	801	- LINEN and CLKEN bits in the USART_CR2 register.
n0tform3	8:1c6281289d67	802	- SCEN and IREN bits in the USART_CR3 register.
n0tform3	8:1c6281289d67	803
n0tform3	8:1c6281289d67	804	@endverbatim
n0tform3	8:1c6281289d67	805	* @{
n0tform3	8:1c6281289d67	806	*/
n0tform3	8:1c6281289d67	807
n0tform3	8:1c6281289d67	808	/**
n0tform3	8:1c6281289d67	809	* @brief Enables or disables the USART's Half Duplex communication.
n0tform3	8:1c6281289d67	810	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	811	* UART peripheral.
n0tform3	8:1c6281289d67	812	* @param NewState: new state of the USART Communication.
n0tform3	8:1c6281289d67	813	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	814	* @retval None
n0tform3	8:1c6281289d67	815	*/
n0tform3	8:1c6281289d67	816	void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	817	{
n0tform3	8:1c6281289d67	818	/* Check the parameters */
n0tform3	8:1c6281289d67	819	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	820	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	821
n0tform3	8:1c6281289d67	822	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	823	{
n0tform3	8:1c6281289d67	824	/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
n0tform3	8:1c6281289d67	825	USARTx->CR3 \|= USART_CR3_HDSEL;
n0tform3	8:1c6281289d67	826	}
n0tform3	8:1c6281289d67	827	else
n0tform3	8:1c6281289d67	828	{
n0tform3	8:1c6281289d67	829	/* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
n0tform3	8:1c6281289d67	830	USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
n0tform3	8:1c6281289d67	831	}
n0tform3	8:1c6281289d67	832	}
n0tform3	8:1c6281289d67	833
n0tform3	8:1c6281289d67	834	/**
n0tform3	8:1c6281289d67	835	* @}
n0tform3	8:1c6281289d67	836	*/
n0tform3	8:1c6281289d67	837
n0tform3	8:1c6281289d67	838
n0tform3	8:1c6281289d67	839	/** @defgroup USART_Group6 Smartcard mode functions
n0tform3	8:1c6281289d67	840	* @brief Smartcard mode functions
n0tform3	8:1c6281289d67	841	*
n0tform3	8:1c6281289d67	842	@verbatim
n0tform3	8:1c6281289d67	843	===============================================================================
n0tform3	8:1c6281289d67	844	Smartcard mode functions
n0tform3	8:1c6281289d67	845	===============================================================================
n0tform3	8:1c6281289d67	846
n0tform3	8:1c6281289d67	847	This subsection provides a set of functions allowing to manage the USART
n0tform3	8:1c6281289d67	848	Smartcard communication.
n0tform3	8:1c6281289d67	849
n0tform3	8:1c6281289d67	850	The Smartcard interface is designed to support asynchronous protocol Smartcards as
n0tform3	8:1c6281289d67	851	defined in the ISO 7816-3 standard.
n0tform3	8:1c6281289d67	852
n0tform3	8:1c6281289d67	853	The USART can provide a clock to the smartcard through the SCLK output.
n0tform3	8:1c6281289d67	854	In smartcard mode, SCLK is not associated to the communication but is simply derived
n0tform3	8:1c6281289d67	855	from the internal peripheral input clock through a 5-bit prescaler.
n0tform3	8:1c6281289d67	856
n0tform3	8:1c6281289d67	857	Smartcard communication is possible through the following procedure:
n0tform3	8:1c6281289d67	858	1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
n0tform3	8:1c6281289d67	859	2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
n0tform3	8:1c6281289d67	860	3. Program the USART clock using the USART_ClockInit() function as following:
n0tform3	8:1c6281289d67	861	- USART Clock enabled
n0tform3	8:1c6281289d67	862	- USART CPOL Low
n0tform3	8:1c6281289d67	863	- USART CPHA on first edge
n0tform3	8:1c6281289d67	864	- USART Last Bit Clock Enabled
n0tform3	8:1c6281289d67	865	4. Program the Smartcard interface using the USART_Init() function as following:
n0tform3	8:1c6281289d67	866	- Word Length = 9 Bits
n0tform3	8:1c6281289d67	867	- 1.5 Stop Bit
n0tform3	8:1c6281289d67	868	- Even parity
n0tform3	8:1c6281289d67	869	- BaudRate = 12096 baud
n0tform3	8:1c6281289d67	870	- Hardware flow control disabled (RTS and CTS signals)
n0tform3	8:1c6281289d67	871	- Tx and Rx enabled
n0tform3	8:1c6281289d67	872	5. Optionally you can enable the parity error interrupt using the USART_ITConfig()
n0tform3	8:1c6281289d67	873	function
n0tform3	8:1c6281289d67	874	6. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	875	7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
n0tform3	8:1c6281289d67	876	8. Enable the Smartcard interface using the USART_SmartCardCmd() function.
n0tform3	8:1c6281289d67	877
n0tform3	8:1c6281289d67	878	Please refer to the ISO 7816-3 specification for more details.
n0tform3	8:1c6281289d67	879
n0tform3	8:1c6281289d67	880
n0tform3	8:1c6281289d67	881	@note It is also possible to choose 0.5 stop bit for receiving but it is recommended
n0tform3	8:1c6281289d67	882	to use 1.5 stop bits for both transmitting and receiving to avoid switching
n0tform3	8:1c6281289d67	883	between the two configurations.
n0tform3	8:1c6281289d67	884	@note In smartcard mode, the following bits must be kept cleared:
n0tform3	8:1c6281289d67	885	- LINEN bit in the USART_CR2 register.
n0tform3	8:1c6281289d67	886	- HDSEL and IREN bits in the USART_CR3 register.
n0tform3	8:1c6281289d67	887	@note Smartcard mode is available on USART peripherals only (not available on UART4
n0tform3	8:1c6281289d67	888	and UART5 peripherals).
n0tform3	8:1c6281289d67	889
n0tform3	8:1c6281289d67	890	@endverbatim
n0tform3	8:1c6281289d67	891	* @{
n0tform3	8:1c6281289d67	892	*/
n0tform3	8:1c6281289d67	893
n0tform3	8:1c6281289d67	894	/**
n0tform3	8:1c6281289d67	895	* @brief Sets the specified USART guard time.
n0tform3	8:1c6281289d67	896	* @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
n0tform3	8:1c6281289d67	897	* UART peripheral.
n0tform3	8:1c6281289d67	898	* @param USART_GuardTime: specifies the guard time.
n0tform3	8:1c6281289d67	899	* @retval None
n0tform3	8:1c6281289d67	900	*/
n0tform3	8:1c6281289d67	901	void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
n0tform3	8:1c6281289d67	902	{
n0tform3	8:1c6281289d67	903	/* Check the parameters */
n0tform3	8:1c6281289d67	904	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	905
n0tform3	8:1c6281289d67	906	/* Clear the USART Guard time */
n0tform3	8:1c6281289d67	907	USARTx->GTPR &= USART_GTPR_PSC;
n0tform3	8:1c6281289d67	908	/* Set the USART guard time */
n0tform3	8:1c6281289d67	909	USARTx->GTPR \|= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
n0tform3	8:1c6281289d67	910	}
n0tform3	8:1c6281289d67	911
n0tform3	8:1c6281289d67	912	/**
n0tform3	8:1c6281289d67	913	* @brief Enables or disables the USART's Smart Card mode.
n0tform3	8:1c6281289d67	914	* @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
n0tform3	8:1c6281289d67	915	* UART peripheral.
n0tform3	8:1c6281289d67	916	* @param NewState: new state of the Smart Card mode.
n0tform3	8:1c6281289d67	917	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	918	* @retval None
n0tform3	8:1c6281289d67	919	*/
n0tform3	8:1c6281289d67	920	void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	921	{
n0tform3	8:1c6281289d67	922	/* Check the parameters */
n0tform3	8:1c6281289d67	923	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	924	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	925	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	926	{
n0tform3	8:1c6281289d67	927	/* Enable the SC mode by setting the SCEN bit in the CR3 register */
n0tform3	8:1c6281289d67	928	USARTx->CR3 \|= USART_CR3_SCEN;
n0tform3	8:1c6281289d67	929	}
n0tform3	8:1c6281289d67	930	else
n0tform3	8:1c6281289d67	931	{
n0tform3	8:1c6281289d67	932	/* Disable the SC mode by clearing the SCEN bit in the CR3 register */
n0tform3	8:1c6281289d67	933	USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
n0tform3	8:1c6281289d67	934	}
n0tform3	8:1c6281289d67	935	}
n0tform3	8:1c6281289d67	936
n0tform3	8:1c6281289d67	937	/**
n0tform3	8:1c6281289d67	938	* @brief Enables or disables NACK transmission.
n0tform3	8:1c6281289d67	939	* @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or
n0tform3	8:1c6281289d67	940	* UART peripheral.
n0tform3	8:1c6281289d67	941	* @param NewState: new state of the NACK transmission.
n0tform3	8:1c6281289d67	942	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	943	* @retval None
n0tform3	8:1c6281289d67	944	*/
n0tform3	8:1c6281289d67	945	void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	946	{
n0tform3	8:1c6281289d67	947	/* Check the parameters */
n0tform3	8:1c6281289d67	948	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	949	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	950	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	951	{
n0tform3	8:1c6281289d67	952	/* Enable the NACK transmission by setting the NACK bit in the CR3 register */
n0tform3	8:1c6281289d67	953	USARTx->CR3 \|= USART_CR3_NACK;
n0tform3	8:1c6281289d67	954	}
n0tform3	8:1c6281289d67	955	else
n0tform3	8:1c6281289d67	956	{
n0tform3	8:1c6281289d67	957	/* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
n0tform3	8:1c6281289d67	958	USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
n0tform3	8:1c6281289d67	959	}
n0tform3	8:1c6281289d67	960	}
n0tform3	8:1c6281289d67	961
n0tform3	8:1c6281289d67	962	/**
n0tform3	8:1c6281289d67	963	* @}
n0tform3	8:1c6281289d67	964	*/
n0tform3	8:1c6281289d67	965
n0tform3	8:1c6281289d67	966	/** @defgroup USART_Group7 IrDA mode functions
n0tform3	8:1c6281289d67	967	* @brief IrDA mode functions
n0tform3	8:1c6281289d67	968	*
n0tform3	8:1c6281289d67	969	@verbatim
n0tform3	8:1c6281289d67	970	===============================================================================
n0tform3	8:1c6281289d67	971	IrDA mode functions
n0tform3	8:1c6281289d67	972	===============================================================================
n0tform3	8:1c6281289d67	973
n0tform3	8:1c6281289d67	974	This subsection provides a set of functions allowing to manage the USART
n0tform3	8:1c6281289d67	975	IrDA communication.
n0tform3	8:1c6281289d67	976
n0tform3	8:1c6281289d67	977	IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
n0tform3	8:1c6281289d67	978	on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
n0tform3	8:1c6281289d67	979	is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
n0tform3	8:1c6281289d67	980	While receiving data, transmission should be avoided as the data to be transmitted
n0tform3	8:1c6281289d67	981	could be corrupted.
n0tform3	8:1c6281289d67	982
n0tform3	8:1c6281289d67	983	IrDA communication is possible through the following procedure:
n0tform3	8:1c6281289d67	984	1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver
n0tform3	8:1c6281289d67	985	modes and hardware flow control values using the USART_Init() function.
n0tform3	8:1c6281289d67	986	2. Enable the USART using the USART_Cmd() function.
n0tform3	8:1c6281289d67	987	3. Configures the IrDA pulse width by configuring the prescaler using
n0tform3	8:1c6281289d67	988	the USART_SetPrescaler() function.
n0tform3	8:1c6281289d67	989	4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
n0tform3	8:1c6281289d67	990	using the USART_IrDAConfig() function.
n0tform3	8:1c6281289d67	991	5. Enable the IrDA using the USART_IrDACmd() function.
n0tform3	8:1c6281289d67	992
n0tform3	8:1c6281289d67	993	@note A pulse of width less than two and greater than one PSC period(s) may or may
n0tform3	8:1c6281289d67	994	not be rejected.
n0tform3	8:1c6281289d67	995	@note The receiver set up time should be managed by software. The IrDA physical layer
n0tform3	8:1c6281289d67	996	specification specifies a minimum of 10 ms delay between transmission and
n0tform3	8:1c6281289d67	997	reception (IrDA is a half duplex protocol).
n0tform3	8:1c6281289d67	998	@note In IrDA mode, the following bits must be kept cleared:
n0tform3	8:1c6281289d67	999	- LINEN, STOP and CLKEN bits in the USART_CR2 register.
n0tform3	8:1c6281289d67	1000	- SCEN and HDSEL bits in the USART_CR3 register.
n0tform3	8:1c6281289d67	1001
n0tform3	8:1c6281289d67	1002	@endverbatim
n0tform3	8:1c6281289d67	1003	* @{
n0tform3	8:1c6281289d67	1004	*/
n0tform3	8:1c6281289d67	1005
n0tform3	8:1c6281289d67	1006	/**
n0tform3	8:1c6281289d67	1007	* @brief Configures the USART's IrDA interface.
n0tform3	8:1c6281289d67	1008	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1009	* UART peripheral.
n0tform3	8:1c6281289d67	1010	* @param USART_IrDAMode: specifies the IrDA mode.
n0tform3	8:1c6281289d67	1011	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1012	* @arg USART_IrDAMode_LowPower
n0tform3	8:1c6281289d67	1013	* @arg USART_IrDAMode_Normal
n0tform3	8:1c6281289d67	1014	* @retval None
n0tform3	8:1c6281289d67	1015	*/
n0tform3	8:1c6281289d67	1016	void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
n0tform3	8:1c6281289d67	1017	{
n0tform3	8:1c6281289d67	1018	/* Check the parameters */
n0tform3	8:1c6281289d67	1019	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1020	assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
n0tform3	8:1c6281289d67	1021
n0tform3	8:1c6281289d67	1022	USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
n0tform3	8:1c6281289d67	1023	USARTx->CR3 \|= USART_IrDAMode;
n0tform3	8:1c6281289d67	1024	}
n0tform3	8:1c6281289d67	1025
n0tform3	8:1c6281289d67	1026	/**
n0tform3	8:1c6281289d67	1027	* @brief Enables or disables the USART's IrDA interface.
n0tform3	8:1c6281289d67	1028	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1029	* UART peripheral.
n0tform3	8:1c6281289d67	1030	* @param NewState: new state of the IrDA mode.
n0tform3	8:1c6281289d67	1031	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1032	* @retval None
n0tform3	8:1c6281289d67	1033	*/
n0tform3	8:1c6281289d67	1034	void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
n0tform3	8:1c6281289d67	1035	{
n0tform3	8:1c6281289d67	1036	/* Check the parameters */
n0tform3	8:1c6281289d67	1037	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1038	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1039
n0tform3	8:1c6281289d67	1040	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1041	{
n0tform3	8:1c6281289d67	1042	/* Enable the IrDA mode by setting the IREN bit in the CR3 register */
n0tform3	8:1c6281289d67	1043	USARTx->CR3 \|= USART_CR3_IREN;
n0tform3	8:1c6281289d67	1044	}
n0tform3	8:1c6281289d67	1045	else
n0tform3	8:1c6281289d67	1046	{
n0tform3	8:1c6281289d67	1047	/* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
n0tform3	8:1c6281289d67	1048	USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
n0tform3	8:1c6281289d67	1049	}
n0tform3	8:1c6281289d67	1050	}
n0tform3	8:1c6281289d67	1051
n0tform3	8:1c6281289d67	1052	/**
n0tform3	8:1c6281289d67	1053	* @}
n0tform3	8:1c6281289d67	1054	*/
n0tform3	8:1c6281289d67	1055
n0tform3	8:1c6281289d67	1056	/** @defgroup USART_Group8 DMA transfers management functions
n0tform3	8:1c6281289d67	1057	* @brief DMA transfers management functions
n0tform3	8:1c6281289d67	1058	*
n0tform3	8:1c6281289d67	1059	@verbatim
n0tform3	8:1c6281289d67	1060	===============================================================================
n0tform3	8:1c6281289d67	1061	DMA transfers management functions
n0tform3	8:1c6281289d67	1062	===============================================================================
n0tform3	8:1c6281289d67	1063
n0tform3	8:1c6281289d67	1064	@endverbatim
n0tform3	8:1c6281289d67	1065	* @{
n0tform3	8:1c6281289d67	1066	*/
n0tform3	8:1c6281289d67	1067
n0tform3	8:1c6281289d67	1068	/**
n0tform3	8:1c6281289d67	1069	* @brief Enables or disables the USART's DMA interface.
n0tform3	8:1c6281289d67	1070	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1071	* UART peripheral.
n0tform3	8:1c6281289d67	1072	* @param USART_DMAReq: specifies the DMA request.
n0tform3	8:1c6281289d67	1073	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1074	* @arg USART_DMAReq_Tx: USART DMA transmit request
n0tform3	8:1c6281289d67	1075	* @arg USART_DMAReq_Rx: USART DMA receive request
n0tform3	8:1c6281289d67	1076	* @param NewState: new state of the DMA Request sources.
n0tform3	8:1c6281289d67	1077	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1078	* @retval None
n0tform3	8:1c6281289d67	1079	*/
n0tform3	8:1c6281289d67	1080	void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
n0tform3	8:1c6281289d67	1081	{
n0tform3	8:1c6281289d67	1082	/* Check the parameters */
n0tform3	8:1c6281289d67	1083	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1084	assert_param(IS_USART_DMAREQ(USART_DMAReq));
n0tform3	8:1c6281289d67	1085	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1086
n0tform3	8:1c6281289d67	1087	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1088	{
n0tform3	8:1c6281289d67	1089	/* Enable the DMA transfer for selected requests by setting the DMAT and/or
n0tform3	8:1c6281289d67	1090	DMAR bits in the USART CR3 register */
n0tform3	8:1c6281289d67	1091	USARTx->CR3 \|= USART_DMAReq;
n0tform3	8:1c6281289d67	1092	}
n0tform3	8:1c6281289d67	1093	else
n0tform3	8:1c6281289d67	1094	{
n0tform3	8:1c6281289d67	1095	/* Disable the DMA transfer for selected requests by clearing the DMAT and/or
n0tform3	8:1c6281289d67	1096	DMAR bits in the USART CR3 register */
n0tform3	8:1c6281289d67	1097	USARTx->CR3 &= (uint16_t)~USART_DMAReq;
n0tform3	8:1c6281289d67	1098	}
n0tform3	8:1c6281289d67	1099	}
n0tform3	8:1c6281289d67	1100
n0tform3	8:1c6281289d67	1101	/**
n0tform3	8:1c6281289d67	1102	* @}
n0tform3	8:1c6281289d67	1103	*/
n0tform3	8:1c6281289d67	1104
n0tform3	8:1c6281289d67	1105	/** @defgroup USART_Group9 Interrupts and flags management functions
n0tform3	8:1c6281289d67	1106	* @brief Interrupts and flags management functions
n0tform3	8:1c6281289d67	1107	*
n0tform3	8:1c6281289d67	1108	@verbatim
n0tform3	8:1c6281289d67	1109	===============================================================================
n0tform3	8:1c6281289d67	1110	Interrupts and flags management functions
n0tform3	8:1c6281289d67	1111	===============================================================================
n0tform3	8:1c6281289d67	1112
n0tform3	8:1c6281289d67	1113	This subsection provides a set of functions allowing to configure the USART
n0tform3	8:1c6281289d67	1114	Interrupts sources, DMA channels requests and check or clear the flags or
n0tform3	8:1c6281289d67	1115	pending bits status.
n0tform3	8:1c6281289d67	1116	The user should identify which mode will be used in his application to manage
n0tform3	8:1c6281289d67	1117	the communication: Polling mode, Interrupt mode or DMA mode.
n0tform3	8:1c6281289d67	1118
n0tform3	8:1c6281289d67	1119	Polling Mode
n0tform3	8:1c6281289d67	1120	=============
n0tform3	8:1c6281289d67	1121	In Polling Mode, the SPI communication can be managed by 10 flags:
n0tform3	8:1c6281289d67	1122	1. USART_FLAG_TXE : to indicate the status of the transmit buffer register
n0tform3	8:1c6281289d67	1123	2. USART_FLAG_RXNE : to indicate the status of the receive buffer register
n0tform3	8:1c6281289d67	1124	3. USART_FLAG_TC : to indicate the status of the transmit operation
n0tform3	8:1c6281289d67	1125	4. USART_FLAG_IDLE : to indicate the status of the Idle Line
n0tform3	8:1c6281289d67	1126	5. USART_FLAG_CTS : to indicate the status of the nCTS input
n0tform3	8:1c6281289d67	1127	6. USART_FLAG_LBD : to indicate the status of the LIN break detection
n0tform3	8:1c6281289d67	1128	7. USART_FLAG_NE : to indicate if a noise error occur
n0tform3	8:1c6281289d67	1129	8. USART_FLAG_FE : to indicate if a frame error occur
n0tform3	8:1c6281289d67	1130	9. USART_FLAG_PE : to indicate if a parity error occur
n0tform3	8:1c6281289d67	1131	10. USART_FLAG_ORE : to indicate if an Overrun error occur
n0tform3	8:1c6281289d67	1132
n0tform3	8:1c6281289d67	1133	In this Mode it is advised to use the following functions:
n0tform3	8:1c6281289d67	1134	- FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
n0tform3	8:1c6281289d67	1135	- void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
n0tform3	8:1c6281289d67	1136
n0tform3	8:1c6281289d67	1137	Interrupt Mode
n0tform3	8:1c6281289d67	1138	===============
n0tform3	8:1c6281289d67	1139	In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
n0tform3	8:1c6281289d67	1140	and 10 pending bits:
n0tform3	8:1c6281289d67	1141
n0tform3	8:1c6281289d67	1142	Pending Bits:
n0tform3	8:1c6281289d67	1143	-------------
n0tform3	8:1c6281289d67	1144	1. USART_IT_TXE : to indicate the status of the transmit buffer register
n0tform3	8:1c6281289d67	1145	2. USART_IT_RXNE : to indicate the status of the receive buffer register
n0tform3	8:1c6281289d67	1146	3. USART_IT_TC : to indicate the status of the transmit operation
n0tform3	8:1c6281289d67	1147	4. USART_IT_IDLE : to indicate the status of the Idle Line
n0tform3	8:1c6281289d67	1148	5. USART_IT_CTS : to indicate the status of the nCTS input
n0tform3	8:1c6281289d67	1149	6. USART_IT_LBD : to indicate the status of the LIN break detection
n0tform3	8:1c6281289d67	1150	7. USART_IT_NE : to indicate if a noise error occur
n0tform3	8:1c6281289d67	1151	8. USART_IT_FE : to indicate if a frame error occur
n0tform3	8:1c6281289d67	1152	9. USART_IT_PE : to indicate if a parity error occur
n0tform3	8:1c6281289d67	1153	10. USART_IT_ORE : to indicate if an Overrun error occur
n0tform3	8:1c6281289d67	1154
n0tform3	8:1c6281289d67	1155	Interrupt Source:
n0tform3	8:1c6281289d67	1156	-----------------
n0tform3	8:1c6281289d67	1157	1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty
n0tform3	8:1c6281289d67	1158	interrupt.
n0tform3	8:1c6281289d67	1159	2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not
n0tform3	8:1c6281289d67	1160	empty interrupt.
n0tform3	8:1c6281289d67	1161	3. USART_IT_TC : specifies the interrupt source for the Transmit complete
n0tform3	8:1c6281289d67	1162	interrupt.
n0tform3	8:1c6281289d67	1163	4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.
n0tform3	8:1c6281289d67	1164	5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt.
n0tform3	8:1c6281289d67	1165	6. USART_IT_LBD : specifies the interrupt source for the LIN break detection
n0tform3	8:1c6281289d67	1166	interrupt.
n0tform3	8:1c6281289d67	1167	7. USART_IT_PE : specifies the interrupt source for the parity error interrupt.
n0tform3	8:1c6281289d67	1168	8. USART_IT_ERR : specifies the interrupt source for the errors interrupt.
n0tform3	8:1c6281289d67	1169
n0tform3	8:1c6281289d67	1170	@note Some parameters are coded in order to use them as interrupt source or as pending bits.
n0tform3	8:1c6281289d67	1171
n0tform3	8:1c6281289d67	1172	In this Mode it is advised to use the following functions:
n0tform3	8:1c6281289d67	1173	- void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
n0tform3	8:1c6281289d67	1174	- ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
n0tform3	8:1c6281289d67	1175	- void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
n0tform3	8:1c6281289d67	1176
n0tform3	8:1c6281289d67	1177	DMA Mode
n0tform3	8:1c6281289d67	1178	========
n0tform3	8:1c6281289d67	1179	In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
n0tform3	8:1c6281289d67	1180	1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
n0tform3	8:1c6281289d67	1181	2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
n0tform3	8:1c6281289d67	1182
n0tform3	8:1c6281289d67	1183	In this Mode it is advised to use the following function:
n0tform3	8:1c6281289d67	1184	- void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
n0tform3	8:1c6281289d67	1185
n0tform3	8:1c6281289d67	1186	@endverbatim
n0tform3	8:1c6281289d67	1187	* @{
n0tform3	8:1c6281289d67	1188	*/
n0tform3	8:1c6281289d67	1189
n0tform3	8:1c6281289d67	1190	/**
n0tform3	8:1c6281289d67	1191	* @brief Enables or disables the specified USART interrupts.
n0tform3	8:1c6281289d67	1192	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1193	* UART peripheral.
n0tform3	8:1c6281289d67	1194	* @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
n0tform3	8:1c6281289d67	1195	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1196	* @arg USART_IT_CTS: CTS change interrupt
n0tform3	8:1c6281289d67	1197	* @arg USART_IT_LBD: LIN Break detection interrupt
n0tform3	8:1c6281289d67	1198	* @arg USART_IT_TXE: Transmit Data Register empty interrupt
n0tform3	8:1c6281289d67	1199	* @arg USART_IT_TC: Transmission complete interrupt
n0tform3	8:1c6281289d67	1200	* @arg USART_IT_RXNE: Receive Data register not empty interrupt
n0tform3	8:1c6281289d67	1201	* @arg USART_IT_IDLE: Idle line detection interrupt
n0tform3	8:1c6281289d67	1202	* @arg USART_IT_PE: Parity Error interrupt
n0tform3	8:1c6281289d67	1203	* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
n0tform3	8:1c6281289d67	1204	* @param NewState: new state of the specified USARTx interrupts.
n0tform3	8:1c6281289d67	1205	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1206	* @retval None
n0tform3	8:1c6281289d67	1207	*/
n0tform3	8:1c6281289d67	1208	void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
n0tform3	8:1c6281289d67	1209	{
n0tform3	8:1c6281289d67	1210	uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
n0tform3	8:1c6281289d67	1211	uint32_t usartxbase = 0x00;
n0tform3	8:1c6281289d67	1212	/* Check the parameters */
n0tform3	8:1c6281289d67	1213	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1214	assert_param(IS_USART_CONFIG_IT(USART_IT));
n0tform3	8:1c6281289d67	1215	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1216
n0tform3	8:1c6281289d67	1217	/* The CTS interrupt is not available for UART4 and UART5 */
n0tform3	8:1c6281289d67	1218	if (USART_IT == USART_IT_CTS)
n0tform3	8:1c6281289d67	1219	{
n0tform3	8:1c6281289d67	1220	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1221	}
n0tform3	8:1c6281289d67	1222
n0tform3	8:1c6281289d67	1223	usartxbase = (uint32_t)USARTx;
n0tform3	8:1c6281289d67	1224
n0tform3	8:1c6281289d67	1225	/* Get the USART register index */
n0tform3	8:1c6281289d67	1226	usartreg = (((uint8_t)USART_IT) >> 0x05);
n0tform3	8:1c6281289d67	1227
n0tform3	8:1c6281289d67	1228	/* Get the interrupt position */
n0tform3	8:1c6281289d67	1229	itpos = USART_IT & IT_MASK;
n0tform3	8:1c6281289d67	1230	itmask = (((uint32_t)0x01) << itpos);
n0tform3	8:1c6281289d67	1231
n0tform3	8:1c6281289d67	1232	if (usartreg == 0x01) /* The IT is in CR1 register */
n0tform3	8:1c6281289d67	1233	{
n0tform3	8:1c6281289d67	1234	usartxbase += 0x0C;
n0tform3	8:1c6281289d67	1235	}
n0tform3	8:1c6281289d67	1236	else if (usartreg == 0x02) /* The IT is in CR2 register */
n0tform3	8:1c6281289d67	1237	{
n0tform3	8:1c6281289d67	1238	usartxbase += 0x10;
n0tform3	8:1c6281289d67	1239	}
n0tform3	8:1c6281289d67	1240	else /* The IT is in CR3 register */
n0tform3	8:1c6281289d67	1241	{
n0tform3	8:1c6281289d67	1242	usartxbase += 0x14;
n0tform3	8:1c6281289d67	1243	}
n0tform3	8:1c6281289d67	1244	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1245	{
n0tform3	8:1c6281289d67	1246	(__IO uint32_t)usartxbase \|= itmask;
n0tform3	8:1c6281289d67	1247	}
n0tform3	8:1c6281289d67	1248	else
n0tform3	8:1c6281289d67	1249	{
n0tform3	8:1c6281289d67	1250	(__IO uint32_t)usartxbase &= ~itmask;
n0tform3	8:1c6281289d67	1251	}
n0tform3	8:1c6281289d67	1252	}
n0tform3	8:1c6281289d67	1253
n0tform3	8:1c6281289d67	1254	/**
n0tform3	8:1c6281289d67	1255	* @brief Checks whether the specified USART flag is set or not.
n0tform3	8:1c6281289d67	1256	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1257	* UART peripheral.
n0tform3	8:1c6281289d67	1258	* @param USART_FLAG: specifies the flag to check.
n0tform3	8:1c6281289d67	1259	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1260	* @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
n0tform3	8:1c6281289d67	1261	* @arg USART_FLAG_LBD: LIN Break detection flag
n0tform3	8:1c6281289d67	1262	* @arg USART_FLAG_TXE: Transmit data register empty flag
n0tform3	8:1c6281289d67	1263	* @arg USART_FLAG_TC: Transmission Complete flag
n0tform3	8:1c6281289d67	1264	* @arg USART_FLAG_RXNE: Receive data register not empty flag
n0tform3	8:1c6281289d67	1265	* @arg USART_FLAG_IDLE: Idle Line detection flag
n0tform3	8:1c6281289d67	1266	* @arg USART_FLAG_ORE: OverRun Error flag
n0tform3	8:1c6281289d67	1267	* @arg USART_FLAG_NE: Noise Error flag
n0tform3	8:1c6281289d67	1268	* @arg USART_FLAG_FE: Framing Error flag
n0tform3	8:1c6281289d67	1269	* @arg USART_FLAG_PE: Parity Error flag
n0tform3	8:1c6281289d67	1270	* @retval The new state of USART_FLAG (SET or RESET).
n0tform3	8:1c6281289d67	1271	*/
n0tform3	8:1c6281289d67	1272	FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
n0tform3	8:1c6281289d67	1273	{
n0tform3	8:1c6281289d67	1274	FlagStatus bitstatus = RESET;
n0tform3	8:1c6281289d67	1275	/* Check the parameters */
n0tform3	8:1c6281289d67	1276	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1277	assert_param(IS_USART_FLAG(USART_FLAG));
n0tform3	8:1c6281289d67	1278
n0tform3	8:1c6281289d67	1279	/* The CTS flag is not available for UART4 and UART5 */
n0tform3	8:1c6281289d67	1280	if (USART_FLAG == USART_FLAG_CTS)
n0tform3	8:1c6281289d67	1281	{
n0tform3	8:1c6281289d67	1282	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1283	}
n0tform3	8:1c6281289d67	1284
n0tform3	8:1c6281289d67	1285	if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
n0tform3	8:1c6281289d67	1286	{
n0tform3	8:1c6281289d67	1287	bitstatus = SET;
n0tform3	8:1c6281289d67	1288	}
n0tform3	8:1c6281289d67	1289	else
n0tform3	8:1c6281289d67	1290	{
n0tform3	8:1c6281289d67	1291	bitstatus = RESET;
n0tform3	8:1c6281289d67	1292	}
n0tform3	8:1c6281289d67	1293	return bitstatus;
n0tform3	8:1c6281289d67	1294	}
n0tform3	8:1c6281289d67	1295
n0tform3	8:1c6281289d67	1296	/**
n0tform3	8:1c6281289d67	1297	* @brief Clears the USARTx's pending flags.
n0tform3	8:1c6281289d67	1298	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1299	* UART peripheral.
n0tform3	8:1c6281289d67	1300	* @param USART_FLAG: specifies the flag to clear.
n0tform3	8:1c6281289d67	1301	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1302	* @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
n0tform3	8:1c6281289d67	1303	* @arg USART_FLAG_LBD: LIN Break detection flag.
n0tform3	8:1c6281289d67	1304	* @arg USART_FLAG_TC: Transmission Complete flag.
n0tform3	8:1c6281289d67	1305	* @arg USART_FLAG_RXNE: Receive data register not empty flag.
n0tform3	8:1c6281289d67	1306	*
n0tform3	8:1c6281289d67	1307	* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
n0tform3	8:1c6281289d67	1308	* error) and IDLE (Idle line detected) flags are cleared by software
n0tform3	8:1c6281289d67	1309	* sequence: a read operation to USART_SR register (USART_GetFlagStatus())
n0tform3	8:1c6281289d67	1310	* followed by a read operation to USART_DR register (USART_ReceiveData()).
n0tform3	8:1c6281289d67	1311	* @note RXNE flag can be also cleared by a read to the USART_DR register
n0tform3	8:1c6281289d67	1312	* (USART_ReceiveData()).
n0tform3	8:1c6281289d67	1313	* @note TC flag can be also cleared by software sequence: a read operation to
n0tform3	8:1c6281289d67	1314	* USART_SR register (USART_GetFlagStatus()) followed by a write operation
n0tform3	8:1c6281289d67	1315	* to USART_DR register (USART_SendData()).
n0tform3	8:1c6281289d67	1316	* @note TXE flag is cleared only by a write to the USART_DR register
n0tform3	8:1c6281289d67	1317	* (USART_SendData()).
n0tform3	8:1c6281289d67	1318	*
n0tform3	8:1c6281289d67	1319	* @retval None
n0tform3	8:1c6281289d67	1320	*/
n0tform3	8:1c6281289d67	1321	void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
n0tform3	8:1c6281289d67	1322	{
n0tform3	8:1c6281289d67	1323	/* Check the parameters */
n0tform3	8:1c6281289d67	1324	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1325	assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
n0tform3	8:1c6281289d67	1326
n0tform3	8:1c6281289d67	1327	/* The CTS flag is not available for UART4 and UART5 */
n0tform3	8:1c6281289d67	1328	if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
n0tform3	8:1c6281289d67	1329	{
n0tform3	8:1c6281289d67	1330	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1331	}
n0tform3	8:1c6281289d67	1332
n0tform3	8:1c6281289d67	1333	USARTx->SR = (uint16_t)~USART_FLAG;
n0tform3	8:1c6281289d67	1334	}
n0tform3	8:1c6281289d67	1335
n0tform3	8:1c6281289d67	1336	/**
n0tform3	8:1c6281289d67	1337	* @brief Checks whether the specified USART interrupt has occurred or not.
n0tform3	8:1c6281289d67	1338	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1339	* UART peripheral.
n0tform3	8:1c6281289d67	1340	* @param USART_IT: specifies the USART interrupt source to check.
n0tform3	8:1c6281289d67	1341	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1342	* @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
n0tform3	8:1c6281289d67	1343	* @arg USART_IT_LBD: LIN Break detection interrupt
n0tform3	8:1c6281289d67	1344	* @arg USART_IT_TXE: Transmit Data Register empty interrupt
n0tform3	8:1c6281289d67	1345	* @arg USART_IT_TC: Transmission complete interrupt
n0tform3	8:1c6281289d67	1346	* @arg USART_IT_RXNE: Receive Data register not empty interrupt
n0tform3	8:1c6281289d67	1347	* @arg USART_IT_IDLE: Idle line detection interrupt
n0tform3	8:1c6281289d67	1348	* @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
n0tform3	8:1c6281289d67	1349	* @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
n0tform3	8:1c6281289d67	1350	* @arg USART_IT_NE: Noise Error interrupt
n0tform3	8:1c6281289d67	1351	* @arg USART_IT_FE: Framing Error interrupt
n0tform3	8:1c6281289d67	1352	* @arg USART_IT_PE: Parity Error interrupt
n0tform3	8:1c6281289d67	1353	* @retval The new state of USART_IT (SET or RESET).
n0tform3	8:1c6281289d67	1354	*/
n0tform3	8:1c6281289d67	1355	ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
n0tform3	8:1c6281289d67	1356	{
n0tform3	8:1c6281289d67	1357	uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
n0tform3	8:1c6281289d67	1358	ITStatus bitstatus = RESET;
n0tform3	8:1c6281289d67	1359	/* Check the parameters */
n0tform3	8:1c6281289d67	1360	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1361	assert_param(IS_USART_GET_IT(USART_IT));
n0tform3	8:1c6281289d67	1362
n0tform3	8:1c6281289d67	1363	/* The CTS interrupt is not available for UART4 and UART5 */
n0tform3	8:1c6281289d67	1364	if (USART_IT == USART_IT_CTS)
n0tform3	8:1c6281289d67	1365	{
n0tform3	8:1c6281289d67	1366	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1367	}
n0tform3	8:1c6281289d67	1368
n0tform3	8:1c6281289d67	1369	/* Get the USART register index */
n0tform3	8:1c6281289d67	1370	usartreg = (((uint8_t)USART_IT) >> 0x05);
n0tform3	8:1c6281289d67	1371	/* Get the interrupt position */
n0tform3	8:1c6281289d67	1372	itmask = USART_IT & IT_MASK;
n0tform3	8:1c6281289d67	1373	itmask = (uint32_t)0x01 << itmask;
n0tform3	8:1c6281289d67	1374
n0tform3	8:1c6281289d67	1375	if (usartreg == 0x01) /* The IT is in CR1 register */
n0tform3	8:1c6281289d67	1376	{
n0tform3	8:1c6281289d67	1377	itmask &= USARTx->CR1;
n0tform3	8:1c6281289d67	1378	}
n0tform3	8:1c6281289d67	1379	else if (usartreg == 0x02) /* The IT is in CR2 register */
n0tform3	8:1c6281289d67	1380	{
n0tform3	8:1c6281289d67	1381	itmask &= USARTx->CR2;
n0tform3	8:1c6281289d67	1382	}
n0tform3	8:1c6281289d67	1383	else /* The IT is in CR3 register */
n0tform3	8:1c6281289d67	1384	{
n0tform3	8:1c6281289d67	1385	itmask &= USARTx->CR3;
n0tform3	8:1c6281289d67	1386	}
n0tform3	8:1c6281289d67	1387
n0tform3	8:1c6281289d67	1388	bitpos = USART_IT >> 0x08;
n0tform3	8:1c6281289d67	1389	bitpos = (uint32_t)0x01 << bitpos;
n0tform3	8:1c6281289d67	1390	bitpos &= USARTx->SR;
n0tform3	8:1c6281289d67	1391	if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
n0tform3	8:1c6281289d67	1392	{
n0tform3	8:1c6281289d67	1393	bitstatus = SET;
n0tform3	8:1c6281289d67	1394	}
n0tform3	8:1c6281289d67	1395	else
n0tform3	8:1c6281289d67	1396	{
n0tform3	8:1c6281289d67	1397	bitstatus = RESET;
n0tform3	8:1c6281289d67	1398	}
n0tform3	8:1c6281289d67	1399
n0tform3	8:1c6281289d67	1400	return bitstatus;
n0tform3	8:1c6281289d67	1401	}
n0tform3	8:1c6281289d67	1402
n0tform3	8:1c6281289d67	1403	/**
n0tform3	8:1c6281289d67	1404	* @brief Clears the USARTx's interrupt pending bits.
n0tform3	8:1c6281289d67	1405	* @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or
n0tform3	8:1c6281289d67	1406	* UART peripheral.
n0tform3	8:1c6281289d67	1407	* @param USART_IT: specifies the interrupt pending bit to clear.
n0tform3	8:1c6281289d67	1408	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1409	* @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
n0tform3	8:1c6281289d67	1410	* @arg USART_IT_LBD: LIN Break detection interrupt
n0tform3	8:1c6281289d67	1411	* @arg USART_IT_TC: Transmission complete interrupt.
n0tform3	8:1c6281289d67	1412	* @arg USART_IT_RXNE: Receive Data register not empty interrupt.
n0tform3	8:1c6281289d67	1413	*
n0tform3	8:1c6281289d67	1414	* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
n0tform3	8:1c6281289d67	1415	* error) and IDLE (Idle line detected) pending bits are cleared by
n0tform3	8:1c6281289d67	1416	* software sequence: a read operation to USART_SR register
n0tform3	8:1c6281289d67	1417	* (USART_GetITStatus()) followed by a read operation to USART_DR register
n0tform3	8:1c6281289d67	1418	* (USART_ReceiveData()).
n0tform3	8:1c6281289d67	1419	* @note RXNE pending bit can be also cleared by a read to the USART_DR register
n0tform3	8:1c6281289d67	1420	* (USART_ReceiveData()).
n0tform3	8:1c6281289d67	1421	* @note TC pending bit can be also cleared by software sequence: a read
n0tform3	8:1c6281289d67	1422	* operation to USART_SR register (USART_GetITStatus()) followed by a write
n0tform3	8:1c6281289d67	1423	* operation to USART_DR register (USART_SendData()).
n0tform3	8:1c6281289d67	1424	* @note TXE pending bit is cleared only by a write to the USART_DR register
n0tform3	8:1c6281289d67	1425	* (USART_SendData()).
n0tform3	8:1c6281289d67	1426	*
n0tform3	8:1c6281289d67	1427	* @retval None
n0tform3	8:1c6281289d67	1428	*/
n0tform3	8:1c6281289d67	1429	void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
n0tform3	8:1c6281289d67	1430	{
n0tform3	8:1c6281289d67	1431	uint16_t bitpos = 0x00, itmask = 0x00;
n0tform3	8:1c6281289d67	1432	/* Check the parameters */
n0tform3	8:1c6281289d67	1433	assert_param(IS_USART_ALL_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1434	assert_param(IS_USART_CLEAR_IT(USART_IT));
n0tform3	8:1c6281289d67	1435
n0tform3	8:1c6281289d67	1436	/* The CTS interrupt is not available for UART4 and UART5 */
n0tform3	8:1c6281289d67	1437	if (USART_IT == USART_IT_CTS)
n0tform3	8:1c6281289d67	1438	{
n0tform3	8:1c6281289d67	1439	assert_param(IS_USART_1236_PERIPH(USARTx));
n0tform3	8:1c6281289d67	1440	}
n0tform3	8:1c6281289d67	1441
n0tform3	8:1c6281289d67	1442	bitpos = USART_IT >> 0x08;
n0tform3	8:1c6281289d67	1443	itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
n0tform3	8:1c6281289d67	1444	USARTx->SR = (uint16_t)~itmask;
n0tform3	8:1c6281289d67	1445	}
n0tform3	8:1c6281289d67	1446
n0tform3	8:1c6281289d67	1447	/**
n0tform3	8:1c6281289d67	1448	* @}
n0tform3	8:1c6281289d67	1449	*/
n0tform3	8:1c6281289d67	1450
n0tform3	8:1c6281289d67	1451	/**
n0tform3	8:1c6281289d67	1452	* @}
n0tform3	8:1c6281289d67	1453	*/
n0tform3	8:1c6281289d67	1454
n0tform3	8:1c6281289d67	1455	/**
n0tform3	8:1c6281289d67	1456	* @}
n0tform3	8:1c6281289d67	1457	*/
n0tform3	8:1c6281289d67	1458
n0tform3	8:1c6281289d67	1459	/**
n0tform3	8:1c6281289d67	1460	* @}
n0tform3	8:1c6281289d67	1461	*/
n0tform3	8:1c6281289d67	1462
n0tform3	8:1c6281289d67	1463	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/
n0tform3	8:1c6281289d67	1464

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	15 Nov 2015
Imports:	67
Forks:	0
Commits:	9
Dependents:	0
Dependencies:	4
Followers:	1

stm32f4xx_usart.c@8:1c6281289d67, 2015-11-15 (annotated)

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