HelloWorld_IKS01A1 - Simple "hello world" style program for X-NUCLEO-I…

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mattia griotti / Mbed 2 deprecated HelloWorld_IKS01A1

Simple "hello world" style program for X-NUCLEO-IKS01A1 MEMS Inertial

Dependencies: BLE_API X_NUCLEO_IDB0XA1 X_NUCLEO_IKS01A1 mbed

stm32f4xx_rcc.c@8:1c6281289d67, 2015-11-15 (annotated)

Committer:: n0tform3
Date:: Sun Nov 15 09:00:40 2015 +0000
Revision:: 8:1c6281289d67

test with led

Who changed what in which revision?

User	Revision	Line number	New contents of line
n0tform3	8:1c6281289d67	1	/**
n0tform3	8:1c6281289d67	2	******************************************************************************
n0tform3	8:1c6281289d67	3	* @file stm32f4xx_rcc.c
n0tform3	8:1c6281289d67	4	* @author MCD Application Team
n0tform3	8:1c6281289d67	5	* @version V1.0.0
n0tform3	8:1c6281289d67	6	* @date 30-September-2011
n0tform3	8:1c6281289d67	7	* @brief This file provides firmware functions to manage the following
n0tform3	8:1c6281289d67	8	* functionalities of the Reset and clock control (RCC) peripheral:
n0tform3	8:1c6281289d67	9	* - Internal/external clocks, PLL, CSS and MCO configuration
n0tform3	8:1c6281289d67	10	* - System, AHB and APB busses clocks configuration
n0tform3	8:1c6281289d67	11	* - Peripheral clocks configuration
n0tform3	8:1c6281289d67	12	* - Interrupts and flags management
n0tform3	8:1c6281289d67	13	*
n0tform3	8:1c6281289d67	14	* @verbatim
n0tform3	8:1c6281289d67	15	*
n0tform3	8:1c6281289d67	16	* ===================================================================
n0tform3	8:1c6281289d67	17	* RCC specific features
n0tform3	8:1c6281289d67	18	* ===================================================================
n0tform3	8:1c6281289d67	19	*
n0tform3	8:1c6281289d67	20	* After reset the device is running from Internal High Speed oscillator
n0tform3	8:1c6281289d67	21	* (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
n0tform3	8:1c6281289d67	22	* and I-Cache are disabled, and all peripherals are off except internal
n0tform3	8:1c6281289d67	23	* SRAM, Flash and JTAG.
n0tform3	8:1c6281289d67	24	* - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
n0tform3	8:1c6281289d67	25	* all peripherals mapped on these busses are running at HSI speed.
n0tform3	8:1c6281289d67	26	* - The clock for all peripherals is switched off, except the SRAM and FLASH.
n0tform3	8:1c6281289d67	27	* - All GPIOs are in input floating state, except the JTAG pins which
n0tform3	8:1c6281289d67	28	* are assigned to be used for debug purpose.
n0tform3	8:1c6281289d67	29	*
n0tform3	8:1c6281289d67	30	* Once the device started from reset, the user application has to:
n0tform3	8:1c6281289d67	31	* - Configure the clock source to be used to drive the System clock
n0tform3	8:1c6281289d67	32	* (if the application needs higher frequency/performance)
n0tform3	8:1c6281289d67	33	* - Configure the System clock frequency and Flash settings
n0tform3	8:1c6281289d67	34	* - Configure the AHB and APB busses prescalers
n0tform3	8:1c6281289d67	35	* - Enable the clock for the peripheral(s) to be used
n0tform3	8:1c6281289d67	36	* - Configure the clock source(s) for peripherals which clocks are not
n0tform3	8:1c6281289d67	37	* derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
n0tform3	8:1c6281289d67	38	*
n0tform3	8:1c6281289d67	39	* @endverbatim
n0tform3	8:1c6281289d67	40	*
n0tform3	8:1c6281289d67	41	******************************************************************************
n0tform3	8:1c6281289d67	42	* @attention
n0tform3	8:1c6281289d67	43	*
n0tform3	8:1c6281289d67	44	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
n0tform3	8:1c6281289d67	45	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
n0tform3	8:1c6281289d67	46	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
n0tform3	8:1c6281289d67	47	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
n0tform3	8:1c6281289d67	48	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
n0tform3	8:1c6281289d67	49	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
n0tform3	8:1c6281289d67	50	*
n0tform3	8:1c6281289d67	51	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
n0tform3	8:1c6281289d67	52	******************************************************************************
n0tform3	8:1c6281289d67	53	*/
n0tform3	8:1c6281289d67	54
n0tform3	8:1c6281289d67	55	/* Includes ------------------------------------------------------------------*/
n0tform3	8:1c6281289d67	56	#include "stm32f4xx_rcc.h"
n0tform3	8:1c6281289d67	57
n0tform3	8:1c6281289d67	58	/** @addtogroup STM32F4xx_StdPeriph_Driver
n0tform3	8:1c6281289d67	59	* @{
n0tform3	8:1c6281289d67	60	*/
n0tform3	8:1c6281289d67	61
n0tform3	8:1c6281289d67	62	/** @defgroup RCC
n0tform3	8:1c6281289d67	63	* @brief RCC driver modules
n0tform3	8:1c6281289d67	64	* @{
n0tform3	8:1c6281289d67	65	*/
n0tform3	8:1c6281289d67	66
n0tform3	8:1c6281289d67	67	/* Private typedef -----------------------------------------------------------*/
n0tform3	8:1c6281289d67	68	/* Private define ------------------------------------------------------------*/
n0tform3	8:1c6281289d67	69	/* ------------ RCC registers bit address in the alias region ----------- */
n0tform3	8:1c6281289d67	70	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
n0tform3	8:1c6281289d67	71	/* --- CR Register ---*/
n0tform3	8:1c6281289d67	72	/* Alias word address of HSION bit */
n0tform3	8:1c6281289d67	73	#define CR_OFFSET (RCC_OFFSET + 0x00)
n0tform3	8:1c6281289d67	74	#define HSION_BitNumber 0x00
n0tform3	8:1c6281289d67	75	#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
n0tform3	8:1c6281289d67	76	/* Alias word address of CSSON bit */
n0tform3	8:1c6281289d67	77	#define CSSON_BitNumber 0x13
n0tform3	8:1c6281289d67	78	#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
n0tform3	8:1c6281289d67	79	/* Alias word address of PLLON bit */
n0tform3	8:1c6281289d67	80	#define PLLON_BitNumber 0x18
n0tform3	8:1c6281289d67	81	#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
n0tform3	8:1c6281289d67	82	/* Alias word address of PLLI2SON bit */
n0tform3	8:1c6281289d67	83	#define PLLI2SON_BitNumber 0x1A
n0tform3	8:1c6281289d67	84	#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
n0tform3	8:1c6281289d67	85
n0tform3	8:1c6281289d67	86	/* --- CFGR Register ---*/
n0tform3	8:1c6281289d67	87	/* Alias word address of I2SSRC bit */
n0tform3	8:1c6281289d67	88	#define CFGR_OFFSET (RCC_OFFSET + 0x08)
n0tform3	8:1c6281289d67	89	#define I2SSRC_BitNumber 0x17
n0tform3	8:1c6281289d67	90	#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
n0tform3	8:1c6281289d67	91
n0tform3	8:1c6281289d67	92	/* --- BDCR Register ---*/
n0tform3	8:1c6281289d67	93	/* Alias word address of RTCEN bit */
n0tform3	8:1c6281289d67	94	#define BDCR_OFFSET (RCC_OFFSET + 0x70)
n0tform3	8:1c6281289d67	95	#define RTCEN_BitNumber 0x0F
n0tform3	8:1c6281289d67	96	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
n0tform3	8:1c6281289d67	97	/* Alias word address of BDRST bit */
n0tform3	8:1c6281289d67	98	#define BDRST_BitNumber 0x10
n0tform3	8:1c6281289d67	99	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
n0tform3	8:1c6281289d67	100	/* --- CSR Register ---*/
n0tform3	8:1c6281289d67	101	/* Alias word address of LSION bit */
n0tform3	8:1c6281289d67	102	#define CSR_OFFSET (RCC_OFFSET + 0x74)
n0tform3	8:1c6281289d67	103	#define LSION_BitNumber 0x00
n0tform3	8:1c6281289d67	104	#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
n0tform3	8:1c6281289d67	105	/* ---------------------- RCC registers bit mask ------------------------ */
n0tform3	8:1c6281289d67	106	/* CFGR register bit mask */
n0tform3	8:1c6281289d67	107	#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
n0tform3	8:1c6281289d67	108	#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
n0tform3	8:1c6281289d67	109
n0tform3	8:1c6281289d67	110	/* RCC Flag Mask */
n0tform3	8:1c6281289d67	111	#define FLAG_MASK ((uint8_t)0x1F)
n0tform3	8:1c6281289d67	112
n0tform3	8:1c6281289d67	113	/* CR register byte 3 (Bits[23:16]) base address */
n0tform3	8:1c6281289d67	114	#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
n0tform3	8:1c6281289d67	115
n0tform3	8:1c6281289d67	116	/* CIR register byte 2 (Bits[15:8]) base address */
n0tform3	8:1c6281289d67	117	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
n0tform3	8:1c6281289d67	118
n0tform3	8:1c6281289d67	119	/* CIR register byte 3 (Bits[23:16]) base address */
n0tform3	8:1c6281289d67	120	#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
n0tform3	8:1c6281289d67	121
n0tform3	8:1c6281289d67	122	/* BDCR register base address */
n0tform3	8:1c6281289d67	123	#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
n0tform3	8:1c6281289d67	124
n0tform3	8:1c6281289d67	125	/* Private macro -------------------------------------------------------------*/
n0tform3	8:1c6281289d67	126	/* Private variables ---------------------------------------------------------*/
n0tform3	8:1c6281289d67	127	static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
n0tform3	8:1c6281289d67	128
n0tform3	8:1c6281289d67	129	/* Private function prototypes -----------------------------------------------*/
n0tform3	8:1c6281289d67	130	/* Private functions ---------------------------------------------------------*/
n0tform3	8:1c6281289d67	131
n0tform3	8:1c6281289d67	132	/** @defgroup RCC_Private_Functions
n0tform3	8:1c6281289d67	133	* @{
n0tform3	8:1c6281289d67	134	*/
n0tform3	8:1c6281289d67	135
n0tform3	8:1c6281289d67	136	/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
n0tform3	8:1c6281289d67	137	* @brief Internal and external clocks, PLL, CSS and MCO configuration functions
n0tform3	8:1c6281289d67	138	*
n0tform3	8:1c6281289d67	139	@verbatim
n0tform3	8:1c6281289d67	140	===============================================================================
n0tform3	8:1c6281289d67	141	Internal/external clocks, PLL, CSS and MCO configuration functions
n0tform3	8:1c6281289d67	142	===============================================================================
n0tform3	8:1c6281289d67	143
n0tform3	8:1c6281289d67	144	This section provide functions allowing to configure the internal/external clocks,
n0tform3	8:1c6281289d67	145	PLLs, CSS and MCO pins.
n0tform3	8:1c6281289d67	146
n0tform3	8:1c6281289d67	147	1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
n0tform3	8:1c6281289d67	148	the PLL as System clock source.
n0tform3	8:1c6281289d67	149
n0tform3	8:1c6281289d67	150	2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
n0tform3	8:1c6281289d67	151	clock source.
n0tform3	8:1c6281289d67	152
n0tform3	8:1c6281289d67	153	3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
n0tform3	8:1c6281289d67	154	through the PLL as System clock source. Can be used also as RTC clock source.
n0tform3	8:1c6281289d67	155
n0tform3	8:1c6281289d67	156	4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
n0tform3	8:1c6281289d67	157
n0tform3	8:1c6281289d67	158	5. PLL (clocked by HSI or HSE), featuring two different output clocks:
n0tform3	8:1c6281289d67	159	- The first output is used to generate the high speed system clock (up to 168 MHz)
n0tform3	8:1c6281289d67	160	- The second output is used to generate the clock for the USB OTG FS (48 MHz),
n0tform3	8:1c6281289d67	161	the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
n0tform3	8:1c6281289d67	162
n0tform3	8:1c6281289d67	163	6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
n0tform3	8:1c6281289d67	164	high-quality audio performance on the I2S interface.
n0tform3	8:1c6281289d67	165
n0tform3	8:1c6281289d67	166	7. CSS (Clock security system), once enable and if a HSE clock failure occurs
n0tform3	8:1c6281289d67	167	(HSE used directly or through PLL as System clock source), the System clock
n0tform3	8:1c6281289d67	168	is automatically switched to HSI and an interrupt is generated if enabled.
n0tform3	8:1c6281289d67	169	The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
n0tform3	8:1c6281289d67	170	exception vector.
n0tform3	8:1c6281289d67	171
n0tform3	8:1c6281289d67	172	8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
n0tform3	8:1c6281289d67	173	clock (through a configurable prescaler) on PA8 pin.
n0tform3	8:1c6281289d67	174
n0tform3	8:1c6281289d67	175	9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
n0tform3	8:1c6281289d67	176	clock (through a configurable prescaler) on PC9 pin.
n0tform3	8:1c6281289d67	177
n0tform3	8:1c6281289d67	178	@endverbatim
n0tform3	8:1c6281289d67	179	* @{
n0tform3	8:1c6281289d67	180	*/
n0tform3	8:1c6281289d67	181
n0tform3	8:1c6281289d67	182	/**
n0tform3	8:1c6281289d67	183	* @brief Resets the RCC clock configuration to the default reset state.
n0tform3	8:1c6281289d67	184	* @note The default reset state of the clock configuration is given below:
n0tform3	8:1c6281289d67	185	* - HSI ON and used as system clock source
n0tform3	8:1c6281289d67	186	* - HSE, PLL and PLLI2S OFF
n0tform3	8:1c6281289d67	187	* - AHB, APB1 and APB2 prescaler set to 1.
n0tform3	8:1c6281289d67	188	* - CSS, MCO1 and MCO2 OFF
n0tform3	8:1c6281289d67	189	* - All interrupts disabled
n0tform3	8:1c6281289d67	190	* @note This function doesn't modify the configuration of the
n0tform3	8:1c6281289d67	191	* - Peripheral clocks
n0tform3	8:1c6281289d67	192	* - LSI, LSE and RTC clocks
n0tform3	8:1c6281289d67	193	* @param None
n0tform3	8:1c6281289d67	194	* @retval None
n0tform3	8:1c6281289d67	195	*/
n0tform3	8:1c6281289d67	196	void RCC_DeInit(void)
n0tform3	8:1c6281289d67	197	{
n0tform3	8:1c6281289d67	198	/* Set HSION bit */
n0tform3	8:1c6281289d67	199	RCC->CR \|= (uint32_t)0x00000001;
n0tform3	8:1c6281289d67	200
n0tform3	8:1c6281289d67	201	/* Reset CFGR register */
n0tform3	8:1c6281289d67	202	RCC->CFGR = 0x00000000;
n0tform3	8:1c6281289d67	203
n0tform3	8:1c6281289d67	204	/* Reset HSEON, CSSON and PLLON bits */
n0tform3	8:1c6281289d67	205	RCC->CR &= (uint32_t)0xFEF6FFFF;
n0tform3	8:1c6281289d67	206
n0tform3	8:1c6281289d67	207	/* Reset PLLCFGR register */
n0tform3	8:1c6281289d67	208	RCC->PLLCFGR = 0x24003010;
n0tform3	8:1c6281289d67	209
n0tform3	8:1c6281289d67	210	/* Reset HSEBYP bit */
n0tform3	8:1c6281289d67	211	RCC->CR &= (uint32_t)0xFFFBFFFF;
n0tform3	8:1c6281289d67	212
n0tform3	8:1c6281289d67	213	/* Disable all interrupts */
n0tform3	8:1c6281289d67	214	RCC->CIR = 0x00000000;
n0tform3	8:1c6281289d67	215	}
n0tform3	8:1c6281289d67	216
n0tform3	8:1c6281289d67	217	/**
n0tform3	8:1c6281289d67	218	* @brief Configures the External High Speed oscillator (HSE).
n0tform3	8:1c6281289d67	219	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
n0tform3	8:1c6281289d67	220	* software should wait on HSERDY flag to be set indicating that HSE clock
n0tform3	8:1c6281289d67	221	* is stable and can be used to clock the PLL and/or system clock.
n0tform3	8:1c6281289d67	222	* @note HSE state can not be changed if it is used directly or through the
n0tform3	8:1c6281289d67	223	* PLL as system clock. In this case, you have to select another source
n0tform3	8:1c6281289d67	224	* of the system clock then change the HSE state (ex. disable it).
n0tform3	8:1c6281289d67	225	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
n0tform3	8:1c6281289d67	226	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
n0tform3	8:1c6281289d67	227	* was previously enabled you have to enable it again after calling this
n0tform3	8:1c6281289d67	228	* function.
n0tform3	8:1c6281289d67	229	* @param RCC_HSE: specifies the new state of the HSE.
n0tform3	8:1c6281289d67	230	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	231	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
n0tform3	8:1c6281289d67	232	* 6 HSE oscillator clock cycles.
n0tform3	8:1c6281289d67	233	* @arg RCC_HSE_ON: turn ON the HSE oscillator
n0tform3	8:1c6281289d67	234	* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
n0tform3	8:1c6281289d67	235	* @retval None
n0tform3	8:1c6281289d67	236	*/
n0tform3	8:1c6281289d67	237	void RCC_HSEConfig(uint8_t RCC_HSE)
n0tform3	8:1c6281289d67	238	{
n0tform3	8:1c6281289d67	239	/* Check the parameters */
n0tform3	8:1c6281289d67	240	assert_param(IS_RCC_HSE(RCC_HSE));
n0tform3	8:1c6281289d67	241
n0tform3	8:1c6281289d67	242	/* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
n0tform3	8:1c6281289d67	243	(__IO uint8_t ) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
n0tform3	8:1c6281289d67	244
n0tform3	8:1c6281289d67	245	/* Set the new HSE configuration -------------------------------------------*/
n0tform3	8:1c6281289d67	246	(__IO uint8_t ) CR_BYTE3_ADDRESS = RCC_HSE;
n0tform3	8:1c6281289d67	247	}
n0tform3	8:1c6281289d67	248
n0tform3	8:1c6281289d67	249	/**
n0tform3	8:1c6281289d67	250	* @brief Waits for HSE start-up.
n0tform3	8:1c6281289d67	251	* @note This functions waits on HSERDY flag to be set and return SUCCESS if
n0tform3	8:1c6281289d67	252	* this flag is set, otherwise returns ERROR if the timeout is reached
n0tform3	8:1c6281289d67	253	* and this flag is not set. The timeout value is defined by the constant
n0tform3	8:1c6281289d67	254	* HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
n0tform3	8:1c6281289d67	255	* on the HSE crystal used in your application.
n0tform3	8:1c6281289d67	256	* @param None
n0tform3	8:1c6281289d67	257	* @retval An ErrorStatus enumeration value:
n0tform3	8:1c6281289d67	258	* - SUCCESS: HSE oscillator is stable and ready to use
n0tform3	8:1c6281289d67	259	* - ERROR: HSE oscillator not yet ready
n0tform3	8:1c6281289d67	260	*/
n0tform3	8:1c6281289d67	261	ErrorStatus RCC_WaitForHSEStartUp(void)
n0tform3	8:1c6281289d67	262	{
n0tform3	8:1c6281289d67	263	__IO uint32_t startupcounter = 0;
n0tform3	8:1c6281289d67	264	ErrorStatus status = ERROR;
n0tform3	8:1c6281289d67	265	FlagStatus hsestatus = RESET;
n0tform3	8:1c6281289d67	266	/* Wait till HSE is ready and if Time out is reached exit */
n0tform3	8:1c6281289d67	267	do
n0tform3	8:1c6281289d67	268	{
n0tform3	8:1c6281289d67	269	hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
n0tform3	8:1c6281289d67	270	startupcounter++;
n0tform3	8:1c6281289d67	271	} while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
n0tform3	8:1c6281289d67	272
n0tform3	8:1c6281289d67	273	if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
n0tform3	8:1c6281289d67	274	{
n0tform3	8:1c6281289d67	275	status = SUCCESS;
n0tform3	8:1c6281289d67	276	}
n0tform3	8:1c6281289d67	277	else
n0tform3	8:1c6281289d67	278	{
n0tform3	8:1c6281289d67	279	status = ERROR;
n0tform3	8:1c6281289d67	280	}
n0tform3	8:1c6281289d67	281	return (status);
n0tform3	8:1c6281289d67	282	}
n0tform3	8:1c6281289d67	283
n0tform3	8:1c6281289d67	284	/**
n0tform3	8:1c6281289d67	285	* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
n0tform3	8:1c6281289d67	286	* @note The calibration is used to compensate for the variations in voltage
n0tform3	8:1c6281289d67	287	* and temperature that influence the frequency of the internal HSI RC.
n0tform3	8:1c6281289d67	288	* @param HSICalibrationValue: specifies the calibration trimming value.
n0tform3	8:1c6281289d67	289	* This parameter must be a number between 0 and 0x1F.
n0tform3	8:1c6281289d67	290	* @retval None
n0tform3	8:1c6281289d67	291	*/
n0tform3	8:1c6281289d67	292	void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
n0tform3	8:1c6281289d67	293	{
n0tform3	8:1c6281289d67	294	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	295	/* Check the parameters */
n0tform3	8:1c6281289d67	296	assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
n0tform3	8:1c6281289d67	297
n0tform3	8:1c6281289d67	298	tmpreg = RCC->CR;
n0tform3	8:1c6281289d67	299
n0tform3	8:1c6281289d67	300	/* Clear HSITRIM[4:0] bits */
n0tform3	8:1c6281289d67	301	tmpreg &= ~RCC_CR_HSITRIM;
n0tform3	8:1c6281289d67	302
n0tform3	8:1c6281289d67	303	/* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
n0tform3	8:1c6281289d67	304	tmpreg \|= (uint32_t)HSICalibrationValue << 3;
n0tform3	8:1c6281289d67	305
n0tform3	8:1c6281289d67	306	/* Store the new value */
n0tform3	8:1c6281289d67	307	RCC->CR = tmpreg;
n0tform3	8:1c6281289d67	308	}
n0tform3	8:1c6281289d67	309
n0tform3	8:1c6281289d67	310	/**
n0tform3	8:1c6281289d67	311	* @brief Enables or disables the Internal High Speed oscillator (HSI).
n0tform3	8:1c6281289d67	312	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
n0tform3	8:1c6281289d67	313	* It is used (enabled by hardware) as system clock source after startup
n0tform3	8:1c6281289d67	314	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
n0tform3	8:1c6281289d67	315	* of the HSE used directly or indirectly as system clock (if the Clock
n0tform3	8:1c6281289d67	316	* Security System CSS is enabled).
n0tform3	8:1c6281289d67	317	* @note HSI can not be stopped if it is used as system clock source. In this case,
n0tform3	8:1c6281289d67	318	* you have to select another source of the system clock then stop the HSI.
n0tform3	8:1c6281289d67	319	* @note After enabling the HSI, the application software should wait on HSIRDY
n0tform3	8:1c6281289d67	320	* flag to be set indicating that HSI clock is stable and can be used as
n0tform3	8:1c6281289d67	321	* system clock source.
n0tform3	8:1c6281289d67	322	* @param NewState: new state of the HSI.
n0tform3	8:1c6281289d67	323	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	324	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
n0tform3	8:1c6281289d67	325	* clock cycles.
n0tform3	8:1c6281289d67	326	* @retval None
n0tform3	8:1c6281289d67	327	*/
n0tform3	8:1c6281289d67	328	void RCC_HSICmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	329	{
n0tform3	8:1c6281289d67	330	/* Check the parameters */
n0tform3	8:1c6281289d67	331	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	332
n0tform3	8:1c6281289d67	333	(__IO uint32_t ) CR_HSION_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	334	}
n0tform3	8:1c6281289d67	335
n0tform3	8:1c6281289d67	336	/**
n0tform3	8:1c6281289d67	337	* @brief Configures the External Low Speed oscillator (LSE).
n0tform3	8:1c6281289d67	338	* @note As the LSE is in the Backup domain and write access is denied to
n0tform3	8:1c6281289d67	339	* this domain after reset, you have to enable write access using
n0tform3	8:1c6281289d67	340	* PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
n0tform3	8:1c6281289d67	341	* (to be done once after reset).
n0tform3	8:1c6281289d67	342	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
n0tform3	8:1c6281289d67	343	* software should wait on LSERDY flag to be set indicating that LSE clock
n0tform3	8:1c6281289d67	344	* is stable and can be used to clock the RTC.
n0tform3	8:1c6281289d67	345	* @param RCC_LSE: specifies the new state of the LSE.
n0tform3	8:1c6281289d67	346	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	347	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
n0tform3	8:1c6281289d67	348	* 6 LSE oscillator clock cycles.
n0tform3	8:1c6281289d67	349	* @arg RCC_LSE_ON: turn ON the LSE oscillator
n0tform3	8:1c6281289d67	350	* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
n0tform3	8:1c6281289d67	351	* @retval None
n0tform3	8:1c6281289d67	352	*/
n0tform3	8:1c6281289d67	353	void RCC_LSEConfig(uint8_t RCC_LSE)
n0tform3	8:1c6281289d67	354	{
n0tform3	8:1c6281289d67	355	/* Check the parameters */
n0tform3	8:1c6281289d67	356	assert_param(IS_RCC_LSE(RCC_LSE));
n0tform3	8:1c6281289d67	357
n0tform3	8:1c6281289d67	358	/* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
n0tform3	8:1c6281289d67	359	/* Reset LSEON bit */
n0tform3	8:1c6281289d67	360	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_OFF;
n0tform3	8:1c6281289d67	361
n0tform3	8:1c6281289d67	362	/* Reset LSEBYP bit */
n0tform3	8:1c6281289d67	363	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_OFF;
n0tform3	8:1c6281289d67	364
n0tform3	8:1c6281289d67	365	/* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
n0tform3	8:1c6281289d67	366	switch (RCC_LSE)
n0tform3	8:1c6281289d67	367	{
n0tform3	8:1c6281289d67	368	case RCC_LSE_ON:
n0tform3	8:1c6281289d67	369	/* Set LSEON bit */
n0tform3	8:1c6281289d67	370	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_ON;
n0tform3	8:1c6281289d67	371	break;
n0tform3	8:1c6281289d67	372	case RCC_LSE_Bypass:
n0tform3	8:1c6281289d67	373	/* Set LSEBYP and LSEON bits */
n0tform3	8:1c6281289d67	374	(__IO uint8_t ) BDCR_ADDRESS = RCC_LSE_Bypass \| RCC_LSE_ON;
n0tform3	8:1c6281289d67	375	break;
n0tform3	8:1c6281289d67	376	default:
n0tform3	8:1c6281289d67	377	break;
n0tform3	8:1c6281289d67	378	}
n0tform3	8:1c6281289d67	379	}
n0tform3	8:1c6281289d67	380
n0tform3	8:1c6281289d67	381	/**
n0tform3	8:1c6281289d67	382	* @brief Enables or disables the Internal Low Speed oscillator (LSI).
n0tform3	8:1c6281289d67	383	* @note After enabling the LSI, the application software should wait on
n0tform3	8:1c6281289d67	384	* LSIRDY flag to be set indicating that LSI clock is stable and can
n0tform3	8:1c6281289d67	385	* be used to clock the IWDG and/or the RTC.
n0tform3	8:1c6281289d67	386	* @note LSI can not be disabled if the IWDG is running.
n0tform3	8:1c6281289d67	387	* @param NewState: new state of the LSI.
n0tform3	8:1c6281289d67	388	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	389	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
n0tform3	8:1c6281289d67	390	* clock cycles.
n0tform3	8:1c6281289d67	391	* @retval None
n0tform3	8:1c6281289d67	392	*/
n0tform3	8:1c6281289d67	393	void RCC_LSICmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	394	{
n0tform3	8:1c6281289d67	395	/* Check the parameters */
n0tform3	8:1c6281289d67	396	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	397
n0tform3	8:1c6281289d67	398	(__IO uint32_t ) CSR_LSION_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	399	}
n0tform3	8:1c6281289d67	400
n0tform3	8:1c6281289d67	401	/**
n0tform3	8:1c6281289d67	402	* @brief Configures the main PLL clock source, multiplication and division factors.
n0tform3	8:1c6281289d67	403	* @note This function must be used only when the main PLL is disabled.
n0tform3	8:1c6281289d67	404	*
n0tform3	8:1c6281289d67	405	* @param RCC_PLLSource: specifies the PLL entry clock source.
n0tform3	8:1c6281289d67	406	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	407	* @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
n0tform3	8:1c6281289d67	408	* @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
n0tform3	8:1c6281289d67	409	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
n0tform3	8:1c6281289d67	410	*
n0tform3	8:1c6281289d67	411	* @param PLLM: specifies the division factor for PLL VCO input clock
n0tform3	8:1c6281289d67	412	* This parameter must be a number between 0 and 63.
n0tform3	8:1c6281289d67	413	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
n0tform3	8:1c6281289d67	414	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
n0tform3	8:1c6281289d67	415	* of 2 MHz to limit PLL jitter.
n0tform3	8:1c6281289d67	416	*
n0tform3	8:1c6281289d67	417	* @param PLLN: specifies the multiplication factor for PLL VCO output clock
n0tform3	8:1c6281289d67	418	* This parameter must be a number between 192 and 432.
n0tform3	8:1c6281289d67	419	* @note You have to set the PLLN parameter correctly to ensure that the VCO
n0tform3	8:1c6281289d67	420	* output frequency is between 192 and 432 MHz.
n0tform3	8:1c6281289d67	421	*
n0tform3	8:1c6281289d67	422	* @param PLLP: specifies the division factor for main system clock (SYSCLK)
n0tform3	8:1c6281289d67	423	* This parameter must be a number in the range {2, 4, 6, or 8}.
n0tform3	8:1c6281289d67	424	* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
n0tform3	8:1c6281289d67	425	* the System clock frequency.
n0tform3	8:1c6281289d67	426	*
n0tform3	8:1c6281289d67	427	* @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
n0tform3	8:1c6281289d67	428	* This parameter must be a number between 4 and 15.
n0tform3	8:1c6281289d67	429	* @note If the USB OTG FS is used in your application, you have to set the
n0tform3	8:1c6281289d67	430	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
n0tform3	8:1c6281289d67	431	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
n0tform3	8:1c6281289d67	432	* correctly.
n0tform3	8:1c6281289d67	433	*
n0tform3	8:1c6281289d67	434	* @retval None
n0tform3	8:1c6281289d67	435	*/
n0tform3	8:1c6281289d67	436	void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
n0tform3	8:1c6281289d67	437	{
n0tform3	8:1c6281289d67	438	/* Check the parameters */
n0tform3	8:1c6281289d67	439	assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
n0tform3	8:1c6281289d67	440	assert_param(IS_RCC_PLLM_VALUE(PLLM));
n0tform3	8:1c6281289d67	441	assert_param(IS_RCC_PLLN_VALUE(PLLN));
n0tform3	8:1c6281289d67	442	assert_param(IS_RCC_PLLP_VALUE(PLLP));
n0tform3	8:1c6281289d67	443	assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
n0tform3	8:1c6281289d67	444
n0tform3	8:1c6281289d67	445	RCC->PLLCFGR = PLLM \| (PLLN << 6) \| (((PLLP >> 1) -1) << 16) \| (RCC_PLLSource) \|
n0tform3	8:1c6281289d67	446	(PLLQ << 24);
n0tform3	8:1c6281289d67	447	}
n0tform3	8:1c6281289d67	448
n0tform3	8:1c6281289d67	449	/**
n0tform3	8:1c6281289d67	450	* @brief Enables or disables the main PLL.
n0tform3	8:1c6281289d67	451	* @note After enabling the main PLL, the application software should wait on
n0tform3	8:1c6281289d67	452	* PLLRDY flag to be set indicating that PLL clock is stable and can
n0tform3	8:1c6281289d67	453	* be used as system clock source.
n0tform3	8:1c6281289d67	454	* @note The main PLL can not be disabled if it is used as system clock source
n0tform3	8:1c6281289d67	455	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
n0tform3	8:1c6281289d67	456	* @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	457	* @retval None
n0tform3	8:1c6281289d67	458	*/
n0tform3	8:1c6281289d67	459	void RCC_PLLCmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	460	{
n0tform3	8:1c6281289d67	461	/* Check the parameters */
n0tform3	8:1c6281289d67	462	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	463	(__IO uint32_t ) CR_PLLON_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	464	}
n0tform3	8:1c6281289d67	465
n0tform3	8:1c6281289d67	466	/**
n0tform3	8:1c6281289d67	467	* @brief Configures the PLLI2S clock multiplication and division factors.
n0tform3	8:1c6281289d67	468	*
n0tform3	8:1c6281289d67	469	* @note This function must be used only when the PLLI2S is disabled.
n0tform3	8:1c6281289d67	470	* @note PLLI2S clock source is common with the main PLL (configured in
n0tform3	8:1c6281289d67	471	* RCC_PLLConfig function )
n0tform3	8:1c6281289d67	472	*
n0tform3	8:1c6281289d67	473	* @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
n0tform3	8:1c6281289d67	474	* This parameter must be a number between 192 and 432.
n0tform3	8:1c6281289d67	475	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
n0tform3	8:1c6281289d67	476	* output frequency is between 192 and 432 MHz.
n0tform3	8:1c6281289d67	477	*
n0tform3	8:1c6281289d67	478	* @param PLLI2SR: specifies the division factor for I2S clock
n0tform3	8:1c6281289d67	479	* This parameter must be a number between 2 and 7.
n0tform3	8:1c6281289d67	480	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
n0tform3	8:1c6281289d67	481	* on the I2S clock frequency.
n0tform3	8:1c6281289d67	482	*
n0tform3	8:1c6281289d67	483	* @retval None
n0tform3	8:1c6281289d67	484	*/
n0tform3	8:1c6281289d67	485	void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
n0tform3	8:1c6281289d67	486	{
n0tform3	8:1c6281289d67	487	/* Check the parameters */
n0tform3	8:1c6281289d67	488	assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
n0tform3	8:1c6281289d67	489	assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
n0tform3	8:1c6281289d67	490
n0tform3	8:1c6281289d67	491	RCC->PLLI2SCFGR = (PLLI2SN << 6) \| (PLLI2SR << 28);
n0tform3	8:1c6281289d67	492	}
n0tform3	8:1c6281289d67	493
n0tform3	8:1c6281289d67	494	/**
n0tform3	8:1c6281289d67	495	* @brief Enables or disables the PLLI2S.
n0tform3	8:1c6281289d67	496	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
n0tform3	8:1c6281289d67	497	* @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	498	* @retval None
n0tform3	8:1c6281289d67	499	*/
n0tform3	8:1c6281289d67	500	void RCC_PLLI2SCmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	501	{
n0tform3	8:1c6281289d67	502	/* Check the parameters */
n0tform3	8:1c6281289d67	503	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	504	(__IO uint32_t ) CR_PLLI2SON_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	505	}
n0tform3	8:1c6281289d67	506
n0tform3	8:1c6281289d67	507	/**
n0tform3	8:1c6281289d67	508	* @brief Enables or disables the Clock Security System.
n0tform3	8:1c6281289d67	509	* @note If a failure is detected on the HSE oscillator clock, this oscillator
n0tform3	8:1c6281289d67	510	* is automatically disabled and an interrupt is generated to inform the
n0tform3	8:1c6281289d67	511	* software about the failure (Clock Security System Interrupt, CSSI),
n0tform3	8:1c6281289d67	512	* allowing the MCU to perform rescue operations. The CSSI is linked to
n0tform3	8:1c6281289d67	513	* the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
n0tform3	8:1c6281289d67	514	* @param NewState: new state of the Clock Security System.
n0tform3	8:1c6281289d67	515	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	516	* @retval None
n0tform3	8:1c6281289d67	517	*/
n0tform3	8:1c6281289d67	518	void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	519	{
n0tform3	8:1c6281289d67	520	/* Check the parameters */
n0tform3	8:1c6281289d67	521	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	522	(__IO uint32_t ) CR_CSSON_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	523	}
n0tform3	8:1c6281289d67	524
n0tform3	8:1c6281289d67	525	/**
n0tform3	8:1c6281289d67	526	* @brief Selects the clock source to output on MCO1 pin(PA8).
n0tform3	8:1c6281289d67	527	* @note PA8 should be configured in alternate function mode.
n0tform3	8:1c6281289d67	528	* @param RCC_MCO1Source: specifies the clock source to output.
n0tform3	8:1c6281289d67	529	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	530	* @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
n0tform3	8:1c6281289d67	531	* @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
n0tform3	8:1c6281289d67	532	* @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
n0tform3	8:1c6281289d67	533	* @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
n0tform3	8:1c6281289d67	534	* @param RCC_MCO1Div: specifies the MCO1 prescaler.
n0tform3	8:1c6281289d67	535	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	536	* @arg RCC_MCO1Div_1: no division applied to MCO1 clock
n0tform3	8:1c6281289d67	537	* @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
n0tform3	8:1c6281289d67	538	* @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
n0tform3	8:1c6281289d67	539	* @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
n0tform3	8:1c6281289d67	540	* @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
n0tform3	8:1c6281289d67	541	* @retval None
n0tform3	8:1c6281289d67	542	*/
n0tform3	8:1c6281289d67	543	void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
n0tform3	8:1c6281289d67	544	{
n0tform3	8:1c6281289d67	545	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	546
n0tform3	8:1c6281289d67	547	/* Check the parameters */
n0tform3	8:1c6281289d67	548	assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
n0tform3	8:1c6281289d67	549	assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
n0tform3	8:1c6281289d67	550
n0tform3	8:1c6281289d67	551	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	552
n0tform3	8:1c6281289d67	553	/* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
n0tform3	8:1c6281289d67	554	tmpreg &= CFGR_MCO1_RESET_MASK;
n0tform3	8:1c6281289d67	555
n0tform3	8:1c6281289d67	556	/* Select MCO1 clock source and prescaler */
n0tform3	8:1c6281289d67	557	tmpreg \|= RCC_MCO1Source \| RCC_MCO1Div;
n0tform3	8:1c6281289d67	558
n0tform3	8:1c6281289d67	559	/* Store the new value */
n0tform3	8:1c6281289d67	560	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	561	}
n0tform3	8:1c6281289d67	562
n0tform3	8:1c6281289d67	563	/**
n0tform3	8:1c6281289d67	564	* @brief Selects the clock source to output on MCO2 pin(PC9).
n0tform3	8:1c6281289d67	565	* @note PC9 should be configured in alternate function mode.
n0tform3	8:1c6281289d67	566	* @param RCC_MCO2Source: specifies the clock source to output.
n0tform3	8:1c6281289d67	567	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	568	* @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
n0tform3	8:1c6281289d67	569	* @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
n0tform3	8:1c6281289d67	570	* @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
n0tform3	8:1c6281289d67	571	* @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
n0tform3	8:1c6281289d67	572	* @param RCC_MCO2Div: specifies the MCO2 prescaler.
n0tform3	8:1c6281289d67	573	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	574	* @arg RCC_MCO2Div_1: no division applied to MCO2 clock
n0tform3	8:1c6281289d67	575	* @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
n0tform3	8:1c6281289d67	576	* @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
n0tform3	8:1c6281289d67	577	* @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
n0tform3	8:1c6281289d67	578	* @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
n0tform3	8:1c6281289d67	579	* @retval None
n0tform3	8:1c6281289d67	580	*/
n0tform3	8:1c6281289d67	581	void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
n0tform3	8:1c6281289d67	582	{
n0tform3	8:1c6281289d67	583	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	584
n0tform3	8:1c6281289d67	585	/* Check the parameters */
n0tform3	8:1c6281289d67	586	assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
n0tform3	8:1c6281289d67	587	assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
n0tform3	8:1c6281289d67	588
n0tform3	8:1c6281289d67	589	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	590
n0tform3	8:1c6281289d67	591	/* Clear MCO2 and MCO2PRE[2:0] bits */
n0tform3	8:1c6281289d67	592	tmpreg &= CFGR_MCO2_RESET_MASK;
n0tform3	8:1c6281289d67	593
n0tform3	8:1c6281289d67	594	/* Select MCO2 clock source and prescaler */
n0tform3	8:1c6281289d67	595	tmpreg \|= RCC_MCO2Source \| RCC_MCO2Div;
n0tform3	8:1c6281289d67	596
n0tform3	8:1c6281289d67	597	/* Store the new value */
n0tform3	8:1c6281289d67	598	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	599	}
n0tform3	8:1c6281289d67	600
n0tform3	8:1c6281289d67	601	/**
n0tform3	8:1c6281289d67	602	* @}
n0tform3	8:1c6281289d67	603	*/
n0tform3	8:1c6281289d67	604
n0tform3	8:1c6281289d67	605	/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
n0tform3	8:1c6281289d67	606	* @brief System, AHB and APB busses clocks configuration functions
n0tform3	8:1c6281289d67	607	*
n0tform3	8:1c6281289d67	608	@verbatim
n0tform3	8:1c6281289d67	609	===============================================================================
n0tform3	8:1c6281289d67	610	System, AHB and APB busses clocks configuration functions
n0tform3	8:1c6281289d67	611	===============================================================================
n0tform3	8:1c6281289d67	612
n0tform3	8:1c6281289d67	613	This section provide functions allowing to configure the System, AHB, APB1 and
n0tform3	8:1c6281289d67	614	APB2 busses clocks.
n0tform3	8:1c6281289d67	615
n0tform3	8:1c6281289d67	616	1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
n0tform3	8:1c6281289d67	617	HSE and PLL.
n0tform3	8:1c6281289d67	618	The AHB clock (HCLK) is derived from System clock through configurable prescaler
n0tform3	8:1c6281289d67	619	and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
n0tform3	8:1c6281289d67	620	APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
n0tform3	8:1c6281289d67	621	configurable prescalers and used to clock the peripherals mapped on these busses.
n0tform3	8:1c6281289d67	622	You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
n0tform3	8:1c6281289d67	623
n0tform3	8:1c6281289d67	624	@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
n0tform3	8:1c6281289d67	625	- I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
n0tform3	8:1c6281289d67	626	from an external clock mapped on the I2S_CKIN pin.
n0tform3	8:1c6281289d67	627	You have to use RCC_I2SCLKConfig() function to configure this clock.
n0tform3	8:1c6281289d67	628	- RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
n0tform3	8:1c6281289d67	629	divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
n0tform3	8:1c6281289d67	630	functions to configure this clock.
n0tform3	8:1c6281289d67	631	- USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
n0tform3	8:1c6281289d67	632	to work correctly, while the SDIO require a frequency equal or lower than
n0tform3	8:1c6281289d67	633	to 48. This clock is derived of the main PLL through PLLQ divider.
n0tform3	8:1c6281289d67	634	- IWDG clock which is always the LSI clock.
n0tform3	8:1c6281289d67	635
n0tform3	8:1c6281289d67	636	2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.
n0tform3	8:1c6281289d67	637	Depending on the device voltage range, the maximum frequency should be
n0tform3	8:1c6281289d67	638	adapted accordingly:
n0tform3	8:1c6281289d67	639	+-------------------------------------------------------------------------------------+
n0tform3	8:1c6281289d67	640	\| Latency \| HCLK clock frequency (MHz) \|
n0tform3	8:1c6281289d67	641	\| \|---------------------------------------------------------------------\|
n0tform3	8:1c6281289d67	642	\| \| voltage range \| voltage range \| voltage range \| voltage range \|
n0tform3	8:1c6281289d67	643	\| \| 2.7 V - 3.6 V \| 2.4 V - 2.7 V \| 2.1 V - 2.4 V \| 1.8 V - 2.1 V \|
n0tform3	8:1c6281289d67	644	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	645	\|0WS(1CPU cycle)\|0 < HCLK <= 30 \|0 < HCLK <= 24 \|0 < HCLK <= 18 \|0 < HCLK <= 16 \|
n0tform3	8:1c6281289d67	646	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	647	\|1WS(2CPU cycle)\|30 < HCLK <= 60 \|24 < HCLK <= 48 \|18 < HCLK <= 36 \|16 < HCLK <= 32 \|
n0tform3	8:1c6281289d67	648	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	649	\|2WS(3CPU cycle)\|60 < HCLK <= 90 \|48 < HCLK <= 72 \|36 < HCLK <= 54 \|32 < HCLK <= 48 \|
n0tform3	8:1c6281289d67	650	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	651	\|3WS(4CPU cycle)\|90 < HCLK <= 120\|72 < HCLK <= 96 \|54 < HCLK <= 72 \|48 < HCLK <= 64 \|
n0tform3	8:1c6281289d67	652	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	653	\|4WS(5CPU cycle)\|120< HCLK <= 150\|96 < HCLK <= 120\|72 < HCLK <= 90 \|64 < HCLK <= 80 \|
n0tform3	8:1c6281289d67	654	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	655	\|5WS(6CPU cycle)\|120< HCLK <= 168\|120< HCLK <= 144\|90 < HCLK <= 108 \|80 < HCLK <= 96 \|
n0tform3	8:1c6281289d67	656	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	657	\|6WS(7CPU cycle)\| NA \|144< HCLK <= 168\|108 < HCLK <= 120\|96 < HCLK <= 112 \|
n0tform3	8:1c6281289d67	658	\|---------------\|----------------\|----------------\|-----------------\|-----------------\|
n0tform3	8:1c6281289d67	659	\|7WS(8CPU cycle)\| NA \| NA \|120 < HCLK <= 138\|112 < HCLK <= 120\|
n0tform3	8:1c6281289d67	660	+-------------------------------------------------------------------------------------+
n0tform3	8:1c6281289d67	661	@note When VOS bit (in PWR_CR register) is reset to '0, the maximum value of HCLK is 144 MHz.
n0tform3	8:1c6281289d67	662	You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
n0tform3	8:1c6281289d67	663
n0tform3	8:1c6281289d67	664	@endverbatim
n0tform3	8:1c6281289d67	665	* @{
n0tform3	8:1c6281289d67	666	*/
n0tform3	8:1c6281289d67	667
n0tform3	8:1c6281289d67	668	/**
n0tform3	8:1c6281289d67	669	* @brief Configures the system clock (SYSCLK).
n0tform3	8:1c6281289d67	670	* @note The HSI is used (enabled by hardware) as system clock source after
n0tform3	8:1c6281289d67	671	* startup from Reset, wake-up from STOP and STANDBY mode, or in case
n0tform3	8:1c6281289d67	672	* of failure of the HSE used directly or indirectly as system clock
n0tform3	8:1c6281289d67	673	* (if the Clock Security System CSS is enabled).
n0tform3	8:1c6281289d67	674	* @note A switch from one clock source to another occurs only if the target
n0tform3	8:1c6281289d67	675	* clock source is ready (clock stable after startup delay or PLL locked).
n0tform3	8:1c6281289d67	676	* If a clock source which is not yet ready is selected, the switch will
n0tform3	8:1c6281289d67	677	* occur when the clock source will be ready.
n0tform3	8:1c6281289d67	678	* You can use RCC_GetSYSCLKSource() function to know which clock is
n0tform3	8:1c6281289d67	679	* currently used as system clock source.
n0tform3	8:1c6281289d67	680	* @param RCC_SYSCLKSource: specifies the clock source used as system clock.
n0tform3	8:1c6281289d67	681	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	682	* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
n0tform3	8:1c6281289d67	683	* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
n0tform3	8:1c6281289d67	684	* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
n0tform3	8:1c6281289d67	685	* @retval None
n0tform3	8:1c6281289d67	686	*/
n0tform3	8:1c6281289d67	687	void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
n0tform3	8:1c6281289d67	688	{
n0tform3	8:1c6281289d67	689	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	690
n0tform3	8:1c6281289d67	691	/* Check the parameters */
n0tform3	8:1c6281289d67	692	assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
n0tform3	8:1c6281289d67	693
n0tform3	8:1c6281289d67	694	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	695
n0tform3	8:1c6281289d67	696	/* Clear SW[1:0] bits */
n0tform3	8:1c6281289d67	697	tmpreg &= ~RCC_CFGR_SW;
n0tform3	8:1c6281289d67	698
n0tform3	8:1c6281289d67	699	/* Set SW[1:0] bits according to RCC_SYSCLKSource value */
n0tform3	8:1c6281289d67	700	tmpreg \|= RCC_SYSCLKSource;
n0tform3	8:1c6281289d67	701
n0tform3	8:1c6281289d67	702	/* Store the new value */
n0tform3	8:1c6281289d67	703	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	704	}
n0tform3	8:1c6281289d67	705
n0tform3	8:1c6281289d67	706	/**
n0tform3	8:1c6281289d67	707	* @brief Returns the clock source used as system clock.
n0tform3	8:1c6281289d67	708	* @param None
n0tform3	8:1c6281289d67	709	* @retval The clock source used as system clock. The returned value can be one
n0tform3	8:1c6281289d67	710	* of the following:
n0tform3	8:1c6281289d67	711	* - 0x00: HSI used as system clock
n0tform3	8:1c6281289d67	712	* - 0x04: HSE used as system clock
n0tform3	8:1c6281289d67	713	* - 0x08: PLL used as system clock
n0tform3	8:1c6281289d67	714	*/
n0tform3	8:1c6281289d67	715	uint8_t RCC_GetSYSCLKSource(void)
n0tform3	8:1c6281289d67	716	{
n0tform3	8:1c6281289d67	717	return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
n0tform3	8:1c6281289d67	718	}
n0tform3	8:1c6281289d67	719
n0tform3	8:1c6281289d67	720	/**
n0tform3	8:1c6281289d67	721	* @brief Configures the AHB clock (HCLK).
n0tform3	8:1c6281289d67	722	* @note Depending on the device voltage range, the software has to set correctly
n0tform3	8:1c6281289d67	723	* these bits to ensure that HCLK not exceed the maximum allowed frequency
n0tform3	8:1c6281289d67	724	* (for more details refer to section above
n0tform3	8:1c6281289d67	725	* "CPU, AHB and APB busses clocks configuration functions")
n0tform3	8:1c6281289d67	726	* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
n0tform3	8:1c6281289d67	727	* the system clock (SYSCLK).
n0tform3	8:1c6281289d67	728	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	729	* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
n0tform3	8:1c6281289d67	730	* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
n0tform3	8:1c6281289d67	731	* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
n0tform3	8:1c6281289d67	732	* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
n0tform3	8:1c6281289d67	733	* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
n0tform3	8:1c6281289d67	734	* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
n0tform3	8:1c6281289d67	735	* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
n0tform3	8:1c6281289d67	736	* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
n0tform3	8:1c6281289d67	737	* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
n0tform3	8:1c6281289d67	738	* @retval None
n0tform3	8:1c6281289d67	739	*/
n0tform3	8:1c6281289d67	740	void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
n0tform3	8:1c6281289d67	741	{
n0tform3	8:1c6281289d67	742	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	743
n0tform3	8:1c6281289d67	744	/* Check the parameters */
n0tform3	8:1c6281289d67	745	assert_param(IS_RCC_HCLK(RCC_SYSCLK));
n0tform3	8:1c6281289d67	746
n0tform3	8:1c6281289d67	747	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	748
n0tform3	8:1c6281289d67	749	/* Clear HPRE[3:0] bits */
n0tform3	8:1c6281289d67	750	tmpreg &= ~RCC_CFGR_HPRE;
n0tform3	8:1c6281289d67	751
n0tform3	8:1c6281289d67	752	/* Set HPRE[3:0] bits according to RCC_SYSCLK value */
n0tform3	8:1c6281289d67	753	tmpreg \|= RCC_SYSCLK;
n0tform3	8:1c6281289d67	754
n0tform3	8:1c6281289d67	755	/* Store the new value */
n0tform3	8:1c6281289d67	756	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	757	}
n0tform3	8:1c6281289d67	758
n0tform3	8:1c6281289d67	759
n0tform3	8:1c6281289d67	760	/**
n0tform3	8:1c6281289d67	761	* @brief Configures the Low Speed APB clock (PCLK1).
n0tform3	8:1c6281289d67	762	* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
n0tform3	8:1c6281289d67	763	* the AHB clock (HCLK).
n0tform3	8:1c6281289d67	764	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	765	* @arg RCC_HCLK_Div1: APB1 clock = HCLK
n0tform3	8:1c6281289d67	766	* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
n0tform3	8:1c6281289d67	767	* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
n0tform3	8:1c6281289d67	768	* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
n0tform3	8:1c6281289d67	769	* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
n0tform3	8:1c6281289d67	770	* @retval None
n0tform3	8:1c6281289d67	771	*/
n0tform3	8:1c6281289d67	772	void RCC_PCLK1Config(uint32_t RCC_HCLK)
n0tform3	8:1c6281289d67	773	{
n0tform3	8:1c6281289d67	774	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	775
n0tform3	8:1c6281289d67	776	/* Check the parameters */
n0tform3	8:1c6281289d67	777	assert_param(IS_RCC_PCLK(RCC_HCLK));
n0tform3	8:1c6281289d67	778
n0tform3	8:1c6281289d67	779	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	780
n0tform3	8:1c6281289d67	781	/* Clear PPRE1[2:0] bits */
n0tform3	8:1c6281289d67	782	tmpreg &= ~RCC_CFGR_PPRE1;
n0tform3	8:1c6281289d67	783
n0tform3	8:1c6281289d67	784	/* Set PPRE1[2:0] bits according to RCC_HCLK value */
n0tform3	8:1c6281289d67	785	tmpreg \|= RCC_HCLK;
n0tform3	8:1c6281289d67	786
n0tform3	8:1c6281289d67	787	/* Store the new value */
n0tform3	8:1c6281289d67	788	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	789	}
n0tform3	8:1c6281289d67	790
n0tform3	8:1c6281289d67	791	/**
n0tform3	8:1c6281289d67	792	* @brief Configures the High Speed APB clock (PCLK2).
n0tform3	8:1c6281289d67	793	* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
n0tform3	8:1c6281289d67	794	* the AHB clock (HCLK).
n0tform3	8:1c6281289d67	795	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	796	* @arg RCC_HCLK_Div1: APB2 clock = HCLK
n0tform3	8:1c6281289d67	797	* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
n0tform3	8:1c6281289d67	798	* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
n0tform3	8:1c6281289d67	799	* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
n0tform3	8:1c6281289d67	800	* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
n0tform3	8:1c6281289d67	801	* @retval None
n0tform3	8:1c6281289d67	802	*/
n0tform3	8:1c6281289d67	803	void RCC_PCLK2Config(uint32_t RCC_HCLK)
n0tform3	8:1c6281289d67	804	{
n0tform3	8:1c6281289d67	805	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	806
n0tform3	8:1c6281289d67	807	/* Check the parameters */
n0tform3	8:1c6281289d67	808	assert_param(IS_RCC_PCLK(RCC_HCLK));
n0tform3	8:1c6281289d67	809
n0tform3	8:1c6281289d67	810	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	811
n0tform3	8:1c6281289d67	812	/* Clear PPRE2[2:0] bits */
n0tform3	8:1c6281289d67	813	tmpreg &= ~RCC_CFGR_PPRE2;
n0tform3	8:1c6281289d67	814
n0tform3	8:1c6281289d67	815	/* Set PPRE2[2:0] bits according to RCC_HCLK value */
n0tform3	8:1c6281289d67	816	tmpreg \|= RCC_HCLK << 3;
n0tform3	8:1c6281289d67	817
n0tform3	8:1c6281289d67	818	/* Store the new value */
n0tform3	8:1c6281289d67	819	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	820	}
n0tform3	8:1c6281289d67	821
n0tform3	8:1c6281289d67	822	/**
n0tform3	8:1c6281289d67	823	* @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
n0tform3	8:1c6281289d67	824	* PCLK1 and PCLK2.
n0tform3	8:1c6281289d67	825	*
n0tform3	8:1c6281289d67	826	* @note The system frequency computed by this function is not the real
n0tform3	8:1c6281289d67	827	* frequency in the chip. It is calculated based on the predefined
n0tform3	8:1c6281289d67	828	* constant and the selected clock source:
n0tform3	8:1c6281289d67	829	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
n0tform3	8:1c6281289d67	830	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
n0tform3	8:1c6281289d67	831	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
n0tform3	8:1c6281289d67	832	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
n0tform3	8:1c6281289d67	833	* @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
n0tform3	8:1c6281289d67	834	* 16 MHz) but the real value may vary depending on the variations
n0tform3	8:1c6281289d67	835	* in voltage and temperature.
n0tform3	8:1c6281289d67	836	* @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
n0tform3	8:1c6281289d67	837	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
n0tform3	8:1c6281289d67	838	* frequency of the crystal used. Otherwise, this function may
n0tform3	8:1c6281289d67	839	* have wrong result.
n0tform3	8:1c6281289d67	840	*
n0tform3	8:1c6281289d67	841	* @note The result of this function could be not correct when using fractional
n0tform3	8:1c6281289d67	842	* value for HSE crystal.
n0tform3	8:1c6281289d67	843	*
n0tform3	8:1c6281289d67	844	* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
n0tform3	8:1c6281289d67	845	* the clocks frequencies.
n0tform3	8:1c6281289d67	846	*
n0tform3	8:1c6281289d67	847	* @note This function can be used by the user application to compute the
n0tform3	8:1c6281289d67	848	* baudrate for the communication peripherals or configure other parameters.
n0tform3	8:1c6281289d67	849	* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
n0tform3	8:1c6281289d67	850	* must be called to update the structure's field. Otherwise, any
n0tform3	8:1c6281289d67	851	* configuration based on this function will be incorrect.
n0tform3	8:1c6281289d67	852	*
n0tform3	8:1c6281289d67	853	* @retval None
n0tform3	8:1c6281289d67	854	*/
n0tform3	8:1c6281289d67	855	void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
n0tform3	8:1c6281289d67	856	{
n0tform3	8:1c6281289d67	857	uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
n0tform3	8:1c6281289d67	858
n0tform3	8:1c6281289d67	859	/* Get SYSCLK source -------------------------------------------------------*/
n0tform3	8:1c6281289d67	860	tmp = RCC->CFGR & RCC_CFGR_SWS;
n0tform3	8:1c6281289d67	861
n0tform3	8:1c6281289d67	862	switch (tmp)
n0tform3	8:1c6281289d67	863	{
n0tform3	8:1c6281289d67	864	case 0x00: /* HSI used as system clock source */
n0tform3	8:1c6281289d67	865	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
n0tform3	8:1c6281289d67	866	break;
n0tform3	8:1c6281289d67	867	case 0x04: /* HSE used as system clock source */
n0tform3	8:1c6281289d67	868	RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
n0tform3	8:1c6281289d67	869	break;
n0tform3	8:1c6281289d67	870	case 0x08: /* PLL used as system clock source */
n0tform3	8:1c6281289d67	871
n0tform3	8:1c6281289d67	872	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
n0tform3	8:1c6281289d67	873	SYSCLK = PLL_VCO / PLLP
n0tform3	8:1c6281289d67	874	*/
n0tform3	8:1c6281289d67	875	pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
n0tform3	8:1c6281289d67	876	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
n0tform3	8:1c6281289d67	877
n0tform3	8:1c6281289d67	878	if (pllsource != 0)
n0tform3	8:1c6281289d67	879	{
n0tform3	8:1c6281289d67	880	/* HSE used as PLL clock source */
n0tform3	8:1c6281289d67	881	pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
n0tform3	8:1c6281289d67	882	}
n0tform3	8:1c6281289d67	883	else
n0tform3	8:1c6281289d67	884	{
n0tform3	8:1c6281289d67	885	/* HSI used as PLL clock source */
n0tform3	8:1c6281289d67	886	pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
n0tform3	8:1c6281289d67	887	}
n0tform3	8:1c6281289d67	888
n0tform3	8:1c6281289d67	889	pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
n0tform3	8:1c6281289d67	890	RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
n0tform3	8:1c6281289d67	891	break;
n0tform3	8:1c6281289d67	892	default:
n0tform3	8:1c6281289d67	893	RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
n0tform3	8:1c6281289d67	894	break;
n0tform3	8:1c6281289d67	895	}
n0tform3	8:1c6281289d67	896	/* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
n0tform3	8:1c6281289d67	897
n0tform3	8:1c6281289d67	898	/* Get HCLK prescaler */
n0tform3	8:1c6281289d67	899	tmp = RCC->CFGR & RCC_CFGR_HPRE;
n0tform3	8:1c6281289d67	900	tmp = tmp >> 4;
n0tform3	8:1c6281289d67	901	presc = APBAHBPrescTable[tmp];
n0tform3	8:1c6281289d67	902	/* HCLK clock frequency */
n0tform3	8:1c6281289d67	903	RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
n0tform3	8:1c6281289d67	904
n0tform3	8:1c6281289d67	905	/* Get PCLK1 prescaler */
n0tform3	8:1c6281289d67	906	tmp = RCC->CFGR & RCC_CFGR_PPRE1;
n0tform3	8:1c6281289d67	907	tmp = tmp >> 10;
n0tform3	8:1c6281289d67	908	presc = APBAHBPrescTable[tmp];
n0tform3	8:1c6281289d67	909	/* PCLK1 clock frequency */
n0tform3	8:1c6281289d67	910	RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
n0tform3	8:1c6281289d67	911
n0tform3	8:1c6281289d67	912	/* Get PCLK2 prescaler */
n0tform3	8:1c6281289d67	913	tmp = RCC->CFGR & RCC_CFGR_PPRE2;
n0tform3	8:1c6281289d67	914	tmp = tmp >> 13;
n0tform3	8:1c6281289d67	915	presc = APBAHBPrescTable[tmp];
n0tform3	8:1c6281289d67	916	/* PCLK2 clock frequency */
n0tform3	8:1c6281289d67	917	RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
n0tform3	8:1c6281289d67	918	}
n0tform3	8:1c6281289d67	919
n0tform3	8:1c6281289d67	920	/**
n0tform3	8:1c6281289d67	921	* @}
n0tform3	8:1c6281289d67	922	*/
n0tform3	8:1c6281289d67	923
n0tform3	8:1c6281289d67	924	/** @defgroup RCC_Group3 Peripheral clocks configuration functions
n0tform3	8:1c6281289d67	925	* @brief Peripheral clocks configuration functions
n0tform3	8:1c6281289d67	926	*
n0tform3	8:1c6281289d67	927	@verbatim
n0tform3	8:1c6281289d67	928	===============================================================================
n0tform3	8:1c6281289d67	929	Peripheral clocks configuration functions
n0tform3	8:1c6281289d67	930	===============================================================================
n0tform3	8:1c6281289d67	931
n0tform3	8:1c6281289d67	932	This section provide functions allowing to configure the Peripheral clocks.
n0tform3	8:1c6281289d67	933
n0tform3	8:1c6281289d67	934	1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.
n0tform3	8:1c6281289d67	935
n0tform3	8:1c6281289d67	936	2. After restart from Reset or wakeup from STANDBY, all peripherals are off
n0tform3	8:1c6281289d67	937	except internal SRAM, Flash and JTAG. Before to start using a peripheral you
n0tform3	8:1c6281289d67	938	have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()
n0tform3	8:1c6281289d67	939	, RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
n0tform3	8:1c6281289d67	940
n0tform3	8:1c6281289d67	941	3. To reset the peripherals configuration (to the default state after device reset)
n0tform3	8:1c6281289d67	942	you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
n0tform3	8:1c6281289d67	943	RCC_APB1PeriphResetCmd() functions.
n0tform3	8:1c6281289d67	944
n0tform3	8:1c6281289d67	945	4. To further reduce power consumption in SLEEP mode the peripheral clocks can
n0tform3	8:1c6281289d67	946	be disabled prior to executing the WFI or WFE instructions. You can do this
n0tform3	8:1c6281289d67	947	using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and
n0tform3	8:1c6281289d67	948	RCC_APB1PeriphClockLPModeCmd() functions.
n0tform3	8:1c6281289d67	949
n0tform3	8:1c6281289d67	950	@endverbatim
n0tform3	8:1c6281289d67	951	* @{
n0tform3	8:1c6281289d67	952	*/
n0tform3	8:1c6281289d67	953
n0tform3	8:1c6281289d67	954	/**
n0tform3	8:1c6281289d67	955	* @brief Configures the RTC clock (RTCCLK).
n0tform3	8:1c6281289d67	956	* @note As the RTC clock configuration bits are in the Backup domain and write
n0tform3	8:1c6281289d67	957	* access is denied to this domain after reset, you have to enable write
n0tform3	8:1c6281289d67	958	* access using PWR_BackupAccessCmd(ENABLE) function before to configure
n0tform3	8:1c6281289d67	959	* the RTC clock source (to be done once after reset).
n0tform3	8:1c6281289d67	960	* @note Once the RTC clock is configured it can't be changed unless the
n0tform3	8:1c6281289d67	961	* Backup domain is reset using RCC_BackupResetCmd() function, or by
n0tform3	8:1c6281289d67	962	* a Power On Reset (POR).
n0tform3	8:1c6281289d67	963	*
n0tform3	8:1c6281289d67	964	* @param RCC_RTCCLKSource: specifies the RTC clock source.
n0tform3	8:1c6281289d67	965	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	966	* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
n0tform3	8:1c6281289d67	967	* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
n0tform3	8:1c6281289d67	968	* @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
n0tform3	8:1c6281289d67	969	* as RTC clock, where x:[2,31]
n0tform3	8:1c6281289d67	970	*
n0tform3	8:1c6281289d67	971	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
n0tform3	8:1c6281289d67	972	* work in STOP and STANDBY modes, and can be used as wakeup source.
n0tform3	8:1c6281289d67	973	* However, when the HSE clock is used as RTC clock source, the RTC
n0tform3	8:1c6281289d67	974	* cannot be used in STOP and STANDBY modes.
n0tform3	8:1c6281289d67	975	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
n0tform3	8:1c6281289d67	976	* RTC clock source).
n0tform3	8:1c6281289d67	977	*
n0tform3	8:1c6281289d67	978	* @retval None
n0tform3	8:1c6281289d67	979	*/
n0tform3	8:1c6281289d67	980	void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
n0tform3	8:1c6281289d67	981	{
n0tform3	8:1c6281289d67	982	uint32_t tmpreg = 0;
n0tform3	8:1c6281289d67	983
n0tform3	8:1c6281289d67	984	/* Check the parameters */
n0tform3	8:1c6281289d67	985	assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
n0tform3	8:1c6281289d67	986
n0tform3	8:1c6281289d67	987	if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
n0tform3	8:1c6281289d67	988	{ /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
n0tform3	8:1c6281289d67	989	tmpreg = RCC->CFGR;
n0tform3	8:1c6281289d67	990
n0tform3	8:1c6281289d67	991	/* Clear RTCPRE[4:0] bits */
n0tform3	8:1c6281289d67	992	tmpreg &= ~RCC_CFGR_RTCPRE;
n0tform3	8:1c6281289d67	993
n0tform3	8:1c6281289d67	994	/* Configure HSE division factor for RTC clock */
n0tform3	8:1c6281289d67	995	tmpreg \|= (RCC_RTCCLKSource & 0xFFFFCFF);
n0tform3	8:1c6281289d67	996
n0tform3	8:1c6281289d67	997	/* Store the new value */
n0tform3	8:1c6281289d67	998	RCC->CFGR = tmpreg;
n0tform3	8:1c6281289d67	999	}
n0tform3	8:1c6281289d67	1000
n0tform3	8:1c6281289d67	1001	/* Select the RTC clock source */
n0tform3	8:1c6281289d67	1002	RCC->BDCR \|= (RCC_RTCCLKSource & 0x00000FFF);
n0tform3	8:1c6281289d67	1003	}
n0tform3	8:1c6281289d67	1004
n0tform3	8:1c6281289d67	1005	/**
n0tform3	8:1c6281289d67	1006	* @brief Enables or disables the RTC clock.
n0tform3	8:1c6281289d67	1007	* @note This function must be used only after the RTC clock source was selected
n0tform3	8:1c6281289d67	1008	* using the RCC_RTCCLKConfig function.
n0tform3	8:1c6281289d67	1009	* @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1010	* @retval None
n0tform3	8:1c6281289d67	1011	*/
n0tform3	8:1c6281289d67	1012	void RCC_RTCCLKCmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	1013	{
n0tform3	8:1c6281289d67	1014	/* Check the parameters */
n0tform3	8:1c6281289d67	1015	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1016
n0tform3	8:1c6281289d67	1017	(__IO uint32_t ) BDCR_RTCEN_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	1018	}
n0tform3	8:1c6281289d67	1019
n0tform3	8:1c6281289d67	1020	/**
n0tform3	8:1c6281289d67	1021	* @brief Forces or releases the Backup domain reset.
n0tform3	8:1c6281289d67	1022	* @note This function resets the RTC peripheral (including the backup registers)
n0tform3	8:1c6281289d67	1023	* and the RTC clock source selection in RCC_CSR register.
n0tform3	8:1c6281289d67	1024	* @note The BKPSRAM is not affected by this reset.
n0tform3	8:1c6281289d67	1025	* @param NewState: new state of the Backup domain reset.
n0tform3	8:1c6281289d67	1026	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1027	* @retval None
n0tform3	8:1c6281289d67	1028	*/
n0tform3	8:1c6281289d67	1029	void RCC_BackupResetCmd(FunctionalState NewState)
n0tform3	8:1c6281289d67	1030	{
n0tform3	8:1c6281289d67	1031	/* Check the parameters */
n0tform3	8:1c6281289d67	1032	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1033	(__IO uint32_t ) BDCR_BDRST_BB = (uint32_t)NewState;
n0tform3	8:1c6281289d67	1034	}
n0tform3	8:1c6281289d67	1035
n0tform3	8:1c6281289d67	1036	/**
n0tform3	8:1c6281289d67	1037	* @brief Configures the I2S clock source (I2SCLK).
n0tform3	8:1c6281289d67	1038	* @note This function must be called before enabling the I2S APB clock.
n0tform3	8:1c6281289d67	1039	* @param RCC_I2SCLKSource: specifies the I2S clock source.
n0tform3	8:1c6281289d67	1040	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1041	* @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
n0tform3	8:1c6281289d67	1042	* @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
n0tform3	8:1c6281289d67	1043	* used as I2S clock source
n0tform3	8:1c6281289d67	1044	* @retval None
n0tform3	8:1c6281289d67	1045	*/
n0tform3	8:1c6281289d67	1046	void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
n0tform3	8:1c6281289d67	1047	{
n0tform3	8:1c6281289d67	1048	/* Check the parameters */
n0tform3	8:1c6281289d67	1049	assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
n0tform3	8:1c6281289d67	1050
n0tform3	8:1c6281289d67	1051	(__IO uint32_t ) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
n0tform3	8:1c6281289d67	1052	}
n0tform3	8:1c6281289d67	1053
n0tform3	8:1c6281289d67	1054	/**
n0tform3	8:1c6281289d67	1055	* @brief Enables or disables the AHB1 peripheral clock.
n0tform3	8:1c6281289d67	1056	* @note After reset, the peripheral clock (used for registers read/write access)
n0tform3	8:1c6281289d67	1057	* is disabled and the application software has to enable this clock before
n0tform3	8:1c6281289d67	1058	* using it.
n0tform3	8:1c6281289d67	1059	* @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1060	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1061	* @arg RCC_AHB1Periph_GPIOA: GPIOA clock
n0tform3	8:1c6281289d67	1062	* @arg RCC_AHB1Periph_GPIOB: GPIOB clock
n0tform3	8:1c6281289d67	1063	* @arg RCC_AHB1Periph_GPIOC: GPIOC clock
n0tform3	8:1c6281289d67	1064	* @arg RCC_AHB1Periph_GPIOD: GPIOD clock
n0tform3	8:1c6281289d67	1065	* @arg RCC_AHB1Periph_GPIOE: GPIOE clock
n0tform3	8:1c6281289d67	1066	* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
n0tform3	8:1c6281289d67	1067	* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
n0tform3	8:1c6281289d67	1068	* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
n0tform3	8:1c6281289d67	1069	* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
n0tform3	8:1c6281289d67	1070	* @arg RCC_AHB1Periph_CRC: CRC clock
n0tform3	8:1c6281289d67	1071	* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
n0tform3	8:1c6281289d67	1072	* @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
n0tform3	8:1c6281289d67	1073	* @arg RCC_AHB1Periph_DMA1: DMA1 clock
n0tform3	8:1c6281289d67	1074	* @arg RCC_AHB1Periph_DMA2: DMA2 clock
n0tform3	8:1c6281289d67	1075	* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
n0tform3	8:1c6281289d67	1076	* @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
n0tform3	8:1c6281289d67	1077	* @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
n0tform3	8:1c6281289d67	1078	* @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
n0tform3	8:1c6281289d67	1079	* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
n0tform3	8:1c6281289d67	1080	* @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
n0tform3	8:1c6281289d67	1081	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1082	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1083	* @retval None
n0tform3	8:1c6281289d67	1084	*/
n0tform3	8:1c6281289d67	1085	void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1086	{
n0tform3	8:1c6281289d67	1087	/* Check the parameters */
n0tform3	8:1c6281289d67	1088	assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
n0tform3	8:1c6281289d67	1089
n0tform3	8:1c6281289d67	1090	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1091	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1092	{
n0tform3	8:1c6281289d67	1093	RCC->AHB1ENR \|= RCC_AHB1Periph;
n0tform3	8:1c6281289d67	1094	}
n0tform3	8:1c6281289d67	1095	else
n0tform3	8:1c6281289d67	1096	{
n0tform3	8:1c6281289d67	1097	RCC->AHB1ENR &= ~RCC_AHB1Periph;
n0tform3	8:1c6281289d67	1098	}
n0tform3	8:1c6281289d67	1099	}
n0tform3	8:1c6281289d67	1100
n0tform3	8:1c6281289d67	1101	/**
n0tform3	8:1c6281289d67	1102	* @brief Enables or disables the AHB2 peripheral clock.
n0tform3	8:1c6281289d67	1103	* @note After reset, the peripheral clock (used for registers read/write access)
n0tform3	8:1c6281289d67	1104	* is disabled and the application software has to enable this clock before
n0tform3	8:1c6281289d67	1105	* using it.
n0tform3	8:1c6281289d67	1106	* @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1107	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1108	* @arg RCC_AHB2Periph_DCMI: DCMI clock
n0tform3	8:1c6281289d67	1109	* @arg RCC_AHB2Periph_CRYP: CRYP clock
n0tform3	8:1c6281289d67	1110	* @arg RCC_AHB2Periph_HASH: HASH clock
n0tform3	8:1c6281289d67	1111	* @arg RCC_AHB2Periph_RNG: RNG clock
n0tform3	8:1c6281289d67	1112	* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
n0tform3	8:1c6281289d67	1113	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1114	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1115	* @retval None
n0tform3	8:1c6281289d67	1116	*/
n0tform3	8:1c6281289d67	1117	void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1118	{
n0tform3	8:1c6281289d67	1119	/* Check the parameters */
n0tform3	8:1c6281289d67	1120	assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
n0tform3	8:1c6281289d67	1121	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1122
n0tform3	8:1c6281289d67	1123	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1124	{
n0tform3	8:1c6281289d67	1125	RCC->AHB2ENR \|= RCC_AHB2Periph;
n0tform3	8:1c6281289d67	1126	}
n0tform3	8:1c6281289d67	1127	else
n0tform3	8:1c6281289d67	1128	{
n0tform3	8:1c6281289d67	1129	RCC->AHB2ENR &= ~RCC_AHB2Periph;
n0tform3	8:1c6281289d67	1130	}
n0tform3	8:1c6281289d67	1131	}
n0tform3	8:1c6281289d67	1132
n0tform3	8:1c6281289d67	1133	/**
n0tform3	8:1c6281289d67	1134	* @brief Enables or disables the AHB3 peripheral clock.
n0tform3	8:1c6281289d67	1135	* @note After reset, the peripheral clock (used for registers read/write access)
n0tform3	8:1c6281289d67	1136	* is disabled and the application software has to enable this clock before
n0tform3	8:1c6281289d67	1137	* using it.
n0tform3	8:1c6281289d67	1138	* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1139	* This parameter must be: RCC_AHB3Periph_FSMC
n0tform3	8:1c6281289d67	1140	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1141	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1142	* @retval None
n0tform3	8:1c6281289d67	1143	*/
n0tform3	8:1c6281289d67	1144	void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1145	{
n0tform3	8:1c6281289d67	1146	/* Check the parameters */
n0tform3	8:1c6281289d67	1147	assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
n0tform3	8:1c6281289d67	1148	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1149
n0tform3	8:1c6281289d67	1150	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1151	{
n0tform3	8:1c6281289d67	1152	RCC->AHB3ENR \|= RCC_AHB3Periph;
n0tform3	8:1c6281289d67	1153	}
n0tform3	8:1c6281289d67	1154	else
n0tform3	8:1c6281289d67	1155	{
n0tform3	8:1c6281289d67	1156	RCC->AHB3ENR &= ~RCC_AHB3Periph;
n0tform3	8:1c6281289d67	1157	}
n0tform3	8:1c6281289d67	1158	}
n0tform3	8:1c6281289d67	1159
n0tform3	8:1c6281289d67	1160	/**
n0tform3	8:1c6281289d67	1161	* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
n0tform3	8:1c6281289d67	1162	* @note After reset, the peripheral clock (used for registers read/write access)
n0tform3	8:1c6281289d67	1163	* is disabled and the application software has to enable this clock before
n0tform3	8:1c6281289d67	1164	* using it.
n0tform3	8:1c6281289d67	1165	* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1166	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1167	* @arg RCC_APB1Periph_TIM2: TIM2 clock
n0tform3	8:1c6281289d67	1168	* @arg RCC_APB1Periph_TIM3: TIM3 clock
n0tform3	8:1c6281289d67	1169	* @arg RCC_APB1Periph_TIM4: TIM4 clock
n0tform3	8:1c6281289d67	1170	* @arg RCC_APB1Periph_TIM5: TIM5 clock
n0tform3	8:1c6281289d67	1171	* @arg RCC_APB1Periph_TIM6: TIM6 clock
n0tform3	8:1c6281289d67	1172	* @arg RCC_APB1Periph_TIM7: TIM7 clock
n0tform3	8:1c6281289d67	1173	* @arg RCC_APB1Periph_TIM12: TIM12 clock
n0tform3	8:1c6281289d67	1174	* @arg RCC_APB1Periph_TIM13: TIM13 clock
n0tform3	8:1c6281289d67	1175	* @arg RCC_APB1Periph_TIM14: TIM14 clock
n0tform3	8:1c6281289d67	1176	* @arg RCC_APB1Periph_WWDG: WWDG clock
n0tform3	8:1c6281289d67	1177	* @arg RCC_APB1Periph_SPI2: SPI2 clock
n0tform3	8:1c6281289d67	1178	* @arg RCC_APB1Periph_SPI3: SPI3 clock
n0tform3	8:1c6281289d67	1179	* @arg RCC_APB1Periph_USART2: USART2 clock
n0tform3	8:1c6281289d67	1180	* @arg RCC_APB1Periph_USART3: USART3 clock
n0tform3	8:1c6281289d67	1181	* @arg RCC_APB1Periph_UART4: UART4 clock
n0tform3	8:1c6281289d67	1182	* @arg RCC_APB1Periph_UART5: UART5 clock
n0tform3	8:1c6281289d67	1183	* @arg RCC_APB1Periph_I2C1: I2C1 clock
n0tform3	8:1c6281289d67	1184	* @arg RCC_APB1Periph_I2C2: I2C2 clock
n0tform3	8:1c6281289d67	1185	* @arg RCC_APB1Periph_I2C3: I2C3 clock
n0tform3	8:1c6281289d67	1186	* @arg RCC_APB1Periph_CAN1: CAN1 clock
n0tform3	8:1c6281289d67	1187	* @arg RCC_APB1Periph_CAN2: CAN2 clock
n0tform3	8:1c6281289d67	1188	* @arg RCC_APB1Periph_PWR: PWR clock
n0tform3	8:1c6281289d67	1189	* @arg RCC_APB1Periph_DAC: DAC clock
n0tform3	8:1c6281289d67	1190	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1191	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1192	* @retval None
n0tform3	8:1c6281289d67	1193	*/
n0tform3	8:1c6281289d67	1194	void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1195	{
n0tform3	8:1c6281289d67	1196	/* Check the parameters */
n0tform3	8:1c6281289d67	1197	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
n0tform3	8:1c6281289d67	1198	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1199
n0tform3	8:1c6281289d67	1200	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1201	{
n0tform3	8:1c6281289d67	1202	RCC->APB1ENR \|= RCC_APB1Periph;
n0tform3	8:1c6281289d67	1203	}
n0tform3	8:1c6281289d67	1204	else
n0tform3	8:1c6281289d67	1205	{
n0tform3	8:1c6281289d67	1206	RCC->APB1ENR &= ~RCC_APB1Periph;
n0tform3	8:1c6281289d67	1207	}
n0tform3	8:1c6281289d67	1208	}
n0tform3	8:1c6281289d67	1209
n0tform3	8:1c6281289d67	1210	/**
n0tform3	8:1c6281289d67	1211	* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
n0tform3	8:1c6281289d67	1212	* @note After reset, the peripheral clock (used for registers read/write access)
n0tform3	8:1c6281289d67	1213	* is disabled and the application software has to enable this clock before
n0tform3	8:1c6281289d67	1214	* using it.
n0tform3	8:1c6281289d67	1215	* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1216	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1217	* @arg RCC_APB2Periph_TIM1: TIM1 clock
n0tform3	8:1c6281289d67	1218	* @arg RCC_APB2Periph_TIM8: TIM8 clock
n0tform3	8:1c6281289d67	1219	* @arg RCC_APB2Periph_USART1: USART1 clock
n0tform3	8:1c6281289d67	1220	* @arg RCC_APB2Periph_USART6: USART6 clock
n0tform3	8:1c6281289d67	1221	* @arg RCC_APB2Periph_ADC1: ADC1 clock
n0tform3	8:1c6281289d67	1222	* @arg RCC_APB2Periph_ADC2: ADC2 clock
n0tform3	8:1c6281289d67	1223	* @arg RCC_APB2Periph_ADC3: ADC3 clock
n0tform3	8:1c6281289d67	1224	* @arg RCC_APB2Periph_SDIO: SDIO clock
n0tform3	8:1c6281289d67	1225	* @arg RCC_APB2Periph_SPI1: SPI1 clock
n0tform3	8:1c6281289d67	1226	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
n0tform3	8:1c6281289d67	1227	* @arg RCC_APB2Periph_TIM9: TIM9 clock
n0tform3	8:1c6281289d67	1228	* @arg RCC_APB2Periph_TIM10: TIM10 clock
n0tform3	8:1c6281289d67	1229	* @arg RCC_APB2Periph_TIM11: TIM11 clock
n0tform3	8:1c6281289d67	1230	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1231	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1232	* @retval None
n0tform3	8:1c6281289d67	1233	*/
n0tform3	8:1c6281289d67	1234	void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1235	{
n0tform3	8:1c6281289d67	1236	/* Check the parameters */
n0tform3	8:1c6281289d67	1237	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
n0tform3	8:1c6281289d67	1238	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1239
n0tform3	8:1c6281289d67	1240	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1241	{
n0tform3	8:1c6281289d67	1242	RCC->APB2ENR \|= RCC_APB2Periph;
n0tform3	8:1c6281289d67	1243	}
n0tform3	8:1c6281289d67	1244	else
n0tform3	8:1c6281289d67	1245	{
n0tform3	8:1c6281289d67	1246	RCC->APB2ENR &= ~RCC_APB2Periph;
n0tform3	8:1c6281289d67	1247	}
n0tform3	8:1c6281289d67	1248	}
n0tform3	8:1c6281289d67	1249
n0tform3	8:1c6281289d67	1250	/**
n0tform3	8:1c6281289d67	1251	* @brief Forces or releases AHB1 peripheral reset.
n0tform3	8:1c6281289d67	1252	* @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
n0tform3	8:1c6281289d67	1253	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1254	* @arg RCC_AHB1Periph_GPIOA: GPIOA clock
n0tform3	8:1c6281289d67	1255	* @arg RCC_AHB1Periph_GPIOB: GPIOB clock
n0tform3	8:1c6281289d67	1256	* @arg RCC_AHB1Periph_GPIOC: GPIOC clock
n0tform3	8:1c6281289d67	1257	* @arg RCC_AHB1Periph_GPIOD: GPIOD clock
n0tform3	8:1c6281289d67	1258	* @arg RCC_AHB1Periph_GPIOE: GPIOE clock
n0tform3	8:1c6281289d67	1259	* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
n0tform3	8:1c6281289d67	1260	* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
n0tform3	8:1c6281289d67	1261	* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
n0tform3	8:1c6281289d67	1262	* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
n0tform3	8:1c6281289d67	1263	* @arg RCC_AHB1Periph_CRC: CRC clock
n0tform3	8:1c6281289d67	1264	* @arg RCC_AHB1Periph_DMA1: DMA1 clock
n0tform3	8:1c6281289d67	1265	* @arg RCC_AHB1Periph_DMA2: DMA2 clock
n0tform3	8:1c6281289d67	1266	* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
n0tform3	8:1c6281289d67	1267	* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
n0tform3	8:1c6281289d67	1268	*
n0tform3	8:1c6281289d67	1269	* @param NewState: new state of the specified peripheral reset.
n0tform3	8:1c6281289d67	1270	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1271	* @retval None
n0tform3	8:1c6281289d67	1272	*/
n0tform3	8:1c6281289d67	1273	void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1274	{
n0tform3	8:1c6281289d67	1275	/* Check the parameters */
n0tform3	8:1c6281289d67	1276	assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
n0tform3	8:1c6281289d67	1277	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1278
n0tform3	8:1c6281289d67	1279	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1280	{
n0tform3	8:1c6281289d67	1281	RCC->AHB1RSTR \|= RCC_AHB1Periph;
n0tform3	8:1c6281289d67	1282	}
n0tform3	8:1c6281289d67	1283	else
n0tform3	8:1c6281289d67	1284	{
n0tform3	8:1c6281289d67	1285	RCC->AHB1RSTR &= ~RCC_AHB1Periph;
n0tform3	8:1c6281289d67	1286	}
n0tform3	8:1c6281289d67	1287	}
n0tform3	8:1c6281289d67	1288
n0tform3	8:1c6281289d67	1289	/**
n0tform3	8:1c6281289d67	1290	* @brief Forces or releases AHB2 peripheral reset.
n0tform3	8:1c6281289d67	1291	* @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
n0tform3	8:1c6281289d67	1292	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1293	* @arg RCC_AHB2Periph_DCMI: DCMI clock
n0tform3	8:1c6281289d67	1294	* @arg RCC_AHB2Periph_CRYP: CRYP clock
n0tform3	8:1c6281289d67	1295	* @arg RCC_AHB2Periph_HASH: HASH clock
n0tform3	8:1c6281289d67	1296	* @arg RCC_AHB2Periph_RNG: RNG clock
n0tform3	8:1c6281289d67	1297	* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
n0tform3	8:1c6281289d67	1298	* @param NewState: new state of the specified peripheral reset.
n0tform3	8:1c6281289d67	1299	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1300	* @retval None
n0tform3	8:1c6281289d67	1301	*/
n0tform3	8:1c6281289d67	1302	void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1303	{
n0tform3	8:1c6281289d67	1304	/* Check the parameters */
n0tform3	8:1c6281289d67	1305	assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
n0tform3	8:1c6281289d67	1306	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1307
n0tform3	8:1c6281289d67	1308	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1309	{
n0tform3	8:1c6281289d67	1310	RCC->AHB2RSTR \|= RCC_AHB2Periph;
n0tform3	8:1c6281289d67	1311	}
n0tform3	8:1c6281289d67	1312	else
n0tform3	8:1c6281289d67	1313	{
n0tform3	8:1c6281289d67	1314	RCC->AHB2RSTR &= ~RCC_AHB2Periph;
n0tform3	8:1c6281289d67	1315	}
n0tform3	8:1c6281289d67	1316	}
n0tform3	8:1c6281289d67	1317
n0tform3	8:1c6281289d67	1318	/**
n0tform3	8:1c6281289d67	1319	* @brief Forces or releases AHB3 peripheral reset.
n0tform3	8:1c6281289d67	1320	* @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
n0tform3	8:1c6281289d67	1321	* This parameter must be: RCC_AHB3Periph_FSMC
n0tform3	8:1c6281289d67	1322	* @param NewState: new state of the specified peripheral reset.
n0tform3	8:1c6281289d67	1323	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1324	* @retval None
n0tform3	8:1c6281289d67	1325	*/
n0tform3	8:1c6281289d67	1326	void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1327	{
n0tform3	8:1c6281289d67	1328	/* Check the parameters */
n0tform3	8:1c6281289d67	1329	assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
n0tform3	8:1c6281289d67	1330	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1331
n0tform3	8:1c6281289d67	1332	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1333	{
n0tform3	8:1c6281289d67	1334	RCC->AHB3RSTR \|= RCC_AHB3Periph;
n0tform3	8:1c6281289d67	1335	}
n0tform3	8:1c6281289d67	1336	else
n0tform3	8:1c6281289d67	1337	{
n0tform3	8:1c6281289d67	1338	RCC->AHB3RSTR &= ~RCC_AHB3Periph;
n0tform3	8:1c6281289d67	1339	}
n0tform3	8:1c6281289d67	1340	}
n0tform3	8:1c6281289d67	1341
n0tform3	8:1c6281289d67	1342	/**
n0tform3	8:1c6281289d67	1343	* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
n0tform3	8:1c6281289d67	1344	* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
n0tform3	8:1c6281289d67	1345	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1346	* @arg RCC_APB1Periph_TIM2: TIM2 clock
n0tform3	8:1c6281289d67	1347	* @arg RCC_APB1Periph_TIM3: TIM3 clock
n0tform3	8:1c6281289d67	1348	* @arg RCC_APB1Periph_TIM4: TIM4 clock
n0tform3	8:1c6281289d67	1349	* @arg RCC_APB1Periph_TIM5: TIM5 clock
n0tform3	8:1c6281289d67	1350	* @arg RCC_APB1Periph_TIM6: TIM6 clock
n0tform3	8:1c6281289d67	1351	* @arg RCC_APB1Periph_TIM7: TIM7 clock
n0tform3	8:1c6281289d67	1352	* @arg RCC_APB1Periph_TIM12: TIM12 clock
n0tform3	8:1c6281289d67	1353	* @arg RCC_APB1Periph_TIM13: TIM13 clock
n0tform3	8:1c6281289d67	1354	* @arg RCC_APB1Periph_TIM14: TIM14 clock
n0tform3	8:1c6281289d67	1355	* @arg RCC_APB1Periph_WWDG: WWDG clock
n0tform3	8:1c6281289d67	1356	* @arg RCC_APB1Periph_SPI2: SPI2 clock
n0tform3	8:1c6281289d67	1357	* @arg RCC_APB1Periph_SPI3: SPI3 clock
n0tform3	8:1c6281289d67	1358	* @arg RCC_APB1Periph_USART2: USART2 clock
n0tform3	8:1c6281289d67	1359	* @arg RCC_APB1Periph_USART3: USART3 clock
n0tform3	8:1c6281289d67	1360	* @arg RCC_APB1Periph_UART4: UART4 clock
n0tform3	8:1c6281289d67	1361	* @arg RCC_APB1Periph_UART5: UART5 clock
n0tform3	8:1c6281289d67	1362	* @arg RCC_APB1Periph_I2C1: I2C1 clock
n0tform3	8:1c6281289d67	1363	* @arg RCC_APB1Periph_I2C2: I2C2 clock
n0tform3	8:1c6281289d67	1364	* @arg RCC_APB1Periph_I2C3: I2C3 clock
n0tform3	8:1c6281289d67	1365	* @arg RCC_APB1Periph_CAN1: CAN1 clock
n0tform3	8:1c6281289d67	1366	* @arg RCC_APB1Periph_CAN2: CAN2 clock
n0tform3	8:1c6281289d67	1367	* @arg RCC_APB1Periph_PWR: PWR clock
n0tform3	8:1c6281289d67	1368	* @arg RCC_APB1Periph_DAC: DAC clock
n0tform3	8:1c6281289d67	1369	* @param NewState: new state of the specified peripheral reset.
n0tform3	8:1c6281289d67	1370	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1371	* @retval None
n0tform3	8:1c6281289d67	1372	*/
n0tform3	8:1c6281289d67	1373	void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1374	{
n0tform3	8:1c6281289d67	1375	/* Check the parameters */
n0tform3	8:1c6281289d67	1376	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
n0tform3	8:1c6281289d67	1377	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1378	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1379	{
n0tform3	8:1c6281289d67	1380	RCC->APB1RSTR \|= RCC_APB1Periph;
n0tform3	8:1c6281289d67	1381	}
n0tform3	8:1c6281289d67	1382	else
n0tform3	8:1c6281289d67	1383	{
n0tform3	8:1c6281289d67	1384	RCC->APB1RSTR &= ~RCC_APB1Periph;
n0tform3	8:1c6281289d67	1385	}
n0tform3	8:1c6281289d67	1386	}
n0tform3	8:1c6281289d67	1387
n0tform3	8:1c6281289d67	1388	/**
n0tform3	8:1c6281289d67	1389	* @brief Forces or releases High Speed APB (APB2) peripheral reset.
n0tform3	8:1c6281289d67	1390	* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
n0tform3	8:1c6281289d67	1391	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1392	* @arg RCC_APB2Periph_TIM1: TIM1 clock
n0tform3	8:1c6281289d67	1393	* @arg RCC_APB2Periph_TIM8: TIM8 clock
n0tform3	8:1c6281289d67	1394	* @arg RCC_APB2Periph_USART1: USART1 clock
n0tform3	8:1c6281289d67	1395	* @arg RCC_APB2Periph_USART6: USART6 clock
n0tform3	8:1c6281289d67	1396	* @arg RCC_APB2Periph_ADC1: ADC1 clock
n0tform3	8:1c6281289d67	1397	* @arg RCC_APB2Periph_ADC2: ADC2 clock
n0tform3	8:1c6281289d67	1398	* @arg RCC_APB2Periph_ADC3: ADC3 clock
n0tform3	8:1c6281289d67	1399	* @arg RCC_APB2Periph_SDIO: SDIO clock
n0tform3	8:1c6281289d67	1400	* @arg RCC_APB2Periph_SPI1: SPI1 clock
n0tform3	8:1c6281289d67	1401	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
n0tform3	8:1c6281289d67	1402	* @arg RCC_APB2Periph_TIM9: TIM9 clock
n0tform3	8:1c6281289d67	1403	* @arg RCC_APB2Periph_TIM10: TIM10 clock
n0tform3	8:1c6281289d67	1404	* @arg RCC_APB2Periph_TIM11: TIM11 clock
n0tform3	8:1c6281289d67	1405	* @param NewState: new state of the specified peripheral reset.
n0tform3	8:1c6281289d67	1406	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1407	* @retval None
n0tform3	8:1c6281289d67	1408	*/
n0tform3	8:1c6281289d67	1409	void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1410	{
n0tform3	8:1c6281289d67	1411	/* Check the parameters */
n0tform3	8:1c6281289d67	1412	assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
n0tform3	8:1c6281289d67	1413	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1414	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1415	{
n0tform3	8:1c6281289d67	1416	RCC->APB2RSTR \|= RCC_APB2Periph;
n0tform3	8:1c6281289d67	1417	}
n0tform3	8:1c6281289d67	1418	else
n0tform3	8:1c6281289d67	1419	{
n0tform3	8:1c6281289d67	1420	RCC->APB2RSTR &= ~RCC_APB2Periph;
n0tform3	8:1c6281289d67	1421	}
n0tform3	8:1c6281289d67	1422	}
n0tform3	8:1c6281289d67	1423
n0tform3	8:1c6281289d67	1424	/**
n0tform3	8:1c6281289d67	1425	* @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
n0tform3	8:1c6281289d67	1426	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
n0tform3	8:1c6281289d67	1427	* power consumption.
n0tform3	8:1c6281289d67	1428	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
n0tform3	8:1c6281289d67	1429	* @note By default, all peripheral clocks are enabled during SLEEP mode.
n0tform3	8:1c6281289d67	1430	* @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1431	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1432	* @arg RCC_AHB1Periph_GPIOA: GPIOA clock
n0tform3	8:1c6281289d67	1433	* @arg RCC_AHB1Periph_GPIOB: GPIOB clock
n0tform3	8:1c6281289d67	1434	* @arg RCC_AHB1Periph_GPIOC: GPIOC clock
n0tform3	8:1c6281289d67	1435	* @arg RCC_AHB1Periph_GPIOD: GPIOD clock
n0tform3	8:1c6281289d67	1436	* @arg RCC_AHB1Periph_GPIOE: GPIOE clock
n0tform3	8:1c6281289d67	1437	* @arg RCC_AHB1Periph_GPIOF: GPIOF clock
n0tform3	8:1c6281289d67	1438	* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
n0tform3	8:1c6281289d67	1439	* @arg RCC_AHB1Periph_GPIOG: GPIOG clock
n0tform3	8:1c6281289d67	1440	* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
n0tform3	8:1c6281289d67	1441	* @arg RCC_AHB1Periph_CRC: CRC clock
n0tform3	8:1c6281289d67	1442	* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
n0tform3	8:1c6281289d67	1443	* @arg RCC_AHB1Periph_DMA1: DMA1 clock
n0tform3	8:1c6281289d67	1444	* @arg RCC_AHB1Periph_DMA2: DMA2 clock
n0tform3	8:1c6281289d67	1445	* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
n0tform3	8:1c6281289d67	1446	* @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
n0tform3	8:1c6281289d67	1447	* @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
n0tform3	8:1c6281289d67	1448	* @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
n0tform3	8:1c6281289d67	1449	* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
n0tform3	8:1c6281289d67	1450	* @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
n0tform3	8:1c6281289d67	1451	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1452	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1453	* @retval None
n0tform3	8:1c6281289d67	1454	*/
n0tform3	8:1c6281289d67	1455	void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1456	{
n0tform3	8:1c6281289d67	1457	/* Check the parameters */
n0tform3	8:1c6281289d67	1458	assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
n0tform3	8:1c6281289d67	1459	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1460	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1461	{
n0tform3	8:1c6281289d67	1462	RCC->AHB1LPENR \|= RCC_AHB1Periph;
n0tform3	8:1c6281289d67	1463	}
n0tform3	8:1c6281289d67	1464	else
n0tform3	8:1c6281289d67	1465	{
n0tform3	8:1c6281289d67	1466	RCC->AHB1LPENR &= ~RCC_AHB1Periph;
n0tform3	8:1c6281289d67	1467	}
n0tform3	8:1c6281289d67	1468	}
n0tform3	8:1c6281289d67	1469
n0tform3	8:1c6281289d67	1470	/**
n0tform3	8:1c6281289d67	1471	* @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
n0tform3	8:1c6281289d67	1472	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
n0tform3	8:1c6281289d67	1473	* power consumption.
n0tform3	8:1c6281289d67	1474	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
n0tform3	8:1c6281289d67	1475	* @note By default, all peripheral clocks are enabled during SLEEP mode.
n0tform3	8:1c6281289d67	1476	* @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1477	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1478	* @arg RCC_AHB2Periph_DCMI: DCMI clock
n0tform3	8:1c6281289d67	1479	* @arg RCC_AHB2Periph_CRYP: CRYP clock
n0tform3	8:1c6281289d67	1480	* @arg RCC_AHB2Periph_HASH: HASH clock
n0tform3	8:1c6281289d67	1481	* @arg RCC_AHB2Periph_RNG: RNG clock
n0tform3	8:1c6281289d67	1482	* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
n0tform3	8:1c6281289d67	1483	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1484	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1485	* @retval None
n0tform3	8:1c6281289d67	1486	*/
n0tform3	8:1c6281289d67	1487	void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1488	{
n0tform3	8:1c6281289d67	1489	/* Check the parameters */
n0tform3	8:1c6281289d67	1490	assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
n0tform3	8:1c6281289d67	1491	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1492	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1493	{
n0tform3	8:1c6281289d67	1494	RCC->AHB2LPENR \|= RCC_AHB2Periph;
n0tform3	8:1c6281289d67	1495	}
n0tform3	8:1c6281289d67	1496	else
n0tform3	8:1c6281289d67	1497	{
n0tform3	8:1c6281289d67	1498	RCC->AHB2LPENR &= ~RCC_AHB2Periph;
n0tform3	8:1c6281289d67	1499	}
n0tform3	8:1c6281289d67	1500	}
n0tform3	8:1c6281289d67	1501
n0tform3	8:1c6281289d67	1502	/**
n0tform3	8:1c6281289d67	1503	* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
n0tform3	8:1c6281289d67	1504	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
n0tform3	8:1c6281289d67	1505	* power consumption.
n0tform3	8:1c6281289d67	1506	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
n0tform3	8:1c6281289d67	1507	* @note By default, all peripheral clocks are enabled during SLEEP mode.
n0tform3	8:1c6281289d67	1508	* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1509	* This parameter must be: RCC_AHB3Periph_FSMC
n0tform3	8:1c6281289d67	1510	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1511	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1512	* @retval None
n0tform3	8:1c6281289d67	1513	*/
n0tform3	8:1c6281289d67	1514	void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1515	{
n0tform3	8:1c6281289d67	1516	/* Check the parameters */
n0tform3	8:1c6281289d67	1517	assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
n0tform3	8:1c6281289d67	1518	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1519	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1520	{
n0tform3	8:1c6281289d67	1521	RCC->AHB3LPENR \|= RCC_AHB3Periph;
n0tform3	8:1c6281289d67	1522	}
n0tform3	8:1c6281289d67	1523	else
n0tform3	8:1c6281289d67	1524	{
n0tform3	8:1c6281289d67	1525	RCC->AHB3LPENR &= ~RCC_AHB3Periph;
n0tform3	8:1c6281289d67	1526	}
n0tform3	8:1c6281289d67	1527	}
n0tform3	8:1c6281289d67	1528
n0tform3	8:1c6281289d67	1529	/**
n0tform3	8:1c6281289d67	1530	* @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
n0tform3	8:1c6281289d67	1531	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
n0tform3	8:1c6281289d67	1532	* power consumption.
n0tform3	8:1c6281289d67	1533	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
n0tform3	8:1c6281289d67	1534	* @note By default, all peripheral clocks are enabled during SLEEP mode.
n0tform3	8:1c6281289d67	1535	* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1536	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1537	* @arg RCC_APB1Periph_TIM2: TIM2 clock
n0tform3	8:1c6281289d67	1538	* @arg RCC_APB1Periph_TIM3: TIM3 clock
n0tform3	8:1c6281289d67	1539	* @arg RCC_APB1Periph_TIM4: TIM4 clock
n0tform3	8:1c6281289d67	1540	* @arg RCC_APB1Periph_TIM5: TIM5 clock
n0tform3	8:1c6281289d67	1541	* @arg RCC_APB1Periph_TIM6: TIM6 clock
n0tform3	8:1c6281289d67	1542	* @arg RCC_APB1Periph_TIM7: TIM7 clock
n0tform3	8:1c6281289d67	1543	* @arg RCC_APB1Periph_TIM12: TIM12 clock
n0tform3	8:1c6281289d67	1544	* @arg RCC_APB1Periph_TIM13: TIM13 clock
n0tform3	8:1c6281289d67	1545	* @arg RCC_APB1Periph_TIM14: TIM14 clock
n0tform3	8:1c6281289d67	1546	* @arg RCC_APB1Periph_WWDG: WWDG clock
n0tform3	8:1c6281289d67	1547	* @arg RCC_APB1Periph_SPI2: SPI2 clock
n0tform3	8:1c6281289d67	1548	* @arg RCC_APB1Periph_SPI3: SPI3 clock
n0tform3	8:1c6281289d67	1549	* @arg RCC_APB1Periph_USART2: USART2 clock
n0tform3	8:1c6281289d67	1550	* @arg RCC_APB1Periph_USART3: USART3 clock
n0tform3	8:1c6281289d67	1551	* @arg RCC_APB1Periph_UART4: UART4 clock
n0tform3	8:1c6281289d67	1552	* @arg RCC_APB1Periph_UART5: UART5 clock
n0tform3	8:1c6281289d67	1553	* @arg RCC_APB1Periph_I2C1: I2C1 clock
n0tform3	8:1c6281289d67	1554	* @arg RCC_APB1Periph_I2C2: I2C2 clock
n0tform3	8:1c6281289d67	1555	* @arg RCC_APB1Periph_I2C3: I2C3 clock
n0tform3	8:1c6281289d67	1556	* @arg RCC_APB1Periph_CAN1: CAN1 clock
n0tform3	8:1c6281289d67	1557	* @arg RCC_APB1Periph_CAN2: CAN2 clock
n0tform3	8:1c6281289d67	1558	* @arg RCC_APB1Periph_PWR: PWR clock
n0tform3	8:1c6281289d67	1559	* @arg RCC_APB1Periph_DAC: DAC clock
n0tform3	8:1c6281289d67	1560	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1561	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1562	* @retval None
n0tform3	8:1c6281289d67	1563	*/
n0tform3	8:1c6281289d67	1564	void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1565	{
n0tform3	8:1c6281289d67	1566	/* Check the parameters */
n0tform3	8:1c6281289d67	1567	assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
n0tform3	8:1c6281289d67	1568	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1569	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1570	{
n0tform3	8:1c6281289d67	1571	RCC->APB1LPENR \|= RCC_APB1Periph;
n0tform3	8:1c6281289d67	1572	}
n0tform3	8:1c6281289d67	1573	else
n0tform3	8:1c6281289d67	1574	{
n0tform3	8:1c6281289d67	1575	RCC->APB1LPENR &= ~RCC_APB1Periph;
n0tform3	8:1c6281289d67	1576	}
n0tform3	8:1c6281289d67	1577	}
n0tform3	8:1c6281289d67	1578
n0tform3	8:1c6281289d67	1579	/**
n0tform3	8:1c6281289d67	1580	* @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
n0tform3	8:1c6281289d67	1581	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
n0tform3	8:1c6281289d67	1582	* power consumption.
n0tform3	8:1c6281289d67	1583	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
n0tform3	8:1c6281289d67	1584	* @note By default, all peripheral clocks are enabled during SLEEP mode.
n0tform3	8:1c6281289d67	1585	* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
n0tform3	8:1c6281289d67	1586	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1587	* @arg RCC_APB2Periph_TIM1: TIM1 clock
n0tform3	8:1c6281289d67	1588	* @arg RCC_APB2Periph_TIM8: TIM8 clock
n0tform3	8:1c6281289d67	1589	* @arg RCC_APB2Periph_USART1: USART1 clock
n0tform3	8:1c6281289d67	1590	* @arg RCC_APB2Periph_USART6: USART6 clock
n0tform3	8:1c6281289d67	1591	* @arg RCC_APB2Periph_ADC1: ADC1 clock
n0tform3	8:1c6281289d67	1592	* @arg RCC_APB2Periph_ADC2: ADC2 clock
n0tform3	8:1c6281289d67	1593	* @arg RCC_APB2Periph_ADC3: ADC3 clock
n0tform3	8:1c6281289d67	1594	* @arg RCC_APB2Periph_SDIO: SDIO clock
n0tform3	8:1c6281289d67	1595	* @arg RCC_APB2Periph_SPI1: SPI1 clock
n0tform3	8:1c6281289d67	1596	* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
n0tform3	8:1c6281289d67	1597	* @arg RCC_APB2Periph_TIM9: TIM9 clock
n0tform3	8:1c6281289d67	1598	* @arg RCC_APB2Periph_TIM10: TIM10 clock
n0tform3	8:1c6281289d67	1599	* @arg RCC_APB2Periph_TIM11: TIM11 clock
n0tform3	8:1c6281289d67	1600	* @param NewState: new state of the specified peripheral clock.
n0tform3	8:1c6281289d67	1601	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1602	* @retval None
n0tform3	8:1c6281289d67	1603	*/
n0tform3	8:1c6281289d67	1604	void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
n0tform3	8:1c6281289d67	1605	{
n0tform3	8:1c6281289d67	1606	/* Check the parameters */
n0tform3	8:1c6281289d67	1607	assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
n0tform3	8:1c6281289d67	1608	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1609	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1610	{
n0tform3	8:1c6281289d67	1611	RCC->APB2LPENR \|= RCC_APB2Periph;
n0tform3	8:1c6281289d67	1612	}
n0tform3	8:1c6281289d67	1613	else
n0tform3	8:1c6281289d67	1614	{
n0tform3	8:1c6281289d67	1615	RCC->APB2LPENR &= ~RCC_APB2Periph;
n0tform3	8:1c6281289d67	1616	}
n0tform3	8:1c6281289d67	1617	}
n0tform3	8:1c6281289d67	1618
n0tform3	8:1c6281289d67	1619	/**
n0tform3	8:1c6281289d67	1620	* @}
n0tform3	8:1c6281289d67	1621	*/
n0tform3	8:1c6281289d67	1622
n0tform3	8:1c6281289d67	1623	/** @defgroup RCC_Group4 Interrupts and flags management functions
n0tform3	8:1c6281289d67	1624	* @brief Interrupts and flags management functions
n0tform3	8:1c6281289d67	1625	*
n0tform3	8:1c6281289d67	1626	@verbatim
n0tform3	8:1c6281289d67	1627	===============================================================================
n0tform3	8:1c6281289d67	1628	Interrupts and flags management functions
n0tform3	8:1c6281289d67	1629	===============================================================================
n0tform3	8:1c6281289d67	1630
n0tform3	8:1c6281289d67	1631	@endverbatim
n0tform3	8:1c6281289d67	1632	* @{
n0tform3	8:1c6281289d67	1633	*/
n0tform3	8:1c6281289d67	1634
n0tform3	8:1c6281289d67	1635	/**
n0tform3	8:1c6281289d67	1636	* @brief Enables or disables the specified RCC interrupts.
n0tform3	8:1c6281289d67	1637	* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
n0tform3	8:1c6281289d67	1638	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1639	* @arg RCC_IT_LSIRDY: LSI ready interrupt
n0tform3	8:1c6281289d67	1640	* @arg RCC_IT_LSERDY: LSE ready interrupt
n0tform3	8:1c6281289d67	1641	* @arg RCC_IT_HSIRDY: HSI ready interrupt
n0tform3	8:1c6281289d67	1642	* @arg RCC_IT_HSERDY: HSE ready interrupt
n0tform3	8:1c6281289d67	1643	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
n0tform3	8:1c6281289d67	1644	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
n0tform3	8:1c6281289d67	1645	* @param NewState: new state of the specified RCC interrupts.
n0tform3	8:1c6281289d67	1646	* This parameter can be: ENABLE or DISABLE.
n0tform3	8:1c6281289d67	1647	* @retval None
n0tform3	8:1c6281289d67	1648	*/
n0tform3	8:1c6281289d67	1649	void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
n0tform3	8:1c6281289d67	1650	{
n0tform3	8:1c6281289d67	1651	/* Check the parameters */
n0tform3	8:1c6281289d67	1652	assert_param(IS_RCC_IT(RCC_IT));
n0tform3	8:1c6281289d67	1653	assert_param(IS_FUNCTIONAL_STATE(NewState));
n0tform3	8:1c6281289d67	1654	if (NewState != DISABLE)
n0tform3	8:1c6281289d67	1655	{
n0tform3	8:1c6281289d67	1656	/* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
n0tform3	8:1c6281289d67	1657	(__IO uint8_t ) CIR_BYTE2_ADDRESS \|= RCC_IT;
n0tform3	8:1c6281289d67	1658	}
n0tform3	8:1c6281289d67	1659	else
n0tform3	8:1c6281289d67	1660	{
n0tform3	8:1c6281289d67	1661	/* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
n0tform3	8:1c6281289d67	1662	(__IO uint8_t ) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
n0tform3	8:1c6281289d67	1663	}
n0tform3	8:1c6281289d67	1664	}
n0tform3	8:1c6281289d67	1665
n0tform3	8:1c6281289d67	1666	/**
n0tform3	8:1c6281289d67	1667	* @brief Checks whether the specified RCC flag is set or not.
n0tform3	8:1c6281289d67	1668	* @param RCC_FLAG: specifies the flag to check.
n0tform3	8:1c6281289d67	1669	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1670	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
n0tform3	8:1c6281289d67	1671	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
n0tform3	8:1c6281289d67	1672	* @arg RCC_FLAG_PLLRDY: main PLL clock ready
n0tform3	8:1c6281289d67	1673	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
n0tform3	8:1c6281289d67	1674	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
n0tform3	8:1c6281289d67	1675	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
n0tform3	8:1c6281289d67	1676	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
n0tform3	8:1c6281289d67	1677	* @arg RCC_FLAG_PINRST: Pin reset
n0tform3	8:1c6281289d67	1678	* @arg RCC_FLAG_PORRST: POR/PDR reset
n0tform3	8:1c6281289d67	1679	* @arg RCC_FLAG_SFTRST: Software reset
n0tform3	8:1c6281289d67	1680	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
n0tform3	8:1c6281289d67	1681	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
n0tform3	8:1c6281289d67	1682	* @arg RCC_FLAG_LPWRRST: Low Power reset
n0tform3	8:1c6281289d67	1683	* @retval The new state of RCC_FLAG (SET or RESET).
n0tform3	8:1c6281289d67	1684	*/
n0tform3	8:1c6281289d67	1685	FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
n0tform3	8:1c6281289d67	1686	{
n0tform3	8:1c6281289d67	1687	uint32_t tmp = 0;
n0tform3	8:1c6281289d67	1688	uint32_t statusreg = 0;
n0tform3	8:1c6281289d67	1689	FlagStatus bitstatus = RESET;
n0tform3	8:1c6281289d67	1690
n0tform3	8:1c6281289d67	1691	/* Check the parameters */
n0tform3	8:1c6281289d67	1692	assert_param(IS_RCC_FLAG(RCC_FLAG));
n0tform3	8:1c6281289d67	1693
n0tform3	8:1c6281289d67	1694	/* Get the RCC register index */
n0tform3	8:1c6281289d67	1695	tmp = RCC_FLAG >> 5;
n0tform3	8:1c6281289d67	1696	if (tmp == 1) /* The flag to check is in CR register */
n0tform3	8:1c6281289d67	1697	{
n0tform3	8:1c6281289d67	1698	statusreg = RCC->CR;
n0tform3	8:1c6281289d67	1699	}
n0tform3	8:1c6281289d67	1700	else if (tmp == 2) /* The flag to check is in BDCR register */
n0tform3	8:1c6281289d67	1701	{
n0tform3	8:1c6281289d67	1702	statusreg = RCC->BDCR;
n0tform3	8:1c6281289d67	1703	}
n0tform3	8:1c6281289d67	1704	else /* The flag to check is in CSR register */
n0tform3	8:1c6281289d67	1705	{
n0tform3	8:1c6281289d67	1706	statusreg = RCC->CSR;
n0tform3	8:1c6281289d67	1707	}
n0tform3	8:1c6281289d67	1708
n0tform3	8:1c6281289d67	1709	/* Get the flag position */
n0tform3	8:1c6281289d67	1710	tmp = RCC_FLAG & FLAG_MASK;
n0tform3	8:1c6281289d67	1711	if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
n0tform3	8:1c6281289d67	1712	{
n0tform3	8:1c6281289d67	1713	bitstatus = SET;
n0tform3	8:1c6281289d67	1714	}
n0tform3	8:1c6281289d67	1715	else
n0tform3	8:1c6281289d67	1716	{
n0tform3	8:1c6281289d67	1717	bitstatus = RESET;
n0tform3	8:1c6281289d67	1718	}
n0tform3	8:1c6281289d67	1719	/* Return the flag status */
n0tform3	8:1c6281289d67	1720	return bitstatus;
n0tform3	8:1c6281289d67	1721	}
n0tform3	8:1c6281289d67	1722
n0tform3	8:1c6281289d67	1723	/**
n0tform3	8:1c6281289d67	1724	* @brief Clears the RCC reset flags.
n0tform3	8:1c6281289d67	1725	* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
n0tform3	8:1c6281289d67	1726	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
n0tform3	8:1c6281289d67	1727	* @param None
n0tform3	8:1c6281289d67	1728	* @retval None
n0tform3	8:1c6281289d67	1729	*/
n0tform3	8:1c6281289d67	1730	void RCC_ClearFlag(void)
n0tform3	8:1c6281289d67	1731	{
n0tform3	8:1c6281289d67	1732	/* Set RMVF bit to clear the reset flags */
n0tform3	8:1c6281289d67	1733	RCC->CSR \|= RCC_CSR_RMVF;
n0tform3	8:1c6281289d67	1734	}
n0tform3	8:1c6281289d67	1735
n0tform3	8:1c6281289d67	1736	/**
n0tform3	8:1c6281289d67	1737	* @brief Checks whether the specified RCC interrupt has occurred or not.
n0tform3	8:1c6281289d67	1738	* @param RCC_IT: specifies the RCC interrupt source to check.
n0tform3	8:1c6281289d67	1739	* This parameter can be one of the following values:
n0tform3	8:1c6281289d67	1740	* @arg RCC_IT_LSIRDY: LSI ready interrupt
n0tform3	8:1c6281289d67	1741	* @arg RCC_IT_LSERDY: LSE ready interrupt
n0tform3	8:1c6281289d67	1742	* @arg RCC_IT_HSIRDY: HSI ready interrupt
n0tform3	8:1c6281289d67	1743	* @arg RCC_IT_HSERDY: HSE ready interrupt
n0tform3	8:1c6281289d67	1744	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
n0tform3	8:1c6281289d67	1745	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
n0tform3	8:1c6281289d67	1746	* @arg RCC_IT_CSS: Clock Security System interrupt
n0tform3	8:1c6281289d67	1747	* @retval The new state of RCC_IT (SET or RESET).
n0tform3	8:1c6281289d67	1748	*/
n0tform3	8:1c6281289d67	1749	ITStatus RCC_GetITStatus(uint8_t RCC_IT)
n0tform3	8:1c6281289d67	1750	{
n0tform3	8:1c6281289d67	1751	ITStatus bitstatus = RESET;
n0tform3	8:1c6281289d67	1752
n0tform3	8:1c6281289d67	1753	/* Check the parameters */
n0tform3	8:1c6281289d67	1754	assert_param(IS_RCC_GET_IT(RCC_IT));
n0tform3	8:1c6281289d67	1755
n0tform3	8:1c6281289d67	1756	/* Check the status of the specified RCC interrupt */
n0tform3	8:1c6281289d67	1757	if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
n0tform3	8:1c6281289d67	1758	{
n0tform3	8:1c6281289d67	1759	bitstatus = SET;
n0tform3	8:1c6281289d67	1760	}
n0tform3	8:1c6281289d67	1761	else
n0tform3	8:1c6281289d67	1762	{
n0tform3	8:1c6281289d67	1763	bitstatus = RESET;
n0tform3	8:1c6281289d67	1764	}
n0tform3	8:1c6281289d67	1765	/* Return the RCC_IT status */
n0tform3	8:1c6281289d67	1766	return bitstatus;
n0tform3	8:1c6281289d67	1767	}
n0tform3	8:1c6281289d67	1768
n0tform3	8:1c6281289d67	1769	/**
n0tform3	8:1c6281289d67	1770	* @brief Clears the RCC's interrupt pending bits.
n0tform3	8:1c6281289d67	1771	* @param RCC_IT: specifies the interrupt pending bit to clear.
n0tform3	8:1c6281289d67	1772	* This parameter can be any combination of the following values:
n0tform3	8:1c6281289d67	1773	* @arg RCC_IT_LSIRDY: LSI ready interrupt
n0tform3	8:1c6281289d67	1774	* @arg RCC_IT_LSERDY: LSE ready interrupt
n0tform3	8:1c6281289d67	1775	* @arg RCC_IT_HSIRDY: HSI ready interrupt
n0tform3	8:1c6281289d67	1776	* @arg RCC_IT_HSERDY: HSE ready interrupt
n0tform3	8:1c6281289d67	1777	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
n0tform3	8:1c6281289d67	1778	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
n0tform3	8:1c6281289d67	1779	* @arg RCC_IT_CSS: Clock Security System interrupt
n0tform3	8:1c6281289d67	1780	* @retval None
n0tform3	8:1c6281289d67	1781	*/
n0tform3	8:1c6281289d67	1782	void RCC_ClearITPendingBit(uint8_t RCC_IT)
n0tform3	8:1c6281289d67	1783	{
n0tform3	8:1c6281289d67	1784	/* Check the parameters */
n0tform3	8:1c6281289d67	1785	assert_param(IS_RCC_CLEAR_IT(RCC_IT));
n0tform3	8:1c6281289d67	1786
n0tform3	8:1c6281289d67	1787	/* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
n0tform3	8:1c6281289d67	1788	pending bits */
n0tform3	8:1c6281289d67	1789	(__IO uint8_t ) CIR_BYTE3_ADDRESS = RCC_IT;
n0tform3	8:1c6281289d67	1790	}
n0tform3	8:1c6281289d67	1791
n0tform3	8:1c6281289d67	1792	/**
n0tform3	8:1c6281289d67	1793	* @}
n0tform3	8:1c6281289d67	1794	*/
n0tform3	8:1c6281289d67	1795
n0tform3	8:1c6281289d67	1796	/**
n0tform3	8:1c6281289d67	1797	* @}
n0tform3	8:1c6281289d67	1798	*/
n0tform3	8:1c6281289d67	1799
n0tform3	8:1c6281289d67	1800	/**
n0tform3	8:1c6281289d67	1801	* @}
n0tform3	8:1c6281289d67	1802	*/
n0tform3	8:1c6281289d67	1803
n0tform3	8:1c6281289d67	1804	/**
n0tform3	8:1c6281289d67	1805	* @}
n0tform3	8:1c6281289d67	1806	*/
n0tform3	8:1c6281289d67	1807
n0tform3	8:1c6281289d67	1808	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/
n0tform3	8:1c6281289d67	1809

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	15 Nov 2015
Imports:	67
Forks:	0
Commits:	9
Dependents:	0
Dependencies:	4
Followers:	1

stm32f4xx_rcc.c@8:1c6281289d67, 2015-11-15 (annotated)

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