AirioBase + 2 chip PicoSSD board.
Dependencies: mbed EEPROM USBDevice
RawNAND.h@4:2e8b78a74493, 2021-09-15 (annotated)
- Committer:
- muraguchi
- Date:
- Wed Sep 15 16:32:12 2021 +0000
- Revision:
- 4:2e8b78a74493
- Parent:
- 0:1472308ded03
AirioBase + 2 chip PicoSSD board.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
muraguchi | 0:1472308ded03 | 1 | #ifndef RAWNAND_H |
muraguchi | 0:1472308ded03 | 2 | #define RAWNAND_H |
muraguchi | 0:1472308ded03 | 3 | |
muraguchi | 0:1472308ded03 | 4 | #include "mbed.h" |
muraguchi | 0:1472308ded03 | 5 | |
muraguchi | 0:1472308ded03 | 6 | // KIOXIA 1Gbit SLC NAND, 3.3V, x8, 24nm, TSOP |
muraguchi | 0:1472308ded03 | 7 | // TC58NVG0S3HTA00 datasheet 2019-10-01C |
muraguchi | 0:1472308ded03 | 8 | |
muraguchi | 0:1472308ded03 | 9 | // |
muraguchi | 0:1472308ded03 | 10 | // Timing parameter |
muraguchi | 0:1472308ded03 | 11 | // |
muraguchi | 0:1472308ded03 | 12 | // CLE Setup Time |
muraguchi | 0:1472308ded03 | 13 | #define tCLS_US 0.012 |
muraguchi | 0:1472308ded03 | 14 | |
muraguchi | 0:1472308ded03 | 15 | // CLE Hold Time |
muraguchi | 0:1472308ded03 | 16 | #define tCLH_US 0.005 |
muraguchi | 0:1472308ded03 | 17 | |
muraguchi | 0:1472308ded03 | 18 | // CEB Setup Time |
muraguchi | 0:1472308ded03 | 19 | #define tCS_US 0.020 |
muraguchi | 0:1472308ded03 | 20 | |
muraguchi | 0:1472308ded03 | 21 | // CEB Hold Time |
muraguchi | 0:1472308ded03 | 22 | #define tCH_US 0.005 |
muraguchi | 0:1472308ded03 | 23 | |
muraguchi | 0:1472308ded03 | 24 | // Write Pulse Width |
muraguchi | 0:1472308ded03 | 25 | #define tWP_US 0.012 |
muraguchi | 0:1472308ded03 | 26 | |
muraguchi | 0:1472308ded03 | 27 | // ALE Setup Time |
muraguchi | 0:1472308ded03 | 28 | #define tALS_US 0.012 |
muraguchi | 0:1472308ded03 | 29 | |
muraguchi | 0:1472308ded03 | 30 | // ALE Hold Time |
muraguchi | 0:1472308ded03 | 31 | #define tALH_US 0.005 |
muraguchi | 0:1472308ded03 | 32 | |
muraguchi | 0:1472308ded03 | 33 | // DATA Setup Time |
muraguchi | 0:1472308ded03 | 34 | #define tDS_US 0.012 |
muraguchi | 0:1472308ded03 | 35 | |
muraguchi | 0:1472308ded03 | 36 | // DATA Hold Time |
muraguchi | 0:1472308ded03 | 37 | #define tDH_US 0.005 |
muraguchi | 0:1472308ded03 | 38 | |
muraguchi | 0:1472308ded03 | 39 | // Write Cycle Time |
muraguchi | 0:1472308ded03 | 40 | #define tWC_US 0.025 |
muraguchi | 0:1472308ded03 | 41 | |
muraguchi | 0:1472308ded03 | 42 | // WEB High Hold Time |
muraguchi | 0:1472308ded03 | 43 | #define tWH_US 0.010 |
muraguchi | 0:1472308ded03 | 44 | |
muraguchi | 0:1472308ded03 | 45 | // WPB High to WEB Low |
muraguchi | 0:1472308ded03 | 46 | #define tWW_US 0.100 |
muraguchi | 0:1472308ded03 | 47 | |
muraguchi | 0:1472308ded03 | 48 | // Ready to REB Falling Edge |
muraguchi | 0:1472308ded03 | 49 | #define tRR_US 0.020 |
muraguchi | 0:1472308ded03 | 50 | |
muraguchi | 0:1472308ded03 | 51 | // Ready to WEB Falling Edge |
muraguchi | 0:1472308ded03 | 52 | #define tRW_US 0.020 |
muraguchi | 0:1472308ded03 | 53 | |
muraguchi | 0:1472308ded03 | 54 | // Read Pulse Width |
muraguchi | 0:1472308ded03 | 55 | #define tRP_US 0.012 |
muraguchi | 0:1472308ded03 | 56 | |
muraguchi | 0:1472308ded03 | 57 | // Read Cycle Time |
muraguchi | 0:1472308ded03 | 58 | #define tRC_US 0.025 |
muraguchi | 0:1472308ded03 | 59 | |
muraguchi | 0:1472308ded03 | 60 | // REB Access Time |
muraguchi | 0:1472308ded03 | 61 | #define tREA_US 0.020 |
muraguchi | 0:1472308ded03 | 62 | |
muraguchi | 0:1472308ded03 | 63 | // CEB Access Time |
muraguchi | 0:1472308ded03 | 64 | #define tCEA_US 0.025 |
muraguchi | 0:1472308ded03 | 65 | |
muraguchi | 0:1472308ded03 | 66 | // CLE Low to REB Low |
muraguchi | 0:1472308ded03 | 67 | #define tCLR_US 0.010 |
muraguchi | 0:1472308ded03 | 68 | |
muraguchi | 0:1472308ded03 | 69 | // ALE Low to REB Low |
muraguchi | 0:1472308ded03 | 70 | #define tAR_US 0.010 |
muraguchi | 0:1472308ded03 | 71 | |
muraguchi | 0:1472308ded03 | 72 | // REB High to Output Hold Time |
muraguchi | 0:1472308ded03 | 73 | #define tRHOH_US 0.025 |
muraguchi | 0:1472308ded03 | 74 | |
muraguchi | 0:1472308ded03 | 75 | // REB Low to Output Hold Time |
muraguchi | 0:1472308ded03 | 76 | #define tRLOH_US 0.005 |
muraguchi | 0:1472308ded03 | 77 | |
muraguchi | 0:1472308ded03 | 78 | // REB High to Output High Impedance |
muraguchi | 0:1472308ded03 | 79 | #define tRHZ_US 0.060 |
muraguchi | 0:1472308ded03 | 80 | |
muraguchi | 0:1472308ded03 | 81 | // CEB High to Output High Impedance |
muraguchi | 0:1472308ded03 | 82 | #define tCHZ_US 0.020 |
muraguchi | 0:1472308ded03 | 83 | |
muraguchi | 0:1472308ded03 | 84 | // CEB High to ALE or CLE Don't care |
muraguchi | 0:1472308ded03 | 85 | #define tCSD_US 0.000 |
muraguchi | 0:1472308ded03 | 86 | |
muraguchi | 0:1472308ded03 | 87 | // REB High Hold Time |
muraguchi | 0:1472308ded03 | 88 | #define tREH_US 0.010 |
muraguchi | 0:1472308ded03 | 89 | |
muraguchi | 0:1472308ded03 | 90 | // Output-High-Impedance-to-REB Falling Edge |
muraguchi | 0:1472308ded03 | 91 | #define tIR_US 0.000 |
muraguchi | 0:1472308ded03 | 92 | |
muraguchi | 0:1472308ded03 | 93 | // REB High to WEB Low |
muraguchi | 0:1472308ded03 | 94 | #define tRHW_US 0.030 |
muraguchi | 0:1472308ded03 | 95 | |
muraguchi | 0:1472308ded03 | 96 | // WEB High to CEB Low |
muraguchi | 0:1472308ded03 | 97 | #define tWHC_US 0.030 |
muraguchi | 0:1472308ded03 | 98 | |
muraguchi | 0:1472308ded03 | 99 | // WEB High to REB Low |
muraguchi | 0:1472308ded03 | 100 | #define tWHR_US 0.060 |
muraguchi | 0:1472308ded03 | 101 | |
muraguchi | 0:1472308ded03 | 102 | // WEB High to Busy |
muraguchi | 0:1472308ded03 | 103 | #define tWB_US 0.100 |
muraguchi | 0:1472308ded03 | 104 | |
muraguchi | 0:1472308ded03 | 105 | // Device Reset Time(Ready) |
muraguchi | 0:1472308ded03 | 106 | #define tRST_RDY_US 5.0 |
muraguchi | 0:1472308ded03 | 107 | |
muraguchi | 0:1472308ded03 | 108 | // Device Reset Time(Read) |
muraguchi | 0:1472308ded03 | 109 | #define tRST_READ_US 5.0 |
muraguchi | 0:1472308ded03 | 110 | |
muraguchi | 0:1472308ded03 | 111 | // Device Reset Time(Program) |
muraguchi | 0:1472308ded03 | 112 | #define tRST_PROGRAM_US 10.0 |
muraguchi | 0:1472308ded03 | 113 | |
muraguchi | 0:1472308ded03 | 114 | // Devise Reset Time(Erase) |
muraguchi | 0:1472308ded03 | 115 | #define tRST_ERASE_US 500.0 |
muraguchi | 0:1472308ded03 | 116 | |
muraguchi | 0:1472308ded03 | 117 | // Programming Time |
muraguchi | 0:1472308ded03 | 118 | #define tPROG_US 700.0 |
muraguchi | 0:1472308ded03 | 119 | |
muraguchi | 0:1472308ded03 | 120 | // Data Cache Busy Time in Write Cache( following 15h ) |
muraguchi | 0:1472308ded03 | 121 | #define tDCBAYW2_US 700.0 |
muraguchi | 0:1472308ded03 | 122 | |
muraguchi | 0:1472308ded03 | 123 | // Number of Partial Program Cycles in the same page |
muraguchi | 0:1472308ded03 | 124 | #define NCYCLES_SAME_PAGE 4 |
muraguchi | 0:1472308ded03 | 125 | |
muraguchi | 0:1472308ded03 | 126 | // Block Erasing Time |
muraguchi | 0:1472308ded03 | 127 | #define tBERASE_US 5000.0 |
muraguchi | 0:1472308ded03 | 128 | |
muraguchi | 0:1472308ded03 | 129 | // Memory Cell Array to Staring Address ( tR ) |
muraguchi | 0:1472308ded03 | 130 | #define MC2SA_US 25.0 |
muraguchi | 0:1472308ded03 | 131 | |
muraguchi | 0:1472308ded03 | 132 | // Data Cache Busy in Read Cache ( following 31h and 3Fh ) |
muraguchi | 0:1472308ded03 | 133 | #define tDCBSYR1_US 25.0 |
muraguchi | 0:1472308ded03 | 134 | |
muraguchi | 0:1472308ded03 | 135 | // Data Cache Busy in Page Copy ( following 3Ah ) |
muraguchi | 0:1472308ded03 | 136 | #define tDCBSYR2_US 30.0 |
muraguchi | 0:1472308ded03 | 137 | |
muraguchi | 0:1472308ded03 | 138 | |
muraguchi | 0:1472308ded03 | 139 | |
muraguchi | 0:1472308ded03 | 140 | class RawNAND |
muraguchi | 0:1472308ded03 | 141 | { |
muraguchi | 0:1472308ded03 | 142 | public: |
muraguchi | 4:2e8b78a74493 | 143 | RawNAND(PinName ceb0, PinName ceb1, |
muraguchi | 4:2e8b78a74493 | 144 | PinName cle , PinName ale , |
muraguchi | 4:2e8b78a74493 | 145 | PinName web , PinName reb , |
muraguchi | 4:2e8b78a74493 | 146 | PinName wpb , PinName rbb , |
muraguchi | 4:2e8b78a74493 | 147 | PinName io1 , PinName io2 , |
muraguchi | 4:2e8b78a74493 | 148 | PinName io3 , PinName io4 , |
muraguchi | 4:2e8b78a74493 | 149 | PinName io5 , PinName io6 , |
muraguchi | 4:2e8b78a74493 | 150 | PinName io7 , PinName io8 ); |
muraguchi | 4:2e8b78a74493 | 151 | void reset(uint8_t cs); |
muraguchi | 4:2e8b78a74493 | 152 | void idRead(uint8_t cs, uint8_t * readData); |
muraguchi | 4:2e8b78a74493 | 153 | uint8_t statusRead(uint8_t cs); |
muraguchi | 0:1472308ded03 | 154 | void setWriteProtect(uint8_t writeProtect); |
muraguchi | 4:2e8b78a74493 | 155 | void pageRead(uint8_t cs, uint8_t * readData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats); |
muraguchi | 0:1472308ded03 | 156 | // return status |
muraguchi | 4:2e8b78a74493 | 157 | uint8_t pageProgram(uint8_t cs, const uint8_t * writeData,uint16_t blockAddress,uint8_t pageAddress,uint16_t columnAddress,uint16_t beats); |
muraguchi | 0:1472308ded03 | 158 | // return status |
muraguchi | 4:2e8b78a74493 | 159 | uint8_t erase(uint8_t cs, uint16_t blockAddress); |
muraguchi | 0:1472308ded03 | 160 | |
muraguchi | 0:1472308ded03 | 161 | |
muraguchi | 0:1472308ded03 | 162 | private: |
muraguchi | 4:2e8b78a74493 | 163 | DigitalOut _ceb0; |
muraguchi | 4:2e8b78a74493 | 164 | DigitalOut _ceb1; |
muraguchi | 0:1472308ded03 | 165 | DigitalOut _cle; |
muraguchi | 0:1472308ded03 | 166 | DigitalOut _ale; |
muraguchi | 0:1472308ded03 | 167 | DigitalOut _web; |
muraguchi | 0:1472308ded03 | 168 | DigitalOut _reb; |
muraguchi | 0:1472308ded03 | 169 | DigitalOut _wpb; |
muraguchi | 0:1472308ded03 | 170 | DigitalIn _rbb; |
muraguchi | 0:1472308ded03 | 171 | BusInOut _io; |
muraguchi | 0:1472308ded03 | 172 | |
muraguchi | 0:1472308ded03 | 173 | }; |
muraguchi | 0:1472308ded03 | 174 | |
muraguchi | 0:1472308ded03 | 175 | #endif |