ST_L152_32MHZ.cpp

00001 /* mbed library for the ST NUCLEO board L152RE 
00002  * to change the CPU clock to 32 MHz
00003  * A pll clock of 96 MHz is used to enable USB  
00004  *
00005  * Copyright (c) 2014 Peter Drescher - DC2PD
00006  * Released under the MIT License: http://mbed.org/license/mit
00007  *
00008  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00009  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00010  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00011  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00012  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00013  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
00014  * THE SOFTWARE.
00015  */
00016  
00017 #include "stm32l1xx.h"
00018 #include "stm32l1xx_hal_rcc.h"
00019 #include "ST_L152_32MHZ.h"
00020 
00021 // only the constructor  
00022 L152_init32::L152_init32(unsigned int external){
00023     Status = setup_clock_32MHZ(external);
00024     }
00025 
00026 #define PLL_STARTUP_TIMEOUT 0x5000
00027 
00028 ClockStatus L152_init32::setup_clock_32MHZ(int external)
00029 {
00030    
00031    
00032    
00033    
00034    
00035    
00036     uint32_t PLLStartUpCounter = 0,PLLStatus = 0,error;
00037 
00038     HAL_RCC_DeInit();  // we have to reset the clock settings !
00039 /* Enable 64-bit access */
00040     FLASH->ACR |= FLASH_ACR_ACC64;
00041 
00042     /* Enable Prefetch Buffer */
00043     FLASH->ACR |= FLASH_ACR_PRFTEN;
00044 
00045     /* Flash 1 wait state */
00046     FLASH->ACR |= FLASH_ACR_LATENCY;
00047     
00048     /* Power enable */
00049     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
00050   
00051     /* Select the Voltage Range 1 (1.8 V) */
00052     PWR->CR = PWR_CR_VOS_0;
00053   
00054     /* Wait Until the Voltage Regulator is ready */
00055     while((PWR->CSR & PWR_CSR_VOSF) != RESET)
00056     {
00057     }
00058       
00059     /* HCLK = SYSCLK /1*/
00060     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00061     /* PCLK2 = HCLK /1*/
00062     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00063     
00064     /* PCLK1 = HCLK /1*/
00065     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
00066   
00067     /*  PLL configuration */
00068     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
00069                                         RCC_CFGR_PLLDIV));
00070                                         
00071     if(external == 0){                                                                        
00072         RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL6 | RCC_CFGR_PLLDIV3);
00073         }
00074     else{
00075        
00076        /** Need to be update with HAL_RCC_OscConfig
00077                                                          **/
00078        // __HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
00079         //error = RCC_WaitForHSEStartUp();
00080        // if(error == ERROR ) { // no external crystal
00081          //   return(EXT_ERR);
00082           //  }    
00083         //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);    
00084         }    
00085 
00086     /* Enable PLL */
00087     RCC->CR |= RCC_CR_PLLON;
00088 
00089     /* Wait till PLL is ready */
00090     do {
00091         PLLStatus = RCC->CR & RCC_CR_PLLRDY;
00092     } while((PLLStatus == 0) && (PLLStartUpCounter < PLL_STARTUP_TIMEOUT)); // wait for pll
00093     if(PLLStatus == 0) {
00094         return(PLL_ERR);
00095     }
00096 
00097     /* Select PLL as system clock source */
00098     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00099     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00100 
00101     /* Wait till PLL is used as system clock source */
00102     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
00103     {
00104     }
00105     SystemCoreClockUpdate();                    // update SystemCoreClock var
00106     return(OK);
00107 }
00108