Camille Muller / ST_L152_32MHZ

Fixed with HAL.

Fork of ST_L152_32MHZ by Peter Drescher

Not finish yet. External crystal doesn't work.

ST_L152_32MHZ.cpp@4:13f94218b838, 2015-04-21 (annotated)

Committer:
mullercamille
Date:
Tue Apr 21 20:55:37 2015 +0000
Revision:
4:13f94218b838
Parent:
3:1e82f1f333ad 
Add somes fix.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 1:bdeac50afe1a 1 /* mbed library for the ST NUCLEO board L152RE
dreschpe 1:bdeac50afe1a 2 * to change the CPU clock to 32 MHz
dreschpe 1:bdeac50afe1a 3 * A pll clock of 96 MHz is used to enable USB
dreschpe 1:bdeac50afe1a 4 *
dreschpe 1:bdeac50afe1a 5 * Copyright (c) 2014 Peter Drescher - DC2PD
dreschpe 1:bdeac50afe1a 6 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 1:bdeac50afe1a 7 *
dreschpe 1:bdeac50afe1a 8 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
dreschpe 1:bdeac50afe1a 9 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
dreschpe 1:bdeac50afe1a 10 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
dreschpe 1:bdeac50afe1a 11 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
dreschpe 1:bdeac50afe1a 12 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
dreschpe 1:bdeac50afe1a 13 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
dreschpe 1:bdeac50afe1a 14 * THE SOFTWARE.
dreschpe 1:bdeac50afe1a 15 */
dreschpe 1:bdeac50afe1a 16
dreschpe 0:84e23a19e37d 17 #include "stm32l1xx.h"
mullercamille 4:13f94218b838 18 #include "stm32l1xx_hal_rcc.h"
dreschpe 0:84e23a19e37d 19 #include "ST_L152_32MHZ.h"
dreschpe 0:84e23a19e37d 20
dreschpe 1:bdeac50afe1a 21 // only the constructor
dreschpe 0:84e23a19e37d 22 L152_init32::L152_init32(unsigned int external){
dreschpe 1:bdeac50afe1a 23 Status = setup_clock_32MHZ(external);
dreschpe 0:84e23a19e37d 24 }
dreschpe 0:84e23a19e37d 25
dreschpe 0:84e23a19e37d 26 #define PLL_STARTUP_TIMEOUT 0x5000
dreschpe 0:84e23a19e37d 27
dreschpe 1:bdeac50afe1a 28 ClockStatus L152_init32::setup_clock_32MHZ(int external)
dreschpe 0:84e23a19e37d 29 {
mullercamille 4:13f94218b838 30
mullercamille 4:13f94218b838 31
mullercamille 4:13f94218b838 32
mullercamille 4:13f94218b838 33
mullercamille 4:13f94218b838 34
mullercamille 4:13f94218b838 35
dreschpe 0:84e23a19e37d 36 uint32_t PLLStartUpCounter = 0,PLLStatus = 0,error;
dreschpe 0:84e23a19e37d 37
mullercamille 4:13f94218b838 38 HAL_RCC_DeInit(); // we have to reset the clock settings !
dreschpe 2:9e2ba1d93567 39 /* Enable 64-bit access */
dreschpe 2:9e2ba1d93567 40 FLASH->ACR |= FLASH_ACR_ACC64;
dreschpe 2:9e2ba1d93567 41
dreschpe 2:9e2ba1d93567 42 /* Enable Prefetch Buffer */
dreschpe 2:9e2ba1d93567 43 FLASH->ACR |= FLASH_ACR_PRFTEN;
dreschpe 2:9e2ba1d93567 44
dreschpe 2:9e2ba1d93567 45 /* Flash 1 wait state */
dreschpe 2:9e2ba1d93567 46 FLASH->ACR |= FLASH_ACR_LATENCY;
dreschpe 2:9e2ba1d93567 47
dreschpe 2:9e2ba1d93567 48 /* Power enable */
dreschpe 2:9e2ba1d93567 49 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
dreschpe 2:9e2ba1d93567 50
dreschpe 2:9e2ba1d93567 51 /* Select the Voltage Range 1 (1.8 V) */
dreschpe 2:9e2ba1d93567 52 PWR->CR = PWR_CR_VOS_0;
dreschpe 2:9e2ba1d93567 53
dreschpe 2:9e2ba1d93567 54 /* Wait Until the Voltage Regulator is ready */
dreschpe 2:9e2ba1d93567 55 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
dreschpe 2:9e2ba1d93567 56 {
dreschpe 2:9e2ba1d93567 57 }
dreschpe 2:9e2ba1d93567 58
dreschpe 2:9e2ba1d93567 59 /* HCLK = SYSCLK /1*/
dreschpe 2:9e2ba1d93567 60 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
dreschpe 2:9e2ba1d93567 61 /* PCLK2 = HCLK /1*/
dreschpe 2:9e2ba1d93567 62 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
dreschpe 2:9e2ba1d93567 63
dreschpe 2:9e2ba1d93567 64 /* PCLK1 = HCLK /1*/
dreschpe 2:9e2ba1d93567 65 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
dreschpe 2:9e2ba1d93567 66
dreschpe 2:9e2ba1d93567 67 /* PLL configuration */
dreschpe 2:9e2ba1d93567 68 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
dreschpe 2:9e2ba1d93567 69 RCC_CFGR_PLLDIV));
dreschpe 2:9e2ba1d93567 70
dreschpe 2:9e2ba1d93567 71 if(external == 0){
dreschpe 2:9e2ba1d93567 72 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL6 | RCC_CFGR_PLLDIV3);
dreschpe 2:9e2ba1d93567 73 }
dreschpe 2:9e2ba1d93567 74 else{
mullercamille 4:13f94218b838 75
mullercamille 4:13f94218b838 76 /** Need to be update with HAL_RCC_OscConfig
mullercamille 4:13f94218b838 77 **/
mullercamille 4:13f94218b838 78 // __HAL_RCC_HSE_CONFIG(RCC_HSE_ON);
mullercamille 4:13f94218b838 79 //error = RCC_WaitForHSEStartUp();
mullercamille 4:13f94218b838 80 // if(error == ERROR ) { // no external crystal
mullercamille 4:13f94218b838 81 // return(EXT_ERR);
mullercamille 4:13f94218b838 82 // }
mullercamille 4:13f94218b838 83 //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
dreschpe 2:9e2ba1d93567 84 }
dreschpe 2:9e2ba1d93567 85
dreschpe 2:9e2ba1d93567 86 /* Enable PLL */
dreschpe 2:9e2ba1d93567 87 RCC->CR |= RCC_CR_PLLON;
dreschpe 2:9e2ba1d93567 88
dreschpe 2:9e2ba1d93567 89 /* Wait till PLL is ready */
dreschpe 0:84e23a19e37d 90 do {
dreschpe 0:84e23a19e37d 91 PLLStatus = RCC->CR & RCC_CR_PLLRDY;
dreschpe 0:84e23a19e37d 92 } while((PLLStatus == 0) && (PLLStartUpCounter < PLL_STARTUP_TIMEOUT)); // wait for pll
dreschpe 0:84e23a19e37d 93 if(PLLStatus == 0) {
dreschpe 1:bdeac50afe1a 94 return(PLL_ERR);
dreschpe 0:84e23a19e37d 95 }
dreschpe 2:9e2ba1d93567 96
dreschpe 2:9e2ba1d93567 97 /* Select PLL as system clock source */
dreschpe 2:9e2ba1d93567 98 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
dreschpe 2:9e2ba1d93567 99 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
dreschpe 2:9e2ba1d93567 100
dreschpe 2:9e2ba1d93567 101 /* Wait till PLL is used as system clock source */
dreschpe 2:9e2ba1d93567 102 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
dreschpe 2:9e2ba1d93567 103 {
dreschpe 2:9e2ba1d93567 104 }
dreschpe 0:84e23a19e37d 105 SystemCoreClockUpdate(); // update SystemCoreClock var
dreschpe 1:bdeac50afe1a 106 return(OK);
dreschpe 2:9e2ba1d93567 107 }
dreschpe 2:9e2ba1d93567 108