Camille Muller / ST_L152_32MHZ

Fixed with HAL.

Fork of ST_L152_32MHZ by Peter Drescher

Not finish yet. External crystal doesn't work.

ST_L152_32MHZ.cpp@0:84e23a19e37d, 2014-03-11 (annotated)

Committer:
dreschpe
Date:
Tue Mar 11 20:34:57 2014 +0000
Revision:
0:84e23a19e37d
Child:
1:bdeac50afe1a
Lib for the ST Nucleo L152RE board to switch the clock to 32MHz.; Out of the box the board is running on 16MHz.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 0:84e23a19e37d 1
dreschpe 0:84e23a19e37d 2
dreschpe 0:84e23a19e37d 3 #include "stm32l1xx.h"
dreschpe 0:84e23a19e37d 4 #include "stm32l1xx_flash.h"
dreschpe 0:84e23a19e37d 5 #include "stm32l1xx_rcc.h"
dreschpe 0:84e23a19e37d 6 #include "ST_L152_32MHZ.h"
dreschpe 0:84e23a19e37d 7
dreschpe 0:84e23a19e37d 8 // set cpu clock to 32MHz
dreschpe 0:84e23a19e37d 9
dreschpe 0:84e23a19e37d 10
dreschpe 0:84e23a19e37d 11
dreschpe 0:84e23a19e37d 12 L152_init32::L152_init32(unsigned int external){
dreschpe 0:84e23a19e37d 13 clk_err = setup_clock_32MHZ(external);
dreschpe 0:84e23a19e37d 14 }
dreschpe 0:84e23a19e37d 15
dreschpe 0:84e23a19e37d 16 #define PLL_STARTUP_TIMEOUT 0x5000
dreschpe 0:84e23a19e37d 17
dreschpe 0:84e23a19e37d 18 int L152_init32::setup_clock_32MHZ(int external)
dreschpe 0:84e23a19e37d 19 {
dreschpe 0:84e23a19e37d 20 uint32_t PLLStartUpCounter = 0,PLLStatus = 0,error;
dreschpe 0:84e23a19e37d 21
dreschpe 0:84e23a19e37d 22 if(external == 0) { // internal Oscillator
dreschpe 0:84e23a19e37d 23 RCC_PLLConfig(RCC_PLLSource_HSI,RCC_PLLMul_6,RCC_PLLDiv_3); // setup pll to 96MHz to use USB
dreschpe 0:84e23a19e37d 24 } else {
dreschpe 0:84e23a19e37d 25 RCC_HSEConfig(RCC_HSE_ON); // start external crystal osc.
dreschpe 0:84e23a19e37d 26 error = RCC_WaitForHSEStartUp();
dreschpe 0:84e23a19e37d 27 if(error == ERROR ) { // no external crystal
dreschpe 0:84e23a19e37d 28 return(0);
dreschpe 0:84e23a19e37d 29 }
dreschpe 0:84e23a19e37d 30 RCC_PLLConfig(RCC_PLLSource_HSE,RCC_PLLMul_12,RCC_PLLDiv_3); // setup pll to 96MHz to use USB
dreschpe 0:84e23a19e37d 31 }
dreschpe 0:84e23a19e37d 32 RCC_PLLCmd(ENABLE); // switch on pll
dreschpe 0:84e23a19e37d 33 do {
dreschpe 0:84e23a19e37d 34 PLLStatus = RCC->CR & RCC_CR_PLLRDY;
dreschpe 0:84e23a19e37d 35 } while((PLLStatus == 0) && (PLLStartUpCounter < PLL_STARTUP_TIMEOUT)); // wait for pll
dreschpe 0:84e23a19e37d 36 if(PLLStatus == 0) {
dreschpe 0:84e23a19e37d 37 return(0);
dreschpe 0:84e23a19e37d 38 }
dreschpe 0:84e23a19e37d 39 FLASH_SetLatency(FLASH_Latency_1);
dreschpe 0:84e23a19e37d 40 FLASH_PrefetchBufferCmd(ENABLE);
dreschpe 0:84e23a19e37d 41 FLASH_ReadAccess64Cmd(ENABLE);
dreschpe 0:84e23a19e37d 42 RCC_HCLKConfig(RCC_SYSCLK_Div2);
dreschpe 0:84e23a19e37d 43 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); // switch to 32 MHz clock
dreschpe 0:84e23a19e37d 44 SystemCoreClockUpdate(); // update SystemCoreClock var
dreschpe 0:84e23a19e37d 45 return(1);
dreschpe 0:84e23a19e37d 46 }