Mark Turner / mbed

mbed library for slider v2

Dependents:   kl46z_slider_v2

TARGET_KL46Z/core_cmFunc.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:
mturner5
Date:
Wed Sep 14 07:04:27 2016 +0000
Revision:
0:b7116bd48af6
Tried to use the timer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:b7116bd48af6 1 /**************************************************************************//**
mturner5 0:b7116bd48af6 2 * @file core_cmFunc.h
mturner5 0:b7116bd48af6 3 * @brief CMSIS Cortex-M Core Function Access Header File
mturner5 0:b7116bd48af6 4 * @version V4.10
mturner5 0:b7116bd48af6 5 * @date 18. March 2015
mturner5 0:b7116bd48af6 6 *
mturner5 0:b7116bd48af6 7 * @note
mturner5 0:b7116bd48af6 8 *
mturner5 0:b7116bd48af6 9 ******************************************************************************/
mturner5 0:b7116bd48af6 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mturner5 0:b7116bd48af6 11
mturner5 0:b7116bd48af6 12 All rights reserved.
mturner5 0:b7116bd48af6 13 Redistribution and use in source and binary forms, with or without
mturner5 0:b7116bd48af6 14 modification, are permitted provided that the following conditions are met:
mturner5 0:b7116bd48af6 15 - Redistributions of source code must retain the above copyright
mturner5 0:b7116bd48af6 16 notice, this list of conditions and the following disclaimer.
mturner5 0:b7116bd48af6 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:b7116bd48af6 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:b7116bd48af6 19 documentation and/or other materials provided with the distribution.
mturner5 0:b7116bd48af6 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:b7116bd48af6 21 to endorse or promote products derived from this software without
mturner5 0:b7116bd48af6 22 specific prior written permission.
mturner5 0:b7116bd48af6 23 *
mturner5 0:b7116bd48af6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:b7116bd48af6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:b7116bd48af6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:b7116bd48af6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:b7116bd48af6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:b7116bd48af6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:b7116bd48af6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:b7116bd48af6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:b7116bd48af6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:b7116bd48af6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:b7116bd48af6 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:b7116bd48af6 35 ---------------------------------------------------------------------------*/
mturner5 0:b7116bd48af6 36
mturner5 0:b7116bd48af6 37
mturner5 0:b7116bd48af6 38 #ifndef __CORE_CMFUNC_H
mturner5 0:b7116bd48af6 39 #define __CORE_CMFUNC_H
mturner5 0:b7116bd48af6 40
mturner5 0:b7116bd48af6 41
mturner5 0:b7116bd48af6 42 /* ########################### Core Function Access ########################### */
mturner5 0:b7116bd48af6 43 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:b7116bd48af6 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mturner5 0:b7116bd48af6 45 @{
mturner5 0:b7116bd48af6 46 */
mturner5 0:b7116bd48af6 47
mturner5 0:b7116bd48af6 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mturner5 0:b7116bd48af6 49 /* ARM armcc specific functions */
mturner5 0:b7116bd48af6 50
mturner5 0:b7116bd48af6 51 #if (__ARMCC_VERSION < 400677)
mturner5 0:b7116bd48af6 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mturner5 0:b7116bd48af6 53 #endif
mturner5 0:b7116bd48af6 54
mturner5 0:b7116bd48af6 55 /* intrinsic void __enable_irq(); */
mturner5 0:b7116bd48af6 56 /* intrinsic void __disable_irq(); */
mturner5 0:b7116bd48af6 57
mturner5 0:b7116bd48af6 58 /** \brief Get Control Register
mturner5 0:b7116bd48af6 59
mturner5 0:b7116bd48af6 60 This function returns the content of the Control Register.
mturner5 0:b7116bd48af6 61
mturner5 0:b7116bd48af6 62 \return Control Register value
mturner5 0:b7116bd48af6 63 */
mturner5 0:b7116bd48af6 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
mturner5 0:b7116bd48af6 65 {
mturner5 0:b7116bd48af6 66 register uint32_t __regControl __ASM("control");
mturner5 0:b7116bd48af6 67 return(__regControl);
mturner5 0:b7116bd48af6 68 }
mturner5 0:b7116bd48af6 69
mturner5 0:b7116bd48af6 70
mturner5 0:b7116bd48af6 71 /** \brief Set Control Register
mturner5 0:b7116bd48af6 72
mturner5 0:b7116bd48af6 73 This function writes the given value to the Control Register.
mturner5 0:b7116bd48af6 74
mturner5 0:b7116bd48af6 75 \param [in] control Control Register value to set
mturner5 0:b7116bd48af6 76 */
mturner5 0:b7116bd48af6 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
mturner5 0:b7116bd48af6 78 {
mturner5 0:b7116bd48af6 79 register uint32_t __regControl __ASM("control");
mturner5 0:b7116bd48af6 80 __regControl = control;
mturner5 0:b7116bd48af6 81 }
mturner5 0:b7116bd48af6 82
mturner5 0:b7116bd48af6 83
mturner5 0:b7116bd48af6 84 /** \brief Get IPSR Register
mturner5 0:b7116bd48af6 85
mturner5 0:b7116bd48af6 86 This function returns the content of the IPSR Register.
mturner5 0:b7116bd48af6 87
mturner5 0:b7116bd48af6 88 \return IPSR Register value
mturner5 0:b7116bd48af6 89 */
mturner5 0:b7116bd48af6 90 __STATIC_INLINE uint32_t __get_IPSR(void)
mturner5 0:b7116bd48af6 91 {
mturner5 0:b7116bd48af6 92 register uint32_t __regIPSR __ASM("ipsr");
mturner5 0:b7116bd48af6 93 return(__regIPSR);
mturner5 0:b7116bd48af6 94 }
mturner5 0:b7116bd48af6 95
mturner5 0:b7116bd48af6 96
mturner5 0:b7116bd48af6 97 /** \brief Get APSR Register
mturner5 0:b7116bd48af6 98
mturner5 0:b7116bd48af6 99 This function returns the content of the APSR Register.
mturner5 0:b7116bd48af6 100
mturner5 0:b7116bd48af6 101 \return APSR Register value
mturner5 0:b7116bd48af6 102 */
mturner5 0:b7116bd48af6 103 __STATIC_INLINE uint32_t __get_APSR(void)
mturner5 0:b7116bd48af6 104 {
mturner5 0:b7116bd48af6 105 register uint32_t __regAPSR __ASM("apsr");
mturner5 0:b7116bd48af6 106 return(__regAPSR);
mturner5 0:b7116bd48af6 107 }
mturner5 0:b7116bd48af6 108
mturner5 0:b7116bd48af6 109
mturner5 0:b7116bd48af6 110 /** \brief Get xPSR Register
mturner5 0:b7116bd48af6 111
mturner5 0:b7116bd48af6 112 This function returns the content of the xPSR Register.
mturner5 0:b7116bd48af6 113
mturner5 0:b7116bd48af6 114 \return xPSR Register value
mturner5 0:b7116bd48af6 115 */
mturner5 0:b7116bd48af6 116 __STATIC_INLINE uint32_t __get_xPSR(void)
mturner5 0:b7116bd48af6 117 {
mturner5 0:b7116bd48af6 118 register uint32_t __regXPSR __ASM("xpsr");
mturner5 0:b7116bd48af6 119 return(__regXPSR);
mturner5 0:b7116bd48af6 120 }
mturner5 0:b7116bd48af6 121
mturner5 0:b7116bd48af6 122
mturner5 0:b7116bd48af6 123 /** \brief Get Process Stack Pointer
mturner5 0:b7116bd48af6 124
mturner5 0:b7116bd48af6 125 This function returns the current value of the Process Stack Pointer (PSP).
mturner5 0:b7116bd48af6 126
mturner5 0:b7116bd48af6 127 \return PSP Register value
mturner5 0:b7116bd48af6 128 */
mturner5 0:b7116bd48af6 129 __STATIC_INLINE uint32_t __get_PSP(void)
mturner5 0:b7116bd48af6 130 {
mturner5 0:b7116bd48af6 131 register uint32_t __regProcessStackPointer __ASM("psp");
mturner5 0:b7116bd48af6 132 return(__regProcessStackPointer);
mturner5 0:b7116bd48af6 133 }
mturner5 0:b7116bd48af6 134
mturner5 0:b7116bd48af6 135
mturner5 0:b7116bd48af6 136 /** \brief Set Process Stack Pointer
mturner5 0:b7116bd48af6 137
mturner5 0:b7116bd48af6 138 This function assigns the given value to the Process Stack Pointer (PSP).
mturner5 0:b7116bd48af6 139
mturner5 0:b7116bd48af6 140 \param [in] topOfProcStack Process Stack Pointer value to set
mturner5 0:b7116bd48af6 141 */
mturner5 0:b7116bd48af6 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mturner5 0:b7116bd48af6 143 {
mturner5 0:b7116bd48af6 144 register uint32_t __regProcessStackPointer __ASM("psp");
mturner5 0:b7116bd48af6 145 __regProcessStackPointer = topOfProcStack;
mturner5 0:b7116bd48af6 146 }
mturner5 0:b7116bd48af6 147
mturner5 0:b7116bd48af6 148
mturner5 0:b7116bd48af6 149 /** \brief Get Main Stack Pointer
mturner5 0:b7116bd48af6 150
mturner5 0:b7116bd48af6 151 This function returns the current value of the Main Stack Pointer (MSP).
mturner5 0:b7116bd48af6 152
mturner5 0:b7116bd48af6 153 \return MSP Register value
mturner5 0:b7116bd48af6 154 */
mturner5 0:b7116bd48af6 155 __STATIC_INLINE uint32_t __get_MSP(void)
mturner5 0:b7116bd48af6 156 {
mturner5 0:b7116bd48af6 157 register uint32_t __regMainStackPointer __ASM("msp");
mturner5 0:b7116bd48af6 158 return(__regMainStackPointer);
mturner5 0:b7116bd48af6 159 }
mturner5 0:b7116bd48af6 160
mturner5 0:b7116bd48af6 161
mturner5 0:b7116bd48af6 162 /** \brief Set Main Stack Pointer
mturner5 0:b7116bd48af6 163
mturner5 0:b7116bd48af6 164 This function assigns the given value to the Main Stack Pointer (MSP).
mturner5 0:b7116bd48af6 165
mturner5 0:b7116bd48af6 166 \param [in] topOfMainStack Main Stack Pointer value to set
mturner5 0:b7116bd48af6 167 */
mturner5 0:b7116bd48af6 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mturner5 0:b7116bd48af6 169 {
mturner5 0:b7116bd48af6 170 register uint32_t __regMainStackPointer __ASM("msp");
mturner5 0:b7116bd48af6 171 __regMainStackPointer = topOfMainStack;
mturner5 0:b7116bd48af6 172 }
mturner5 0:b7116bd48af6 173
mturner5 0:b7116bd48af6 174
mturner5 0:b7116bd48af6 175 /** \brief Get Priority Mask
mturner5 0:b7116bd48af6 176
mturner5 0:b7116bd48af6 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
mturner5 0:b7116bd48af6 178
mturner5 0:b7116bd48af6 179 \return Priority Mask value
mturner5 0:b7116bd48af6 180 */
mturner5 0:b7116bd48af6 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
mturner5 0:b7116bd48af6 182 {
mturner5 0:b7116bd48af6 183 register uint32_t __regPriMask __ASM("primask");
mturner5 0:b7116bd48af6 184 return(__regPriMask);
mturner5 0:b7116bd48af6 185 }
mturner5 0:b7116bd48af6 186
mturner5 0:b7116bd48af6 187
mturner5 0:b7116bd48af6 188 /** \brief Set Priority Mask
mturner5 0:b7116bd48af6 189
mturner5 0:b7116bd48af6 190 This function assigns the given value to the Priority Mask Register.
mturner5 0:b7116bd48af6 191
mturner5 0:b7116bd48af6 192 \param [in] priMask Priority Mask
mturner5 0:b7116bd48af6 193 */
mturner5 0:b7116bd48af6 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mturner5 0:b7116bd48af6 195 {
mturner5 0:b7116bd48af6 196 register uint32_t __regPriMask __ASM("primask");
mturner5 0:b7116bd48af6 197 __regPriMask = (priMask);
mturner5 0:b7116bd48af6 198 }
mturner5 0:b7116bd48af6 199
mturner5 0:b7116bd48af6 200
mturner5 0:b7116bd48af6 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mturner5 0:b7116bd48af6 202
mturner5 0:b7116bd48af6 203 /** \brief Enable FIQ
mturner5 0:b7116bd48af6 204
mturner5 0:b7116bd48af6 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mturner5 0:b7116bd48af6 206 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 207 */
mturner5 0:b7116bd48af6 208 #define __enable_fault_irq __enable_fiq
mturner5 0:b7116bd48af6 209
mturner5 0:b7116bd48af6 210
mturner5 0:b7116bd48af6 211 /** \brief Disable FIQ
mturner5 0:b7116bd48af6 212
mturner5 0:b7116bd48af6 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mturner5 0:b7116bd48af6 214 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 215 */
mturner5 0:b7116bd48af6 216 #define __disable_fault_irq __disable_fiq
mturner5 0:b7116bd48af6 217
mturner5 0:b7116bd48af6 218
mturner5 0:b7116bd48af6 219 /** \brief Get Base Priority
mturner5 0:b7116bd48af6 220
mturner5 0:b7116bd48af6 221 This function returns the current value of the Base Priority register.
mturner5 0:b7116bd48af6 222
mturner5 0:b7116bd48af6 223 \return Base Priority register value
mturner5 0:b7116bd48af6 224 */
mturner5 0:b7116bd48af6 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
mturner5 0:b7116bd48af6 226 {
mturner5 0:b7116bd48af6 227 register uint32_t __regBasePri __ASM("basepri");
mturner5 0:b7116bd48af6 228 return(__regBasePri);
mturner5 0:b7116bd48af6 229 }
mturner5 0:b7116bd48af6 230
mturner5 0:b7116bd48af6 231
mturner5 0:b7116bd48af6 232 /** \brief Set Base Priority
mturner5 0:b7116bd48af6 233
mturner5 0:b7116bd48af6 234 This function assigns the given value to the Base Priority register.
mturner5 0:b7116bd48af6 235
mturner5 0:b7116bd48af6 236 \param [in] basePri Base Priority value to set
mturner5 0:b7116bd48af6 237 */
mturner5 0:b7116bd48af6 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
mturner5 0:b7116bd48af6 239 {
mturner5 0:b7116bd48af6 240 register uint32_t __regBasePri __ASM("basepri");
mturner5 0:b7116bd48af6 241 __regBasePri = (basePri & 0xff);
mturner5 0:b7116bd48af6 242 }
mturner5 0:b7116bd48af6 243
mturner5 0:b7116bd48af6 244
mturner5 0:b7116bd48af6 245 /** \brief Set Base Priority with condition
mturner5 0:b7116bd48af6 246
mturner5 0:b7116bd48af6 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
mturner5 0:b7116bd48af6 248 or the new value increases the BASEPRI priority level.
mturner5 0:b7116bd48af6 249
mturner5 0:b7116bd48af6 250 \param [in] basePri Base Priority value to set
mturner5 0:b7116bd48af6 251 */
mturner5 0:b7116bd48af6 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
mturner5 0:b7116bd48af6 253 {
mturner5 0:b7116bd48af6 254 register uint32_t __regBasePriMax __ASM("basepri_max");
mturner5 0:b7116bd48af6 255 __regBasePriMax = (basePri & 0xff);
mturner5 0:b7116bd48af6 256 }
mturner5 0:b7116bd48af6 257
mturner5 0:b7116bd48af6 258
mturner5 0:b7116bd48af6 259 /** \brief Get Fault Mask
mturner5 0:b7116bd48af6 260
mturner5 0:b7116bd48af6 261 This function returns the current value of the Fault Mask register.
mturner5 0:b7116bd48af6 262
mturner5 0:b7116bd48af6 263 \return Fault Mask register value
mturner5 0:b7116bd48af6 264 */
mturner5 0:b7116bd48af6 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mturner5 0:b7116bd48af6 266 {
mturner5 0:b7116bd48af6 267 register uint32_t __regFaultMask __ASM("faultmask");
mturner5 0:b7116bd48af6 268 return(__regFaultMask);
mturner5 0:b7116bd48af6 269 }
mturner5 0:b7116bd48af6 270
mturner5 0:b7116bd48af6 271
mturner5 0:b7116bd48af6 272 /** \brief Set Fault Mask
mturner5 0:b7116bd48af6 273
mturner5 0:b7116bd48af6 274 This function assigns the given value to the Fault Mask register.
mturner5 0:b7116bd48af6 275
mturner5 0:b7116bd48af6 276 \param [in] faultMask Fault Mask value to set
mturner5 0:b7116bd48af6 277 */
mturner5 0:b7116bd48af6 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mturner5 0:b7116bd48af6 279 {
mturner5 0:b7116bd48af6 280 register uint32_t __regFaultMask __ASM("faultmask");
mturner5 0:b7116bd48af6 281 __regFaultMask = (faultMask & (uint32_t)1);
mturner5 0:b7116bd48af6 282 }
mturner5 0:b7116bd48af6 283
mturner5 0:b7116bd48af6 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
mturner5 0:b7116bd48af6 285
mturner5 0:b7116bd48af6 286
mturner5 0:b7116bd48af6 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
mturner5 0:b7116bd48af6 288
mturner5 0:b7116bd48af6 289 /** \brief Get FPSCR
mturner5 0:b7116bd48af6 290
mturner5 0:b7116bd48af6 291 This function returns the current value of the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 292
mturner5 0:b7116bd48af6 293 \return Floating Point Status/Control register value
mturner5 0:b7116bd48af6 294 */
mturner5 0:b7116bd48af6 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
mturner5 0:b7116bd48af6 296 {
mturner5 0:b7116bd48af6 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 298 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:b7116bd48af6 299 return(__regfpscr);
mturner5 0:b7116bd48af6 300 #else
mturner5 0:b7116bd48af6 301 return(0);
mturner5 0:b7116bd48af6 302 #endif
mturner5 0:b7116bd48af6 303 }
mturner5 0:b7116bd48af6 304
mturner5 0:b7116bd48af6 305
mturner5 0:b7116bd48af6 306 /** \brief Set FPSCR
mturner5 0:b7116bd48af6 307
mturner5 0:b7116bd48af6 308 This function assigns the given value to the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 309
mturner5 0:b7116bd48af6 310 \param [in] fpscr Floating Point Status/Control value to set
mturner5 0:b7116bd48af6 311 */
mturner5 0:b7116bd48af6 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mturner5 0:b7116bd48af6 313 {
mturner5 0:b7116bd48af6 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 315 register uint32_t __regfpscr __ASM("fpscr");
mturner5 0:b7116bd48af6 316 __regfpscr = (fpscr);
mturner5 0:b7116bd48af6 317 #endif
mturner5 0:b7116bd48af6 318 }
mturner5 0:b7116bd48af6 319
mturner5 0:b7116bd48af6 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
mturner5 0:b7116bd48af6 321
mturner5 0:b7116bd48af6 322
mturner5 0:b7116bd48af6 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mturner5 0:b7116bd48af6 324 /* GNU gcc specific functions */
mturner5 0:b7116bd48af6 325
mturner5 0:b7116bd48af6 326 /** \brief Enable IRQ Interrupts
mturner5 0:b7116bd48af6 327
mturner5 0:b7116bd48af6 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
mturner5 0:b7116bd48af6 329 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 330 */
mturner5 0:b7116bd48af6 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mturner5 0:b7116bd48af6 332 {
mturner5 0:b7116bd48af6 333 __ASM volatile ("cpsie i" : : : "memory");
mturner5 0:b7116bd48af6 334 }
mturner5 0:b7116bd48af6 335
mturner5 0:b7116bd48af6 336
mturner5 0:b7116bd48af6 337 /** \brief Disable IRQ Interrupts
mturner5 0:b7116bd48af6 338
mturner5 0:b7116bd48af6 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mturner5 0:b7116bd48af6 340 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 341 */
mturner5 0:b7116bd48af6 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
mturner5 0:b7116bd48af6 343 {
mturner5 0:b7116bd48af6 344 __ASM volatile ("cpsid i" : : : "memory");
mturner5 0:b7116bd48af6 345 }
mturner5 0:b7116bd48af6 346
mturner5 0:b7116bd48af6 347
mturner5 0:b7116bd48af6 348 /** \brief Get Control Register
mturner5 0:b7116bd48af6 349
mturner5 0:b7116bd48af6 350 This function returns the content of the Control Register.
mturner5 0:b7116bd48af6 351
mturner5 0:b7116bd48af6 352 \return Control Register value
mturner5 0:b7116bd48af6 353 */
mturner5 0:b7116bd48af6 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
mturner5 0:b7116bd48af6 355 {
mturner5 0:b7116bd48af6 356 uint32_t result;
mturner5 0:b7116bd48af6 357
mturner5 0:b7116bd48af6 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
mturner5 0:b7116bd48af6 359 return(result);
mturner5 0:b7116bd48af6 360 }
mturner5 0:b7116bd48af6 361
mturner5 0:b7116bd48af6 362
mturner5 0:b7116bd48af6 363 /** \brief Set Control Register
mturner5 0:b7116bd48af6 364
mturner5 0:b7116bd48af6 365 This function writes the given value to the Control Register.
mturner5 0:b7116bd48af6 366
mturner5 0:b7116bd48af6 367 \param [in] control Control Register value to set
mturner5 0:b7116bd48af6 368 */
mturner5 0:b7116bd48af6 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
mturner5 0:b7116bd48af6 370 {
mturner5 0:b7116bd48af6 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
mturner5 0:b7116bd48af6 372 }
mturner5 0:b7116bd48af6 373
mturner5 0:b7116bd48af6 374
mturner5 0:b7116bd48af6 375 /** \brief Get IPSR Register
mturner5 0:b7116bd48af6 376
mturner5 0:b7116bd48af6 377 This function returns the content of the IPSR Register.
mturner5 0:b7116bd48af6 378
mturner5 0:b7116bd48af6 379 \return IPSR Register value
mturner5 0:b7116bd48af6 380 */
mturner5 0:b7116bd48af6 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
mturner5 0:b7116bd48af6 382 {
mturner5 0:b7116bd48af6 383 uint32_t result;
mturner5 0:b7116bd48af6 384
mturner5 0:b7116bd48af6 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
mturner5 0:b7116bd48af6 386 return(result);
mturner5 0:b7116bd48af6 387 }
mturner5 0:b7116bd48af6 388
mturner5 0:b7116bd48af6 389
mturner5 0:b7116bd48af6 390 /** \brief Get APSR Register
mturner5 0:b7116bd48af6 391
mturner5 0:b7116bd48af6 392 This function returns the content of the APSR Register.
mturner5 0:b7116bd48af6 393
mturner5 0:b7116bd48af6 394 \return APSR Register value
mturner5 0:b7116bd48af6 395 */
mturner5 0:b7116bd48af6 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mturner5 0:b7116bd48af6 397 {
mturner5 0:b7116bd48af6 398 uint32_t result;
mturner5 0:b7116bd48af6 399
mturner5 0:b7116bd48af6 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
mturner5 0:b7116bd48af6 401 return(result);
mturner5 0:b7116bd48af6 402 }
mturner5 0:b7116bd48af6 403
mturner5 0:b7116bd48af6 404
mturner5 0:b7116bd48af6 405 /** \brief Get xPSR Register
mturner5 0:b7116bd48af6 406
mturner5 0:b7116bd48af6 407 This function returns the content of the xPSR Register.
mturner5 0:b7116bd48af6 408
mturner5 0:b7116bd48af6 409 \return xPSR Register value
mturner5 0:b7116bd48af6 410 */
mturner5 0:b7116bd48af6 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
mturner5 0:b7116bd48af6 412 {
mturner5 0:b7116bd48af6 413 uint32_t result;
mturner5 0:b7116bd48af6 414
mturner5 0:b7116bd48af6 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
mturner5 0:b7116bd48af6 416 return(result);
mturner5 0:b7116bd48af6 417 }
mturner5 0:b7116bd48af6 418
mturner5 0:b7116bd48af6 419
mturner5 0:b7116bd48af6 420 /** \brief Get Process Stack Pointer
mturner5 0:b7116bd48af6 421
mturner5 0:b7116bd48af6 422 This function returns the current value of the Process Stack Pointer (PSP).
mturner5 0:b7116bd48af6 423
mturner5 0:b7116bd48af6 424 \return PSP Register value
mturner5 0:b7116bd48af6 425 */
mturner5 0:b7116bd48af6 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
mturner5 0:b7116bd48af6 427 {
mturner5 0:b7116bd48af6 428 register uint32_t result;
mturner5 0:b7116bd48af6 429
mturner5 0:b7116bd48af6 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
mturner5 0:b7116bd48af6 431 return(result);
mturner5 0:b7116bd48af6 432 }
mturner5 0:b7116bd48af6 433
mturner5 0:b7116bd48af6 434
mturner5 0:b7116bd48af6 435 /** \brief Set Process Stack Pointer
mturner5 0:b7116bd48af6 436
mturner5 0:b7116bd48af6 437 This function assigns the given value to the Process Stack Pointer (PSP).
mturner5 0:b7116bd48af6 438
mturner5 0:b7116bd48af6 439 \param [in] topOfProcStack Process Stack Pointer value to set
mturner5 0:b7116bd48af6 440 */
mturner5 0:b7116bd48af6 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mturner5 0:b7116bd48af6 442 {
mturner5 0:b7116bd48af6 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
mturner5 0:b7116bd48af6 444 }
mturner5 0:b7116bd48af6 445
mturner5 0:b7116bd48af6 446
mturner5 0:b7116bd48af6 447 /** \brief Get Main Stack Pointer
mturner5 0:b7116bd48af6 448
mturner5 0:b7116bd48af6 449 This function returns the current value of the Main Stack Pointer (MSP).
mturner5 0:b7116bd48af6 450
mturner5 0:b7116bd48af6 451 \return MSP Register value
mturner5 0:b7116bd48af6 452 */
mturner5 0:b7116bd48af6 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
mturner5 0:b7116bd48af6 454 {
mturner5 0:b7116bd48af6 455 register uint32_t result;
mturner5 0:b7116bd48af6 456
mturner5 0:b7116bd48af6 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
mturner5 0:b7116bd48af6 458 return(result);
mturner5 0:b7116bd48af6 459 }
mturner5 0:b7116bd48af6 460
mturner5 0:b7116bd48af6 461
mturner5 0:b7116bd48af6 462 /** \brief Set Main Stack Pointer
mturner5 0:b7116bd48af6 463
mturner5 0:b7116bd48af6 464 This function assigns the given value to the Main Stack Pointer (MSP).
mturner5 0:b7116bd48af6 465
mturner5 0:b7116bd48af6 466 \param [in] topOfMainStack Main Stack Pointer value to set
mturner5 0:b7116bd48af6 467 */
mturner5 0:b7116bd48af6 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mturner5 0:b7116bd48af6 469 {
mturner5 0:b7116bd48af6 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
mturner5 0:b7116bd48af6 471 }
mturner5 0:b7116bd48af6 472
mturner5 0:b7116bd48af6 473
mturner5 0:b7116bd48af6 474 /** \brief Get Priority Mask
mturner5 0:b7116bd48af6 475
mturner5 0:b7116bd48af6 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
mturner5 0:b7116bd48af6 477
mturner5 0:b7116bd48af6 478 \return Priority Mask value
mturner5 0:b7116bd48af6 479 */
mturner5 0:b7116bd48af6 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
mturner5 0:b7116bd48af6 481 {
mturner5 0:b7116bd48af6 482 uint32_t result;
mturner5 0:b7116bd48af6 483
mturner5 0:b7116bd48af6 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
mturner5 0:b7116bd48af6 485 return(result);
mturner5 0:b7116bd48af6 486 }
mturner5 0:b7116bd48af6 487
mturner5 0:b7116bd48af6 488
mturner5 0:b7116bd48af6 489 /** \brief Set Priority Mask
mturner5 0:b7116bd48af6 490
mturner5 0:b7116bd48af6 491 This function assigns the given value to the Priority Mask Register.
mturner5 0:b7116bd48af6 492
mturner5 0:b7116bd48af6 493 \param [in] priMask Priority Mask
mturner5 0:b7116bd48af6 494 */
mturner5 0:b7116bd48af6 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mturner5 0:b7116bd48af6 496 {
mturner5 0:b7116bd48af6 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
mturner5 0:b7116bd48af6 498 }
mturner5 0:b7116bd48af6 499
mturner5 0:b7116bd48af6 500
mturner5 0:b7116bd48af6 501 #if (__CORTEX_M >= 0x03)
mturner5 0:b7116bd48af6 502
mturner5 0:b7116bd48af6 503 /** \brief Enable FIQ
mturner5 0:b7116bd48af6 504
mturner5 0:b7116bd48af6 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mturner5 0:b7116bd48af6 506 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 507 */
mturner5 0:b7116bd48af6 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
mturner5 0:b7116bd48af6 509 {
mturner5 0:b7116bd48af6 510 __ASM volatile ("cpsie f" : : : "memory");
mturner5 0:b7116bd48af6 511 }
mturner5 0:b7116bd48af6 512
mturner5 0:b7116bd48af6 513
mturner5 0:b7116bd48af6 514 /** \brief Disable FIQ
mturner5 0:b7116bd48af6 515
mturner5 0:b7116bd48af6 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mturner5 0:b7116bd48af6 517 Can only be executed in Privileged modes.
mturner5 0:b7116bd48af6 518 */
mturner5 0:b7116bd48af6 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
mturner5 0:b7116bd48af6 520 {
mturner5 0:b7116bd48af6 521 __ASM volatile ("cpsid f" : : : "memory");
mturner5 0:b7116bd48af6 522 }
mturner5 0:b7116bd48af6 523
mturner5 0:b7116bd48af6 524
mturner5 0:b7116bd48af6 525 /** \brief Get Base Priority
mturner5 0:b7116bd48af6 526
mturner5 0:b7116bd48af6 527 This function returns the current value of the Base Priority register.
mturner5 0:b7116bd48af6 528
mturner5 0:b7116bd48af6 529 \return Base Priority register value
mturner5 0:b7116bd48af6 530 */
mturner5 0:b7116bd48af6 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
mturner5 0:b7116bd48af6 532 {
mturner5 0:b7116bd48af6 533 uint32_t result;
mturner5 0:b7116bd48af6 534
mturner5 0:b7116bd48af6 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
mturner5 0:b7116bd48af6 536 return(result);
mturner5 0:b7116bd48af6 537 }
mturner5 0:b7116bd48af6 538
mturner5 0:b7116bd48af6 539
mturner5 0:b7116bd48af6 540 /** \brief Set Base Priority
mturner5 0:b7116bd48af6 541
mturner5 0:b7116bd48af6 542 This function assigns the given value to the Base Priority register.
mturner5 0:b7116bd48af6 543
mturner5 0:b7116bd48af6 544 \param [in] basePri Base Priority value to set
mturner5 0:b7116bd48af6 545 */
mturner5 0:b7116bd48af6 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
mturner5 0:b7116bd48af6 547 {
mturner5 0:b7116bd48af6 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
mturner5 0:b7116bd48af6 549 }
mturner5 0:b7116bd48af6 550
mturner5 0:b7116bd48af6 551
mturner5 0:b7116bd48af6 552 /** \brief Set Base Priority with condition
mturner5 0:b7116bd48af6 553
mturner5 0:b7116bd48af6 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
mturner5 0:b7116bd48af6 555 or the new value increases the BASEPRI priority level.
mturner5 0:b7116bd48af6 556
mturner5 0:b7116bd48af6 557 \param [in] basePri Base Priority value to set
mturner5 0:b7116bd48af6 558 */
mturner5 0:b7116bd48af6 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
mturner5 0:b7116bd48af6 560 {
mturner5 0:b7116bd48af6 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
mturner5 0:b7116bd48af6 562 }
mturner5 0:b7116bd48af6 563
mturner5 0:b7116bd48af6 564
mturner5 0:b7116bd48af6 565 /** \brief Get Fault Mask
mturner5 0:b7116bd48af6 566
mturner5 0:b7116bd48af6 567 This function returns the current value of the Fault Mask register.
mturner5 0:b7116bd48af6 568
mturner5 0:b7116bd48af6 569 \return Fault Mask register value
mturner5 0:b7116bd48af6 570 */
mturner5 0:b7116bd48af6 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mturner5 0:b7116bd48af6 572 {
mturner5 0:b7116bd48af6 573 uint32_t result;
mturner5 0:b7116bd48af6 574
mturner5 0:b7116bd48af6 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
mturner5 0:b7116bd48af6 576 return(result);
mturner5 0:b7116bd48af6 577 }
mturner5 0:b7116bd48af6 578
mturner5 0:b7116bd48af6 579
mturner5 0:b7116bd48af6 580 /** \brief Set Fault Mask
mturner5 0:b7116bd48af6 581
mturner5 0:b7116bd48af6 582 This function assigns the given value to the Fault Mask register.
mturner5 0:b7116bd48af6 583
mturner5 0:b7116bd48af6 584 \param [in] faultMask Fault Mask value to set
mturner5 0:b7116bd48af6 585 */
mturner5 0:b7116bd48af6 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mturner5 0:b7116bd48af6 587 {
mturner5 0:b7116bd48af6 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
mturner5 0:b7116bd48af6 589 }
mturner5 0:b7116bd48af6 590
mturner5 0:b7116bd48af6 591 #endif /* (__CORTEX_M >= 0x03) */
mturner5 0:b7116bd48af6 592
mturner5 0:b7116bd48af6 593
mturner5 0:b7116bd48af6 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
mturner5 0:b7116bd48af6 595
mturner5 0:b7116bd48af6 596 /** \brief Get FPSCR
mturner5 0:b7116bd48af6 597
mturner5 0:b7116bd48af6 598 This function returns the current value of the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 599
mturner5 0:b7116bd48af6 600 \return Floating Point Status/Control register value
mturner5 0:b7116bd48af6 601 */
mturner5 0:b7116bd48af6 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mturner5 0:b7116bd48af6 603 {
mturner5 0:b7116bd48af6 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 605 uint32_t result;
mturner5 0:b7116bd48af6 606
mturner5 0:b7116bd48af6 607 /* Empty asm statement works as a scheduling barrier */
mturner5 0:b7116bd48af6 608 __ASM volatile ("");
mturner5 0:b7116bd48af6 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
mturner5 0:b7116bd48af6 610 __ASM volatile ("");
mturner5 0:b7116bd48af6 611 return(result);
mturner5 0:b7116bd48af6 612 #else
mturner5 0:b7116bd48af6 613 return(0);
mturner5 0:b7116bd48af6 614 #endif
mturner5 0:b7116bd48af6 615 }
mturner5 0:b7116bd48af6 616
mturner5 0:b7116bd48af6 617
mturner5 0:b7116bd48af6 618 /** \brief Set FPSCR
mturner5 0:b7116bd48af6 619
mturner5 0:b7116bd48af6 620 This function assigns the given value to the Floating Point Status/Control register.
mturner5 0:b7116bd48af6 621
mturner5 0:b7116bd48af6 622 \param [in] fpscr Floating Point Status/Control value to set
mturner5 0:b7116bd48af6 623 */
mturner5 0:b7116bd48af6 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mturner5 0:b7116bd48af6 625 {
mturner5 0:b7116bd48af6 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mturner5 0:b7116bd48af6 627 /* Empty asm statement works as a scheduling barrier */
mturner5 0:b7116bd48af6 628 __ASM volatile ("");
mturner5 0:b7116bd48af6 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
mturner5 0:b7116bd48af6 630 __ASM volatile ("");
mturner5 0:b7116bd48af6 631 #endif
mturner5 0:b7116bd48af6 632 }
mturner5 0:b7116bd48af6 633
mturner5 0:b7116bd48af6 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
mturner5 0:b7116bd48af6 635
mturner5 0:b7116bd48af6 636
mturner5 0:b7116bd48af6 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mturner5 0:b7116bd48af6 638 /* IAR iccarm specific functions */
mturner5 0:b7116bd48af6 639 #include <cmsis_iar.h>
mturner5 0:b7116bd48af6 640
mturner5 0:b7116bd48af6 641
mturner5 0:b7116bd48af6 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mturner5 0:b7116bd48af6 643 /* TI CCS specific functions */
mturner5 0:b7116bd48af6 644 #include <cmsis_ccs.h>
mturner5 0:b7116bd48af6 645
mturner5 0:b7116bd48af6 646
mturner5 0:b7116bd48af6 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mturner5 0:b7116bd48af6 648 /* TASKING carm specific functions */
mturner5 0:b7116bd48af6 649 /*
mturner5 0:b7116bd48af6 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
mturner5 0:b7116bd48af6 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
mturner5 0:b7116bd48af6 652 * Including the CMSIS ones.
mturner5 0:b7116bd48af6 653 */
mturner5 0:b7116bd48af6 654
mturner5 0:b7116bd48af6 655
mturner5 0:b7116bd48af6 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
mturner5 0:b7116bd48af6 657 /* Cosmic specific functions */
mturner5 0:b7116bd48af6 658 #include <cmsis_csm.h>
mturner5 0:b7116bd48af6 659
mturner5 0:b7116bd48af6 660 #endif
mturner5 0:b7116bd48af6 661
mturner5 0:b7116bd48af6 662 /*@} end of CMSIS_Core_RegAccFunctions */
mturner5 0:b7116bd48af6 663
mturner5 0:b7116bd48af6 664 #endif /* __CORE_CMFUNC_H */