mbed - mbed library for slider v2

Users » mturner5 » Code » mbed

mbed library for slider v2

TARGET_KL46Z/core_cm3.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:: mturner5
Date:: Wed Sep 14 07:04:27 2016 +0000
Revision:: 0:b7116bd48af6

Tried to use the timer.

Who changed what in which revision?

User	Revision	Line number	New contents of line
mturner5	0:b7116bd48af6	1	/************************************************************************//
mturner5	0:b7116bd48af6	2	* @file core_cm3.h
mturner5	0:b7116bd48af6	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
mturner5	0:b7116bd48af6	4	* @version V4.10
mturner5	0:b7116bd48af6	5	* @date 18. March 2015
mturner5	0:b7116bd48af6	6	*
mturner5	0:b7116bd48af6	7	* @note
mturner5	0:b7116bd48af6	8	*
mturner5	0:b7116bd48af6	9	******************************************************************************/
mturner5	0:b7116bd48af6	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
mturner5	0:b7116bd48af6	11
mturner5	0:b7116bd48af6	12	All rights reserved.
mturner5	0:b7116bd48af6	13	Redistribution and use in source and binary forms, with or without
mturner5	0:b7116bd48af6	14	modification, are permitted provided that the following conditions are met:
mturner5	0:b7116bd48af6	15	- Redistributions of source code must retain the above copyright
mturner5	0:b7116bd48af6	16	notice, this list of conditions and the following disclaimer.
mturner5	0:b7116bd48af6	17	- Redistributions in binary form must reproduce the above copyright
mturner5	0:b7116bd48af6	18	notice, this list of conditions and the following disclaimer in the
mturner5	0:b7116bd48af6	19	documentation and/or other materials provided with the distribution.
mturner5	0:b7116bd48af6	20	- Neither the name of ARM nor the names of its contributors may be used
mturner5	0:b7116bd48af6	21	to endorse or promote products derived from this software without
mturner5	0:b7116bd48af6	22	specific prior written permission.
mturner5	0:b7116bd48af6	23	*
mturner5	0:b7116bd48af6	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5	0:b7116bd48af6	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5	0:b7116bd48af6	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5	0:b7116bd48af6	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5	0:b7116bd48af6	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5	0:b7116bd48af6	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5	0:b7116bd48af6	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5	0:b7116bd48af6	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5	0:b7116bd48af6	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5	0:b7116bd48af6	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5	0:b7116bd48af6	34	POSSIBILITY OF SUCH DAMAGE.
mturner5	0:b7116bd48af6	35	---------------------------------------------------------------------------*/
mturner5	0:b7116bd48af6	36
mturner5	0:b7116bd48af6	37
mturner5	0:b7116bd48af6	38	#if defined ( __ICCARM__ )
mturner5	0:b7116bd48af6	39	#pragma system_include /* treat file as system include file for MISRA check */
mturner5	0:b7116bd48af6	40	#endif
mturner5	0:b7116bd48af6	41
mturner5	0:b7116bd48af6	42	#ifndef __CORE_CM3_H_GENERIC
mturner5	0:b7116bd48af6	43	#define __CORE_CM3_H_GENERIC
mturner5	0:b7116bd48af6	44
mturner5	0:b7116bd48af6	45	#ifdef __cplusplus
mturner5	0:b7116bd48af6	46	extern "C" {
mturner5	0:b7116bd48af6	47	#endif
mturner5	0:b7116bd48af6	48
mturner5	0:b7116bd48af6	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mturner5	0:b7116bd48af6	50	CMSIS violates the following MISRA-C:2004 rules:
mturner5	0:b7116bd48af6	51
mturner5	0:b7116bd48af6	52	\li Required Rule 8.5, object/function definition in header file.<br>
mturner5	0:b7116bd48af6	53	Function definitions in header files are used to allow 'inlining'.
mturner5	0:b7116bd48af6	54
mturner5	0:b7116bd48af6	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mturner5	0:b7116bd48af6	56	Unions are used for effective representation of core registers.
mturner5	0:b7116bd48af6	57
mturner5	0:b7116bd48af6	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
mturner5	0:b7116bd48af6	59	Function-like macros are used to allow more efficient code.
mturner5	0:b7116bd48af6	60	*/
mturner5	0:b7116bd48af6	61
mturner5	0:b7116bd48af6	62
mturner5	0:b7116bd48af6	63	/*******************************************************************************
mturner5	0:b7116bd48af6	64	* CMSIS definitions
mturner5	0:b7116bd48af6	65	******************************************************************************/
mturner5	0:b7116bd48af6	66	/** \ingroup Cortex_M3
mturner5	0:b7116bd48af6	67	@{
mturner5	0:b7116bd48af6	68	*/
mturner5	0:b7116bd48af6	69
mturner5	0:b7116bd48af6	70	/* CMSIS CM3 definitions */
mturner5	0:b7116bd48af6	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
mturner5	0:b7116bd48af6	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
mturner5	0:b7116bd48af6	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
mturner5	0:b7116bd48af6	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
mturner5	0:b7116bd48af6	75
mturner5	0:b7116bd48af6	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
mturner5	0:b7116bd48af6	77
mturner5	0:b7116bd48af6	78
mturner5	0:b7116bd48af6	79	#if defined ( __CC_ARM )
mturner5	0:b7116bd48af6	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
mturner5	0:b7116bd48af6	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
mturner5	0:b7116bd48af6	82	#define __STATIC_INLINE static __inline
mturner5	0:b7116bd48af6	83
mturner5	0:b7116bd48af6	84	#elif defined ( __GNUC__ )
mturner5	0:b7116bd48af6	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
mturner5	0:b7116bd48af6	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
mturner5	0:b7116bd48af6	87	#define __STATIC_INLINE static inline
mturner5	0:b7116bd48af6	88
mturner5	0:b7116bd48af6	89	#elif defined ( __ICCARM__ )
mturner5	0:b7116bd48af6	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
mturner5	0:b7116bd48af6	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
mturner5	0:b7116bd48af6	92	#define __STATIC_INLINE static inline
mturner5	0:b7116bd48af6	93
mturner5	0:b7116bd48af6	94	#elif defined ( __TMS470__ )
mturner5	0:b7116bd48af6	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
mturner5	0:b7116bd48af6	96	#define __STATIC_INLINE static inline
mturner5	0:b7116bd48af6	97
mturner5	0:b7116bd48af6	98	#elif defined ( __TASKING__ )
mturner5	0:b7116bd48af6	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
mturner5	0:b7116bd48af6	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
mturner5	0:b7116bd48af6	101	#define __STATIC_INLINE static inline
mturner5	0:b7116bd48af6	102
mturner5	0:b7116bd48af6	103	#elif defined ( __CSMC__ )
mturner5	0:b7116bd48af6	104	#define __packed
mturner5	0:b7116bd48af6	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
mturner5	0:b7116bd48af6	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
mturner5	0:b7116bd48af6	107	#define __STATIC_INLINE static inline
mturner5	0:b7116bd48af6	108
mturner5	0:b7116bd48af6	109	#endif
mturner5	0:b7116bd48af6	110
mturner5	0:b7116bd48af6	111	/** __FPU_USED indicates whether an FPU is used or not.
mturner5	0:b7116bd48af6	112	This core does not support an FPU at all
mturner5	0:b7116bd48af6	113	*/
mturner5	0:b7116bd48af6	114	#define __FPU_USED 0
mturner5	0:b7116bd48af6	115
mturner5	0:b7116bd48af6	116	#if defined ( __CC_ARM )
mturner5	0:b7116bd48af6	117	#if defined __TARGET_FPU_VFP
mturner5	0:b7116bd48af6	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5	0:b7116bd48af6	119	#endif
mturner5	0:b7116bd48af6	120
mturner5	0:b7116bd48af6	121	#elif defined ( __GNUC__ )
mturner5	0:b7116bd48af6	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
mturner5	0:b7116bd48af6	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5	0:b7116bd48af6	124	#endif
mturner5	0:b7116bd48af6	125
mturner5	0:b7116bd48af6	126	#elif defined ( __ICCARM__ )
mturner5	0:b7116bd48af6	127	#if defined __ARMVFP__
mturner5	0:b7116bd48af6	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5	0:b7116bd48af6	129	#endif
mturner5	0:b7116bd48af6	130
mturner5	0:b7116bd48af6	131	#elif defined ( __TMS470__ )
mturner5	0:b7116bd48af6	132	#if defined __TI__VFP_SUPPORT____
mturner5	0:b7116bd48af6	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5	0:b7116bd48af6	134	#endif
mturner5	0:b7116bd48af6	135
mturner5	0:b7116bd48af6	136	#elif defined ( __TASKING__ )
mturner5	0:b7116bd48af6	137	#if defined __FPU_VFP__
mturner5	0:b7116bd48af6	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5	0:b7116bd48af6	139	#endif
mturner5	0:b7116bd48af6	140
mturner5	0:b7116bd48af6	141	#elif defined ( __CSMC__ ) /* Cosmic */
mturner5	0:b7116bd48af6	142	#if ( __CSMC__ & 0x400) // FPU present for parser
mturner5	0:b7116bd48af6	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5	0:b7116bd48af6	144	#endif
mturner5	0:b7116bd48af6	145	#endif
mturner5	0:b7116bd48af6	146
mturner5	0:b7116bd48af6	147	#include <stdint.h> /* standard types definitions */
mturner5	0:b7116bd48af6	148	#include <core_cmInstr.h> /* Core Instruction Access */
mturner5	0:b7116bd48af6	149	#include <core_cmFunc.h> /* Core Function Access */
mturner5	0:b7116bd48af6	150
mturner5	0:b7116bd48af6	151	#ifdef __cplusplus
mturner5	0:b7116bd48af6	152	}
mturner5	0:b7116bd48af6	153	#endif
mturner5	0:b7116bd48af6	154
mturner5	0:b7116bd48af6	155	#endif /* __CORE_CM3_H_GENERIC */
mturner5	0:b7116bd48af6	156
mturner5	0:b7116bd48af6	157	#ifndef __CMSIS_GENERIC
mturner5	0:b7116bd48af6	158
mturner5	0:b7116bd48af6	159	#ifndef __CORE_CM3_H_DEPENDANT
mturner5	0:b7116bd48af6	160	#define __CORE_CM3_H_DEPENDANT
mturner5	0:b7116bd48af6	161
mturner5	0:b7116bd48af6	162	#ifdef __cplusplus
mturner5	0:b7116bd48af6	163	extern "C" {
mturner5	0:b7116bd48af6	164	#endif
mturner5	0:b7116bd48af6	165
mturner5	0:b7116bd48af6	166	/* check device defines and use defaults */
mturner5	0:b7116bd48af6	167	#if defined __CHECK_DEVICE_DEFINES
mturner5	0:b7116bd48af6	168	#ifndef __CM3_REV
mturner5	0:b7116bd48af6	169	#define __CM3_REV 0x0200
mturner5	0:b7116bd48af6	170	#warning "__CM3_REV not defined in device header file; using default!"
mturner5	0:b7116bd48af6	171	#endif
mturner5	0:b7116bd48af6	172
mturner5	0:b7116bd48af6	173	#ifndef __MPU_PRESENT
mturner5	0:b7116bd48af6	174	#define __MPU_PRESENT 0
mturner5	0:b7116bd48af6	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
mturner5	0:b7116bd48af6	176	#endif
mturner5	0:b7116bd48af6	177
mturner5	0:b7116bd48af6	178	#ifndef __NVIC_PRIO_BITS
mturner5	0:b7116bd48af6	179	#define __NVIC_PRIO_BITS 4
mturner5	0:b7116bd48af6	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mturner5	0:b7116bd48af6	181	#endif
mturner5	0:b7116bd48af6	182
mturner5	0:b7116bd48af6	183	#ifndef __Vendor_SysTickConfig
mturner5	0:b7116bd48af6	184	#define __Vendor_SysTickConfig 0
mturner5	0:b7116bd48af6	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mturner5	0:b7116bd48af6	186	#endif
mturner5	0:b7116bd48af6	187	#endif
mturner5	0:b7116bd48af6	188
mturner5	0:b7116bd48af6	189	/* IO definitions (access restrictions to peripheral registers) */
mturner5	0:b7116bd48af6	190	/**
mturner5	0:b7116bd48af6	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
mturner5	0:b7116bd48af6	192
mturner5	0:b7116bd48af6	193	<strong>IO Type Qualifiers</strong> are used
mturner5	0:b7116bd48af6	194	\li to specify the access to peripheral variables.
mturner5	0:b7116bd48af6	195	\li for automatic generation of peripheral register debug information.
mturner5	0:b7116bd48af6	196	*/
mturner5	0:b7116bd48af6	197	#ifdef __cplusplus
mturner5	0:b7116bd48af6	198	#define __I volatile /!< Defines 'read only' permissions /
mturner5	0:b7116bd48af6	199	#else
mturner5	0:b7116bd48af6	200	#define __I volatile const /!< Defines 'read only' permissions /
mturner5	0:b7116bd48af6	201	#endif
mturner5	0:b7116bd48af6	202	#define __O volatile /!< Defines 'write only' permissions /
mturner5	0:b7116bd48af6	203	#define __IO volatile /!< Defines 'read / write' permissions /
mturner5	0:b7116bd48af6	204
mturner5	0:b7116bd48af6	205	/@} end of group Cortex_M3 /
mturner5	0:b7116bd48af6	206
mturner5	0:b7116bd48af6	207
mturner5	0:b7116bd48af6	208
mturner5	0:b7116bd48af6	209	/*******************************************************************************
mturner5	0:b7116bd48af6	210	* Register Abstraction
mturner5	0:b7116bd48af6	211	Core Register contain:
mturner5	0:b7116bd48af6	212	- Core Register
mturner5	0:b7116bd48af6	213	- Core NVIC Register
mturner5	0:b7116bd48af6	214	- Core SCB Register
mturner5	0:b7116bd48af6	215	- Core SysTick Register
mturner5	0:b7116bd48af6	216	- Core Debug Register
mturner5	0:b7116bd48af6	217	- Core MPU Register
mturner5	0:b7116bd48af6	218	******************************************************************************/
mturner5	0:b7116bd48af6	219	/** \defgroup CMSIS_core_register Defines and Type Definitions
mturner5	0:b7116bd48af6	220	\brief Type definitions and defines for Cortex-M processor based devices.
mturner5	0:b7116bd48af6	221	*/
mturner5	0:b7116bd48af6	222
mturner5	0:b7116bd48af6	223	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	224	\defgroup CMSIS_CORE Status and Control Registers
mturner5	0:b7116bd48af6	225	\brief Core Register type definitions.
mturner5	0:b7116bd48af6	226	@{
mturner5	0:b7116bd48af6	227	*/
mturner5	0:b7116bd48af6	228
mturner5	0:b7116bd48af6	229	/** \brief Union type to access the Application Program Status Register (APSR).
mturner5	0:b7116bd48af6	230	*/
mturner5	0:b7116bd48af6	231	typedef union
mturner5	0:b7116bd48af6	232	{
mturner5	0:b7116bd48af6	233	struct
mturner5	0:b7116bd48af6	234	{
mturner5	0:b7116bd48af6	235	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
mturner5	0:b7116bd48af6	236	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mturner5	0:b7116bd48af6	237	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mturner5	0:b7116bd48af6	238	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mturner5	0:b7116bd48af6	239	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mturner5	0:b7116bd48af6	240	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mturner5	0:b7116bd48af6	241	} b; /!< Structure used for bit access /
mturner5	0:b7116bd48af6	242	uint32_t w; /!< Type used for word access /
mturner5	0:b7116bd48af6	243	} APSR_Type;
mturner5	0:b7116bd48af6	244
mturner5	0:b7116bd48af6	245	/* APSR Register Definitions */
mturner5	0:b7116bd48af6	246	#define APSR_N_Pos 31 /!< APSR: N Position /
mturner5	0:b7116bd48af6	247	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
mturner5	0:b7116bd48af6	248
mturner5	0:b7116bd48af6	249	#define APSR_Z_Pos 30 /!< APSR: Z Position /
mturner5	0:b7116bd48af6	250	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
mturner5	0:b7116bd48af6	251
mturner5	0:b7116bd48af6	252	#define APSR_C_Pos 29 /!< APSR: C Position /
mturner5	0:b7116bd48af6	253	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
mturner5	0:b7116bd48af6	254
mturner5	0:b7116bd48af6	255	#define APSR_V_Pos 28 /!< APSR: V Position /
mturner5	0:b7116bd48af6	256	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
mturner5	0:b7116bd48af6	257
mturner5	0:b7116bd48af6	258	#define APSR_Q_Pos 27 /!< APSR: Q Position /
mturner5	0:b7116bd48af6	259	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
mturner5	0:b7116bd48af6	260
mturner5	0:b7116bd48af6	261
mturner5	0:b7116bd48af6	262	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
mturner5	0:b7116bd48af6	263	*/
mturner5	0:b7116bd48af6	264	typedef union
mturner5	0:b7116bd48af6	265	{
mturner5	0:b7116bd48af6	266	struct
mturner5	0:b7116bd48af6	267	{
mturner5	0:b7116bd48af6	268	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mturner5	0:b7116bd48af6	269	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
mturner5	0:b7116bd48af6	270	} b; /!< Structure used for bit access /
mturner5	0:b7116bd48af6	271	uint32_t w; /!< Type used for word access /
mturner5	0:b7116bd48af6	272	} IPSR_Type;
mturner5	0:b7116bd48af6	273
mturner5	0:b7116bd48af6	274	/* IPSR Register Definitions */
mturner5	0:b7116bd48af6	275	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
mturner5	0:b7116bd48af6	276	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
mturner5	0:b7116bd48af6	277
mturner5	0:b7116bd48af6	278
mturner5	0:b7116bd48af6	279	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mturner5	0:b7116bd48af6	280	*/
mturner5	0:b7116bd48af6	281	typedef union
mturner5	0:b7116bd48af6	282	{
mturner5	0:b7116bd48af6	283	struct
mturner5	0:b7116bd48af6	284	{
mturner5	0:b7116bd48af6	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mturner5	0:b7116bd48af6	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
mturner5	0:b7116bd48af6	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
mturner5	0:b7116bd48af6	288	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
mturner5	0:b7116bd48af6	289	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mturner5	0:b7116bd48af6	290	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mturner5	0:b7116bd48af6	291	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mturner5	0:b7116bd48af6	292	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mturner5	0:b7116bd48af6	293	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mturner5	0:b7116bd48af6	294	} b; /!< Structure used for bit access /
mturner5	0:b7116bd48af6	295	uint32_t w; /!< Type used for word access /
mturner5	0:b7116bd48af6	296	} xPSR_Type;
mturner5	0:b7116bd48af6	297
mturner5	0:b7116bd48af6	298	/* xPSR Register Definitions */
mturner5	0:b7116bd48af6	299	#define xPSR_N_Pos 31 /!< xPSR: N Position /
mturner5	0:b7116bd48af6	300	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
mturner5	0:b7116bd48af6	301
mturner5	0:b7116bd48af6	302	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
mturner5	0:b7116bd48af6	303	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
mturner5	0:b7116bd48af6	304
mturner5	0:b7116bd48af6	305	#define xPSR_C_Pos 29 /!< xPSR: C Position /
mturner5	0:b7116bd48af6	306	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
mturner5	0:b7116bd48af6	307
mturner5	0:b7116bd48af6	308	#define xPSR_V_Pos 28 /!< xPSR: V Position /
mturner5	0:b7116bd48af6	309	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
mturner5	0:b7116bd48af6	310
mturner5	0:b7116bd48af6	311	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
mturner5	0:b7116bd48af6	312	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
mturner5	0:b7116bd48af6	313
mturner5	0:b7116bd48af6	314	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
mturner5	0:b7116bd48af6	315	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
mturner5	0:b7116bd48af6	316
mturner5	0:b7116bd48af6	317	#define xPSR_T_Pos 24 /!< xPSR: T Position /
mturner5	0:b7116bd48af6	318	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
mturner5	0:b7116bd48af6	319
mturner5	0:b7116bd48af6	320	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
mturner5	0:b7116bd48af6	321	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
mturner5	0:b7116bd48af6	322
mturner5	0:b7116bd48af6	323
mturner5	0:b7116bd48af6	324	/** \brief Union type to access the Control Registers (CONTROL).
mturner5	0:b7116bd48af6	325	*/
mturner5	0:b7116bd48af6	326	typedef union
mturner5	0:b7116bd48af6	327	{
mturner5	0:b7116bd48af6	328	struct
mturner5	0:b7116bd48af6	329	{
mturner5	0:b7116bd48af6	330	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
mturner5	0:b7116bd48af6	331	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
mturner5	0:b7116bd48af6	332	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
mturner5	0:b7116bd48af6	333	} b; /!< Structure used for bit access /
mturner5	0:b7116bd48af6	334	uint32_t w; /!< Type used for word access /
mturner5	0:b7116bd48af6	335	} CONTROL_Type;
mturner5	0:b7116bd48af6	336
mturner5	0:b7116bd48af6	337	/* CONTROL Register Definitions */
mturner5	0:b7116bd48af6	338	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
mturner5	0:b7116bd48af6	339	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
mturner5	0:b7116bd48af6	340
mturner5	0:b7116bd48af6	341	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
mturner5	0:b7116bd48af6	342	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
mturner5	0:b7116bd48af6	343
mturner5	0:b7116bd48af6	344	/@} end of group CMSIS_CORE /
mturner5	0:b7116bd48af6	345
mturner5	0:b7116bd48af6	346
mturner5	0:b7116bd48af6	347	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	348	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mturner5	0:b7116bd48af6	349	\brief Type definitions for the NVIC Registers
mturner5	0:b7116bd48af6	350	@{
mturner5	0:b7116bd48af6	351	*/
mturner5	0:b7116bd48af6	352
mturner5	0:b7116bd48af6	353	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mturner5	0:b7116bd48af6	354	*/
mturner5	0:b7116bd48af6	355	typedef struct
mturner5	0:b7116bd48af6	356	{
mturner5	0:b7116bd48af6	357	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
mturner5	0:b7116bd48af6	358	uint32_t RESERVED0[24];
mturner5	0:b7116bd48af6	359	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
mturner5	0:b7116bd48af6	360	uint32_t RSERVED1[24];
mturner5	0:b7116bd48af6	361	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
mturner5	0:b7116bd48af6	362	uint32_t RESERVED2[24];
mturner5	0:b7116bd48af6	363	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
mturner5	0:b7116bd48af6	364	uint32_t RESERVED3[24];
mturner5	0:b7116bd48af6	365	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
mturner5	0:b7116bd48af6	366	uint32_t RESERVED4[56];
mturner5	0:b7116bd48af6	367	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
mturner5	0:b7116bd48af6	368	uint32_t RESERVED5[644];
mturner5	0:b7116bd48af6	369	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
mturner5	0:b7116bd48af6	370	} NVIC_Type;
mturner5	0:b7116bd48af6	371
mturner5	0:b7116bd48af6	372	/* Software Triggered Interrupt Register Definitions */
mturner5	0:b7116bd48af6	373	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
mturner5	0:b7116bd48af6	374	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
mturner5	0:b7116bd48af6	375
mturner5	0:b7116bd48af6	376	/@} end of group CMSIS_NVIC /
mturner5	0:b7116bd48af6	377
mturner5	0:b7116bd48af6	378
mturner5	0:b7116bd48af6	379	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	380	\defgroup CMSIS_SCB System Control Block (SCB)
mturner5	0:b7116bd48af6	381	\brief Type definitions for the System Control Block Registers
mturner5	0:b7116bd48af6	382	@{
mturner5	0:b7116bd48af6	383	*/
mturner5	0:b7116bd48af6	384
mturner5	0:b7116bd48af6	385	/** \brief Structure type to access the System Control Block (SCB).
mturner5	0:b7116bd48af6	386	*/
mturner5	0:b7116bd48af6	387	typedef struct
mturner5	0:b7116bd48af6	388	{
mturner5	0:b7116bd48af6	389	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
mturner5	0:b7116bd48af6	390	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
mturner5	0:b7116bd48af6	391	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
mturner5	0:b7116bd48af6	392	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
mturner5	0:b7116bd48af6	393	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
mturner5	0:b7116bd48af6	394	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
mturner5	0:b7116bd48af6	395	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
mturner5	0:b7116bd48af6	396	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
mturner5	0:b7116bd48af6	397	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
mturner5	0:b7116bd48af6	398	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
mturner5	0:b7116bd48af6	399	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
mturner5	0:b7116bd48af6	400	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
mturner5	0:b7116bd48af6	401	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
mturner5	0:b7116bd48af6	402	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
mturner5	0:b7116bd48af6	403	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
mturner5	0:b7116bd48af6	404	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
mturner5	0:b7116bd48af6	405	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
mturner5	0:b7116bd48af6	406	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
mturner5	0:b7116bd48af6	407	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
mturner5	0:b7116bd48af6	408	uint32_t RESERVED0[5];
mturner5	0:b7116bd48af6	409	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
mturner5	0:b7116bd48af6	410	} SCB_Type;
mturner5	0:b7116bd48af6	411
mturner5	0:b7116bd48af6	412	/* SCB CPUID Register Definitions */
mturner5	0:b7116bd48af6	413	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
mturner5	0:b7116bd48af6	414	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
mturner5	0:b7116bd48af6	415
mturner5	0:b7116bd48af6	416	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
mturner5	0:b7116bd48af6	417	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
mturner5	0:b7116bd48af6	418
mturner5	0:b7116bd48af6	419	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
mturner5	0:b7116bd48af6	420	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
mturner5	0:b7116bd48af6	421
mturner5	0:b7116bd48af6	422	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
mturner5	0:b7116bd48af6	423	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
mturner5	0:b7116bd48af6	424
mturner5	0:b7116bd48af6	425	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
mturner5	0:b7116bd48af6	426	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
mturner5	0:b7116bd48af6	427
mturner5	0:b7116bd48af6	428	/* SCB Interrupt Control State Register Definitions */
mturner5	0:b7116bd48af6	429	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
mturner5	0:b7116bd48af6	430	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
mturner5	0:b7116bd48af6	431
mturner5	0:b7116bd48af6	432	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
mturner5	0:b7116bd48af6	433	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
mturner5	0:b7116bd48af6	434
mturner5	0:b7116bd48af6	435	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
mturner5	0:b7116bd48af6	436	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
mturner5	0:b7116bd48af6	437
mturner5	0:b7116bd48af6	438	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
mturner5	0:b7116bd48af6	439	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
mturner5	0:b7116bd48af6	440
mturner5	0:b7116bd48af6	441	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
mturner5	0:b7116bd48af6	442	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
mturner5	0:b7116bd48af6	443
mturner5	0:b7116bd48af6	444	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
mturner5	0:b7116bd48af6	445	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
mturner5	0:b7116bd48af6	446
mturner5	0:b7116bd48af6	447	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
mturner5	0:b7116bd48af6	448	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
mturner5	0:b7116bd48af6	449
mturner5	0:b7116bd48af6	450	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
mturner5	0:b7116bd48af6	451	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
mturner5	0:b7116bd48af6	452
mturner5	0:b7116bd48af6	453	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
mturner5	0:b7116bd48af6	454	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
mturner5	0:b7116bd48af6	455
mturner5	0:b7116bd48af6	456	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
mturner5	0:b7116bd48af6	457	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
mturner5	0:b7116bd48af6	458
mturner5	0:b7116bd48af6	459	/* SCB Vector Table Offset Register Definitions */
mturner5	0:b7116bd48af6	460	#if (__CM3_REV < 0x0201) /* core r2p1 */
mturner5	0:b7116bd48af6	461	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
mturner5	0:b7116bd48af6	462	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
mturner5	0:b7116bd48af6	463
mturner5	0:b7116bd48af6	464	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
mturner5	0:b7116bd48af6	465	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mturner5	0:b7116bd48af6	466	#else
mturner5	0:b7116bd48af6	467	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
mturner5	0:b7116bd48af6	468	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mturner5	0:b7116bd48af6	469	#endif
mturner5	0:b7116bd48af6	470
mturner5	0:b7116bd48af6	471	/* SCB Application Interrupt and Reset Control Register Definitions */
mturner5	0:b7116bd48af6	472	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
mturner5	0:b7116bd48af6	473	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
mturner5	0:b7116bd48af6	474
mturner5	0:b7116bd48af6	475	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
mturner5	0:b7116bd48af6	476	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
mturner5	0:b7116bd48af6	477
mturner5	0:b7116bd48af6	478	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
mturner5	0:b7116bd48af6	479	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
mturner5	0:b7116bd48af6	480
mturner5	0:b7116bd48af6	481	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
mturner5	0:b7116bd48af6	482	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
mturner5	0:b7116bd48af6	483
mturner5	0:b7116bd48af6	484	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
mturner5	0:b7116bd48af6	485	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
mturner5	0:b7116bd48af6	486
mturner5	0:b7116bd48af6	487	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
mturner5	0:b7116bd48af6	488	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
mturner5	0:b7116bd48af6	489
mturner5	0:b7116bd48af6	490	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
mturner5	0:b7116bd48af6	491	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
mturner5	0:b7116bd48af6	492
mturner5	0:b7116bd48af6	493	/* SCB System Control Register Definitions */
mturner5	0:b7116bd48af6	494	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
mturner5	0:b7116bd48af6	495	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
mturner5	0:b7116bd48af6	496
mturner5	0:b7116bd48af6	497	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
mturner5	0:b7116bd48af6	498	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
mturner5	0:b7116bd48af6	499
mturner5	0:b7116bd48af6	500	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
mturner5	0:b7116bd48af6	501	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
mturner5	0:b7116bd48af6	502
mturner5	0:b7116bd48af6	503	/* SCB Configuration Control Register Definitions */
mturner5	0:b7116bd48af6	504	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
mturner5	0:b7116bd48af6	505	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
mturner5	0:b7116bd48af6	506
mturner5	0:b7116bd48af6	507	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
mturner5	0:b7116bd48af6	508	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
mturner5	0:b7116bd48af6	509
mturner5	0:b7116bd48af6	510	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
mturner5	0:b7116bd48af6	511	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
mturner5	0:b7116bd48af6	512
mturner5	0:b7116bd48af6	513	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
mturner5	0:b7116bd48af6	514	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
mturner5	0:b7116bd48af6	515
mturner5	0:b7116bd48af6	516	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
mturner5	0:b7116bd48af6	517	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
mturner5	0:b7116bd48af6	518
mturner5	0:b7116bd48af6	519	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
mturner5	0:b7116bd48af6	520	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
mturner5	0:b7116bd48af6	521
mturner5	0:b7116bd48af6	522	/* SCB System Handler Control and State Register Definitions */
mturner5	0:b7116bd48af6	523	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
mturner5	0:b7116bd48af6	524	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
mturner5	0:b7116bd48af6	525
mturner5	0:b7116bd48af6	526	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
mturner5	0:b7116bd48af6	527	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
mturner5	0:b7116bd48af6	528
mturner5	0:b7116bd48af6	529	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
mturner5	0:b7116bd48af6	530	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
mturner5	0:b7116bd48af6	531
mturner5	0:b7116bd48af6	532	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
mturner5	0:b7116bd48af6	533	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
mturner5	0:b7116bd48af6	534
mturner5	0:b7116bd48af6	535	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
mturner5	0:b7116bd48af6	536	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
mturner5	0:b7116bd48af6	537
mturner5	0:b7116bd48af6	538	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
mturner5	0:b7116bd48af6	539	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
mturner5	0:b7116bd48af6	540
mturner5	0:b7116bd48af6	541	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
mturner5	0:b7116bd48af6	542	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
mturner5	0:b7116bd48af6	543
mturner5	0:b7116bd48af6	544	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
mturner5	0:b7116bd48af6	545	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
mturner5	0:b7116bd48af6	546
mturner5	0:b7116bd48af6	547	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
mturner5	0:b7116bd48af6	548	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
mturner5	0:b7116bd48af6	549
mturner5	0:b7116bd48af6	550	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
mturner5	0:b7116bd48af6	551	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
mturner5	0:b7116bd48af6	552
mturner5	0:b7116bd48af6	553	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
mturner5	0:b7116bd48af6	554	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
mturner5	0:b7116bd48af6	555
mturner5	0:b7116bd48af6	556	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
mturner5	0:b7116bd48af6	557	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
mturner5	0:b7116bd48af6	558
mturner5	0:b7116bd48af6	559	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
mturner5	0:b7116bd48af6	560	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
mturner5	0:b7116bd48af6	561
mturner5	0:b7116bd48af6	562	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
mturner5	0:b7116bd48af6	563	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
mturner5	0:b7116bd48af6	564
mturner5	0:b7116bd48af6	565	/* SCB Configurable Fault Status Registers Definitions */
mturner5	0:b7116bd48af6	566	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
mturner5	0:b7116bd48af6	567	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
mturner5	0:b7116bd48af6	568
mturner5	0:b7116bd48af6	569	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
mturner5	0:b7116bd48af6	570	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
mturner5	0:b7116bd48af6	571
mturner5	0:b7116bd48af6	572	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
mturner5	0:b7116bd48af6	573	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
mturner5	0:b7116bd48af6	574
mturner5	0:b7116bd48af6	575	/* SCB Hard Fault Status Registers Definitions */
mturner5	0:b7116bd48af6	576	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
mturner5	0:b7116bd48af6	577	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
mturner5	0:b7116bd48af6	578
mturner5	0:b7116bd48af6	579	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
mturner5	0:b7116bd48af6	580	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
mturner5	0:b7116bd48af6	581
mturner5	0:b7116bd48af6	582	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
mturner5	0:b7116bd48af6	583	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
mturner5	0:b7116bd48af6	584
mturner5	0:b7116bd48af6	585	/* SCB Debug Fault Status Register Definitions */
mturner5	0:b7116bd48af6	586	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
mturner5	0:b7116bd48af6	587	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
mturner5	0:b7116bd48af6	588
mturner5	0:b7116bd48af6	589	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
mturner5	0:b7116bd48af6	590	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
mturner5	0:b7116bd48af6	591
mturner5	0:b7116bd48af6	592	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
mturner5	0:b7116bd48af6	593	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
mturner5	0:b7116bd48af6	594
mturner5	0:b7116bd48af6	595	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
mturner5	0:b7116bd48af6	596	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
mturner5	0:b7116bd48af6	597
mturner5	0:b7116bd48af6	598	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
mturner5	0:b7116bd48af6	599	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
mturner5	0:b7116bd48af6	600
mturner5	0:b7116bd48af6	601	/@} end of group CMSIS_SCB /
mturner5	0:b7116bd48af6	602
mturner5	0:b7116bd48af6	603
mturner5	0:b7116bd48af6	604	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	605	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mturner5	0:b7116bd48af6	606	\brief Type definitions for the System Control and ID Register not in the SCB
mturner5	0:b7116bd48af6	607	@{
mturner5	0:b7116bd48af6	608	*/
mturner5	0:b7116bd48af6	609
mturner5	0:b7116bd48af6	610	/** \brief Structure type to access the System Control and ID Register not in the SCB.
mturner5	0:b7116bd48af6	611	*/
mturner5	0:b7116bd48af6	612	typedef struct
mturner5	0:b7116bd48af6	613	{
mturner5	0:b7116bd48af6	614	uint32_t RESERVED0[1];
mturner5	0:b7116bd48af6	615	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
mturner5	0:b7116bd48af6	616	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
mturner5	0:b7116bd48af6	617	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
mturner5	0:b7116bd48af6	618	#else
mturner5	0:b7116bd48af6	619	uint32_t RESERVED1[1];
mturner5	0:b7116bd48af6	620	#endif
mturner5	0:b7116bd48af6	621	} SCnSCB_Type;
mturner5	0:b7116bd48af6	622
mturner5	0:b7116bd48af6	623	/* Interrupt Controller Type Register Definitions */
mturner5	0:b7116bd48af6	624	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
mturner5	0:b7116bd48af6	625	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
mturner5	0:b7116bd48af6	626
mturner5	0:b7116bd48af6	627	/* Auxiliary Control Register Definitions */
mturner5	0:b7116bd48af6	628
mturner5	0:b7116bd48af6	629	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
mturner5	0:b7116bd48af6	630	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
mturner5	0:b7116bd48af6	631
mturner5	0:b7116bd48af6	632	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
mturner5	0:b7116bd48af6	633	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
mturner5	0:b7116bd48af6	634
mturner5	0:b7116bd48af6	635	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
mturner5	0:b7116bd48af6	636	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
mturner5	0:b7116bd48af6	637
mturner5	0:b7116bd48af6	638	/@} end of group CMSIS_SCnotSCB /
mturner5	0:b7116bd48af6	639
mturner5	0:b7116bd48af6	640
mturner5	0:b7116bd48af6	641	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	642	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
mturner5	0:b7116bd48af6	643	\brief Type definitions for the System Timer Registers.
mturner5	0:b7116bd48af6	644	@{
mturner5	0:b7116bd48af6	645	*/
mturner5	0:b7116bd48af6	646
mturner5	0:b7116bd48af6	647	/** \brief Structure type to access the System Timer (SysTick).
mturner5	0:b7116bd48af6	648	*/
mturner5	0:b7116bd48af6	649	typedef struct
mturner5	0:b7116bd48af6	650	{
mturner5	0:b7116bd48af6	651	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
mturner5	0:b7116bd48af6	652	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
mturner5	0:b7116bd48af6	653	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
mturner5	0:b7116bd48af6	654	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
mturner5	0:b7116bd48af6	655	} SysTick_Type;
mturner5	0:b7116bd48af6	656
mturner5	0:b7116bd48af6	657	/* SysTick Control / Status Register Definitions */
mturner5	0:b7116bd48af6	658	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
mturner5	0:b7116bd48af6	659	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
mturner5	0:b7116bd48af6	660
mturner5	0:b7116bd48af6	661	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
mturner5	0:b7116bd48af6	662	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
mturner5	0:b7116bd48af6	663
mturner5	0:b7116bd48af6	664	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
mturner5	0:b7116bd48af6	665	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
mturner5	0:b7116bd48af6	666
mturner5	0:b7116bd48af6	667	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
mturner5	0:b7116bd48af6	668	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
mturner5	0:b7116bd48af6	669
mturner5	0:b7116bd48af6	670	/* SysTick Reload Register Definitions */
mturner5	0:b7116bd48af6	671	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
mturner5	0:b7116bd48af6	672	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
mturner5	0:b7116bd48af6	673
mturner5	0:b7116bd48af6	674	/* SysTick Current Register Definitions */
mturner5	0:b7116bd48af6	675	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
mturner5	0:b7116bd48af6	676	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
mturner5	0:b7116bd48af6	677
mturner5	0:b7116bd48af6	678	/* SysTick Calibration Register Definitions */
mturner5	0:b7116bd48af6	679	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
mturner5	0:b7116bd48af6	680	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
mturner5	0:b7116bd48af6	681
mturner5	0:b7116bd48af6	682	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
mturner5	0:b7116bd48af6	683	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
mturner5	0:b7116bd48af6	684
mturner5	0:b7116bd48af6	685	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
mturner5	0:b7116bd48af6	686	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
mturner5	0:b7116bd48af6	687
mturner5	0:b7116bd48af6	688	/@} end of group CMSIS_SysTick /
mturner5	0:b7116bd48af6	689
mturner5	0:b7116bd48af6	690
mturner5	0:b7116bd48af6	691	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	692	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mturner5	0:b7116bd48af6	693	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mturner5	0:b7116bd48af6	694	@{
mturner5	0:b7116bd48af6	695	*/
mturner5	0:b7116bd48af6	696
mturner5	0:b7116bd48af6	697	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mturner5	0:b7116bd48af6	698	*/
mturner5	0:b7116bd48af6	699	typedef struct
mturner5	0:b7116bd48af6	700	{
mturner5	0:b7116bd48af6	701	__O union
mturner5	0:b7116bd48af6	702	{
mturner5	0:b7116bd48af6	703	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
mturner5	0:b7116bd48af6	704	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
mturner5	0:b7116bd48af6	705	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
mturner5	0:b7116bd48af6	706	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
mturner5	0:b7116bd48af6	707	uint32_t RESERVED0[864];
mturner5	0:b7116bd48af6	708	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
mturner5	0:b7116bd48af6	709	uint32_t RESERVED1[15];
mturner5	0:b7116bd48af6	710	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
mturner5	0:b7116bd48af6	711	uint32_t RESERVED2[15];
mturner5	0:b7116bd48af6	712	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
mturner5	0:b7116bd48af6	713	uint32_t RESERVED3[29];
mturner5	0:b7116bd48af6	714	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
mturner5	0:b7116bd48af6	715	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
mturner5	0:b7116bd48af6	716	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
mturner5	0:b7116bd48af6	717	uint32_t RESERVED4[43];
mturner5	0:b7116bd48af6	718	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
mturner5	0:b7116bd48af6	719	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
mturner5	0:b7116bd48af6	720	uint32_t RESERVED5[6];
mturner5	0:b7116bd48af6	721	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
mturner5	0:b7116bd48af6	722	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
mturner5	0:b7116bd48af6	723	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
mturner5	0:b7116bd48af6	724	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
mturner5	0:b7116bd48af6	725	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
mturner5	0:b7116bd48af6	726	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
mturner5	0:b7116bd48af6	727	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
mturner5	0:b7116bd48af6	728	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
mturner5	0:b7116bd48af6	729	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
mturner5	0:b7116bd48af6	730	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
mturner5	0:b7116bd48af6	731	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
mturner5	0:b7116bd48af6	732	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
mturner5	0:b7116bd48af6	733	} ITM_Type;
mturner5	0:b7116bd48af6	734
mturner5	0:b7116bd48af6	735	/* ITM Trace Privilege Register Definitions */
mturner5	0:b7116bd48af6	736	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
mturner5	0:b7116bd48af6	737	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
mturner5	0:b7116bd48af6	738
mturner5	0:b7116bd48af6	739	/* ITM Trace Control Register Definitions */
mturner5	0:b7116bd48af6	740	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
mturner5	0:b7116bd48af6	741	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
mturner5	0:b7116bd48af6	742
mturner5	0:b7116bd48af6	743	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
mturner5	0:b7116bd48af6	744	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
mturner5	0:b7116bd48af6	745
mturner5	0:b7116bd48af6	746	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
mturner5	0:b7116bd48af6	747	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
mturner5	0:b7116bd48af6	748
mturner5	0:b7116bd48af6	749	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
mturner5	0:b7116bd48af6	750	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
mturner5	0:b7116bd48af6	751
mturner5	0:b7116bd48af6	752	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
mturner5	0:b7116bd48af6	753	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
mturner5	0:b7116bd48af6	754
mturner5	0:b7116bd48af6	755	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
mturner5	0:b7116bd48af6	756	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
mturner5	0:b7116bd48af6	757
mturner5	0:b7116bd48af6	758	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
mturner5	0:b7116bd48af6	759	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
mturner5	0:b7116bd48af6	760
mturner5	0:b7116bd48af6	761	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
mturner5	0:b7116bd48af6	762	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
mturner5	0:b7116bd48af6	763
mturner5	0:b7116bd48af6	764	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
mturner5	0:b7116bd48af6	765	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
mturner5	0:b7116bd48af6	766
mturner5	0:b7116bd48af6	767	/* ITM Integration Write Register Definitions */
mturner5	0:b7116bd48af6	768	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
mturner5	0:b7116bd48af6	769	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
mturner5	0:b7116bd48af6	770
mturner5	0:b7116bd48af6	771	/* ITM Integration Read Register Definitions */
mturner5	0:b7116bd48af6	772	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
mturner5	0:b7116bd48af6	773	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
mturner5	0:b7116bd48af6	774
mturner5	0:b7116bd48af6	775	/* ITM Integration Mode Control Register Definitions */
mturner5	0:b7116bd48af6	776	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
mturner5	0:b7116bd48af6	777	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
mturner5	0:b7116bd48af6	778
mturner5	0:b7116bd48af6	779	/* ITM Lock Status Register Definitions */
mturner5	0:b7116bd48af6	780	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
mturner5	0:b7116bd48af6	781	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
mturner5	0:b7116bd48af6	782
mturner5	0:b7116bd48af6	783	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
mturner5	0:b7116bd48af6	784	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
mturner5	0:b7116bd48af6	785
mturner5	0:b7116bd48af6	786	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
mturner5	0:b7116bd48af6	787	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
mturner5	0:b7116bd48af6	788
mturner5	0:b7116bd48af6	789	/@}/ /* end of group CMSIS_ITM */
mturner5	0:b7116bd48af6	790
mturner5	0:b7116bd48af6	791
mturner5	0:b7116bd48af6	792	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	793	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mturner5	0:b7116bd48af6	794	\brief Type definitions for the Data Watchpoint and Trace (DWT)
mturner5	0:b7116bd48af6	795	@{
mturner5	0:b7116bd48af6	796	*/
mturner5	0:b7116bd48af6	797
mturner5	0:b7116bd48af6	798	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mturner5	0:b7116bd48af6	799	*/
mturner5	0:b7116bd48af6	800	typedef struct
mturner5	0:b7116bd48af6	801	{
mturner5	0:b7116bd48af6	802	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
mturner5	0:b7116bd48af6	803	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
mturner5	0:b7116bd48af6	804	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
mturner5	0:b7116bd48af6	805	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
mturner5	0:b7116bd48af6	806	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
mturner5	0:b7116bd48af6	807	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
mturner5	0:b7116bd48af6	808	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
mturner5	0:b7116bd48af6	809	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
mturner5	0:b7116bd48af6	810	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
mturner5	0:b7116bd48af6	811	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
mturner5	0:b7116bd48af6	812	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
mturner5	0:b7116bd48af6	813	uint32_t RESERVED0[1];
mturner5	0:b7116bd48af6	814	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
mturner5	0:b7116bd48af6	815	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
mturner5	0:b7116bd48af6	816	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
mturner5	0:b7116bd48af6	817	uint32_t RESERVED1[1];
mturner5	0:b7116bd48af6	818	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
mturner5	0:b7116bd48af6	819	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
mturner5	0:b7116bd48af6	820	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
mturner5	0:b7116bd48af6	821	uint32_t RESERVED2[1];
mturner5	0:b7116bd48af6	822	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
mturner5	0:b7116bd48af6	823	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
mturner5	0:b7116bd48af6	824	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
mturner5	0:b7116bd48af6	825	} DWT_Type;
mturner5	0:b7116bd48af6	826
mturner5	0:b7116bd48af6	827	/* DWT Control Register Definitions */
mturner5	0:b7116bd48af6	828	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
mturner5	0:b7116bd48af6	829	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
mturner5	0:b7116bd48af6	830
mturner5	0:b7116bd48af6	831	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
mturner5	0:b7116bd48af6	832	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
mturner5	0:b7116bd48af6	833
mturner5	0:b7116bd48af6	834	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
mturner5	0:b7116bd48af6	835	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
mturner5	0:b7116bd48af6	836
mturner5	0:b7116bd48af6	837	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
mturner5	0:b7116bd48af6	838	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
mturner5	0:b7116bd48af6	839
mturner5	0:b7116bd48af6	840	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
mturner5	0:b7116bd48af6	841	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
mturner5	0:b7116bd48af6	842
mturner5	0:b7116bd48af6	843	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
mturner5	0:b7116bd48af6	844	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
mturner5	0:b7116bd48af6	845
mturner5	0:b7116bd48af6	846	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
mturner5	0:b7116bd48af6	847	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
mturner5	0:b7116bd48af6	848
mturner5	0:b7116bd48af6	849	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
mturner5	0:b7116bd48af6	850	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
mturner5	0:b7116bd48af6	851
mturner5	0:b7116bd48af6	852	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
mturner5	0:b7116bd48af6	853	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
mturner5	0:b7116bd48af6	854
mturner5	0:b7116bd48af6	855	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
mturner5	0:b7116bd48af6	856	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
mturner5	0:b7116bd48af6	857
mturner5	0:b7116bd48af6	858	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
mturner5	0:b7116bd48af6	859	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
mturner5	0:b7116bd48af6	860
mturner5	0:b7116bd48af6	861	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
mturner5	0:b7116bd48af6	862	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
mturner5	0:b7116bd48af6	863
mturner5	0:b7116bd48af6	864	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
mturner5	0:b7116bd48af6	865	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
mturner5	0:b7116bd48af6	866
mturner5	0:b7116bd48af6	867	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
mturner5	0:b7116bd48af6	868	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
mturner5	0:b7116bd48af6	869
mturner5	0:b7116bd48af6	870	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
mturner5	0:b7116bd48af6	871	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
mturner5	0:b7116bd48af6	872
mturner5	0:b7116bd48af6	873	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
mturner5	0:b7116bd48af6	874	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
mturner5	0:b7116bd48af6	875
mturner5	0:b7116bd48af6	876	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
mturner5	0:b7116bd48af6	877	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
mturner5	0:b7116bd48af6	878
mturner5	0:b7116bd48af6	879	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
mturner5	0:b7116bd48af6	880	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
mturner5	0:b7116bd48af6	881
mturner5	0:b7116bd48af6	882	/* DWT CPI Count Register Definitions */
mturner5	0:b7116bd48af6	883	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
mturner5	0:b7116bd48af6	884	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
mturner5	0:b7116bd48af6	885
mturner5	0:b7116bd48af6	886	/* DWT Exception Overhead Count Register Definitions */
mturner5	0:b7116bd48af6	887	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
mturner5	0:b7116bd48af6	888	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
mturner5	0:b7116bd48af6	889
mturner5	0:b7116bd48af6	890	/* DWT Sleep Count Register Definitions */
mturner5	0:b7116bd48af6	891	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
mturner5	0:b7116bd48af6	892	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
mturner5	0:b7116bd48af6	893
mturner5	0:b7116bd48af6	894	/* DWT LSU Count Register Definitions */
mturner5	0:b7116bd48af6	895	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
mturner5	0:b7116bd48af6	896	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
mturner5	0:b7116bd48af6	897
mturner5	0:b7116bd48af6	898	/* DWT Folded-instruction Count Register Definitions */
mturner5	0:b7116bd48af6	899	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
mturner5	0:b7116bd48af6	900	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
mturner5	0:b7116bd48af6	901
mturner5	0:b7116bd48af6	902	/* DWT Comparator Mask Register Definitions */
mturner5	0:b7116bd48af6	903	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
mturner5	0:b7116bd48af6	904	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
mturner5	0:b7116bd48af6	905
mturner5	0:b7116bd48af6	906	/* DWT Comparator Function Register Definitions */
mturner5	0:b7116bd48af6	907	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
mturner5	0:b7116bd48af6	908	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
mturner5	0:b7116bd48af6	909
mturner5	0:b7116bd48af6	910	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
mturner5	0:b7116bd48af6	911	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
mturner5	0:b7116bd48af6	912
mturner5	0:b7116bd48af6	913	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
mturner5	0:b7116bd48af6	914	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
mturner5	0:b7116bd48af6	915
mturner5	0:b7116bd48af6	916	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
mturner5	0:b7116bd48af6	917	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
mturner5	0:b7116bd48af6	918
mturner5	0:b7116bd48af6	919	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
mturner5	0:b7116bd48af6	920	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
mturner5	0:b7116bd48af6	921
mturner5	0:b7116bd48af6	922	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
mturner5	0:b7116bd48af6	923	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
mturner5	0:b7116bd48af6	924
mturner5	0:b7116bd48af6	925	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
mturner5	0:b7116bd48af6	926	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
mturner5	0:b7116bd48af6	927
mturner5	0:b7116bd48af6	928	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
mturner5	0:b7116bd48af6	929	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
mturner5	0:b7116bd48af6	930
mturner5	0:b7116bd48af6	931	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
mturner5	0:b7116bd48af6	932	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
mturner5	0:b7116bd48af6	933
mturner5	0:b7116bd48af6	934	/@}/ /* end of group CMSIS_DWT */
mturner5	0:b7116bd48af6	935
mturner5	0:b7116bd48af6	936
mturner5	0:b7116bd48af6	937	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	938	\defgroup CMSIS_TPI Trace Port Interface (TPI)
mturner5	0:b7116bd48af6	939	\brief Type definitions for the Trace Port Interface (TPI)
mturner5	0:b7116bd48af6	940	@{
mturner5	0:b7116bd48af6	941	*/
mturner5	0:b7116bd48af6	942
mturner5	0:b7116bd48af6	943	/** \brief Structure type to access the Trace Port Interface Register (TPI).
mturner5	0:b7116bd48af6	944	*/
mturner5	0:b7116bd48af6	945	typedef struct
mturner5	0:b7116bd48af6	946	{
mturner5	0:b7116bd48af6	947	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
mturner5	0:b7116bd48af6	948	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
mturner5	0:b7116bd48af6	949	uint32_t RESERVED0[2];
mturner5	0:b7116bd48af6	950	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
mturner5	0:b7116bd48af6	951	uint32_t RESERVED1[55];
mturner5	0:b7116bd48af6	952	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
mturner5	0:b7116bd48af6	953	uint32_t RESERVED2[131];
mturner5	0:b7116bd48af6	954	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
mturner5	0:b7116bd48af6	955	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
mturner5	0:b7116bd48af6	956	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
mturner5	0:b7116bd48af6	957	uint32_t RESERVED3[759];
mturner5	0:b7116bd48af6	958	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
mturner5	0:b7116bd48af6	959	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
mturner5	0:b7116bd48af6	960	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
mturner5	0:b7116bd48af6	961	uint32_t RESERVED4[1];
mturner5	0:b7116bd48af6	962	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
mturner5	0:b7116bd48af6	963	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
mturner5	0:b7116bd48af6	964	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
mturner5	0:b7116bd48af6	965	uint32_t RESERVED5[39];
mturner5	0:b7116bd48af6	966	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
mturner5	0:b7116bd48af6	967	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
mturner5	0:b7116bd48af6	968	uint32_t RESERVED7[8];
mturner5	0:b7116bd48af6	969	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
mturner5	0:b7116bd48af6	970	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
mturner5	0:b7116bd48af6	971	} TPI_Type;
mturner5	0:b7116bd48af6	972
mturner5	0:b7116bd48af6	973	/* TPI Asynchronous Clock Prescaler Register Definitions */
mturner5	0:b7116bd48af6	974	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
mturner5	0:b7116bd48af6	975	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
mturner5	0:b7116bd48af6	976
mturner5	0:b7116bd48af6	977	/* TPI Selected Pin Protocol Register Definitions */
mturner5	0:b7116bd48af6	978	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
mturner5	0:b7116bd48af6	979	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
mturner5	0:b7116bd48af6	980
mturner5	0:b7116bd48af6	981	/* TPI Formatter and Flush Status Register Definitions */
mturner5	0:b7116bd48af6	982	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
mturner5	0:b7116bd48af6	983	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
mturner5	0:b7116bd48af6	984
mturner5	0:b7116bd48af6	985	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
mturner5	0:b7116bd48af6	986	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
mturner5	0:b7116bd48af6	987
mturner5	0:b7116bd48af6	988	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
mturner5	0:b7116bd48af6	989	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
mturner5	0:b7116bd48af6	990
mturner5	0:b7116bd48af6	991	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
mturner5	0:b7116bd48af6	992	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
mturner5	0:b7116bd48af6	993
mturner5	0:b7116bd48af6	994	/* TPI Formatter and Flush Control Register Definitions */
mturner5	0:b7116bd48af6	995	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
mturner5	0:b7116bd48af6	996	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
mturner5	0:b7116bd48af6	997
mturner5	0:b7116bd48af6	998	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
mturner5	0:b7116bd48af6	999	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
mturner5	0:b7116bd48af6	1000
mturner5	0:b7116bd48af6	1001	/* TPI TRIGGER Register Definitions */
mturner5	0:b7116bd48af6	1002	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
mturner5	0:b7116bd48af6	1003	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
mturner5	0:b7116bd48af6	1004
mturner5	0:b7116bd48af6	1005	/* TPI Integration ETM Data Register Definitions (FIFO0) */
mturner5	0:b7116bd48af6	1006	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
mturner5	0:b7116bd48af6	1007	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
mturner5	0:b7116bd48af6	1008
mturner5	0:b7116bd48af6	1009	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
mturner5	0:b7116bd48af6	1010	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
mturner5	0:b7116bd48af6	1011
mturner5	0:b7116bd48af6	1012	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
mturner5	0:b7116bd48af6	1013	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
mturner5	0:b7116bd48af6	1014
mturner5	0:b7116bd48af6	1015	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
mturner5	0:b7116bd48af6	1016	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
mturner5	0:b7116bd48af6	1017
mturner5	0:b7116bd48af6	1018	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
mturner5	0:b7116bd48af6	1019	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
mturner5	0:b7116bd48af6	1020
mturner5	0:b7116bd48af6	1021	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
mturner5	0:b7116bd48af6	1022	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
mturner5	0:b7116bd48af6	1023
mturner5	0:b7116bd48af6	1024	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
mturner5	0:b7116bd48af6	1025	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
mturner5	0:b7116bd48af6	1026
mturner5	0:b7116bd48af6	1027	/* TPI ITATBCTR2 Register Definitions */
mturner5	0:b7116bd48af6	1028	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
mturner5	0:b7116bd48af6	1029	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
mturner5	0:b7116bd48af6	1030
mturner5	0:b7116bd48af6	1031	/* TPI Integration ITM Data Register Definitions (FIFO1) */
mturner5	0:b7116bd48af6	1032	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
mturner5	0:b7116bd48af6	1033	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
mturner5	0:b7116bd48af6	1034
mturner5	0:b7116bd48af6	1035	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
mturner5	0:b7116bd48af6	1036	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
mturner5	0:b7116bd48af6	1037
mturner5	0:b7116bd48af6	1038	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
mturner5	0:b7116bd48af6	1039	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
mturner5	0:b7116bd48af6	1040
mturner5	0:b7116bd48af6	1041	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
mturner5	0:b7116bd48af6	1042	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
mturner5	0:b7116bd48af6	1043
mturner5	0:b7116bd48af6	1044	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
mturner5	0:b7116bd48af6	1045	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
mturner5	0:b7116bd48af6	1046
mturner5	0:b7116bd48af6	1047	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
mturner5	0:b7116bd48af6	1048	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
mturner5	0:b7116bd48af6	1049
mturner5	0:b7116bd48af6	1050	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
mturner5	0:b7116bd48af6	1051	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
mturner5	0:b7116bd48af6	1052
mturner5	0:b7116bd48af6	1053	/* TPI ITATBCTR0 Register Definitions */
mturner5	0:b7116bd48af6	1054	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
mturner5	0:b7116bd48af6	1055	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
mturner5	0:b7116bd48af6	1056
mturner5	0:b7116bd48af6	1057	/* TPI Integration Mode Control Register Definitions */
mturner5	0:b7116bd48af6	1058	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
mturner5	0:b7116bd48af6	1059	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
mturner5	0:b7116bd48af6	1060
mturner5	0:b7116bd48af6	1061	/* TPI DEVID Register Definitions */
mturner5	0:b7116bd48af6	1062	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
mturner5	0:b7116bd48af6	1063	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
mturner5	0:b7116bd48af6	1064
mturner5	0:b7116bd48af6	1065	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
mturner5	0:b7116bd48af6	1066	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
mturner5	0:b7116bd48af6	1067
mturner5	0:b7116bd48af6	1068	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
mturner5	0:b7116bd48af6	1069	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
mturner5	0:b7116bd48af6	1070
mturner5	0:b7116bd48af6	1071	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
mturner5	0:b7116bd48af6	1072	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
mturner5	0:b7116bd48af6	1073
mturner5	0:b7116bd48af6	1074	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
mturner5	0:b7116bd48af6	1075	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
mturner5	0:b7116bd48af6	1076
mturner5	0:b7116bd48af6	1077	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
mturner5	0:b7116bd48af6	1078	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
mturner5	0:b7116bd48af6	1079
mturner5	0:b7116bd48af6	1080	/* TPI DEVTYPE Register Definitions */
mturner5	0:b7116bd48af6	1081	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
mturner5	0:b7116bd48af6	1082	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
mturner5	0:b7116bd48af6	1083
mturner5	0:b7116bd48af6	1084	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
mturner5	0:b7116bd48af6	1085	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
mturner5	0:b7116bd48af6	1086
mturner5	0:b7116bd48af6	1087	/@}/ /* end of group CMSIS_TPI */
mturner5	0:b7116bd48af6	1088
mturner5	0:b7116bd48af6	1089
mturner5	0:b7116bd48af6	1090	#if (__MPU_PRESENT == 1)
mturner5	0:b7116bd48af6	1091	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	1092	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
mturner5	0:b7116bd48af6	1093	\brief Type definitions for the Memory Protection Unit (MPU)
mturner5	0:b7116bd48af6	1094	@{
mturner5	0:b7116bd48af6	1095	*/
mturner5	0:b7116bd48af6	1096
mturner5	0:b7116bd48af6	1097	/** \brief Structure type to access the Memory Protection Unit (MPU).
mturner5	0:b7116bd48af6	1098	*/
mturner5	0:b7116bd48af6	1099	typedef struct
mturner5	0:b7116bd48af6	1100	{
mturner5	0:b7116bd48af6	1101	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
mturner5	0:b7116bd48af6	1102	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
mturner5	0:b7116bd48af6	1103	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
mturner5	0:b7116bd48af6	1104	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
mturner5	0:b7116bd48af6	1105	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
mturner5	0:b7116bd48af6	1106	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
mturner5	0:b7116bd48af6	1107	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
mturner5	0:b7116bd48af6	1108	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
mturner5	0:b7116bd48af6	1109	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
mturner5	0:b7116bd48af6	1110	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
mturner5	0:b7116bd48af6	1111	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
mturner5	0:b7116bd48af6	1112	} MPU_Type;
mturner5	0:b7116bd48af6	1113
mturner5	0:b7116bd48af6	1114	/* MPU Type Register */
mturner5	0:b7116bd48af6	1115	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
mturner5	0:b7116bd48af6	1116	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
mturner5	0:b7116bd48af6	1117
mturner5	0:b7116bd48af6	1118	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
mturner5	0:b7116bd48af6	1119	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
mturner5	0:b7116bd48af6	1120
mturner5	0:b7116bd48af6	1121	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
mturner5	0:b7116bd48af6	1122	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
mturner5	0:b7116bd48af6	1123
mturner5	0:b7116bd48af6	1124	/* MPU Control Register */
mturner5	0:b7116bd48af6	1125	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
mturner5	0:b7116bd48af6	1126	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
mturner5	0:b7116bd48af6	1127
mturner5	0:b7116bd48af6	1128	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
mturner5	0:b7116bd48af6	1129	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
mturner5	0:b7116bd48af6	1130
mturner5	0:b7116bd48af6	1131	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
mturner5	0:b7116bd48af6	1132	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
mturner5	0:b7116bd48af6	1133
mturner5	0:b7116bd48af6	1134	/* MPU Region Number Register */
mturner5	0:b7116bd48af6	1135	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
mturner5	0:b7116bd48af6	1136	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
mturner5	0:b7116bd48af6	1137
mturner5	0:b7116bd48af6	1138	/* MPU Region Base Address Register */
mturner5	0:b7116bd48af6	1139	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
mturner5	0:b7116bd48af6	1140	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
mturner5	0:b7116bd48af6	1141
mturner5	0:b7116bd48af6	1142	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
mturner5	0:b7116bd48af6	1143	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
mturner5	0:b7116bd48af6	1144
mturner5	0:b7116bd48af6	1145	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
mturner5	0:b7116bd48af6	1146	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
mturner5	0:b7116bd48af6	1147
mturner5	0:b7116bd48af6	1148	/* MPU Region Attribute and Size Register */
mturner5	0:b7116bd48af6	1149	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
mturner5	0:b7116bd48af6	1150	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
mturner5	0:b7116bd48af6	1151
mturner5	0:b7116bd48af6	1152	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
mturner5	0:b7116bd48af6	1153	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
mturner5	0:b7116bd48af6	1154
mturner5	0:b7116bd48af6	1155	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
mturner5	0:b7116bd48af6	1156	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
mturner5	0:b7116bd48af6	1157
mturner5	0:b7116bd48af6	1158	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
mturner5	0:b7116bd48af6	1159	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
mturner5	0:b7116bd48af6	1160
mturner5	0:b7116bd48af6	1161	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
mturner5	0:b7116bd48af6	1162	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
mturner5	0:b7116bd48af6	1163
mturner5	0:b7116bd48af6	1164	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
mturner5	0:b7116bd48af6	1165	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
mturner5	0:b7116bd48af6	1166
mturner5	0:b7116bd48af6	1167	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
mturner5	0:b7116bd48af6	1168	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
mturner5	0:b7116bd48af6	1169
mturner5	0:b7116bd48af6	1170	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
mturner5	0:b7116bd48af6	1171	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
mturner5	0:b7116bd48af6	1172
mturner5	0:b7116bd48af6	1173	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
mturner5	0:b7116bd48af6	1174	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
mturner5	0:b7116bd48af6	1175
mturner5	0:b7116bd48af6	1176	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
mturner5	0:b7116bd48af6	1177	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
mturner5	0:b7116bd48af6	1178
mturner5	0:b7116bd48af6	1179	/@} end of group CMSIS_MPU /
mturner5	0:b7116bd48af6	1180	#endif
mturner5	0:b7116bd48af6	1181
mturner5	0:b7116bd48af6	1182
mturner5	0:b7116bd48af6	1183	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	1184	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mturner5	0:b7116bd48af6	1185	\brief Type definitions for the Core Debug Registers
mturner5	0:b7116bd48af6	1186	@{
mturner5	0:b7116bd48af6	1187	*/
mturner5	0:b7116bd48af6	1188
mturner5	0:b7116bd48af6	1189	/** \brief Structure type to access the Core Debug Register (CoreDebug).
mturner5	0:b7116bd48af6	1190	*/
mturner5	0:b7116bd48af6	1191	typedef struct
mturner5	0:b7116bd48af6	1192	{
mturner5	0:b7116bd48af6	1193	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
mturner5	0:b7116bd48af6	1194	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
mturner5	0:b7116bd48af6	1195	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
mturner5	0:b7116bd48af6	1196	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
mturner5	0:b7116bd48af6	1197	} CoreDebug_Type;
mturner5	0:b7116bd48af6	1198
mturner5	0:b7116bd48af6	1199	/* Debug Halting Control and Status Register */
mturner5	0:b7116bd48af6	1200	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
mturner5	0:b7116bd48af6	1201	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
mturner5	0:b7116bd48af6	1202
mturner5	0:b7116bd48af6	1203	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
mturner5	0:b7116bd48af6	1204	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
mturner5	0:b7116bd48af6	1205
mturner5	0:b7116bd48af6	1206	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
mturner5	0:b7116bd48af6	1207	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
mturner5	0:b7116bd48af6	1208
mturner5	0:b7116bd48af6	1209	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
mturner5	0:b7116bd48af6	1210	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
mturner5	0:b7116bd48af6	1211
mturner5	0:b7116bd48af6	1212	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
mturner5	0:b7116bd48af6	1213	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
mturner5	0:b7116bd48af6	1214
mturner5	0:b7116bd48af6	1215	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
mturner5	0:b7116bd48af6	1216	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
mturner5	0:b7116bd48af6	1217
mturner5	0:b7116bd48af6	1218	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
mturner5	0:b7116bd48af6	1219	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
mturner5	0:b7116bd48af6	1220
mturner5	0:b7116bd48af6	1221	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
mturner5	0:b7116bd48af6	1222	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
mturner5	0:b7116bd48af6	1223
mturner5	0:b7116bd48af6	1224	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
mturner5	0:b7116bd48af6	1225	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
mturner5	0:b7116bd48af6	1226
mturner5	0:b7116bd48af6	1227	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
mturner5	0:b7116bd48af6	1228	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
mturner5	0:b7116bd48af6	1229
mturner5	0:b7116bd48af6	1230	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
mturner5	0:b7116bd48af6	1231	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
mturner5	0:b7116bd48af6	1232
mturner5	0:b7116bd48af6	1233	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
mturner5	0:b7116bd48af6	1234	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
mturner5	0:b7116bd48af6	1235
mturner5	0:b7116bd48af6	1236	/* Debug Core Register Selector Register */
mturner5	0:b7116bd48af6	1237	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
mturner5	0:b7116bd48af6	1238	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
mturner5	0:b7116bd48af6	1239
mturner5	0:b7116bd48af6	1240	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
mturner5	0:b7116bd48af6	1241	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
mturner5	0:b7116bd48af6	1242
mturner5	0:b7116bd48af6	1243	/* Debug Exception and Monitor Control Register */
mturner5	0:b7116bd48af6	1244	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
mturner5	0:b7116bd48af6	1245	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
mturner5	0:b7116bd48af6	1246
mturner5	0:b7116bd48af6	1247	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
mturner5	0:b7116bd48af6	1248	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
mturner5	0:b7116bd48af6	1249
mturner5	0:b7116bd48af6	1250	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
mturner5	0:b7116bd48af6	1251	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
mturner5	0:b7116bd48af6	1252
mturner5	0:b7116bd48af6	1253	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
mturner5	0:b7116bd48af6	1254	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
mturner5	0:b7116bd48af6	1255
mturner5	0:b7116bd48af6	1256	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
mturner5	0:b7116bd48af6	1257	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
mturner5	0:b7116bd48af6	1258
mturner5	0:b7116bd48af6	1259	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
mturner5	0:b7116bd48af6	1260	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
mturner5	0:b7116bd48af6	1261
mturner5	0:b7116bd48af6	1262	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
mturner5	0:b7116bd48af6	1263	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
mturner5	0:b7116bd48af6	1264
mturner5	0:b7116bd48af6	1265	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
mturner5	0:b7116bd48af6	1266	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
mturner5	0:b7116bd48af6	1267
mturner5	0:b7116bd48af6	1268	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
mturner5	0:b7116bd48af6	1269	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
mturner5	0:b7116bd48af6	1270
mturner5	0:b7116bd48af6	1271	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
mturner5	0:b7116bd48af6	1272	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
mturner5	0:b7116bd48af6	1273
mturner5	0:b7116bd48af6	1274	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
mturner5	0:b7116bd48af6	1275	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
mturner5	0:b7116bd48af6	1276
mturner5	0:b7116bd48af6	1277	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
mturner5	0:b7116bd48af6	1278	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
mturner5	0:b7116bd48af6	1279
mturner5	0:b7116bd48af6	1280	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
mturner5	0:b7116bd48af6	1281	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
mturner5	0:b7116bd48af6	1282
mturner5	0:b7116bd48af6	1283	/@} end of group CMSIS_CoreDebug /
mturner5	0:b7116bd48af6	1284
mturner5	0:b7116bd48af6	1285
mturner5	0:b7116bd48af6	1286	/** \ingroup CMSIS_core_register
mturner5	0:b7116bd48af6	1287	\defgroup CMSIS_core_base Core Definitions
mturner5	0:b7116bd48af6	1288	\brief Definitions for base addresses, unions, and structures.
mturner5	0:b7116bd48af6	1289	@{
mturner5	0:b7116bd48af6	1290	*/
mturner5	0:b7116bd48af6	1291
mturner5	0:b7116bd48af6	1292	/* Memory mapping of Cortex-M3 Hardware */
mturner5	0:b7116bd48af6	1293	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
mturner5	0:b7116bd48af6	1294	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
mturner5	0:b7116bd48af6	1295	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
mturner5	0:b7116bd48af6	1296	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
mturner5	0:b7116bd48af6	1297	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
mturner5	0:b7116bd48af6	1298	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
mturner5	0:b7116bd48af6	1299	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
mturner5	0:b7116bd48af6	1300	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
mturner5	0:b7116bd48af6	1301
mturner5	0:b7116bd48af6	1302	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
mturner5	0:b7116bd48af6	1303	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
mturner5	0:b7116bd48af6	1304	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
mturner5	0:b7116bd48af6	1305	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
mturner5	0:b7116bd48af6	1306	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
mturner5	0:b7116bd48af6	1307	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
mturner5	0:b7116bd48af6	1308	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
mturner5	0:b7116bd48af6	1309	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
mturner5	0:b7116bd48af6	1310
mturner5	0:b7116bd48af6	1311	#if (__MPU_PRESENT == 1)
mturner5	0:b7116bd48af6	1312	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
mturner5	0:b7116bd48af6	1313	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
mturner5	0:b7116bd48af6	1314	#endif
mturner5	0:b7116bd48af6	1315
mturner5	0:b7116bd48af6	1316	/@} /
mturner5	0:b7116bd48af6	1317
mturner5	0:b7116bd48af6	1318
mturner5	0:b7116bd48af6	1319
mturner5	0:b7116bd48af6	1320	/*******************************************************************************
mturner5	0:b7116bd48af6	1321	* Hardware Abstraction Layer
mturner5	0:b7116bd48af6	1322	Core Function Interface contains:
mturner5	0:b7116bd48af6	1323	- Core NVIC Functions
mturner5	0:b7116bd48af6	1324	- Core SysTick Functions
mturner5	0:b7116bd48af6	1325	- Core Debug Functions
mturner5	0:b7116bd48af6	1326	- Core Register Access Functions
mturner5	0:b7116bd48af6	1327	******************************************************************************/
mturner5	0:b7116bd48af6	1328	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mturner5	0:b7116bd48af6	1329	*/
mturner5	0:b7116bd48af6	1330
mturner5	0:b7116bd48af6	1331
mturner5	0:b7116bd48af6	1332
mturner5	0:b7116bd48af6	1333	/* ########################## NVIC functions #################################### */
mturner5	0:b7116bd48af6	1334	/** \ingroup CMSIS_Core_FunctionInterface
mturner5	0:b7116bd48af6	1335	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
mturner5	0:b7116bd48af6	1336	\brief Functions that manage interrupts and exceptions via the NVIC.
mturner5	0:b7116bd48af6	1337	@{
mturner5	0:b7116bd48af6	1338	*/
mturner5	0:b7116bd48af6	1339
mturner5	0:b7116bd48af6	1340	/** \brief Set Priority Grouping
mturner5	0:b7116bd48af6	1341
mturner5	0:b7116bd48af6	1342	The function sets the priority grouping field using the required unlock sequence.
mturner5	0:b7116bd48af6	1343	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mturner5	0:b7116bd48af6	1344	Only values from 0..7 are used.
mturner5	0:b7116bd48af6	1345	In case of a conflict between priority grouping and available
mturner5	0:b7116bd48af6	1346	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mturner5	0:b7116bd48af6	1347
mturner5	0:b7116bd48af6	1348	\param [in] PriorityGroup Priority grouping field.
mturner5	0:b7116bd48af6	1349	*/
mturner5	0:b7116bd48af6	1350	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mturner5	0:b7116bd48af6	1351	{
mturner5	0:b7116bd48af6	1352	uint32_t reg_value;
mturner5	0:b7116bd48af6	1353	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mturner5	0:b7116bd48af6	1354
mturner5	0:b7116bd48af6	1355	reg_value = SCB->AIRCR; /* read old register configuration */
mturner5	0:b7116bd48af6	1356	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mturner5	0:b7116bd48af6	1357	reg_value = (reg_value \|
mturner5	0:b7116bd48af6	1358	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mturner5	0:b7116bd48af6	1359	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
mturner5	0:b7116bd48af6	1360	SCB->AIRCR = reg_value;
mturner5	0:b7116bd48af6	1361	}
mturner5	0:b7116bd48af6	1362
mturner5	0:b7116bd48af6	1363
mturner5	0:b7116bd48af6	1364	/** \brief Get Priority Grouping
mturner5	0:b7116bd48af6	1365
mturner5	0:b7116bd48af6	1366	The function reads the priority grouping field from the NVIC Interrupt Controller.
mturner5	0:b7116bd48af6	1367
mturner5	0:b7116bd48af6	1368	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mturner5	0:b7116bd48af6	1369	*/
mturner5	0:b7116bd48af6	1370	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
mturner5	0:b7116bd48af6	1371	{
mturner5	0:b7116bd48af6	1372	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mturner5	0:b7116bd48af6	1373	}
mturner5	0:b7116bd48af6	1374
mturner5	0:b7116bd48af6	1375
mturner5	0:b7116bd48af6	1376	/** \brief Enable External Interrupt
mturner5	0:b7116bd48af6	1377
mturner5	0:b7116bd48af6	1378	The function enables a device-specific interrupt in the NVIC interrupt controller.
mturner5	0:b7116bd48af6	1379
mturner5	0:b7116bd48af6	1380	\param [in] IRQn External interrupt number. Value cannot be negative.
mturner5	0:b7116bd48af6	1381	*/
mturner5	0:b7116bd48af6	1382	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1383	{
mturner5	0:b7116bd48af6	1384	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5	0:b7116bd48af6	1385	}
mturner5	0:b7116bd48af6	1386
mturner5	0:b7116bd48af6	1387
mturner5	0:b7116bd48af6	1388	/** \brief Disable External Interrupt
mturner5	0:b7116bd48af6	1389
mturner5	0:b7116bd48af6	1390	The function disables a device-specific interrupt in the NVIC interrupt controller.
mturner5	0:b7116bd48af6	1391
mturner5	0:b7116bd48af6	1392	\param [in] IRQn External interrupt number. Value cannot be negative.
mturner5	0:b7116bd48af6	1393	*/
mturner5	0:b7116bd48af6	1394	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1395	{
mturner5	0:b7116bd48af6	1396	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5	0:b7116bd48af6	1397	}
mturner5	0:b7116bd48af6	1398
mturner5	0:b7116bd48af6	1399
mturner5	0:b7116bd48af6	1400	/** \brief Get Pending Interrupt
mturner5	0:b7116bd48af6	1401
mturner5	0:b7116bd48af6	1402	The function reads the pending register in the NVIC and returns the pending bit
mturner5	0:b7116bd48af6	1403	for the specified interrupt.
mturner5	0:b7116bd48af6	1404
mturner5	0:b7116bd48af6	1405	\param [in] IRQn Interrupt number.
mturner5	0:b7116bd48af6	1406
mturner5	0:b7116bd48af6	1407	\return 0 Interrupt status is not pending.
mturner5	0:b7116bd48af6	1408	\return 1 Interrupt status is pending.
mturner5	0:b7116bd48af6	1409	*/
mturner5	0:b7116bd48af6	1410	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1411	{
mturner5	0:b7116bd48af6	1412	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mturner5	0:b7116bd48af6	1413	}
mturner5	0:b7116bd48af6	1414
mturner5	0:b7116bd48af6	1415
mturner5	0:b7116bd48af6	1416	/** \brief Set Pending Interrupt
mturner5	0:b7116bd48af6	1417
mturner5	0:b7116bd48af6	1418	The function sets the pending bit of an external interrupt.
mturner5	0:b7116bd48af6	1419
mturner5	0:b7116bd48af6	1420	\param [in] IRQn Interrupt number. Value cannot be negative.
mturner5	0:b7116bd48af6	1421	*/
mturner5	0:b7116bd48af6	1422	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1423	{
mturner5	0:b7116bd48af6	1424	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5	0:b7116bd48af6	1425	}
mturner5	0:b7116bd48af6	1426
mturner5	0:b7116bd48af6	1427
mturner5	0:b7116bd48af6	1428	/** \brief Clear Pending Interrupt
mturner5	0:b7116bd48af6	1429
mturner5	0:b7116bd48af6	1430	The function clears the pending bit of an external interrupt.
mturner5	0:b7116bd48af6	1431
mturner5	0:b7116bd48af6	1432	\param [in] IRQn External interrupt number. Value cannot be negative.
mturner5	0:b7116bd48af6	1433	*/
mturner5	0:b7116bd48af6	1434	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1435	{
mturner5	0:b7116bd48af6	1436	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5	0:b7116bd48af6	1437	}
mturner5	0:b7116bd48af6	1438
mturner5	0:b7116bd48af6	1439
mturner5	0:b7116bd48af6	1440	/** \brief Get Active Interrupt
mturner5	0:b7116bd48af6	1441
mturner5	0:b7116bd48af6	1442	The function reads the active register in NVIC and returns the active bit.
mturner5	0:b7116bd48af6	1443
mturner5	0:b7116bd48af6	1444	\param [in] IRQn Interrupt number.
mturner5	0:b7116bd48af6	1445
mturner5	0:b7116bd48af6	1446	\return 0 Interrupt status is not active.
mturner5	0:b7116bd48af6	1447	\return 1 Interrupt status is active.
mturner5	0:b7116bd48af6	1448	*/
mturner5	0:b7116bd48af6	1449	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1450	{
mturner5	0:b7116bd48af6	1451	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mturner5	0:b7116bd48af6	1452	}
mturner5	0:b7116bd48af6	1453
mturner5	0:b7116bd48af6	1454
mturner5	0:b7116bd48af6	1455	/** \brief Set Interrupt Priority
mturner5	0:b7116bd48af6	1456
mturner5	0:b7116bd48af6	1457	The function sets the priority of an interrupt.
mturner5	0:b7116bd48af6	1458
mturner5	0:b7116bd48af6	1459	\note The priority cannot be set for every core interrupt.
mturner5	0:b7116bd48af6	1460
mturner5	0:b7116bd48af6	1461	\param [in] IRQn Interrupt number.
mturner5	0:b7116bd48af6	1462	\param [in] priority Priority to set.
mturner5	0:b7116bd48af6	1463	*/
mturner5	0:b7116bd48af6	1464	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mturner5	0:b7116bd48af6	1465	{
mturner5	0:b7116bd48af6	1466	if((int32_t)IRQn < 0) {
mturner5	0:b7116bd48af6	1467	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mturner5	0:b7116bd48af6	1468	}
mturner5	0:b7116bd48af6	1469	else {
mturner5	0:b7116bd48af6	1470	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mturner5	0:b7116bd48af6	1471	}
mturner5	0:b7116bd48af6	1472	}
mturner5	0:b7116bd48af6	1473
mturner5	0:b7116bd48af6	1474
mturner5	0:b7116bd48af6	1475	/** \brief Get Interrupt Priority
mturner5	0:b7116bd48af6	1476
mturner5	0:b7116bd48af6	1477	The function reads the priority of an interrupt. The interrupt
mturner5	0:b7116bd48af6	1478	number can be positive to specify an external (device specific)
mturner5	0:b7116bd48af6	1479	interrupt, or negative to specify an internal (core) interrupt.
mturner5	0:b7116bd48af6	1480
mturner5	0:b7116bd48af6	1481
mturner5	0:b7116bd48af6	1482	\param [in] IRQn Interrupt number.
mturner5	0:b7116bd48af6	1483	\return Interrupt Priority. Value is aligned automatically to the implemented
mturner5	0:b7116bd48af6	1484	priority bits of the microcontroller.
mturner5	0:b7116bd48af6	1485	*/
mturner5	0:b7116bd48af6	1486	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mturner5	0:b7116bd48af6	1487	{
mturner5	0:b7116bd48af6	1488
mturner5	0:b7116bd48af6	1489	if((int32_t)IRQn < 0) {
mturner5	0:b7116bd48af6	1490	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
mturner5	0:b7116bd48af6	1491	}
mturner5	0:b7116bd48af6	1492	else {
mturner5	0:b7116bd48af6	1493	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
mturner5	0:b7116bd48af6	1494	}
mturner5	0:b7116bd48af6	1495	}
mturner5	0:b7116bd48af6	1496
mturner5	0:b7116bd48af6	1497
mturner5	0:b7116bd48af6	1498	/** \brief Encode Priority
mturner5	0:b7116bd48af6	1499
mturner5	0:b7116bd48af6	1500	The function encodes the priority for an interrupt with the given priority group,
mturner5	0:b7116bd48af6	1501	preemptive priority value, and subpriority value.
mturner5	0:b7116bd48af6	1502	In case of a conflict between priority grouping and available
mturner5	0:b7116bd48af6	1503	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mturner5	0:b7116bd48af6	1504
mturner5	0:b7116bd48af6	1505	\param [in] PriorityGroup Used priority group.
mturner5	0:b7116bd48af6	1506	\param [in] PreemptPriority Preemptive priority value (starting from 0).
mturner5	0:b7116bd48af6	1507	\param [in] SubPriority Subpriority value (starting from 0).
mturner5	0:b7116bd48af6	1508	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mturner5	0:b7116bd48af6	1509	*/
mturner5	0:b7116bd48af6	1510	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mturner5	0:b7116bd48af6	1511	{
mturner5	0:b7116bd48af6	1512	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mturner5	0:b7116bd48af6	1513	uint32_t PreemptPriorityBits;
mturner5	0:b7116bd48af6	1514	uint32_t SubPriorityBits;
mturner5	0:b7116bd48af6	1515
mturner5	0:b7116bd48af6	1516	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mturner5	0:b7116bd48af6	1517	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mturner5	0:b7116bd48af6	1518
mturner5	0:b7116bd48af6	1519	return (
mturner5	0:b7116bd48af6	1520	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
mturner5	0:b7116bd48af6	1521	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mturner5	0:b7116bd48af6	1522	);
mturner5	0:b7116bd48af6	1523	}
mturner5	0:b7116bd48af6	1524
mturner5	0:b7116bd48af6	1525
mturner5	0:b7116bd48af6	1526	/** \brief Decode Priority
mturner5	0:b7116bd48af6	1527
mturner5	0:b7116bd48af6	1528	The function decodes an interrupt priority value with a given priority group to
mturner5	0:b7116bd48af6	1529	preemptive priority value and subpriority value.
mturner5	0:b7116bd48af6	1530	In case of a conflict between priority grouping and available
mturner5	0:b7116bd48af6	1531	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mturner5	0:b7116bd48af6	1532
mturner5	0:b7116bd48af6	1533	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mturner5	0:b7116bd48af6	1534	\param [in] PriorityGroup Used priority group.
mturner5	0:b7116bd48af6	1535	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
mturner5	0:b7116bd48af6	1536	\param [out] pSubPriority Subpriority value (starting from 0).
mturner5	0:b7116bd48af6	1537	*/
mturner5	0:b7116bd48af6	1538	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mturner5	0:b7116bd48af6	1539	{
mturner5	0:b7116bd48af6	1540	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mturner5	0:b7116bd48af6	1541	uint32_t PreemptPriorityBits;
mturner5	0:b7116bd48af6	1542	uint32_t SubPriorityBits;
mturner5	0:b7116bd48af6	1543
mturner5	0:b7116bd48af6	1544	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mturner5	0:b7116bd48af6	1545	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mturner5	0:b7116bd48af6	1546
mturner5	0:b7116bd48af6	1547	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mturner5	0:b7116bd48af6	1548	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mturner5	0:b7116bd48af6	1549	}
mturner5	0:b7116bd48af6	1550
mturner5	0:b7116bd48af6	1551
mturner5	0:b7116bd48af6	1552	/** \brief System Reset
mturner5	0:b7116bd48af6	1553
mturner5	0:b7116bd48af6	1554	The function initiates a system reset request to reset the MCU.
mturner5	0:b7116bd48af6	1555	*/
mturner5	0:b7116bd48af6	1556	__STATIC_INLINE void NVIC_SystemReset(void)
mturner5	0:b7116bd48af6	1557	{
mturner5	0:b7116bd48af6	1558	__DSB(); /* Ensure all outstanding memory accesses included
mturner5	0:b7116bd48af6	1559	buffered write are completed before reset */
mturner5	0:b7116bd48af6	1560	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mturner5	0:b7116bd48af6	1561	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
mturner5	0:b7116bd48af6	1562	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mturner5	0:b7116bd48af6	1563	__DSB(); /* Ensure completion of memory access */
mturner5	0:b7116bd48af6	1564	while(1) { __NOP(); } /* wait until reset */
mturner5	0:b7116bd48af6	1565	}
mturner5	0:b7116bd48af6	1566
mturner5	0:b7116bd48af6	1567	/@} end of CMSIS_Core_NVICFunctions /
mturner5	0:b7116bd48af6	1568
mturner5	0:b7116bd48af6	1569
mturner5	0:b7116bd48af6	1570
mturner5	0:b7116bd48af6	1571	/* ################################## SysTick function ############################################ */
mturner5	0:b7116bd48af6	1572	/** \ingroup CMSIS_Core_FunctionInterface
mturner5	0:b7116bd48af6	1573	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mturner5	0:b7116bd48af6	1574	\brief Functions that configure the System.
mturner5	0:b7116bd48af6	1575	@{
mturner5	0:b7116bd48af6	1576	*/
mturner5	0:b7116bd48af6	1577
mturner5	0:b7116bd48af6	1578	#if (__Vendor_SysTickConfig == 0)
mturner5	0:b7116bd48af6	1579
mturner5	0:b7116bd48af6	1580	/** \brief System Tick Configuration
mturner5	0:b7116bd48af6	1581
mturner5	0:b7116bd48af6	1582	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mturner5	0:b7116bd48af6	1583	Counter is in free running mode to generate periodic interrupts.
mturner5	0:b7116bd48af6	1584
mturner5	0:b7116bd48af6	1585	\param [in] ticks Number of ticks between two interrupts.
mturner5	0:b7116bd48af6	1586
mturner5	0:b7116bd48af6	1587	\return 0 Function succeeded.
mturner5	0:b7116bd48af6	1588	\return 1 Function failed.
mturner5	0:b7116bd48af6	1589
mturner5	0:b7116bd48af6	1590	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mturner5	0:b7116bd48af6	1591	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mturner5	0:b7116bd48af6	1592	must contain a vendor-specific implementation of this function.
mturner5	0:b7116bd48af6	1593
mturner5	0:b7116bd48af6	1594	*/
mturner5	0:b7116bd48af6	1595	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mturner5	0:b7116bd48af6	1596	{
mturner5	0:b7116bd48af6	1597	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
mturner5	0:b7116bd48af6	1598
mturner5	0:b7116bd48af6	1599	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mturner5	0:b7116bd48af6	1600	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mturner5	0:b7116bd48af6	1601	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mturner5	0:b7116bd48af6	1602	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mturner5	0:b7116bd48af6	1603	SysTick_CTRL_TICKINT_Msk \|
mturner5	0:b7116bd48af6	1604	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mturner5	0:b7116bd48af6	1605	return (0UL); /* Function successful */
mturner5	0:b7116bd48af6	1606	}
mturner5	0:b7116bd48af6	1607
mturner5	0:b7116bd48af6	1608	#endif
mturner5	0:b7116bd48af6	1609
mturner5	0:b7116bd48af6	1610	/@} end of CMSIS_Core_SysTickFunctions /
mturner5	0:b7116bd48af6	1611
mturner5	0:b7116bd48af6	1612
mturner5	0:b7116bd48af6	1613
mturner5	0:b7116bd48af6	1614	/* ##################################### Debug In/Output function ########################################### */
mturner5	0:b7116bd48af6	1615	/** \ingroup CMSIS_Core_FunctionInterface
mturner5	0:b7116bd48af6	1616	\defgroup CMSIS_core_DebugFunctions ITM Functions
mturner5	0:b7116bd48af6	1617	\brief Functions that access the ITM debug interface.
mturner5	0:b7116bd48af6	1618	@{
mturner5	0:b7116bd48af6	1619	*/
mturner5	0:b7116bd48af6	1620
mturner5	0:b7116bd48af6	1621	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
mturner5	0:b7116bd48af6	1622	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
mturner5	0:b7116bd48af6	1623
mturner5	0:b7116bd48af6	1624
mturner5	0:b7116bd48af6	1625	/** \brief ITM Send Character
mturner5	0:b7116bd48af6	1626
mturner5	0:b7116bd48af6	1627	The function transmits a character via the ITM channel 0, and
mturner5	0:b7116bd48af6	1628	\li Just returns when no debugger is connected that has booked the output.
mturner5	0:b7116bd48af6	1629	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mturner5	0:b7116bd48af6	1630
mturner5	0:b7116bd48af6	1631	\param [in] ch Character to transmit.
mturner5	0:b7116bd48af6	1632
mturner5	0:b7116bd48af6	1633	\returns Character to transmit.
mturner5	0:b7116bd48af6	1634	*/
mturner5	0:b7116bd48af6	1635	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mturner5	0:b7116bd48af6	1636	{
mturner5	0:b7116bd48af6	1637	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mturner5	0:b7116bd48af6	1638	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mturner5	0:b7116bd48af6	1639	{
mturner5	0:b7116bd48af6	1640	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
mturner5	0:b7116bd48af6	1641	ITM->PORT[0].u8 = (uint8_t)ch;
mturner5	0:b7116bd48af6	1642	}
mturner5	0:b7116bd48af6	1643	return (ch);
mturner5	0:b7116bd48af6	1644	}
mturner5	0:b7116bd48af6	1645
mturner5	0:b7116bd48af6	1646
mturner5	0:b7116bd48af6	1647	/** \brief ITM Receive Character
mturner5	0:b7116bd48af6	1648
mturner5	0:b7116bd48af6	1649	The function inputs a character via the external variable \ref ITM_RxBuffer.
mturner5	0:b7116bd48af6	1650
mturner5	0:b7116bd48af6	1651	\return Received character.
mturner5	0:b7116bd48af6	1652	\return -1 No character pending.
mturner5	0:b7116bd48af6	1653	*/
mturner5	0:b7116bd48af6	1654	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mturner5	0:b7116bd48af6	1655	int32_t ch = -1; /* no character available */
mturner5	0:b7116bd48af6	1656
mturner5	0:b7116bd48af6	1657	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mturner5	0:b7116bd48af6	1658	ch = ITM_RxBuffer;
mturner5	0:b7116bd48af6	1659	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mturner5	0:b7116bd48af6	1660	}
mturner5	0:b7116bd48af6	1661
mturner5	0:b7116bd48af6	1662	return (ch);
mturner5	0:b7116bd48af6	1663	}
mturner5	0:b7116bd48af6	1664
mturner5	0:b7116bd48af6	1665
mturner5	0:b7116bd48af6	1666	/** \brief ITM Check Character
mturner5	0:b7116bd48af6	1667
mturner5	0:b7116bd48af6	1668	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mturner5	0:b7116bd48af6	1669
mturner5	0:b7116bd48af6	1670	\return 0 No character available.
mturner5	0:b7116bd48af6	1671	\return 1 Character available.
mturner5	0:b7116bd48af6	1672	*/
mturner5	0:b7116bd48af6	1673	__STATIC_INLINE int32_t ITM_CheckChar (void) {
mturner5	0:b7116bd48af6	1674
mturner5	0:b7116bd48af6	1675	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mturner5	0:b7116bd48af6	1676	return (0); /* no character available */
mturner5	0:b7116bd48af6	1677	} else {
mturner5	0:b7116bd48af6	1678	return (1); /* character available */
mturner5	0:b7116bd48af6	1679	}
mturner5	0:b7116bd48af6	1680	}
mturner5	0:b7116bd48af6	1681
mturner5	0:b7116bd48af6	1682	/@} end of CMSIS_core_DebugFunctions /
mturner5	0:b7116bd48af6	1683
mturner5	0:b7116bd48af6	1684
mturner5	0:b7116bd48af6	1685
mturner5	0:b7116bd48af6	1686
mturner5	0:b7116bd48af6	1687	#ifdef __cplusplus
mturner5	0:b7116bd48af6	1688	}
mturner5	0:b7116bd48af6	1689	#endif
mturner5	0:b7116bd48af6	1690
mturner5	0:b7116bd48af6	1691	#endif /* __CORE_CM3_H_DEPENDANT */
mturner5	0:b7116bd48af6	1692
mturner5	0:b7116bd48af6	1693	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	14 Sep 2016
Imports:	24
Forks:	0
Commits:	1
Dependents:	1
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Followers:	2

TARGET_KL46Z/core_cm3.h@0:b7116bd48af6, 2016-09-14 (annotated)

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