Mark Turner / mbed

mbed library for slider v2

Dependents:   kl46z_slider_v2

TARGET_KL46Z/core_cmInstr.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:
mturner5
Date:
Wed Sep 14 07:04:27 2016 +0000
Revision:
0:b7116bd48af6
Tried to use the timer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:b7116bd48af6 1 /**************************************************************************//**
mturner5 0:b7116bd48af6 2 * @file core_cmInstr.h
mturner5 0:b7116bd48af6 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
mturner5 0:b7116bd48af6 4 * @version V4.10
mturner5 0:b7116bd48af6 5 * @date 18. March 2015
mturner5 0:b7116bd48af6 6 *
mturner5 0:b7116bd48af6 7 * @note
mturner5 0:b7116bd48af6 8 *
mturner5 0:b7116bd48af6 9 ******************************************************************************/
mturner5 0:b7116bd48af6 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
mturner5 0:b7116bd48af6 11
mturner5 0:b7116bd48af6 12 All rights reserved.
mturner5 0:b7116bd48af6 13 Redistribution and use in source and binary forms, with or without
mturner5 0:b7116bd48af6 14 modification, are permitted provided that the following conditions are met:
mturner5 0:b7116bd48af6 15 - Redistributions of source code must retain the above copyright
mturner5 0:b7116bd48af6 16 notice, this list of conditions and the following disclaimer.
mturner5 0:b7116bd48af6 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:b7116bd48af6 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:b7116bd48af6 19 documentation and/or other materials provided with the distribution.
mturner5 0:b7116bd48af6 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:b7116bd48af6 21 to endorse or promote products derived from this software without
mturner5 0:b7116bd48af6 22 specific prior written permission.
mturner5 0:b7116bd48af6 23 *
mturner5 0:b7116bd48af6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:b7116bd48af6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:b7116bd48af6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:b7116bd48af6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:b7116bd48af6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:b7116bd48af6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:b7116bd48af6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:b7116bd48af6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:b7116bd48af6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:b7116bd48af6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:b7116bd48af6 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:b7116bd48af6 35 ---------------------------------------------------------------------------*/
mturner5 0:b7116bd48af6 36
mturner5 0:b7116bd48af6 37
mturner5 0:b7116bd48af6 38 #ifndef __CORE_CMINSTR_H
mturner5 0:b7116bd48af6 39 #define __CORE_CMINSTR_H
mturner5 0:b7116bd48af6 40
mturner5 0:b7116bd48af6 41
mturner5 0:b7116bd48af6 42 /* ########################## Core Instruction Access ######################### */
mturner5 0:b7116bd48af6 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
mturner5 0:b7116bd48af6 44 Access to dedicated instructions
mturner5 0:b7116bd48af6 45 @{
mturner5 0:b7116bd48af6 46 */
mturner5 0:b7116bd48af6 47
mturner5 0:b7116bd48af6 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mturner5 0:b7116bd48af6 49 /* ARM armcc specific functions */
mturner5 0:b7116bd48af6 50
mturner5 0:b7116bd48af6 51 #if (__ARMCC_VERSION < 400677)
mturner5 0:b7116bd48af6 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mturner5 0:b7116bd48af6 53 #endif
mturner5 0:b7116bd48af6 54
mturner5 0:b7116bd48af6 55
mturner5 0:b7116bd48af6 56 /** \brief No Operation
mturner5 0:b7116bd48af6 57
mturner5 0:b7116bd48af6 58 No Operation does nothing. This instruction can be used for code alignment purposes.
mturner5 0:b7116bd48af6 59 */
mturner5 0:b7116bd48af6 60 #define __NOP __nop
mturner5 0:b7116bd48af6 61
mturner5 0:b7116bd48af6 62
mturner5 0:b7116bd48af6 63 /** \brief Wait For Interrupt
mturner5 0:b7116bd48af6 64
mturner5 0:b7116bd48af6 65 Wait For Interrupt is a hint instruction that suspends execution
mturner5 0:b7116bd48af6 66 until one of a number of events occurs.
mturner5 0:b7116bd48af6 67 */
mturner5 0:b7116bd48af6 68 #define __WFI __wfi
mturner5 0:b7116bd48af6 69
mturner5 0:b7116bd48af6 70
mturner5 0:b7116bd48af6 71 /** \brief Wait For Event
mturner5 0:b7116bd48af6 72
mturner5 0:b7116bd48af6 73 Wait For Event is a hint instruction that permits the processor to enter
mturner5 0:b7116bd48af6 74 a low-power state until one of a number of events occurs.
mturner5 0:b7116bd48af6 75 */
mturner5 0:b7116bd48af6 76 #define __WFE __wfe
mturner5 0:b7116bd48af6 77
mturner5 0:b7116bd48af6 78
mturner5 0:b7116bd48af6 79 /** \brief Send Event
mturner5 0:b7116bd48af6 80
mturner5 0:b7116bd48af6 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mturner5 0:b7116bd48af6 82 */
mturner5 0:b7116bd48af6 83 #define __SEV __sev
mturner5 0:b7116bd48af6 84
mturner5 0:b7116bd48af6 85
mturner5 0:b7116bd48af6 86 /** \brief Instruction Synchronization Barrier
mturner5 0:b7116bd48af6 87
mturner5 0:b7116bd48af6 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
mturner5 0:b7116bd48af6 89 so that all instructions following the ISB are fetched from cache or
mturner5 0:b7116bd48af6 90 memory, after the instruction has been completed.
mturner5 0:b7116bd48af6 91 */
mturner5 0:b7116bd48af6 92 #define __ISB() do {\
mturner5 0:b7116bd48af6 93 __schedule_barrier();\
mturner5 0:b7116bd48af6 94 __isb(0xF);\
mturner5 0:b7116bd48af6 95 __schedule_barrier();\
mturner5 0:b7116bd48af6 96 } while (0)
mturner5 0:b7116bd48af6 97
mturner5 0:b7116bd48af6 98 /** \brief Data Synchronization Barrier
mturner5 0:b7116bd48af6 99
mturner5 0:b7116bd48af6 100 This function acts as a special kind of Data Memory Barrier.
mturner5 0:b7116bd48af6 101 It completes when all explicit memory accesses before this instruction complete.
mturner5 0:b7116bd48af6 102 */
mturner5 0:b7116bd48af6 103 #define __DSB() do {\
mturner5 0:b7116bd48af6 104 __schedule_barrier();\
mturner5 0:b7116bd48af6 105 __dsb(0xF);\
mturner5 0:b7116bd48af6 106 __schedule_barrier();\
mturner5 0:b7116bd48af6 107 } while (0)
mturner5 0:b7116bd48af6 108
mturner5 0:b7116bd48af6 109 /** \brief Data Memory Barrier
mturner5 0:b7116bd48af6 110
mturner5 0:b7116bd48af6 111 This function ensures the apparent order of the explicit memory operations before
mturner5 0:b7116bd48af6 112 and after the instruction, without ensuring their completion.
mturner5 0:b7116bd48af6 113 */
mturner5 0:b7116bd48af6 114 #define __DMB() do {\
mturner5 0:b7116bd48af6 115 __schedule_barrier();\
mturner5 0:b7116bd48af6 116 __dmb(0xF);\
mturner5 0:b7116bd48af6 117 __schedule_barrier();\
mturner5 0:b7116bd48af6 118 } while (0)
mturner5 0:b7116bd48af6 119
mturner5 0:b7116bd48af6 120 /** \brief Reverse byte order (32 bit)
mturner5 0:b7116bd48af6 121
mturner5 0:b7116bd48af6 122 This function reverses the byte order in integer value.
mturner5 0:b7116bd48af6 123
mturner5 0:b7116bd48af6 124 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 125 \return Reversed value
mturner5 0:b7116bd48af6 126 */
mturner5 0:b7116bd48af6 127 #define __REV __rev
mturner5 0:b7116bd48af6 128
mturner5 0:b7116bd48af6 129
mturner5 0:b7116bd48af6 130 /** \brief Reverse byte order (16 bit)
mturner5 0:b7116bd48af6 131
mturner5 0:b7116bd48af6 132 This function reverses the byte order in two unsigned short values.
mturner5 0:b7116bd48af6 133
mturner5 0:b7116bd48af6 134 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 135 \return Reversed value
mturner5 0:b7116bd48af6 136 */
mturner5 0:b7116bd48af6 137 #ifndef __NO_EMBEDDED_ASM
mturner5 0:b7116bd48af6 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
mturner5 0:b7116bd48af6 139 {
mturner5 0:b7116bd48af6 140 rev16 r0, r0
mturner5 0:b7116bd48af6 141 bx lr
mturner5 0:b7116bd48af6 142 }
mturner5 0:b7116bd48af6 143 #endif
mturner5 0:b7116bd48af6 144
mturner5 0:b7116bd48af6 145 /** \brief Reverse byte order in signed short value
mturner5 0:b7116bd48af6 146
mturner5 0:b7116bd48af6 147 This function reverses the byte order in a signed short value with sign extension to integer.
mturner5 0:b7116bd48af6 148
mturner5 0:b7116bd48af6 149 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 150 \return Reversed value
mturner5 0:b7116bd48af6 151 */
mturner5 0:b7116bd48af6 152 #ifndef __NO_EMBEDDED_ASM
mturner5 0:b7116bd48af6 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
mturner5 0:b7116bd48af6 154 {
mturner5 0:b7116bd48af6 155 revsh r0, r0
mturner5 0:b7116bd48af6 156 bx lr
mturner5 0:b7116bd48af6 157 }
mturner5 0:b7116bd48af6 158 #endif
mturner5 0:b7116bd48af6 159
mturner5 0:b7116bd48af6 160
mturner5 0:b7116bd48af6 161 /** \brief Rotate Right in unsigned value (32 bit)
mturner5 0:b7116bd48af6 162
mturner5 0:b7116bd48af6 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mturner5 0:b7116bd48af6 164
mturner5 0:b7116bd48af6 165 \param [in] value Value to rotate
mturner5 0:b7116bd48af6 166 \param [in] value Number of Bits to rotate
mturner5 0:b7116bd48af6 167 \return Rotated value
mturner5 0:b7116bd48af6 168 */
mturner5 0:b7116bd48af6 169 #define __ROR __ror
mturner5 0:b7116bd48af6 170
mturner5 0:b7116bd48af6 171
mturner5 0:b7116bd48af6 172 /** \brief Breakpoint
mturner5 0:b7116bd48af6 173
mturner5 0:b7116bd48af6 174 This function causes the processor to enter Debug state.
mturner5 0:b7116bd48af6 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mturner5 0:b7116bd48af6 176
mturner5 0:b7116bd48af6 177 \param [in] value is ignored by the processor.
mturner5 0:b7116bd48af6 178 If required, a debugger can use it to store additional information about the breakpoint.
mturner5 0:b7116bd48af6 179 */
mturner5 0:b7116bd48af6 180 #define __BKPT(value) __breakpoint(value)
mturner5 0:b7116bd48af6 181
mturner5 0:b7116bd48af6 182
mturner5 0:b7116bd48af6 183 /** \brief Reverse bit order of value
mturner5 0:b7116bd48af6 184
mturner5 0:b7116bd48af6 185 This function reverses the bit order of the given value.
mturner5 0:b7116bd48af6 186
mturner5 0:b7116bd48af6 187 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 188 \return Reversed value
mturner5 0:b7116bd48af6 189 */
mturner5 0:b7116bd48af6 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mturner5 0:b7116bd48af6 191 #define __RBIT __rbit
mturner5 0:b7116bd48af6 192 #else
mturner5 0:b7116bd48af6 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
mturner5 0:b7116bd48af6 194 {
mturner5 0:b7116bd48af6 195 uint32_t result;
mturner5 0:b7116bd48af6 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
mturner5 0:b7116bd48af6 197
mturner5 0:b7116bd48af6 198 result = value; // r will be reversed bits of v; first get LSB of v
mturner5 0:b7116bd48af6 199 for (value >>= 1; value; value >>= 1)
mturner5 0:b7116bd48af6 200 {
mturner5 0:b7116bd48af6 201 result <<= 1;
mturner5 0:b7116bd48af6 202 result |= value & 1;
mturner5 0:b7116bd48af6 203 s--;
mturner5 0:b7116bd48af6 204 }
mturner5 0:b7116bd48af6 205 result <<= s; // shift when v's highest bits are zero
mturner5 0:b7116bd48af6 206 return(result);
mturner5 0:b7116bd48af6 207 }
mturner5 0:b7116bd48af6 208 #endif
mturner5 0:b7116bd48af6 209
mturner5 0:b7116bd48af6 210
mturner5 0:b7116bd48af6 211 /** \brief Count leading zeros
mturner5 0:b7116bd48af6 212
mturner5 0:b7116bd48af6 213 This function counts the number of leading zeros of a data value.
mturner5 0:b7116bd48af6 214
mturner5 0:b7116bd48af6 215 \param [in] value Value to count the leading zeros
mturner5 0:b7116bd48af6 216 \return number of leading zeros in value
mturner5 0:b7116bd48af6 217 */
mturner5 0:b7116bd48af6 218 #define __CLZ __clz
mturner5 0:b7116bd48af6 219
mturner5 0:b7116bd48af6 220
mturner5 0:b7116bd48af6 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mturner5 0:b7116bd48af6 222
mturner5 0:b7116bd48af6 223 /** \brief LDR Exclusive (8 bit)
mturner5 0:b7116bd48af6 224
mturner5 0:b7116bd48af6 225 This function executes a exclusive LDR instruction for 8 bit value.
mturner5 0:b7116bd48af6 226
mturner5 0:b7116bd48af6 227 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 228 \return value of type uint8_t at (*ptr)
mturner5 0:b7116bd48af6 229 */
mturner5 0:b7116bd48af6 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
mturner5 0:b7116bd48af6 231
mturner5 0:b7116bd48af6 232
mturner5 0:b7116bd48af6 233 /** \brief LDR Exclusive (16 bit)
mturner5 0:b7116bd48af6 234
mturner5 0:b7116bd48af6 235 This function executes a exclusive LDR instruction for 16 bit values.
mturner5 0:b7116bd48af6 236
mturner5 0:b7116bd48af6 237 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 238 \return value of type uint16_t at (*ptr)
mturner5 0:b7116bd48af6 239 */
mturner5 0:b7116bd48af6 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
mturner5 0:b7116bd48af6 241
mturner5 0:b7116bd48af6 242
mturner5 0:b7116bd48af6 243 /** \brief LDR Exclusive (32 bit)
mturner5 0:b7116bd48af6 244
mturner5 0:b7116bd48af6 245 This function executes a exclusive LDR instruction for 32 bit values.
mturner5 0:b7116bd48af6 246
mturner5 0:b7116bd48af6 247 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 248 \return value of type uint32_t at (*ptr)
mturner5 0:b7116bd48af6 249 */
mturner5 0:b7116bd48af6 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
mturner5 0:b7116bd48af6 251
mturner5 0:b7116bd48af6 252
mturner5 0:b7116bd48af6 253 /** \brief STR Exclusive (8 bit)
mturner5 0:b7116bd48af6 254
mturner5 0:b7116bd48af6 255 This function executes a exclusive STR instruction for 8 bit values.
mturner5 0:b7116bd48af6 256
mturner5 0:b7116bd48af6 257 \param [in] value Value to store
mturner5 0:b7116bd48af6 258 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 259 \return 0 Function succeeded
mturner5 0:b7116bd48af6 260 \return 1 Function failed
mturner5 0:b7116bd48af6 261 */
mturner5 0:b7116bd48af6 262 #define __STREXB(value, ptr) __strex(value, ptr)
mturner5 0:b7116bd48af6 263
mturner5 0:b7116bd48af6 264
mturner5 0:b7116bd48af6 265 /** \brief STR Exclusive (16 bit)
mturner5 0:b7116bd48af6 266
mturner5 0:b7116bd48af6 267 This function executes a exclusive STR instruction for 16 bit values.
mturner5 0:b7116bd48af6 268
mturner5 0:b7116bd48af6 269 \param [in] value Value to store
mturner5 0:b7116bd48af6 270 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 271 \return 0 Function succeeded
mturner5 0:b7116bd48af6 272 \return 1 Function failed
mturner5 0:b7116bd48af6 273 */
mturner5 0:b7116bd48af6 274 #define __STREXH(value, ptr) __strex(value, ptr)
mturner5 0:b7116bd48af6 275
mturner5 0:b7116bd48af6 276
mturner5 0:b7116bd48af6 277 /** \brief STR Exclusive (32 bit)
mturner5 0:b7116bd48af6 278
mturner5 0:b7116bd48af6 279 This function executes a exclusive STR instruction for 32 bit values.
mturner5 0:b7116bd48af6 280
mturner5 0:b7116bd48af6 281 \param [in] value Value to store
mturner5 0:b7116bd48af6 282 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 283 \return 0 Function succeeded
mturner5 0:b7116bd48af6 284 \return 1 Function failed
mturner5 0:b7116bd48af6 285 */
mturner5 0:b7116bd48af6 286 #define __STREXW(value, ptr) __strex(value, ptr)
mturner5 0:b7116bd48af6 287
mturner5 0:b7116bd48af6 288
mturner5 0:b7116bd48af6 289 /** \brief Remove the exclusive lock
mturner5 0:b7116bd48af6 290
mturner5 0:b7116bd48af6 291 This function removes the exclusive lock which is created by LDREX.
mturner5 0:b7116bd48af6 292
mturner5 0:b7116bd48af6 293 */
mturner5 0:b7116bd48af6 294 #define __CLREX __clrex
mturner5 0:b7116bd48af6 295
mturner5 0:b7116bd48af6 296
mturner5 0:b7116bd48af6 297 /** \brief Signed Saturate
mturner5 0:b7116bd48af6 298
mturner5 0:b7116bd48af6 299 This function saturates a signed value.
mturner5 0:b7116bd48af6 300
mturner5 0:b7116bd48af6 301 \param [in] value Value to be saturated
mturner5 0:b7116bd48af6 302 \param [in] sat Bit position to saturate to (1..32)
mturner5 0:b7116bd48af6 303 \return Saturated value
mturner5 0:b7116bd48af6 304 */
mturner5 0:b7116bd48af6 305 #define __SSAT __ssat
mturner5 0:b7116bd48af6 306
mturner5 0:b7116bd48af6 307
mturner5 0:b7116bd48af6 308 /** \brief Unsigned Saturate
mturner5 0:b7116bd48af6 309
mturner5 0:b7116bd48af6 310 This function saturates an unsigned value.
mturner5 0:b7116bd48af6 311
mturner5 0:b7116bd48af6 312 \param [in] value Value to be saturated
mturner5 0:b7116bd48af6 313 \param [in] sat Bit position to saturate to (0..31)
mturner5 0:b7116bd48af6 314 \return Saturated value
mturner5 0:b7116bd48af6 315 */
mturner5 0:b7116bd48af6 316 #define __USAT __usat
mturner5 0:b7116bd48af6 317
mturner5 0:b7116bd48af6 318
mturner5 0:b7116bd48af6 319 /** \brief Rotate Right with Extend (32 bit)
mturner5 0:b7116bd48af6 320
mturner5 0:b7116bd48af6 321 This function moves each bit of a bitstring right by one bit.
mturner5 0:b7116bd48af6 322 The carry input is shifted in at the left end of the bitstring.
mturner5 0:b7116bd48af6 323
mturner5 0:b7116bd48af6 324 \param [in] value Value to rotate
mturner5 0:b7116bd48af6 325 \return Rotated value
mturner5 0:b7116bd48af6 326 */
mturner5 0:b7116bd48af6 327 #ifndef __NO_EMBEDDED_ASM
mturner5 0:b7116bd48af6 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
mturner5 0:b7116bd48af6 329 {
mturner5 0:b7116bd48af6 330 rrx r0, r0
mturner5 0:b7116bd48af6 331 bx lr
mturner5 0:b7116bd48af6 332 }
mturner5 0:b7116bd48af6 333 #endif
mturner5 0:b7116bd48af6 334
mturner5 0:b7116bd48af6 335
mturner5 0:b7116bd48af6 336 /** \brief LDRT Unprivileged (8 bit)
mturner5 0:b7116bd48af6 337
mturner5 0:b7116bd48af6 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
mturner5 0:b7116bd48af6 339
mturner5 0:b7116bd48af6 340 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 341 \return value of type uint8_t at (*ptr)
mturner5 0:b7116bd48af6 342 */
mturner5 0:b7116bd48af6 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
mturner5 0:b7116bd48af6 344
mturner5 0:b7116bd48af6 345
mturner5 0:b7116bd48af6 346 /** \brief LDRT Unprivileged (16 bit)
mturner5 0:b7116bd48af6 347
mturner5 0:b7116bd48af6 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
mturner5 0:b7116bd48af6 349
mturner5 0:b7116bd48af6 350 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 351 \return value of type uint16_t at (*ptr)
mturner5 0:b7116bd48af6 352 */
mturner5 0:b7116bd48af6 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
mturner5 0:b7116bd48af6 354
mturner5 0:b7116bd48af6 355
mturner5 0:b7116bd48af6 356 /** \brief LDRT Unprivileged (32 bit)
mturner5 0:b7116bd48af6 357
mturner5 0:b7116bd48af6 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
mturner5 0:b7116bd48af6 359
mturner5 0:b7116bd48af6 360 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 361 \return value of type uint32_t at (*ptr)
mturner5 0:b7116bd48af6 362 */
mturner5 0:b7116bd48af6 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
mturner5 0:b7116bd48af6 364
mturner5 0:b7116bd48af6 365
mturner5 0:b7116bd48af6 366 /** \brief STRT Unprivileged (8 bit)
mturner5 0:b7116bd48af6 367
mturner5 0:b7116bd48af6 368 This function executes a Unprivileged STRT instruction for 8 bit values.
mturner5 0:b7116bd48af6 369
mturner5 0:b7116bd48af6 370 \param [in] value Value to store
mturner5 0:b7116bd48af6 371 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 372 */
mturner5 0:b7116bd48af6 373 #define __STRBT(value, ptr) __strt(value, ptr)
mturner5 0:b7116bd48af6 374
mturner5 0:b7116bd48af6 375
mturner5 0:b7116bd48af6 376 /** \brief STRT Unprivileged (16 bit)
mturner5 0:b7116bd48af6 377
mturner5 0:b7116bd48af6 378 This function executes a Unprivileged STRT instruction for 16 bit values.
mturner5 0:b7116bd48af6 379
mturner5 0:b7116bd48af6 380 \param [in] value Value to store
mturner5 0:b7116bd48af6 381 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 382 */
mturner5 0:b7116bd48af6 383 #define __STRHT(value, ptr) __strt(value, ptr)
mturner5 0:b7116bd48af6 384
mturner5 0:b7116bd48af6 385
mturner5 0:b7116bd48af6 386 /** \brief STRT Unprivileged (32 bit)
mturner5 0:b7116bd48af6 387
mturner5 0:b7116bd48af6 388 This function executes a Unprivileged STRT instruction for 32 bit values.
mturner5 0:b7116bd48af6 389
mturner5 0:b7116bd48af6 390 \param [in] value Value to store
mturner5 0:b7116bd48af6 391 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 392 */
mturner5 0:b7116bd48af6 393 #define __STRT(value, ptr) __strt(value, ptr)
mturner5 0:b7116bd48af6 394
mturner5 0:b7116bd48af6 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
mturner5 0:b7116bd48af6 396
mturner5 0:b7116bd48af6 397
mturner5 0:b7116bd48af6 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mturner5 0:b7116bd48af6 399 /* GNU gcc specific functions */
mturner5 0:b7116bd48af6 400
mturner5 0:b7116bd48af6 401 /* Define macros for porting to both thumb1 and thumb2.
mturner5 0:b7116bd48af6 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
mturner5 0:b7116bd48af6 403 * Otherwise, use general registers, specified by constrant "r" */
mturner5 0:b7116bd48af6 404 #if defined (__thumb__) && !defined (__thumb2__)
mturner5 0:b7116bd48af6 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
mturner5 0:b7116bd48af6 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
mturner5 0:b7116bd48af6 407 #else
mturner5 0:b7116bd48af6 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
mturner5 0:b7116bd48af6 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
mturner5 0:b7116bd48af6 410 #endif
mturner5 0:b7116bd48af6 411
mturner5 0:b7116bd48af6 412 /** \brief No Operation
mturner5 0:b7116bd48af6 413
mturner5 0:b7116bd48af6 414 No Operation does nothing. This instruction can be used for code alignment purposes.
mturner5 0:b7116bd48af6 415 */
mturner5 0:b7116bd48af6 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
mturner5 0:b7116bd48af6 417 {
mturner5 0:b7116bd48af6 418 __ASM volatile ("nop");
mturner5 0:b7116bd48af6 419 }
mturner5 0:b7116bd48af6 420
mturner5 0:b7116bd48af6 421
mturner5 0:b7116bd48af6 422 /** \brief Wait For Interrupt
mturner5 0:b7116bd48af6 423
mturner5 0:b7116bd48af6 424 Wait For Interrupt is a hint instruction that suspends execution
mturner5 0:b7116bd48af6 425 until one of a number of events occurs.
mturner5 0:b7116bd48af6 426 */
mturner5 0:b7116bd48af6 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
mturner5 0:b7116bd48af6 428 {
mturner5 0:b7116bd48af6 429 __ASM volatile ("wfi");
mturner5 0:b7116bd48af6 430 }
mturner5 0:b7116bd48af6 431
mturner5 0:b7116bd48af6 432
mturner5 0:b7116bd48af6 433 /** \brief Wait For Event
mturner5 0:b7116bd48af6 434
mturner5 0:b7116bd48af6 435 Wait For Event is a hint instruction that permits the processor to enter
mturner5 0:b7116bd48af6 436 a low-power state until one of a number of events occurs.
mturner5 0:b7116bd48af6 437 */
mturner5 0:b7116bd48af6 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
mturner5 0:b7116bd48af6 439 {
mturner5 0:b7116bd48af6 440 __ASM volatile ("wfe");
mturner5 0:b7116bd48af6 441 }
mturner5 0:b7116bd48af6 442
mturner5 0:b7116bd48af6 443
mturner5 0:b7116bd48af6 444 /** \brief Send Event
mturner5 0:b7116bd48af6 445
mturner5 0:b7116bd48af6 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mturner5 0:b7116bd48af6 447 */
mturner5 0:b7116bd48af6 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
mturner5 0:b7116bd48af6 449 {
mturner5 0:b7116bd48af6 450 __ASM volatile ("sev");
mturner5 0:b7116bd48af6 451 }
mturner5 0:b7116bd48af6 452
mturner5 0:b7116bd48af6 453
mturner5 0:b7116bd48af6 454 /** \brief Instruction Synchronization Barrier
mturner5 0:b7116bd48af6 455
mturner5 0:b7116bd48af6 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
mturner5 0:b7116bd48af6 457 so that all instructions following the ISB are fetched from cache or
mturner5 0:b7116bd48af6 458 memory, after the instruction has been completed.
mturner5 0:b7116bd48af6 459 */
mturner5 0:b7116bd48af6 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
mturner5 0:b7116bd48af6 461 {
mturner5 0:b7116bd48af6 462 __ASM volatile ("isb 0xF":::"memory");
mturner5 0:b7116bd48af6 463 }
mturner5 0:b7116bd48af6 464
mturner5 0:b7116bd48af6 465
mturner5 0:b7116bd48af6 466 /** \brief Data Synchronization Barrier
mturner5 0:b7116bd48af6 467
mturner5 0:b7116bd48af6 468 This function acts as a special kind of Data Memory Barrier.
mturner5 0:b7116bd48af6 469 It completes when all explicit memory accesses before this instruction complete.
mturner5 0:b7116bd48af6 470 */
mturner5 0:b7116bd48af6 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
mturner5 0:b7116bd48af6 472 {
mturner5 0:b7116bd48af6 473 __ASM volatile ("dsb 0xF":::"memory");
mturner5 0:b7116bd48af6 474 }
mturner5 0:b7116bd48af6 475
mturner5 0:b7116bd48af6 476
mturner5 0:b7116bd48af6 477 /** \brief Data Memory Barrier
mturner5 0:b7116bd48af6 478
mturner5 0:b7116bd48af6 479 This function ensures the apparent order of the explicit memory operations before
mturner5 0:b7116bd48af6 480 and after the instruction, without ensuring their completion.
mturner5 0:b7116bd48af6 481 */
mturner5 0:b7116bd48af6 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
mturner5 0:b7116bd48af6 483 {
mturner5 0:b7116bd48af6 484 __ASM volatile ("dmb 0xF":::"memory");
mturner5 0:b7116bd48af6 485 }
mturner5 0:b7116bd48af6 486
mturner5 0:b7116bd48af6 487
mturner5 0:b7116bd48af6 488 /** \brief Reverse byte order (32 bit)
mturner5 0:b7116bd48af6 489
mturner5 0:b7116bd48af6 490 This function reverses the byte order in integer value.
mturner5 0:b7116bd48af6 491
mturner5 0:b7116bd48af6 492 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 493 \return Reversed value
mturner5 0:b7116bd48af6 494 */
mturner5 0:b7116bd48af6 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
mturner5 0:b7116bd48af6 496 {
mturner5 0:b7116bd48af6 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
mturner5 0:b7116bd48af6 498 return __builtin_bswap32(value);
mturner5 0:b7116bd48af6 499 #else
mturner5 0:b7116bd48af6 500 uint32_t result;
mturner5 0:b7116bd48af6 501
mturner5 0:b7116bd48af6 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:b7116bd48af6 503 return(result);
mturner5 0:b7116bd48af6 504 #endif
mturner5 0:b7116bd48af6 505 }
mturner5 0:b7116bd48af6 506
mturner5 0:b7116bd48af6 507
mturner5 0:b7116bd48af6 508 /** \brief Reverse byte order (16 bit)
mturner5 0:b7116bd48af6 509
mturner5 0:b7116bd48af6 510 This function reverses the byte order in two unsigned short values.
mturner5 0:b7116bd48af6 511
mturner5 0:b7116bd48af6 512 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 513 \return Reversed value
mturner5 0:b7116bd48af6 514 */
mturner5 0:b7116bd48af6 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
mturner5 0:b7116bd48af6 516 {
mturner5 0:b7116bd48af6 517 uint32_t result;
mturner5 0:b7116bd48af6 518
mturner5 0:b7116bd48af6 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:b7116bd48af6 520 return(result);
mturner5 0:b7116bd48af6 521 }
mturner5 0:b7116bd48af6 522
mturner5 0:b7116bd48af6 523
mturner5 0:b7116bd48af6 524 /** \brief Reverse byte order in signed short value
mturner5 0:b7116bd48af6 525
mturner5 0:b7116bd48af6 526 This function reverses the byte order in a signed short value with sign extension to integer.
mturner5 0:b7116bd48af6 527
mturner5 0:b7116bd48af6 528 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 529 \return Reversed value
mturner5 0:b7116bd48af6 530 */
mturner5 0:b7116bd48af6 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
mturner5 0:b7116bd48af6 532 {
mturner5 0:b7116bd48af6 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:b7116bd48af6 534 return (short)__builtin_bswap16(value);
mturner5 0:b7116bd48af6 535 #else
mturner5 0:b7116bd48af6 536 uint32_t result;
mturner5 0:b7116bd48af6 537
mturner5 0:b7116bd48af6 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:b7116bd48af6 539 return(result);
mturner5 0:b7116bd48af6 540 #endif
mturner5 0:b7116bd48af6 541 }
mturner5 0:b7116bd48af6 542
mturner5 0:b7116bd48af6 543
mturner5 0:b7116bd48af6 544 /** \brief Rotate Right in unsigned value (32 bit)
mturner5 0:b7116bd48af6 545
mturner5 0:b7116bd48af6 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mturner5 0:b7116bd48af6 547
mturner5 0:b7116bd48af6 548 \param [in] value Value to rotate
mturner5 0:b7116bd48af6 549 \param [in] value Number of Bits to rotate
mturner5 0:b7116bd48af6 550 \return Rotated value
mturner5 0:b7116bd48af6 551 */
mturner5 0:b7116bd48af6 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
mturner5 0:b7116bd48af6 553 {
mturner5 0:b7116bd48af6 554 return (op1 >> op2) | (op1 << (32 - op2));
mturner5 0:b7116bd48af6 555 }
mturner5 0:b7116bd48af6 556
mturner5 0:b7116bd48af6 557
mturner5 0:b7116bd48af6 558 /** \brief Breakpoint
mturner5 0:b7116bd48af6 559
mturner5 0:b7116bd48af6 560 This function causes the processor to enter Debug state.
mturner5 0:b7116bd48af6 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mturner5 0:b7116bd48af6 562
mturner5 0:b7116bd48af6 563 \param [in] value is ignored by the processor.
mturner5 0:b7116bd48af6 564 If required, a debugger can use it to store additional information about the breakpoint.
mturner5 0:b7116bd48af6 565 */
mturner5 0:b7116bd48af6 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
mturner5 0:b7116bd48af6 567
mturner5 0:b7116bd48af6 568
mturner5 0:b7116bd48af6 569 /** \brief Reverse bit order of value
mturner5 0:b7116bd48af6 570
mturner5 0:b7116bd48af6 571 This function reverses the bit order of the given value.
mturner5 0:b7116bd48af6 572
mturner5 0:b7116bd48af6 573 \param [in] value Value to reverse
mturner5 0:b7116bd48af6 574 \return Reversed value
mturner5 0:b7116bd48af6 575 */
mturner5 0:b7116bd48af6 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
mturner5 0:b7116bd48af6 577 {
mturner5 0:b7116bd48af6 578 uint32_t result;
mturner5 0:b7116bd48af6 579
mturner5 0:b7116bd48af6 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mturner5 0:b7116bd48af6 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
mturner5 0:b7116bd48af6 582 #else
mturner5 0:b7116bd48af6 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
mturner5 0:b7116bd48af6 584
mturner5 0:b7116bd48af6 585 result = value; // r will be reversed bits of v; first get LSB of v
mturner5 0:b7116bd48af6 586 for (value >>= 1; value; value >>= 1)
mturner5 0:b7116bd48af6 587 {
mturner5 0:b7116bd48af6 588 result <<= 1;
mturner5 0:b7116bd48af6 589 result |= value & 1;
mturner5 0:b7116bd48af6 590 s--;
mturner5 0:b7116bd48af6 591 }
mturner5 0:b7116bd48af6 592 result <<= s; // shift when v's highest bits are zero
mturner5 0:b7116bd48af6 593 #endif
mturner5 0:b7116bd48af6 594 return(result);
mturner5 0:b7116bd48af6 595 }
mturner5 0:b7116bd48af6 596
mturner5 0:b7116bd48af6 597
mturner5 0:b7116bd48af6 598 /** \brief Count leading zeros
mturner5 0:b7116bd48af6 599
mturner5 0:b7116bd48af6 600 This function counts the number of leading zeros of a data value.
mturner5 0:b7116bd48af6 601
mturner5 0:b7116bd48af6 602 \param [in] value Value to count the leading zeros
mturner5 0:b7116bd48af6 603 \return number of leading zeros in value
mturner5 0:b7116bd48af6 604 */
mturner5 0:b7116bd48af6 605 #define __CLZ __builtin_clz
mturner5 0:b7116bd48af6 606
mturner5 0:b7116bd48af6 607
mturner5 0:b7116bd48af6 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mturner5 0:b7116bd48af6 609
mturner5 0:b7116bd48af6 610 /** \brief LDR Exclusive (8 bit)
mturner5 0:b7116bd48af6 611
mturner5 0:b7116bd48af6 612 This function executes a exclusive LDR instruction for 8 bit value.
mturner5 0:b7116bd48af6 613
mturner5 0:b7116bd48af6 614 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 615 \return value of type uint8_t at (*ptr)
mturner5 0:b7116bd48af6 616 */
mturner5 0:b7116bd48af6 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
mturner5 0:b7116bd48af6 618 {
mturner5 0:b7116bd48af6 619 uint32_t result;
mturner5 0:b7116bd48af6 620
mturner5 0:b7116bd48af6 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:b7116bd48af6 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:b7116bd48af6 623 #else
mturner5 0:b7116bd48af6 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mturner5 0:b7116bd48af6 625 accepted by assembler. So has to use following less efficient pattern.
mturner5 0:b7116bd48af6 626 */
mturner5 0:b7116bd48af6 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mturner5 0:b7116bd48af6 628 #endif
mturner5 0:b7116bd48af6 629 return ((uint8_t) result); /* Add explicit type cast here */
mturner5 0:b7116bd48af6 630 }
mturner5 0:b7116bd48af6 631
mturner5 0:b7116bd48af6 632
mturner5 0:b7116bd48af6 633 /** \brief LDR Exclusive (16 bit)
mturner5 0:b7116bd48af6 634
mturner5 0:b7116bd48af6 635 This function executes a exclusive LDR instruction for 16 bit values.
mturner5 0:b7116bd48af6 636
mturner5 0:b7116bd48af6 637 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 638 \return value of type uint16_t at (*ptr)
mturner5 0:b7116bd48af6 639 */
mturner5 0:b7116bd48af6 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
mturner5 0:b7116bd48af6 641 {
mturner5 0:b7116bd48af6 642 uint32_t result;
mturner5 0:b7116bd48af6 643
mturner5 0:b7116bd48af6 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:b7116bd48af6 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:b7116bd48af6 646 #else
mturner5 0:b7116bd48af6 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mturner5 0:b7116bd48af6 648 accepted by assembler. So has to use following less efficient pattern.
mturner5 0:b7116bd48af6 649 */
mturner5 0:b7116bd48af6 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mturner5 0:b7116bd48af6 651 #endif
mturner5 0:b7116bd48af6 652 return ((uint16_t) result); /* Add explicit type cast here */
mturner5 0:b7116bd48af6 653 }
mturner5 0:b7116bd48af6 654
mturner5 0:b7116bd48af6 655
mturner5 0:b7116bd48af6 656 /** \brief LDR Exclusive (32 bit)
mturner5 0:b7116bd48af6 657
mturner5 0:b7116bd48af6 658 This function executes a exclusive LDR instruction for 32 bit values.
mturner5 0:b7116bd48af6 659
mturner5 0:b7116bd48af6 660 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 661 \return value of type uint32_t at (*ptr)
mturner5 0:b7116bd48af6 662 */
mturner5 0:b7116bd48af6 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
mturner5 0:b7116bd48af6 664 {
mturner5 0:b7116bd48af6 665 uint32_t result;
mturner5 0:b7116bd48af6 666
mturner5 0:b7116bd48af6 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:b7116bd48af6 668 return(result);
mturner5 0:b7116bd48af6 669 }
mturner5 0:b7116bd48af6 670
mturner5 0:b7116bd48af6 671
mturner5 0:b7116bd48af6 672 /** \brief STR Exclusive (8 bit)
mturner5 0:b7116bd48af6 673
mturner5 0:b7116bd48af6 674 This function executes a exclusive STR instruction for 8 bit values.
mturner5 0:b7116bd48af6 675
mturner5 0:b7116bd48af6 676 \param [in] value Value to store
mturner5 0:b7116bd48af6 677 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 678 \return 0 Function succeeded
mturner5 0:b7116bd48af6 679 \return 1 Function failed
mturner5 0:b7116bd48af6 680 */
mturner5 0:b7116bd48af6 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
mturner5 0:b7116bd48af6 682 {
mturner5 0:b7116bd48af6 683 uint32_t result;
mturner5 0:b7116bd48af6 684
mturner5 0:b7116bd48af6 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
mturner5 0:b7116bd48af6 686 return(result);
mturner5 0:b7116bd48af6 687 }
mturner5 0:b7116bd48af6 688
mturner5 0:b7116bd48af6 689
mturner5 0:b7116bd48af6 690 /** \brief STR Exclusive (16 bit)
mturner5 0:b7116bd48af6 691
mturner5 0:b7116bd48af6 692 This function executes a exclusive STR instruction for 16 bit values.
mturner5 0:b7116bd48af6 693
mturner5 0:b7116bd48af6 694 \param [in] value Value to store
mturner5 0:b7116bd48af6 695 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 696 \return 0 Function succeeded
mturner5 0:b7116bd48af6 697 \return 1 Function failed
mturner5 0:b7116bd48af6 698 */
mturner5 0:b7116bd48af6 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
mturner5 0:b7116bd48af6 700 {
mturner5 0:b7116bd48af6 701 uint32_t result;
mturner5 0:b7116bd48af6 702
mturner5 0:b7116bd48af6 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
mturner5 0:b7116bd48af6 704 return(result);
mturner5 0:b7116bd48af6 705 }
mturner5 0:b7116bd48af6 706
mturner5 0:b7116bd48af6 707
mturner5 0:b7116bd48af6 708 /** \brief STR Exclusive (32 bit)
mturner5 0:b7116bd48af6 709
mturner5 0:b7116bd48af6 710 This function executes a exclusive STR instruction for 32 bit values.
mturner5 0:b7116bd48af6 711
mturner5 0:b7116bd48af6 712 \param [in] value Value to store
mturner5 0:b7116bd48af6 713 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 714 \return 0 Function succeeded
mturner5 0:b7116bd48af6 715 \return 1 Function failed
mturner5 0:b7116bd48af6 716 */
mturner5 0:b7116bd48af6 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
mturner5 0:b7116bd48af6 718 {
mturner5 0:b7116bd48af6 719 uint32_t result;
mturner5 0:b7116bd48af6 720
mturner5 0:b7116bd48af6 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mturner5 0:b7116bd48af6 722 return(result);
mturner5 0:b7116bd48af6 723 }
mturner5 0:b7116bd48af6 724
mturner5 0:b7116bd48af6 725
mturner5 0:b7116bd48af6 726 /** \brief Remove the exclusive lock
mturner5 0:b7116bd48af6 727
mturner5 0:b7116bd48af6 728 This function removes the exclusive lock which is created by LDREX.
mturner5 0:b7116bd48af6 729
mturner5 0:b7116bd48af6 730 */
mturner5 0:b7116bd48af6 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
mturner5 0:b7116bd48af6 732 {
mturner5 0:b7116bd48af6 733 __ASM volatile ("clrex" ::: "memory");
mturner5 0:b7116bd48af6 734 }
mturner5 0:b7116bd48af6 735
mturner5 0:b7116bd48af6 736
mturner5 0:b7116bd48af6 737 /** \brief Signed Saturate
mturner5 0:b7116bd48af6 738
mturner5 0:b7116bd48af6 739 This function saturates a signed value.
mturner5 0:b7116bd48af6 740
mturner5 0:b7116bd48af6 741 \param [in] value Value to be saturated
mturner5 0:b7116bd48af6 742 \param [in] sat Bit position to saturate to (1..32)
mturner5 0:b7116bd48af6 743 \return Saturated value
mturner5 0:b7116bd48af6 744 */
mturner5 0:b7116bd48af6 745 #define __SSAT(ARG1,ARG2) \
mturner5 0:b7116bd48af6 746 ({ \
mturner5 0:b7116bd48af6 747 uint32_t __RES, __ARG1 = (ARG1); \
mturner5 0:b7116bd48af6 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mturner5 0:b7116bd48af6 749 __RES; \
mturner5 0:b7116bd48af6 750 })
mturner5 0:b7116bd48af6 751
mturner5 0:b7116bd48af6 752
mturner5 0:b7116bd48af6 753 /** \brief Unsigned Saturate
mturner5 0:b7116bd48af6 754
mturner5 0:b7116bd48af6 755 This function saturates an unsigned value.
mturner5 0:b7116bd48af6 756
mturner5 0:b7116bd48af6 757 \param [in] value Value to be saturated
mturner5 0:b7116bd48af6 758 \param [in] sat Bit position to saturate to (0..31)
mturner5 0:b7116bd48af6 759 \return Saturated value
mturner5 0:b7116bd48af6 760 */
mturner5 0:b7116bd48af6 761 #define __USAT(ARG1,ARG2) \
mturner5 0:b7116bd48af6 762 ({ \
mturner5 0:b7116bd48af6 763 uint32_t __RES, __ARG1 = (ARG1); \
mturner5 0:b7116bd48af6 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mturner5 0:b7116bd48af6 765 __RES; \
mturner5 0:b7116bd48af6 766 })
mturner5 0:b7116bd48af6 767
mturner5 0:b7116bd48af6 768
mturner5 0:b7116bd48af6 769 /** \brief Rotate Right with Extend (32 bit)
mturner5 0:b7116bd48af6 770
mturner5 0:b7116bd48af6 771 This function moves each bit of a bitstring right by one bit.
mturner5 0:b7116bd48af6 772 The carry input is shifted in at the left end of the bitstring.
mturner5 0:b7116bd48af6 773
mturner5 0:b7116bd48af6 774 \param [in] value Value to rotate
mturner5 0:b7116bd48af6 775 \return Rotated value
mturner5 0:b7116bd48af6 776 */
mturner5 0:b7116bd48af6 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
mturner5 0:b7116bd48af6 778 {
mturner5 0:b7116bd48af6 779 uint32_t result;
mturner5 0:b7116bd48af6 780
mturner5 0:b7116bd48af6 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mturner5 0:b7116bd48af6 782 return(result);
mturner5 0:b7116bd48af6 783 }
mturner5 0:b7116bd48af6 784
mturner5 0:b7116bd48af6 785
mturner5 0:b7116bd48af6 786 /** \brief LDRT Unprivileged (8 bit)
mturner5 0:b7116bd48af6 787
mturner5 0:b7116bd48af6 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
mturner5 0:b7116bd48af6 789
mturner5 0:b7116bd48af6 790 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 791 \return value of type uint8_t at (*ptr)
mturner5 0:b7116bd48af6 792 */
mturner5 0:b7116bd48af6 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
mturner5 0:b7116bd48af6 794 {
mturner5 0:b7116bd48af6 795 uint32_t result;
mturner5 0:b7116bd48af6 796
mturner5 0:b7116bd48af6 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:b7116bd48af6 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:b7116bd48af6 799 #else
mturner5 0:b7116bd48af6 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mturner5 0:b7116bd48af6 801 accepted by assembler. So has to use following less efficient pattern.
mturner5 0:b7116bd48af6 802 */
mturner5 0:b7116bd48af6 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mturner5 0:b7116bd48af6 804 #endif
mturner5 0:b7116bd48af6 805 return ((uint8_t) result); /* Add explicit type cast here */
mturner5 0:b7116bd48af6 806 }
mturner5 0:b7116bd48af6 807
mturner5 0:b7116bd48af6 808
mturner5 0:b7116bd48af6 809 /** \brief LDRT Unprivileged (16 bit)
mturner5 0:b7116bd48af6 810
mturner5 0:b7116bd48af6 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
mturner5 0:b7116bd48af6 812
mturner5 0:b7116bd48af6 813 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 814 \return value of type uint16_t at (*ptr)
mturner5 0:b7116bd48af6 815 */
mturner5 0:b7116bd48af6 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
mturner5 0:b7116bd48af6 817 {
mturner5 0:b7116bd48af6 818 uint32_t result;
mturner5 0:b7116bd48af6 819
mturner5 0:b7116bd48af6 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mturner5 0:b7116bd48af6 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:b7116bd48af6 822 #else
mturner5 0:b7116bd48af6 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mturner5 0:b7116bd48af6 824 accepted by assembler. So has to use following less efficient pattern.
mturner5 0:b7116bd48af6 825 */
mturner5 0:b7116bd48af6 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mturner5 0:b7116bd48af6 827 #endif
mturner5 0:b7116bd48af6 828 return ((uint16_t) result); /* Add explicit type cast here */
mturner5 0:b7116bd48af6 829 }
mturner5 0:b7116bd48af6 830
mturner5 0:b7116bd48af6 831
mturner5 0:b7116bd48af6 832 /** \brief LDRT Unprivileged (32 bit)
mturner5 0:b7116bd48af6 833
mturner5 0:b7116bd48af6 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
mturner5 0:b7116bd48af6 835
mturner5 0:b7116bd48af6 836 \param [in] ptr Pointer to data
mturner5 0:b7116bd48af6 837 \return value of type uint32_t at (*ptr)
mturner5 0:b7116bd48af6 838 */
mturner5 0:b7116bd48af6 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
mturner5 0:b7116bd48af6 840 {
mturner5 0:b7116bd48af6 841 uint32_t result;
mturner5 0:b7116bd48af6 842
mturner5 0:b7116bd48af6 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
mturner5 0:b7116bd48af6 844 return(result);
mturner5 0:b7116bd48af6 845 }
mturner5 0:b7116bd48af6 846
mturner5 0:b7116bd48af6 847
mturner5 0:b7116bd48af6 848 /** \brief STRT Unprivileged (8 bit)
mturner5 0:b7116bd48af6 849
mturner5 0:b7116bd48af6 850 This function executes a Unprivileged STRT instruction for 8 bit values.
mturner5 0:b7116bd48af6 851
mturner5 0:b7116bd48af6 852 \param [in] value Value to store
mturner5 0:b7116bd48af6 853 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 854 */
mturner5 0:b7116bd48af6 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
mturner5 0:b7116bd48af6 856 {
mturner5 0:b7116bd48af6 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
mturner5 0:b7116bd48af6 858 }
mturner5 0:b7116bd48af6 859
mturner5 0:b7116bd48af6 860
mturner5 0:b7116bd48af6 861 /** \brief STRT Unprivileged (16 bit)
mturner5 0:b7116bd48af6 862
mturner5 0:b7116bd48af6 863 This function executes a Unprivileged STRT instruction for 16 bit values.
mturner5 0:b7116bd48af6 864
mturner5 0:b7116bd48af6 865 \param [in] value Value to store
mturner5 0:b7116bd48af6 866 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 867 */
mturner5 0:b7116bd48af6 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
mturner5 0:b7116bd48af6 869 {
mturner5 0:b7116bd48af6 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
mturner5 0:b7116bd48af6 871 }
mturner5 0:b7116bd48af6 872
mturner5 0:b7116bd48af6 873
mturner5 0:b7116bd48af6 874 /** \brief STRT Unprivileged (32 bit)
mturner5 0:b7116bd48af6 875
mturner5 0:b7116bd48af6 876 This function executes a Unprivileged STRT instruction for 32 bit values.
mturner5 0:b7116bd48af6 877
mturner5 0:b7116bd48af6 878 \param [in] value Value to store
mturner5 0:b7116bd48af6 879 \param [in] ptr Pointer to location
mturner5 0:b7116bd48af6 880 */
mturner5 0:b7116bd48af6 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
mturner5 0:b7116bd48af6 882 {
mturner5 0:b7116bd48af6 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
mturner5 0:b7116bd48af6 884 }
mturner5 0:b7116bd48af6 885
mturner5 0:b7116bd48af6 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
mturner5 0:b7116bd48af6 887
mturner5 0:b7116bd48af6 888
mturner5 0:b7116bd48af6 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mturner5 0:b7116bd48af6 890 /* IAR iccarm specific functions */
mturner5 0:b7116bd48af6 891 #include <cmsis_iar.h>
mturner5 0:b7116bd48af6 892
mturner5 0:b7116bd48af6 893
mturner5 0:b7116bd48af6 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mturner5 0:b7116bd48af6 895 /* TI CCS specific functions */
mturner5 0:b7116bd48af6 896 #include <cmsis_ccs.h>
mturner5 0:b7116bd48af6 897
mturner5 0:b7116bd48af6 898
mturner5 0:b7116bd48af6 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mturner5 0:b7116bd48af6 900 /* TASKING carm specific functions */
mturner5 0:b7116bd48af6 901 /*
mturner5 0:b7116bd48af6 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
mturner5 0:b7116bd48af6 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
mturner5 0:b7116bd48af6 904 * Including the CMSIS ones.
mturner5 0:b7116bd48af6 905 */
mturner5 0:b7116bd48af6 906
mturner5 0:b7116bd48af6 907
mturner5 0:b7116bd48af6 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
mturner5 0:b7116bd48af6 909 /* Cosmic specific functions */
mturner5 0:b7116bd48af6 910 #include <cmsis_csm.h>
mturner5 0:b7116bd48af6 911
mturner5 0:b7116bd48af6 912 #endif
mturner5 0:b7116bd48af6 913
mturner5 0:b7116bd48af6 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
mturner5 0:b7116bd48af6 915
mturner5 0:b7116bd48af6 916 #endif /* __CORE_CMINSTR_H */