Mark Turner / mbed

mbed library for slider v2

Dependents:   kl46z_slider_v2

TARGET_KL46Z/core_cm0.h@0:b7116bd48af6, 2016-09-14 (annotated)

Committer:
mturner5
Date:
Wed Sep 14 07:04:27 2016 +0000
Revision:
0:b7116bd48af6
Tried to use the timer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:b7116bd48af6 1 /**************************************************************************//**
mturner5 0:b7116bd48af6 2 * @file core_cm0.h
mturner5 0:b7116bd48af6 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
mturner5 0:b7116bd48af6 4 * @version V4.10
mturner5 0:b7116bd48af6 5 * @date 18. March 2015
mturner5 0:b7116bd48af6 6 *
mturner5 0:b7116bd48af6 7 * @note
mturner5 0:b7116bd48af6 8 *
mturner5 0:b7116bd48af6 9 ******************************************************************************/
mturner5 0:b7116bd48af6 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mturner5 0:b7116bd48af6 11
mturner5 0:b7116bd48af6 12 All rights reserved.
mturner5 0:b7116bd48af6 13 Redistribution and use in source and binary forms, with or without
mturner5 0:b7116bd48af6 14 modification, are permitted provided that the following conditions are met:
mturner5 0:b7116bd48af6 15 - Redistributions of source code must retain the above copyright
mturner5 0:b7116bd48af6 16 notice, this list of conditions and the following disclaimer.
mturner5 0:b7116bd48af6 17 - Redistributions in binary form must reproduce the above copyright
mturner5 0:b7116bd48af6 18 notice, this list of conditions and the following disclaimer in the
mturner5 0:b7116bd48af6 19 documentation and/or other materials provided with the distribution.
mturner5 0:b7116bd48af6 20 - Neither the name of ARM nor the names of its contributors may be used
mturner5 0:b7116bd48af6 21 to endorse or promote products derived from this software without
mturner5 0:b7116bd48af6 22 specific prior written permission.
mturner5 0:b7116bd48af6 23 *
mturner5 0:b7116bd48af6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mturner5 0:b7116bd48af6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mturner5 0:b7116bd48af6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mturner5 0:b7116bd48af6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mturner5 0:b7116bd48af6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mturner5 0:b7116bd48af6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mturner5 0:b7116bd48af6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mturner5 0:b7116bd48af6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mturner5 0:b7116bd48af6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mturner5 0:b7116bd48af6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mturner5 0:b7116bd48af6 34 POSSIBILITY OF SUCH DAMAGE.
mturner5 0:b7116bd48af6 35 ---------------------------------------------------------------------------*/
mturner5 0:b7116bd48af6 36
mturner5 0:b7116bd48af6 37
mturner5 0:b7116bd48af6 38 #if defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 39 #pragma system_include /* treat file as system include file for MISRA check */
mturner5 0:b7116bd48af6 40 #endif
mturner5 0:b7116bd48af6 41
mturner5 0:b7116bd48af6 42 #ifndef __CORE_CM0_H_GENERIC
mturner5 0:b7116bd48af6 43 #define __CORE_CM0_H_GENERIC
mturner5 0:b7116bd48af6 44
mturner5 0:b7116bd48af6 45 #ifdef __cplusplus
mturner5 0:b7116bd48af6 46 extern "C" {
mturner5 0:b7116bd48af6 47 #endif
mturner5 0:b7116bd48af6 48
mturner5 0:b7116bd48af6 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mturner5 0:b7116bd48af6 50 CMSIS violates the following MISRA-C:2004 rules:
mturner5 0:b7116bd48af6 51
mturner5 0:b7116bd48af6 52 \li Required Rule 8.5, object/function definition in header file.<br>
mturner5 0:b7116bd48af6 53 Function definitions in header files are used to allow 'inlining'.
mturner5 0:b7116bd48af6 54
mturner5 0:b7116bd48af6 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mturner5 0:b7116bd48af6 56 Unions are used for effective representation of core registers.
mturner5 0:b7116bd48af6 57
mturner5 0:b7116bd48af6 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mturner5 0:b7116bd48af6 59 Function-like macros are used to allow more efficient code.
mturner5 0:b7116bd48af6 60 */
mturner5 0:b7116bd48af6 61
mturner5 0:b7116bd48af6 62
mturner5 0:b7116bd48af6 63 /*******************************************************************************
mturner5 0:b7116bd48af6 64 * CMSIS definitions
mturner5 0:b7116bd48af6 65 ******************************************************************************/
mturner5 0:b7116bd48af6 66 /** \ingroup Cortex_M0
mturner5 0:b7116bd48af6 67 @{
mturner5 0:b7116bd48af6 68 */
mturner5 0:b7116bd48af6 69
mturner5 0:b7116bd48af6 70 /* CMSIS CM0 definitions */
mturner5 0:b7116bd48af6 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mturner5 0:b7116bd48af6 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
mturner5 0:b7116bd48af6 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
mturner5 0:b7116bd48af6 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mturner5 0:b7116bd48af6 75
mturner5 0:b7116bd48af6 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mturner5 0:b7116bd48af6 77
mturner5 0:b7116bd48af6 78
mturner5 0:b7116bd48af6 79 #if defined ( __CC_ARM )
mturner5 0:b7116bd48af6 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mturner5 0:b7116bd48af6 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mturner5 0:b7116bd48af6 82 #define __STATIC_INLINE static __inline
mturner5 0:b7116bd48af6 83
mturner5 0:b7116bd48af6 84 #elif defined ( __GNUC__ )
mturner5 0:b7116bd48af6 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mturner5 0:b7116bd48af6 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mturner5 0:b7116bd48af6 87 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 88
mturner5 0:b7116bd48af6 89 #elif defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mturner5 0:b7116bd48af6 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mturner5 0:b7116bd48af6 92 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 93
mturner5 0:b7116bd48af6 94 #elif defined ( __TMS470__ )
mturner5 0:b7116bd48af6 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mturner5 0:b7116bd48af6 96 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 97
mturner5 0:b7116bd48af6 98 #elif defined ( __TASKING__ )
mturner5 0:b7116bd48af6 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mturner5 0:b7116bd48af6 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mturner5 0:b7116bd48af6 101 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 102
mturner5 0:b7116bd48af6 103 #elif defined ( __CSMC__ )
mturner5 0:b7116bd48af6 104 #define __packed
mturner5 0:b7116bd48af6 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mturner5 0:b7116bd48af6 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mturner5 0:b7116bd48af6 107 #define __STATIC_INLINE static inline
mturner5 0:b7116bd48af6 108
mturner5 0:b7116bd48af6 109 #endif
mturner5 0:b7116bd48af6 110
mturner5 0:b7116bd48af6 111 /** __FPU_USED indicates whether an FPU is used or not.
mturner5 0:b7116bd48af6 112 This core does not support an FPU at all
mturner5 0:b7116bd48af6 113 */
mturner5 0:b7116bd48af6 114 #define __FPU_USED 0
mturner5 0:b7116bd48af6 115
mturner5 0:b7116bd48af6 116 #if defined ( __CC_ARM )
mturner5 0:b7116bd48af6 117 #if defined __TARGET_FPU_VFP
mturner5 0:b7116bd48af6 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 119 #endif
mturner5 0:b7116bd48af6 120
mturner5 0:b7116bd48af6 121 #elif defined ( __GNUC__ )
mturner5 0:b7116bd48af6 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mturner5 0:b7116bd48af6 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 124 #endif
mturner5 0:b7116bd48af6 125
mturner5 0:b7116bd48af6 126 #elif defined ( __ICCARM__ )
mturner5 0:b7116bd48af6 127 #if defined __ARMVFP__
mturner5 0:b7116bd48af6 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 129 #endif
mturner5 0:b7116bd48af6 130
mturner5 0:b7116bd48af6 131 #elif defined ( __TMS470__ )
mturner5 0:b7116bd48af6 132 #if defined __TI__VFP_SUPPORT____
mturner5 0:b7116bd48af6 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 134 #endif
mturner5 0:b7116bd48af6 135
mturner5 0:b7116bd48af6 136 #elif defined ( __TASKING__ )
mturner5 0:b7116bd48af6 137 #if defined __FPU_VFP__
mturner5 0:b7116bd48af6 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 139 #endif
mturner5 0:b7116bd48af6 140
mturner5 0:b7116bd48af6 141 #elif defined ( __CSMC__ ) /* Cosmic */
mturner5 0:b7116bd48af6 142 #if ( __CSMC__ & 0x400) // FPU present for parser
mturner5 0:b7116bd48af6 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mturner5 0:b7116bd48af6 144 #endif
mturner5 0:b7116bd48af6 145 #endif
mturner5 0:b7116bd48af6 146
mturner5 0:b7116bd48af6 147 #include <stdint.h> /* standard types definitions */
mturner5 0:b7116bd48af6 148 #include <core_cmInstr.h> /* Core Instruction Access */
mturner5 0:b7116bd48af6 149 #include <core_cmFunc.h> /* Core Function Access */
mturner5 0:b7116bd48af6 150
mturner5 0:b7116bd48af6 151 #ifdef __cplusplus
mturner5 0:b7116bd48af6 152 }
mturner5 0:b7116bd48af6 153 #endif
mturner5 0:b7116bd48af6 154
mturner5 0:b7116bd48af6 155 #endif /* __CORE_CM0_H_GENERIC */
mturner5 0:b7116bd48af6 156
mturner5 0:b7116bd48af6 157 #ifndef __CMSIS_GENERIC
mturner5 0:b7116bd48af6 158
mturner5 0:b7116bd48af6 159 #ifndef __CORE_CM0_H_DEPENDANT
mturner5 0:b7116bd48af6 160 #define __CORE_CM0_H_DEPENDANT
mturner5 0:b7116bd48af6 161
mturner5 0:b7116bd48af6 162 #ifdef __cplusplus
mturner5 0:b7116bd48af6 163 extern "C" {
mturner5 0:b7116bd48af6 164 #endif
mturner5 0:b7116bd48af6 165
mturner5 0:b7116bd48af6 166 /* check device defines and use defaults */
mturner5 0:b7116bd48af6 167 #if defined __CHECK_DEVICE_DEFINES
mturner5 0:b7116bd48af6 168 #ifndef __CM0_REV
mturner5 0:b7116bd48af6 169 #define __CM0_REV 0x0000
mturner5 0:b7116bd48af6 170 #warning "__CM0_REV not defined in device header file; using default!"
mturner5 0:b7116bd48af6 171 #endif
mturner5 0:b7116bd48af6 172
mturner5 0:b7116bd48af6 173 #ifndef __NVIC_PRIO_BITS
mturner5 0:b7116bd48af6 174 #define __NVIC_PRIO_BITS 2
mturner5 0:b7116bd48af6 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mturner5 0:b7116bd48af6 176 #endif
mturner5 0:b7116bd48af6 177
mturner5 0:b7116bd48af6 178 #ifndef __Vendor_SysTickConfig
mturner5 0:b7116bd48af6 179 #define __Vendor_SysTickConfig 0
mturner5 0:b7116bd48af6 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mturner5 0:b7116bd48af6 181 #endif
mturner5 0:b7116bd48af6 182 #endif
mturner5 0:b7116bd48af6 183
mturner5 0:b7116bd48af6 184 /* IO definitions (access restrictions to peripheral registers) */
mturner5 0:b7116bd48af6 185 /**
mturner5 0:b7116bd48af6 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
mturner5 0:b7116bd48af6 187
mturner5 0:b7116bd48af6 188 <strong>IO Type Qualifiers</strong> are used
mturner5 0:b7116bd48af6 189 \li to specify the access to peripheral variables.
mturner5 0:b7116bd48af6 190 \li for automatic generation of peripheral register debug information.
mturner5 0:b7116bd48af6 191 */
mturner5 0:b7116bd48af6 192 #ifdef __cplusplus
mturner5 0:b7116bd48af6 193 #define __I volatile /*!< Defines 'read only' permissions */
mturner5 0:b7116bd48af6 194 #else
mturner5 0:b7116bd48af6 195 #define __I volatile const /*!< Defines 'read only' permissions */
mturner5 0:b7116bd48af6 196 #endif
mturner5 0:b7116bd48af6 197 #define __O volatile /*!< Defines 'write only' permissions */
mturner5 0:b7116bd48af6 198 #define __IO volatile /*!< Defines 'read / write' permissions */
mturner5 0:b7116bd48af6 199
mturner5 0:b7116bd48af6 200 /*@} end of group Cortex_M0 */
mturner5 0:b7116bd48af6 201
mturner5 0:b7116bd48af6 202
mturner5 0:b7116bd48af6 203
mturner5 0:b7116bd48af6 204 /*******************************************************************************
mturner5 0:b7116bd48af6 205 * Register Abstraction
mturner5 0:b7116bd48af6 206 Core Register contain:
mturner5 0:b7116bd48af6 207 - Core Register
mturner5 0:b7116bd48af6 208 - Core NVIC Register
mturner5 0:b7116bd48af6 209 - Core SCB Register
mturner5 0:b7116bd48af6 210 - Core SysTick Register
mturner5 0:b7116bd48af6 211 ******************************************************************************/
mturner5 0:b7116bd48af6 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
mturner5 0:b7116bd48af6 213 \brief Type definitions and defines for Cortex-M processor based devices.
mturner5 0:b7116bd48af6 214 */
mturner5 0:b7116bd48af6 215
mturner5 0:b7116bd48af6 216 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 217 \defgroup CMSIS_CORE Status and Control Registers
mturner5 0:b7116bd48af6 218 \brief Core Register type definitions.
mturner5 0:b7116bd48af6 219 @{
mturner5 0:b7116bd48af6 220 */
mturner5 0:b7116bd48af6 221
mturner5 0:b7116bd48af6 222 /** \brief Union type to access the Application Program Status Register (APSR).
mturner5 0:b7116bd48af6 223 */
mturner5 0:b7116bd48af6 224 typedef union
mturner5 0:b7116bd48af6 225 {
mturner5 0:b7116bd48af6 226 struct
mturner5 0:b7116bd48af6 227 {
mturner5 0:b7116bd48af6 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
mturner5 0:b7116bd48af6 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:b7116bd48af6 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:b7116bd48af6 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:b7116bd48af6 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:b7116bd48af6 233 } b; /*!< Structure used for bit access */
mturner5 0:b7116bd48af6 234 uint32_t w; /*!< Type used for word access */
mturner5 0:b7116bd48af6 235 } APSR_Type;
mturner5 0:b7116bd48af6 236
mturner5 0:b7116bd48af6 237 /* APSR Register Definitions */
mturner5 0:b7116bd48af6 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
mturner5 0:b7116bd48af6 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mturner5 0:b7116bd48af6 240
mturner5 0:b7116bd48af6 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mturner5 0:b7116bd48af6 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mturner5 0:b7116bd48af6 243
mturner5 0:b7116bd48af6 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
mturner5 0:b7116bd48af6 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mturner5 0:b7116bd48af6 246
mturner5 0:b7116bd48af6 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
mturner5 0:b7116bd48af6 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mturner5 0:b7116bd48af6 249
mturner5 0:b7116bd48af6 250
mturner5 0:b7116bd48af6 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mturner5 0:b7116bd48af6 252 */
mturner5 0:b7116bd48af6 253 typedef union
mturner5 0:b7116bd48af6 254 {
mturner5 0:b7116bd48af6 255 struct
mturner5 0:b7116bd48af6 256 {
mturner5 0:b7116bd48af6 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mturner5 0:b7116bd48af6 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mturner5 0:b7116bd48af6 259 } b; /*!< Structure used for bit access */
mturner5 0:b7116bd48af6 260 uint32_t w; /*!< Type used for word access */
mturner5 0:b7116bd48af6 261 } IPSR_Type;
mturner5 0:b7116bd48af6 262
mturner5 0:b7116bd48af6 263 /* IPSR Register Definitions */
mturner5 0:b7116bd48af6 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mturner5 0:b7116bd48af6 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mturner5 0:b7116bd48af6 266
mturner5 0:b7116bd48af6 267
mturner5 0:b7116bd48af6 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mturner5 0:b7116bd48af6 269 */
mturner5 0:b7116bd48af6 270 typedef union
mturner5 0:b7116bd48af6 271 {
mturner5 0:b7116bd48af6 272 struct
mturner5 0:b7116bd48af6 273 {
mturner5 0:b7116bd48af6 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mturner5 0:b7116bd48af6 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mturner5 0:b7116bd48af6 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mturner5 0:b7116bd48af6 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
mturner5 0:b7116bd48af6 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mturner5 0:b7116bd48af6 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mturner5 0:b7116bd48af6 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mturner5 0:b7116bd48af6 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mturner5 0:b7116bd48af6 282 } b; /*!< Structure used for bit access */
mturner5 0:b7116bd48af6 283 uint32_t w; /*!< Type used for word access */
mturner5 0:b7116bd48af6 284 } xPSR_Type;
mturner5 0:b7116bd48af6 285
mturner5 0:b7116bd48af6 286 /* xPSR Register Definitions */
mturner5 0:b7116bd48af6 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mturner5 0:b7116bd48af6 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mturner5 0:b7116bd48af6 289
mturner5 0:b7116bd48af6 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mturner5 0:b7116bd48af6 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mturner5 0:b7116bd48af6 292
mturner5 0:b7116bd48af6 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mturner5 0:b7116bd48af6 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mturner5 0:b7116bd48af6 295
mturner5 0:b7116bd48af6 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mturner5 0:b7116bd48af6 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mturner5 0:b7116bd48af6 298
mturner5 0:b7116bd48af6 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mturner5 0:b7116bd48af6 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mturner5 0:b7116bd48af6 301
mturner5 0:b7116bd48af6 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mturner5 0:b7116bd48af6 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mturner5 0:b7116bd48af6 304
mturner5 0:b7116bd48af6 305
mturner5 0:b7116bd48af6 306 /** \brief Union type to access the Control Registers (CONTROL).
mturner5 0:b7116bd48af6 307 */
mturner5 0:b7116bd48af6 308 typedef union
mturner5 0:b7116bd48af6 309 {
mturner5 0:b7116bd48af6 310 struct
mturner5 0:b7116bd48af6 311 {
mturner5 0:b7116bd48af6 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
mturner5 0:b7116bd48af6 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mturner5 0:b7116bd48af6 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mturner5 0:b7116bd48af6 315 } b; /*!< Structure used for bit access */
mturner5 0:b7116bd48af6 316 uint32_t w; /*!< Type used for word access */
mturner5 0:b7116bd48af6 317 } CONTROL_Type;
mturner5 0:b7116bd48af6 318
mturner5 0:b7116bd48af6 319 /* CONTROL Register Definitions */
mturner5 0:b7116bd48af6 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mturner5 0:b7116bd48af6 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mturner5 0:b7116bd48af6 322
mturner5 0:b7116bd48af6 323 /*@} end of group CMSIS_CORE */
mturner5 0:b7116bd48af6 324
mturner5 0:b7116bd48af6 325
mturner5 0:b7116bd48af6 326 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mturner5 0:b7116bd48af6 328 \brief Type definitions for the NVIC Registers
mturner5 0:b7116bd48af6 329 @{
mturner5 0:b7116bd48af6 330 */
mturner5 0:b7116bd48af6 331
mturner5 0:b7116bd48af6 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mturner5 0:b7116bd48af6 333 */
mturner5 0:b7116bd48af6 334 typedef struct
mturner5 0:b7116bd48af6 335 {
mturner5 0:b7116bd48af6 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mturner5 0:b7116bd48af6 337 uint32_t RESERVED0[31];
mturner5 0:b7116bd48af6 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mturner5 0:b7116bd48af6 339 uint32_t RSERVED1[31];
mturner5 0:b7116bd48af6 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mturner5 0:b7116bd48af6 341 uint32_t RESERVED2[31];
mturner5 0:b7116bd48af6 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mturner5 0:b7116bd48af6 343 uint32_t RESERVED3[31];
mturner5 0:b7116bd48af6 344 uint32_t RESERVED4[64];
mturner5 0:b7116bd48af6 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mturner5 0:b7116bd48af6 346 } NVIC_Type;
mturner5 0:b7116bd48af6 347
mturner5 0:b7116bd48af6 348 /*@} end of group CMSIS_NVIC */
mturner5 0:b7116bd48af6 349
mturner5 0:b7116bd48af6 350
mturner5 0:b7116bd48af6 351 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 352 \defgroup CMSIS_SCB System Control Block (SCB)
mturner5 0:b7116bd48af6 353 \brief Type definitions for the System Control Block Registers
mturner5 0:b7116bd48af6 354 @{
mturner5 0:b7116bd48af6 355 */
mturner5 0:b7116bd48af6 356
mturner5 0:b7116bd48af6 357 /** \brief Structure type to access the System Control Block (SCB).
mturner5 0:b7116bd48af6 358 */
mturner5 0:b7116bd48af6 359 typedef struct
mturner5 0:b7116bd48af6 360 {
mturner5 0:b7116bd48af6 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mturner5 0:b7116bd48af6 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mturner5 0:b7116bd48af6 363 uint32_t RESERVED0;
mturner5 0:b7116bd48af6 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mturner5 0:b7116bd48af6 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mturner5 0:b7116bd48af6 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mturner5 0:b7116bd48af6 367 uint32_t RESERVED1;
mturner5 0:b7116bd48af6 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mturner5 0:b7116bd48af6 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mturner5 0:b7116bd48af6 370 } SCB_Type;
mturner5 0:b7116bd48af6 371
mturner5 0:b7116bd48af6 372 /* SCB CPUID Register Definitions */
mturner5 0:b7116bd48af6 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mturner5 0:b7116bd48af6 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mturner5 0:b7116bd48af6 375
mturner5 0:b7116bd48af6 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mturner5 0:b7116bd48af6 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mturner5 0:b7116bd48af6 378
mturner5 0:b7116bd48af6 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mturner5 0:b7116bd48af6 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mturner5 0:b7116bd48af6 381
mturner5 0:b7116bd48af6 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mturner5 0:b7116bd48af6 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mturner5 0:b7116bd48af6 384
mturner5 0:b7116bd48af6 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mturner5 0:b7116bd48af6 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mturner5 0:b7116bd48af6 387
mturner5 0:b7116bd48af6 388 /* SCB Interrupt Control State Register Definitions */
mturner5 0:b7116bd48af6 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mturner5 0:b7116bd48af6 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mturner5 0:b7116bd48af6 391
mturner5 0:b7116bd48af6 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mturner5 0:b7116bd48af6 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mturner5 0:b7116bd48af6 394
mturner5 0:b7116bd48af6 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mturner5 0:b7116bd48af6 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mturner5 0:b7116bd48af6 397
mturner5 0:b7116bd48af6 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mturner5 0:b7116bd48af6 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mturner5 0:b7116bd48af6 400
mturner5 0:b7116bd48af6 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mturner5 0:b7116bd48af6 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mturner5 0:b7116bd48af6 403
mturner5 0:b7116bd48af6 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mturner5 0:b7116bd48af6 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mturner5 0:b7116bd48af6 406
mturner5 0:b7116bd48af6 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mturner5 0:b7116bd48af6 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mturner5 0:b7116bd48af6 409
mturner5 0:b7116bd48af6 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mturner5 0:b7116bd48af6 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mturner5 0:b7116bd48af6 412
mturner5 0:b7116bd48af6 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mturner5 0:b7116bd48af6 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mturner5 0:b7116bd48af6 415
mturner5 0:b7116bd48af6 416 /* SCB Application Interrupt and Reset Control Register Definitions */
mturner5 0:b7116bd48af6 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mturner5 0:b7116bd48af6 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mturner5 0:b7116bd48af6 419
mturner5 0:b7116bd48af6 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mturner5 0:b7116bd48af6 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mturner5 0:b7116bd48af6 422
mturner5 0:b7116bd48af6 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mturner5 0:b7116bd48af6 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mturner5 0:b7116bd48af6 425
mturner5 0:b7116bd48af6 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mturner5 0:b7116bd48af6 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mturner5 0:b7116bd48af6 428
mturner5 0:b7116bd48af6 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mturner5 0:b7116bd48af6 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mturner5 0:b7116bd48af6 431
mturner5 0:b7116bd48af6 432 /* SCB System Control Register Definitions */
mturner5 0:b7116bd48af6 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mturner5 0:b7116bd48af6 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mturner5 0:b7116bd48af6 435
mturner5 0:b7116bd48af6 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mturner5 0:b7116bd48af6 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mturner5 0:b7116bd48af6 438
mturner5 0:b7116bd48af6 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mturner5 0:b7116bd48af6 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mturner5 0:b7116bd48af6 441
mturner5 0:b7116bd48af6 442 /* SCB Configuration Control Register Definitions */
mturner5 0:b7116bd48af6 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mturner5 0:b7116bd48af6 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mturner5 0:b7116bd48af6 445
mturner5 0:b7116bd48af6 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mturner5 0:b7116bd48af6 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mturner5 0:b7116bd48af6 448
mturner5 0:b7116bd48af6 449 /* SCB System Handler Control and State Register Definitions */
mturner5 0:b7116bd48af6 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mturner5 0:b7116bd48af6 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mturner5 0:b7116bd48af6 452
mturner5 0:b7116bd48af6 453 /*@} end of group CMSIS_SCB */
mturner5 0:b7116bd48af6 454
mturner5 0:b7116bd48af6 455
mturner5 0:b7116bd48af6 456 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mturner5 0:b7116bd48af6 458 \brief Type definitions for the System Timer Registers.
mturner5 0:b7116bd48af6 459 @{
mturner5 0:b7116bd48af6 460 */
mturner5 0:b7116bd48af6 461
mturner5 0:b7116bd48af6 462 /** \brief Structure type to access the System Timer (SysTick).
mturner5 0:b7116bd48af6 463 */
mturner5 0:b7116bd48af6 464 typedef struct
mturner5 0:b7116bd48af6 465 {
mturner5 0:b7116bd48af6 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mturner5 0:b7116bd48af6 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mturner5 0:b7116bd48af6 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mturner5 0:b7116bd48af6 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mturner5 0:b7116bd48af6 470 } SysTick_Type;
mturner5 0:b7116bd48af6 471
mturner5 0:b7116bd48af6 472 /* SysTick Control / Status Register Definitions */
mturner5 0:b7116bd48af6 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mturner5 0:b7116bd48af6 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mturner5 0:b7116bd48af6 475
mturner5 0:b7116bd48af6 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mturner5 0:b7116bd48af6 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mturner5 0:b7116bd48af6 478
mturner5 0:b7116bd48af6 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mturner5 0:b7116bd48af6 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mturner5 0:b7116bd48af6 481
mturner5 0:b7116bd48af6 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mturner5 0:b7116bd48af6 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mturner5 0:b7116bd48af6 484
mturner5 0:b7116bd48af6 485 /* SysTick Reload Register Definitions */
mturner5 0:b7116bd48af6 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mturner5 0:b7116bd48af6 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mturner5 0:b7116bd48af6 488
mturner5 0:b7116bd48af6 489 /* SysTick Current Register Definitions */
mturner5 0:b7116bd48af6 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mturner5 0:b7116bd48af6 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mturner5 0:b7116bd48af6 492
mturner5 0:b7116bd48af6 493 /* SysTick Calibration Register Definitions */
mturner5 0:b7116bd48af6 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mturner5 0:b7116bd48af6 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mturner5 0:b7116bd48af6 496
mturner5 0:b7116bd48af6 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mturner5 0:b7116bd48af6 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mturner5 0:b7116bd48af6 499
mturner5 0:b7116bd48af6 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mturner5 0:b7116bd48af6 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mturner5 0:b7116bd48af6 502
mturner5 0:b7116bd48af6 503 /*@} end of group CMSIS_SysTick */
mturner5 0:b7116bd48af6 504
mturner5 0:b7116bd48af6 505
mturner5 0:b7116bd48af6 506 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mturner5 0:b7116bd48af6 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
mturner5 0:b7116bd48af6 509 are only accessible over DAP and not via processor. Therefore
mturner5 0:b7116bd48af6 510 they are not covered by the Cortex-M0 header file.
mturner5 0:b7116bd48af6 511 @{
mturner5 0:b7116bd48af6 512 */
mturner5 0:b7116bd48af6 513 /*@} end of group CMSIS_CoreDebug */
mturner5 0:b7116bd48af6 514
mturner5 0:b7116bd48af6 515
mturner5 0:b7116bd48af6 516 /** \ingroup CMSIS_core_register
mturner5 0:b7116bd48af6 517 \defgroup CMSIS_core_base Core Definitions
mturner5 0:b7116bd48af6 518 \brief Definitions for base addresses, unions, and structures.
mturner5 0:b7116bd48af6 519 @{
mturner5 0:b7116bd48af6 520 */
mturner5 0:b7116bd48af6 521
mturner5 0:b7116bd48af6 522 /* Memory mapping of Cortex-M0 Hardware */
mturner5 0:b7116bd48af6 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mturner5 0:b7116bd48af6 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mturner5 0:b7116bd48af6 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mturner5 0:b7116bd48af6 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mturner5 0:b7116bd48af6 527
mturner5 0:b7116bd48af6 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mturner5 0:b7116bd48af6 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mturner5 0:b7116bd48af6 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mturner5 0:b7116bd48af6 531
mturner5 0:b7116bd48af6 532
mturner5 0:b7116bd48af6 533 /*@} */
mturner5 0:b7116bd48af6 534
mturner5 0:b7116bd48af6 535
mturner5 0:b7116bd48af6 536
mturner5 0:b7116bd48af6 537 /*******************************************************************************
mturner5 0:b7116bd48af6 538 * Hardware Abstraction Layer
mturner5 0:b7116bd48af6 539 Core Function Interface contains:
mturner5 0:b7116bd48af6 540 - Core NVIC Functions
mturner5 0:b7116bd48af6 541 - Core SysTick Functions
mturner5 0:b7116bd48af6 542 - Core Register Access Functions
mturner5 0:b7116bd48af6 543 ******************************************************************************/
mturner5 0:b7116bd48af6 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mturner5 0:b7116bd48af6 545 */
mturner5 0:b7116bd48af6 546
mturner5 0:b7116bd48af6 547
mturner5 0:b7116bd48af6 548
mturner5 0:b7116bd48af6 549 /* ########################## NVIC functions #################################### */
mturner5 0:b7116bd48af6 550 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:b7116bd48af6 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mturner5 0:b7116bd48af6 552 \brief Functions that manage interrupts and exceptions via the NVIC.
mturner5 0:b7116bd48af6 553 @{
mturner5 0:b7116bd48af6 554 */
mturner5 0:b7116bd48af6 555
mturner5 0:b7116bd48af6 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mturner5 0:b7116bd48af6 557 /* The following MACROS handle generation of the register offset and byte masks */
mturner5 0:b7116bd48af6 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mturner5 0:b7116bd48af6 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mturner5 0:b7116bd48af6 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mturner5 0:b7116bd48af6 561
mturner5 0:b7116bd48af6 562
mturner5 0:b7116bd48af6 563 /** \brief Enable External Interrupt
mturner5 0:b7116bd48af6 564
mturner5 0:b7116bd48af6 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
mturner5 0:b7116bd48af6 566
mturner5 0:b7116bd48af6 567 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:b7116bd48af6 568 */
mturner5 0:b7116bd48af6 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mturner5 0:b7116bd48af6 570 {
mturner5 0:b7116bd48af6 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5 0:b7116bd48af6 572 }
mturner5 0:b7116bd48af6 573
mturner5 0:b7116bd48af6 574
mturner5 0:b7116bd48af6 575 /** \brief Disable External Interrupt
mturner5 0:b7116bd48af6 576
mturner5 0:b7116bd48af6 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
mturner5 0:b7116bd48af6 578
mturner5 0:b7116bd48af6 579 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:b7116bd48af6 580 */
mturner5 0:b7116bd48af6 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mturner5 0:b7116bd48af6 582 {
mturner5 0:b7116bd48af6 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5 0:b7116bd48af6 584 }
mturner5 0:b7116bd48af6 585
mturner5 0:b7116bd48af6 586
mturner5 0:b7116bd48af6 587 /** \brief Get Pending Interrupt
mturner5 0:b7116bd48af6 588
mturner5 0:b7116bd48af6 589 The function reads the pending register in the NVIC and returns the pending bit
mturner5 0:b7116bd48af6 590 for the specified interrupt.
mturner5 0:b7116bd48af6 591
mturner5 0:b7116bd48af6 592 \param [in] IRQn Interrupt number.
mturner5 0:b7116bd48af6 593
mturner5 0:b7116bd48af6 594 \return 0 Interrupt status is not pending.
mturner5 0:b7116bd48af6 595 \return 1 Interrupt status is pending.
mturner5 0:b7116bd48af6 596 */
mturner5 0:b7116bd48af6 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mturner5 0:b7116bd48af6 598 {
mturner5 0:b7116bd48af6 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mturner5 0:b7116bd48af6 600 }
mturner5 0:b7116bd48af6 601
mturner5 0:b7116bd48af6 602
mturner5 0:b7116bd48af6 603 /** \brief Set Pending Interrupt
mturner5 0:b7116bd48af6 604
mturner5 0:b7116bd48af6 605 The function sets the pending bit of an external interrupt.
mturner5 0:b7116bd48af6 606
mturner5 0:b7116bd48af6 607 \param [in] IRQn Interrupt number. Value cannot be negative.
mturner5 0:b7116bd48af6 608 */
mturner5 0:b7116bd48af6 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mturner5 0:b7116bd48af6 610 {
mturner5 0:b7116bd48af6 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5 0:b7116bd48af6 612 }
mturner5 0:b7116bd48af6 613
mturner5 0:b7116bd48af6 614
mturner5 0:b7116bd48af6 615 /** \brief Clear Pending Interrupt
mturner5 0:b7116bd48af6 616
mturner5 0:b7116bd48af6 617 The function clears the pending bit of an external interrupt.
mturner5 0:b7116bd48af6 618
mturner5 0:b7116bd48af6 619 \param [in] IRQn External interrupt number. Value cannot be negative.
mturner5 0:b7116bd48af6 620 */
mturner5 0:b7116bd48af6 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mturner5 0:b7116bd48af6 622 {
mturner5 0:b7116bd48af6 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mturner5 0:b7116bd48af6 624 }
mturner5 0:b7116bd48af6 625
mturner5 0:b7116bd48af6 626
mturner5 0:b7116bd48af6 627 /** \brief Set Interrupt Priority
mturner5 0:b7116bd48af6 628
mturner5 0:b7116bd48af6 629 The function sets the priority of an interrupt.
mturner5 0:b7116bd48af6 630
mturner5 0:b7116bd48af6 631 \note The priority cannot be set for every core interrupt.
mturner5 0:b7116bd48af6 632
mturner5 0:b7116bd48af6 633 \param [in] IRQn Interrupt number.
mturner5 0:b7116bd48af6 634 \param [in] priority Priority to set.
mturner5 0:b7116bd48af6 635 */
mturner5 0:b7116bd48af6 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mturner5 0:b7116bd48af6 637 {
mturner5 0:b7116bd48af6 638 if((int32_t)(IRQn) < 0) {
mturner5 0:b7116bd48af6 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mturner5 0:b7116bd48af6 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mturner5 0:b7116bd48af6 641 }
mturner5 0:b7116bd48af6 642 else {
mturner5 0:b7116bd48af6 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mturner5 0:b7116bd48af6 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mturner5 0:b7116bd48af6 645 }
mturner5 0:b7116bd48af6 646 }
mturner5 0:b7116bd48af6 647
mturner5 0:b7116bd48af6 648
mturner5 0:b7116bd48af6 649 /** \brief Get Interrupt Priority
mturner5 0:b7116bd48af6 650
mturner5 0:b7116bd48af6 651 The function reads the priority of an interrupt. The interrupt
mturner5 0:b7116bd48af6 652 number can be positive to specify an external (device specific)
mturner5 0:b7116bd48af6 653 interrupt, or negative to specify an internal (core) interrupt.
mturner5 0:b7116bd48af6 654
mturner5 0:b7116bd48af6 655
mturner5 0:b7116bd48af6 656 \param [in] IRQn Interrupt number.
mturner5 0:b7116bd48af6 657 \return Interrupt Priority. Value is aligned automatically to the implemented
mturner5 0:b7116bd48af6 658 priority bits of the microcontroller.
mturner5 0:b7116bd48af6 659 */
mturner5 0:b7116bd48af6 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mturner5 0:b7116bd48af6 661 {
mturner5 0:b7116bd48af6 662
mturner5 0:b7116bd48af6 663 if((int32_t)(IRQn) < 0) {
mturner5 0:b7116bd48af6 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mturner5 0:b7116bd48af6 665 }
mturner5 0:b7116bd48af6 666 else {
mturner5 0:b7116bd48af6 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mturner5 0:b7116bd48af6 668 }
mturner5 0:b7116bd48af6 669 }
mturner5 0:b7116bd48af6 670
mturner5 0:b7116bd48af6 671
mturner5 0:b7116bd48af6 672 /** \brief System Reset
mturner5 0:b7116bd48af6 673
mturner5 0:b7116bd48af6 674 The function initiates a system reset request to reset the MCU.
mturner5 0:b7116bd48af6 675 */
mturner5 0:b7116bd48af6 676 __STATIC_INLINE void NVIC_SystemReset(void)
mturner5 0:b7116bd48af6 677 {
mturner5 0:b7116bd48af6 678 __DSB(); /* Ensure all outstanding memory accesses included
mturner5 0:b7116bd48af6 679 buffered write are completed before reset */
mturner5 0:b7116bd48af6 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mturner5 0:b7116bd48af6 681 SCB_AIRCR_SYSRESETREQ_Msk);
mturner5 0:b7116bd48af6 682 __DSB(); /* Ensure completion of memory access */
mturner5 0:b7116bd48af6 683 while(1) { __NOP(); } /* wait until reset */
mturner5 0:b7116bd48af6 684 }
mturner5 0:b7116bd48af6 685
mturner5 0:b7116bd48af6 686 /*@} end of CMSIS_Core_NVICFunctions */
mturner5 0:b7116bd48af6 687
mturner5 0:b7116bd48af6 688
mturner5 0:b7116bd48af6 689
mturner5 0:b7116bd48af6 690 /* ################################## SysTick function ############################################ */
mturner5 0:b7116bd48af6 691 /** \ingroup CMSIS_Core_FunctionInterface
mturner5 0:b7116bd48af6 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mturner5 0:b7116bd48af6 693 \brief Functions that configure the System.
mturner5 0:b7116bd48af6 694 @{
mturner5 0:b7116bd48af6 695 */
mturner5 0:b7116bd48af6 696
mturner5 0:b7116bd48af6 697 #if (__Vendor_SysTickConfig == 0)
mturner5 0:b7116bd48af6 698
mturner5 0:b7116bd48af6 699 /** \brief System Tick Configuration
mturner5 0:b7116bd48af6 700
mturner5 0:b7116bd48af6 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mturner5 0:b7116bd48af6 702 Counter is in free running mode to generate periodic interrupts.
mturner5 0:b7116bd48af6 703
mturner5 0:b7116bd48af6 704 \param [in] ticks Number of ticks between two interrupts.
mturner5 0:b7116bd48af6 705
mturner5 0:b7116bd48af6 706 \return 0 Function succeeded.
mturner5 0:b7116bd48af6 707 \return 1 Function failed.
mturner5 0:b7116bd48af6 708
mturner5 0:b7116bd48af6 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mturner5 0:b7116bd48af6 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mturner5 0:b7116bd48af6 711 must contain a vendor-specific implementation of this function.
mturner5 0:b7116bd48af6 712
mturner5 0:b7116bd48af6 713 */
mturner5 0:b7116bd48af6 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mturner5 0:b7116bd48af6 715 {
mturner5 0:b7116bd48af6 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
mturner5 0:b7116bd48af6 717
mturner5 0:b7116bd48af6 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mturner5 0:b7116bd48af6 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mturner5 0:b7116bd48af6 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mturner5 0:b7116bd48af6 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mturner5 0:b7116bd48af6 722 SysTick_CTRL_TICKINT_Msk |
mturner5 0:b7116bd48af6 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mturner5 0:b7116bd48af6 724 return (0UL); /* Function successful */
mturner5 0:b7116bd48af6 725 }
mturner5 0:b7116bd48af6 726
mturner5 0:b7116bd48af6 727 #endif
mturner5 0:b7116bd48af6 728
mturner5 0:b7116bd48af6 729 /*@} end of CMSIS_Core_SysTickFunctions */
mturner5 0:b7116bd48af6 730
mturner5 0:b7116bd48af6 731
mturner5 0:b7116bd48af6 732
mturner5 0:b7116bd48af6 733
mturner5 0:b7116bd48af6 734 #ifdef __cplusplus
mturner5 0:b7116bd48af6 735 }
mturner5 0:b7116bd48af6 736 #endif
mturner5 0:b7116bd48af6 737
mturner5 0:b7116bd48af6 738 #endif /* __CORE_CM0_H_DEPENDANT */
mturner5 0:b7116bd48af6 739
mturner5 0:b7116bd48af6 740 #endif /* __CMSIS_GENERIC */