Mark Turner / Mbed 2 deprecated lightsense_kl46z_basic_v2

Tried to initialize the buttons and slider but couldn't get it to work.

Dependencies:   mbed

mbed/TARGET_KL46Z/MKL46Z4.h@0:0d6b77c9ae01, 2016-09-19 (annotated)

Committer:
mturner5
Date:
Mon Sep 19 03:28:41 2016 +0000
Revision:
0:0d6b77c9ae01
basic v2;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mturner5 0:0d6b77c9ae01 1 /*
mturner5 0:0d6b77c9ae01 2 ** ###################################################################
mturner5 0:0d6b77c9ae01 3 ** Processors: MKL46Z256VLH4
mturner5 0:0d6b77c9ae01 4 ** MKL46Z128VLH4
mturner5 0:0d6b77c9ae01 5 ** MKL46Z256VLL4
mturner5 0:0d6b77c9ae01 6 ** MKL46Z128VLL4
mturner5 0:0d6b77c9ae01 7 ** MKL46Z256VMC4
mturner5 0:0d6b77c9ae01 8 ** MKL46Z128VMC4
mturner5 0:0d6b77c9ae01 9 **
mturner5 0:0d6b77c9ae01 10 ** Compilers: ARM Compiler
mturner5 0:0d6b77c9ae01 11 ** Freescale C/C++ for Embedded ARM
mturner5 0:0d6b77c9ae01 12 ** GNU C Compiler
mturner5 0:0d6b77c9ae01 13 ** IAR ANSI C/C++ Compiler for ARM
mturner5 0:0d6b77c9ae01 14 **
mturner5 0:0d6b77c9ae01 15 ** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
mturner5 0:0d6b77c9ae01 16 ** Version: rev. 2.2, 2013-04-12
mturner5 0:0d6b77c9ae01 17 **
mturner5 0:0d6b77c9ae01 18 ** Abstract:
mturner5 0:0d6b77c9ae01 19 ** CMSIS Peripheral Access Layer for MKL46Z4
mturner5 0:0d6b77c9ae01 20 **
mturner5 0:0d6b77c9ae01 21 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
mturner5 0:0d6b77c9ae01 22 **
mturner5 0:0d6b77c9ae01 23 ** http: www.freescale.com
mturner5 0:0d6b77c9ae01 24 ** mail: support@freescale.com
mturner5 0:0d6b77c9ae01 25 **
mturner5 0:0d6b77c9ae01 26 ** Revisions:
mturner5 0:0d6b77c9ae01 27 ** - rev. 1.0 (2012-10-16)
mturner5 0:0d6b77c9ae01 28 ** Initial version.
mturner5 0:0d6b77c9ae01 29 ** - rev. 2.0 (2012-12-12)
mturner5 0:0d6b77c9ae01 30 ** Update to reference manual rev. 1.
mturner5 0:0d6b77c9ae01 31 ** - rev. 2.1 (2013-04-05)
mturner5 0:0d6b77c9ae01 32 ** Changed start of doxygen comment.
mturner5 0:0d6b77c9ae01 33 ** - rev. 2.2 (2013-04-12)
mturner5 0:0d6b77c9ae01 34 ** SystemInit function fixed for clock configuration 1.
mturner5 0:0d6b77c9ae01 35 ** Name of the interrupt num. 31 updated to reflect proper function.
mturner5 0:0d6b77c9ae01 36 **
mturner5 0:0d6b77c9ae01 37 ** ###################################################################
mturner5 0:0d6b77c9ae01 38 */
mturner5 0:0d6b77c9ae01 39
mturner5 0:0d6b77c9ae01 40 /*!
mturner5 0:0d6b77c9ae01 41 * @file MKL46Z4.h
mturner5 0:0d6b77c9ae01 42 * @version 2.2
mturner5 0:0d6b77c9ae01 43 * @date 2013-04-12
mturner5 0:0d6b77c9ae01 44 * @brief CMSIS Peripheral Access Layer for MKL46Z4
mturner5 0:0d6b77c9ae01 45 *
mturner5 0:0d6b77c9ae01 46 * CMSIS Peripheral Access Layer for MKL46Z4
mturner5 0:0d6b77c9ae01 47 */
mturner5 0:0d6b77c9ae01 48
mturner5 0:0d6b77c9ae01 49 #if !defined(MKL46Z4_H_)
mturner5 0:0d6b77c9ae01 50 #define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
mturner5 0:0d6b77c9ae01 51
mturner5 0:0d6b77c9ae01 52 /** Memory map major version (memory maps with equal major version number are
mturner5 0:0d6b77c9ae01 53 * compatible) */
mturner5 0:0d6b77c9ae01 54 #define MCU_MEM_MAP_VERSION 0x0200u
mturner5 0:0d6b77c9ae01 55 /** Memory map minor version */
mturner5 0:0d6b77c9ae01 56 #define MCU_MEM_MAP_VERSION_MINOR 0x0002u
mturner5 0:0d6b77c9ae01 57
mturner5 0:0d6b77c9ae01 58
mturner5 0:0d6b77c9ae01 59 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 60 -- Interrupt vector numbers
mturner5 0:0d6b77c9ae01 61 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 62
mturner5 0:0d6b77c9ae01 63 /*!
mturner5 0:0d6b77c9ae01 64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mturner5 0:0d6b77c9ae01 65 * @{
mturner5 0:0d6b77c9ae01 66 */
mturner5 0:0d6b77c9ae01 67
mturner5 0:0d6b77c9ae01 68 /** Interrupt Number Definitions */
mturner5 0:0d6b77c9ae01 69 typedef enum IRQn {
mturner5 0:0d6b77c9ae01 70 /* Core interrupts */
mturner5 0:0d6b77c9ae01 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mturner5 0:0d6b77c9ae01 72 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
mturner5 0:0d6b77c9ae01 73 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
mturner5 0:0d6b77c9ae01 74 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
mturner5 0:0d6b77c9ae01 75 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
mturner5 0:0d6b77c9ae01 76
mturner5 0:0d6b77c9ae01 77 /* Device specific interrupts */
mturner5 0:0d6b77c9ae01 78 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
mturner5 0:0d6b77c9ae01 79 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
mturner5 0:0d6b77c9ae01 80 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
mturner5 0:0d6b77c9ae01 81 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
mturner5 0:0d6b77c9ae01 82 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
mturner5 0:0d6b77c9ae01 83 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
mturner5 0:0d6b77c9ae01 84 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
mturner5 0:0d6b77c9ae01 85 LLW_IRQn = 7, /**< Low Leakage Wakeup */
mturner5 0:0d6b77c9ae01 86 I2C0_IRQn = 8, /**< I2C0 interrupt */
mturner5 0:0d6b77c9ae01 87 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
mturner5 0:0d6b77c9ae01 88 SPI0_IRQn = 10, /**< SPI0 interrupt */
mturner5 0:0d6b77c9ae01 89 SPI1_IRQn = 11, /**< SPI1 interrupt */
mturner5 0:0d6b77c9ae01 90 UART0_IRQn = 12, /**< UART0 status/error interrupt */
mturner5 0:0d6b77c9ae01 91 UART1_IRQn = 13, /**< UART1 status/error interrupt */
mturner5 0:0d6b77c9ae01 92 UART2_IRQn = 14, /**< UART2 status/error interrupt */
mturner5 0:0d6b77c9ae01 93 ADC0_IRQn = 15, /**< ADC0 interrupt */
mturner5 0:0d6b77c9ae01 94 CMP0_IRQn = 16, /**< CMP0 interrupt */
mturner5 0:0d6b77c9ae01 95 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
mturner5 0:0d6b77c9ae01 96 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
mturner5 0:0d6b77c9ae01 97 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
mturner5 0:0d6b77c9ae01 98 RTC_IRQn = 20, /**< RTC interrupt */
mturner5 0:0d6b77c9ae01 99 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
mturner5 0:0d6b77c9ae01 100 PIT_IRQn = 22, /**< PIT timer interrupt */
mturner5 0:0d6b77c9ae01 101 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
mturner5 0:0d6b77c9ae01 102 USB0_IRQn = 24, /**< USB0 interrupt */
mturner5 0:0d6b77c9ae01 103 DAC0_IRQn = 25, /**< DAC0 interrupt */
mturner5 0:0d6b77c9ae01 104 TSI0_IRQn = 26, /**< TSI0 interrupt */
mturner5 0:0d6b77c9ae01 105 MCG_IRQn = 27, /**< MCG interrupt */
mturner5 0:0d6b77c9ae01 106 LPTimer_IRQn = 28, /**< LPTimer interrupt */
mturner5 0:0d6b77c9ae01 107 LCD_IRQn = 29, /**< Segment LCD Interrupt */
mturner5 0:0d6b77c9ae01 108 PORTA_IRQn = 30, /**< Port A interrupt */
mturner5 0:0d6b77c9ae01 109 PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */
mturner5 0:0d6b77c9ae01 110 } IRQn_Type;
mturner5 0:0d6b77c9ae01 111
mturner5 0:0d6b77c9ae01 112 /*!
mturner5 0:0d6b77c9ae01 113 * @}
mturner5 0:0d6b77c9ae01 114 */ /* end of group Interrupt_vector_numbers */
mturner5 0:0d6b77c9ae01 115
mturner5 0:0d6b77c9ae01 116
mturner5 0:0d6b77c9ae01 117 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 118 -- Cortex M0 Core Configuration
mturner5 0:0d6b77c9ae01 119 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 120
mturner5 0:0d6b77c9ae01 121 /*!
mturner5 0:0d6b77c9ae01 122 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
mturner5 0:0d6b77c9ae01 123 * @{
mturner5 0:0d6b77c9ae01 124 */
mturner5 0:0d6b77c9ae01 125
mturner5 0:0d6b77c9ae01 126 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
mturner5 0:0d6b77c9ae01 127 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mturner5 0:0d6b77c9ae01 128 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
mturner5 0:0d6b77c9ae01 129 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
mturner5 0:0d6b77c9ae01 130 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mturner5 0:0d6b77c9ae01 131
mturner5 0:0d6b77c9ae01 132 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
mturner5 0:0d6b77c9ae01 133 #include "system_MKL46Z4.h" /* Device specific configuration file */
mturner5 0:0d6b77c9ae01 134
mturner5 0:0d6b77c9ae01 135 /*!
mturner5 0:0d6b77c9ae01 136 * @}
mturner5 0:0d6b77c9ae01 137 */ /* end of group Cortex_Core_Configuration */
mturner5 0:0d6b77c9ae01 138
mturner5 0:0d6b77c9ae01 139
mturner5 0:0d6b77c9ae01 140 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 141 -- Device Peripheral Access Layer
mturner5 0:0d6b77c9ae01 142 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 143
mturner5 0:0d6b77c9ae01 144 /*!
mturner5 0:0d6b77c9ae01 145 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mturner5 0:0d6b77c9ae01 146 * @{
mturner5 0:0d6b77c9ae01 147 */
mturner5 0:0d6b77c9ae01 148
mturner5 0:0d6b77c9ae01 149
mturner5 0:0d6b77c9ae01 150 /*
mturner5 0:0d6b77c9ae01 151 ** Start of section using anonymous unions
mturner5 0:0d6b77c9ae01 152 */
mturner5 0:0d6b77c9ae01 153
mturner5 0:0d6b77c9ae01 154 #if defined(__ARMCC_VERSION)
mturner5 0:0d6b77c9ae01 155 #pragma push
mturner5 0:0d6b77c9ae01 156 #pragma anon_unions
mturner5 0:0d6b77c9ae01 157 #elif defined(__CWCC__)
mturner5 0:0d6b77c9ae01 158 #pragma push
mturner5 0:0d6b77c9ae01 159 #pragma cpp_extensions on
mturner5 0:0d6b77c9ae01 160 #elif defined(__GNUC__)
mturner5 0:0d6b77c9ae01 161 /* anonymous unions are enabled by default */
mturner5 0:0d6b77c9ae01 162 #elif defined(__IAR_SYSTEMS_ICC__)
mturner5 0:0d6b77c9ae01 163 #pragma language=extended
mturner5 0:0d6b77c9ae01 164 #else
mturner5 0:0d6b77c9ae01 165 #error Not supported compiler type
mturner5 0:0d6b77c9ae01 166 #endif
mturner5 0:0d6b77c9ae01 167
mturner5 0:0d6b77c9ae01 168 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 169 -- ADC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 170 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 171
mturner5 0:0d6b77c9ae01 172 /*!
mturner5 0:0d6b77c9ae01 173 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 174 * @{
mturner5 0:0d6b77c9ae01 175 */
mturner5 0:0d6b77c9ae01 176
mturner5 0:0d6b77c9ae01 177 /** ADC - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 178 typedef struct {
mturner5 0:0d6b77c9ae01 179 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 180 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mturner5 0:0d6b77c9ae01 181 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mturner5 0:0d6b77c9ae01 182 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mturner5 0:0d6b77c9ae01 183 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mturner5 0:0d6b77c9ae01 184 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mturner5 0:0d6b77c9ae01 185 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mturner5 0:0d6b77c9ae01 186 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mturner5 0:0d6b77c9ae01 187 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mturner5 0:0d6b77c9ae01 188 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mturner5 0:0d6b77c9ae01 189 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mturner5 0:0d6b77c9ae01 190 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mturner5 0:0d6b77c9ae01 191 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mturner5 0:0d6b77c9ae01 192 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mturner5 0:0d6b77c9ae01 193 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mturner5 0:0d6b77c9ae01 194 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mturner5 0:0d6b77c9ae01 195 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mturner5 0:0d6b77c9ae01 196 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mturner5 0:0d6b77c9ae01 197 uint8_t RESERVED_0[4];
mturner5 0:0d6b77c9ae01 198 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mturner5 0:0d6b77c9ae01 199 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mturner5 0:0d6b77c9ae01 200 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mturner5 0:0d6b77c9ae01 201 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mturner5 0:0d6b77c9ae01 202 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mturner5 0:0d6b77c9ae01 203 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mturner5 0:0d6b77c9ae01 204 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mturner5 0:0d6b77c9ae01 205 } ADC_Type;
mturner5 0:0d6b77c9ae01 206
mturner5 0:0d6b77c9ae01 207 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 208 -- ADC Register Masks
mturner5 0:0d6b77c9ae01 209 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 210
mturner5 0:0d6b77c9ae01 211 /*!
mturner5 0:0d6b77c9ae01 212 * @addtogroup ADC_Register_Masks ADC Register Masks
mturner5 0:0d6b77c9ae01 213 * @{
mturner5 0:0d6b77c9ae01 214 */
mturner5 0:0d6b77c9ae01 215
mturner5 0:0d6b77c9ae01 216 /* SC1 Bit Fields */
mturner5 0:0d6b77c9ae01 217 #define ADC_SC1_ADCH_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 218 #define ADC_SC1_ADCH_SHIFT 0
mturner5 0:0d6b77c9ae01 219 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mturner5 0:0d6b77c9ae01 220 #define ADC_SC1_DIFF_MASK 0x20u
mturner5 0:0d6b77c9ae01 221 #define ADC_SC1_DIFF_SHIFT 5
mturner5 0:0d6b77c9ae01 222 #define ADC_SC1_AIEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 223 #define ADC_SC1_AIEN_SHIFT 6
mturner5 0:0d6b77c9ae01 224 #define ADC_SC1_COCO_MASK 0x80u
mturner5 0:0d6b77c9ae01 225 #define ADC_SC1_COCO_SHIFT 7
mturner5 0:0d6b77c9ae01 226 /* CFG1 Bit Fields */
mturner5 0:0d6b77c9ae01 227 #define ADC_CFG1_ADICLK_MASK 0x3u
mturner5 0:0d6b77c9ae01 228 #define ADC_CFG1_ADICLK_SHIFT 0
mturner5 0:0d6b77c9ae01 229 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mturner5 0:0d6b77c9ae01 230 #define ADC_CFG1_MODE_MASK 0xCu
mturner5 0:0d6b77c9ae01 231 #define ADC_CFG1_MODE_SHIFT 2
mturner5 0:0d6b77c9ae01 232 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mturner5 0:0d6b77c9ae01 233 #define ADC_CFG1_ADLSMP_MASK 0x10u
mturner5 0:0d6b77c9ae01 234 #define ADC_CFG1_ADLSMP_SHIFT 4
mturner5 0:0d6b77c9ae01 235 #define ADC_CFG1_ADIV_MASK 0x60u
mturner5 0:0d6b77c9ae01 236 #define ADC_CFG1_ADIV_SHIFT 5
mturner5 0:0d6b77c9ae01 237 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mturner5 0:0d6b77c9ae01 238 #define ADC_CFG1_ADLPC_MASK 0x80u
mturner5 0:0d6b77c9ae01 239 #define ADC_CFG1_ADLPC_SHIFT 7
mturner5 0:0d6b77c9ae01 240 /* CFG2 Bit Fields */
mturner5 0:0d6b77c9ae01 241 #define ADC_CFG2_ADLSTS_MASK 0x3u
mturner5 0:0d6b77c9ae01 242 #define ADC_CFG2_ADLSTS_SHIFT 0
mturner5 0:0d6b77c9ae01 243 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mturner5 0:0d6b77c9ae01 244 #define ADC_CFG2_ADHSC_MASK 0x4u
mturner5 0:0d6b77c9ae01 245 #define ADC_CFG2_ADHSC_SHIFT 2
mturner5 0:0d6b77c9ae01 246 #define ADC_CFG2_ADACKEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 247 #define ADC_CFG2_ADACKEN_SHIFT 3
mturner5 0:0d6b77c9ae01 248 #define ADC_CFG2_MUXSEL_MASK 0x10u
mturner5 0:0d6b77c9ae01 249 #define ADC_CFG2_MUXSEL_SHIFT 4
mturner5 0:0d6b77c9ae01 250 /* R Bit Fields */
mturner5 0:0d6b77c9ae01 251 #define ADC_R_D_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 252 #define ADC_R_D_SHIFT 0
mturner5 0:0d6b77c9ae01 253 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mturner5 0:0d6b77c9ae01 254 /* CV1 Bit Fields */
mturner5 0:0d6b77c9ae01 255 #define ADC_CV1_CV_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 256 #define ADC_CV1_CV_SHIFT 0
mturner5 0:0d6b77c9ae01 257 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mturner5 0:0d6b77c9ae01 258 /* CV2 Bit Fields */
mturner5 0:0d6b77c9ae01 259 #define ADC_CV2_CV_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 260 #define ADC_CV2_CV_SHIFT 0
mturner5 0:0d6b77c9ae01 261 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mturner5 0:0d6b77c9ae01 262 /* SC2 Bit Fields */
mturner5 0:0d6b77c9ae01 263 #define ADC_SC2_REFSEL_MASK 0x3u
mturner5 0:0d6b77c9ae01 264 #define ADC_SC2_REFSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 265 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mturner5 0:0d6b77c9ae01 266 #define ADC_SC2_DMAEN_MASK 0x4u
mturner5 0:0d6b77c9ae01 267 #define ADC_SC2_DMAEN_SHIFT 2
mturner5 0:0d6b77c9ae01 268 #define ADC_SC2_ACREN_MASK 0x8u
mturner5 0:0d6b77c9ae01 269 #define ADC_SC2_ACREN_SHIFT 3
mturner5 0:0d6b77c9ae01 270 #define ADC_SC2_ACFGT_MASK 0x10u
mturner5 0:0d6b77c9ae01 271 #define ADC_SC2_ACFGT_SHIFT 4
mturner5 0:0d6b77c9ae01 272 #define ADC_SC2_ACFE_MASK 0x20u
mturner5 0:0d6b77c9ae01 273 #define ADC_SC2_ACFE_SHIFT 5
mturner5 0:0d6b77c9ae01 274 #define ADC_SC2_ADTRG_MASK 0x40u
mturner5 0:0d6b77c9ae01 275 #define ADC_SC2_ADTRG_SHIFT 6
mturner5 0:0d6b77c9ae01 276 #define ADC_SC2_ADACT_MASK 0x80u
mturner5 0:0d6b77c9ae01 277 #define ADC_SC2_ADACT_SHIFT 7
mturner5 0:0d6b77c9ae01 278 /* SC3 Bit Fields */
mturner5 0:0d6b77c9ae01 279 #define ADC_SC3_AVGS_MASK 0x3u
mturner5 0:0d6b77c9ae01 280 #define ADC_SC3_AVGS_SHIFT 0
mturner5 0:0d6b77c9ae01 281 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mturner5 0:0d6b77c9ae01 282 #define ADC_SC3_AVGE_MASK 0x4u
mturner5 0:0d6b77c9ae01 283 #define ADC_SC3_AVGE_SHIFT 2
mturner5 0:0d6b77c9ae01 284 #define ADC_SC3_ADCO_MASK 0x8u
mturner5 0:0d6b77c9ae01 285 #define ADC_SC3_ADCO_SHIFT 3
mturner5 0:0d6b77c9ae01 286 #define ADC_SC3_CALF_MASK 0x40u
mturner5 0:0d6b77c9ae01 287 #define ADC_SC3_CALF_SHIFT 6
mturner5 0:0d6b77c9ae01 288 #define ADC_SC3_CAL_MASK 0x80u
mturner5 0:0d6b77c9ae01 289 #define ADC_SC3_CAL_SHIFT 7
mturner5 0:0d6b77c9ae01 290 /* OFS Bit Fields */
mturner5 0:0d6b77c9ae01 291 #define ADC_OFS_OFS_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 292 #define ADC_OFS_OFS_SHIFT 0
mturner5 0:0d6b77c9ae01 293 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mturner5 0:0d6b77c9ae01 294 /* PG Bit Fields */
mturner5 0:0d6b77c9ae01 295 #define ADC_PG_PG_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 296 #define ADC_PG_PG_SHIFT 0
mturner5 0:0d6b77c9ae01 297 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mturner5 0:0d6b77c9ae01 298 /* MG Bit Fields */
mturner5 0:0d6b77c9ae01 299 #define ADC_MG_MG_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 300 #define ADC_MG_MG_SHIFT 0
mturner5 0:0d6b77c9ae01 301 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mturner5 0:0d6b77c9ae01 302 /* CLPD Bit Fields */
mturner5 0:0d6b77c9ae01 303 #define ADC_CLPD_CLPD_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 304 #define ADC_CLPD_CLPD_SHIFT 0
mturner5 0:0d6b77c9ae01 305 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mturner5 0:0d6b77c9ae01 306 /* CLPS Bit Fields */
mturner5 0:0d6b77c9ae01 307 #define ADC_CLPS_CLPS_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 308 #define ADC_CLPS_CLPS_SHIFT 0
mturner5 0:0d6b77c9ae01 309 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mturner5 0:0d6b77c9ae01 310 /* CLP4 Bit Fields */
mturner5 0:0d6b77c9ae01 311 #define ADC_CLP4_CLP4_MASK 0x3FFu
mturner5 0:0d6b77c9ae01 312 #define ADC_CLP4_CLP4_SHIFT 0
mturner5 0:0d6b77c9ae01 313 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mturner5 0:0d6b77c9ae01 314 /* CLP3 Bit Fields */
mturner5 0:0d6b77c9ae01 315 #define ADC_CLP3_CLP3_MASK 0x1FFu
mturner5 0:0d6b77c9ae01 316 #define ADC_CLP3_CLP3_SHIFT 0
mturner5 0:0d6b77c9ae01 317 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mturner5 0:0d6b77c9ae01 318 /* CLP2 Bit Fields */
mturner5 0:0d6b77c9ae01 319 #define ADC_CLP2_CLP2_MASK 0xFFu
mturner5 0:0d6b77c9ae01 320 #define ADC_CLP2_CLP2_SHIFT 0
mturner5 0:0d6b77c9ae01 321 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mturner5 0:0d6b77c9ae01 322 /* CLP1 Bit Fields */
mturner5 0:0d6b77c9ae01 323 #define ADC_CLP1_CLP1_MASK 0x7Fu
mturner5 0:0d6b77c9ae01 324 #define ADC_CLP1_CLP1_SHIFT 0
mturner5 0:0d6b77c9ae01 325 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mturner5 0:0d6b77c9ae01 326 /* CLP0 Bit Fields */
mturner5 0:0d6b77c9ae01 327 #define ADC_CLP0_CLP0_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 328 #define ADC_CLP0_CLP0_SHIFT 0
mturner5 0:0d6b77c9ae01 329 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mturner5 0:0d6b77c9ae01 330 /* CLMD Bit Fields */
mturner5 0:0d6b77c9ae01 331 #define ADC_CLMD_CLMD_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 332 #define ADC_CLMD_CLMD_SHIFT 0
mturner5 0:0d6b77c9ae01 333 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mturner5 0:0d6b77c9ae01 334 /* CLMS Bit Fields */
mturner5 0:0d6b77c9ae01 335 #define ADC_CLMS_CLMS_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 336 #define ADC_CLMS_CLMS_SHIFT 0
mturner5 0:0d6b77c9ae01 337 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mturner5 0:0d6b77c9ae01 338 /* CLM4 Bit Fields */
mturner5 0:0d6b77c9ae01 339 #define ADC_CLM4_CLM4_MASK 0x3FFu
mturner5 0:0d6b77c9ae01 340 #define ADC_CLM4_CLM4_SHIFT 0
mturner5 0:0d6b77c9ae01 341 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mturner5 0:0d6b77c9ae01 342 /* CLM3 Bit Fields */
mturner5 0:0d6b77c9ae01 343 #define ADC_CLM3_CLM3_MASK 0x1FFu
mturner5 0:0d6b77c9ae01 344 #define ADC_CLM3_CLM3_SHIFT 0
mturner5 0:0d6b77c9ae01 345 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mturner5 0:0d6b77c9ae01 346 /* CLM2 Bit Fields */
mturner5 0:0d6b77c9ae01 347 #define ADC_CLM2_CLM2_MASK 0xFFu
mturner5 0:0d6b77c9ae01 348 #define ADC_CLM2_CLM2_SHIFT 0
mturner5 0:0d6b77c9ae01 349 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mturner5 0:0d6b77c9ae01 350 /* CLM1 Bit Fields */
mturner5 0:0d6b77c9ae01 351 #define ADC_CLM1_CLM1_MASK 0x7Fu
mturner5 0:0d6b77c9ae01 352 #define ADC_CLM1_CLM1_SHIFT 0
mturner5 0:0d6b77c9ae01 353 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mturner5 0:0d6b77c9ae01 354 /* CLM0 Bit Fields */
mturner5 0:0d6b77c9ae01 355 #define ADC_CLM0_CLM0_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 356 #define ADC_CLM0_CLM0_SHIFT 0
mturner5 0:0d6b77c9ae01 357 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mturner5 0:0d6b77c9ae01 358
mturner5 0:0d6b77c9ae01 359 /*!
mturner5 0:0d6b77c9ae01 360 * @}
mturner5 0:0d6b77c9ae01 361 */ /* end of group ADC_Register_Masks */
mturner5 0:0d6b77c9ae01 362
mturner5 0:0d6b77c9ae01 363
mturner5 0:0d6b77c9ae01 364 /* ADC - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 365 /** Peripheral ADC0 base address */
mturner5 0:0d6b77c9ae01 366 #define ADC0_BASE (0x4003B000u)
mturner5 0:0d6b77c9ae01 367 /** Peripheral ADC0 base pointer */
mturner5 0:0d6b77c9ae01 368 #define ADC0 ((ADC_Type *)ADC0_BASE)
mturner5 0:0d6b77c9ae01 369 /** Array initializer of ADC peripheral base pointers */
mturner5 0:0d6b77c9ae01 370 #define ADC_BASES { ADC0 }
mturner5 0:0d6b77c9ae01 371
mturner5 0:0d6b77c9ae01 372 /*!
mturner5 0:0d6b77c9ae01 373 * @}
mturner5 0:0d6b77c9ae01 374 */ /* end of group ADC_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 375
mturner5 0:0d6b77c9ae01 376
mturner5 0:0d6b77c9ae01 377 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 378 -- CMP Peripheral Access Layer
mturner5 0:0d6b77c9ae01 379 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 380
mturner5 0:0d6b77c9ae01 381 /*!
mturner5 0:0d6b77c9ae01 382 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mturner5 0:0d6b77c9ae01 383 * @{
mturner5 0:0d6b77c9ae01 384 */
mturner5 0:0d6b77c9ae01 385
mturner5 0:0d6b77c9ae01 386 /** CMP - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 387 typedef struct {
mturner5 0:0d6b77c9ae01 388 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mturner5 0:0d6b77c9ae01 389 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mturner5 0:0d6b77c9ae01 390 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mturner5 0:0d6b77c9ae01 391 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mturner5 0:0d6b77c9ae01 392 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 393 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mturner5 0:0d6b77c9ae01 394 } CMP_Type;
mturner5 0:0d6b77c9ae01 395
mturner5 0:0d6b77c9ae01 396 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 397 -- CMP Register Masks
mturner5 0:0d6b77c9ae01 398 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 399
mturner5 0:0d6b77c9ae01 400 /*!
mturner5 0:0d6b77c9ae01 401 * @addtogroup CMP_Register_Masks CMP Register Masks
mturner5 0:0d6b77c9ae01 402 * @{
mturner5 0:0d6b77c9ae01 403 */
mturner5 0:0d6b77c9ae01 404
mturner5 0:0d6b77c9ae01 405 /* CR0 Bit Fields */
mturner5 0:0d6b77c9ae01 406 #define CMP_CR0_HYSTCTR_MASK 0x3u
mturner5 0:0d6b77c9ae01 407 #define CMP_CR0_HYSTCTR_SHIFT 0
mturner5 0:0d6b77c9ae01 408 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mturner5 0:0d6b77c9ae01 409 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mturner5 0:0d6b77c9ae01 410 #define CMP_CR0_FILTER_CNT_SHIFT 4
mturner5 0:0d6b77c9ae01 411 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mturner5 0:0d6b77c9ae01 412 /* CR1 Bit Fields */
mturner5 0:0d6b77c9ae01 413 #define CMP_CR1_EN_MASK 0x1u
mturner5 0:0d6b77c9ae01 414 #define CMP_CR1_EN_SHIFT 0
mturner5 0:0d6b77c9ae01 415 #define CMP_CR1_OPE_MASK 0x2u
mturner5 0:0d6b77c9ae01 416 #define CMP_CR1_OPE_SHIFT 1
mturner5 0:0d6b77c9ae01 417 #define CMP_CR1_COS_MASK 0x4u
mturner5 0:0d6b77c9ae01 418 #define CMP_CR1_COS_SHIFT 2
mturner5 0:0d6b77c9ae01 419 #define CMP_CR1_INV_MASK 0x8u
mturner5 0:0d6b77c9ae01 420 #define CMP_CR1_INV_SHIFT 3
mturner5 0:0d6b77c9ae01 421 #define CMP_CR1_PMODE_MASK 0x10u
mturner5 0:0d6b77c9ae01 422 #define CMP_CR1_PMODE_SHIFT 4
mturner5 0:0d6b77c9ae01 423 #define CMP_CR1_TRIGM_MASK 0x20u
mturner5 0:0d6b77c9ae01 424 #define CMP_CR1_TRIGM_SHIFT 5
mturner5 0:0d6b77c9ae01 425 #define CMP_CR1_WE_MASK 0x40u
mturner5 0:0d6b77c9ae01 426 #define CMP_CR1_WE_SHIFT 6
mturner5 0:0d6b77c9ae01 427 #define CMP_CR1_SE_MASK 0x80u
mturner5 0:0d6b77c9ae01 428 #define CMP_CR1_SE_SHIFT 7
mturner5 0:0d6b77c9ae01 429 /* FPR Bit Fields */
mturner5 0:0d6b77c9ae01 430 #define CMP_FPR_FILT_PER_MASK 0xFFu
mturner5 0:0d6b77c9ae01 431 #define CMP_FPR_FILT_PER_SHIFT 0
mturner5 0:0d6b77c9ae01 432 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mturner5 0:0d6b77c9ae01 433 /* SCR Bit Fields */
mturner5 0:0d6b77c9ae01 434 #define CMP_SCR_COUT_MASK 0x1u
mturner5 0:0d6b77c9ae01 435 #define CMP_SCR_COUT_SHIFT 0
mturner5 0:0d6b77c9ae01 436 #define CMP_SCR_CFF_MASK 0x2u
mturner5 0:0d6b77c9ae01 437 #define CMP_SCR_CFF_SHIFT 1
mturner5 0:0d6b77c9ae01 438 #define CMP_SCR_CFR_MASK 0x4u
mturner5 0:0d6b77c9ae01 439 #define CMP_SCR_CFR_SHIFT 2
mturner5 0:0d6b77c9ae01 440 #define CMP_SCR_IEF_MASK 0x8u
mturner5 0:0d6b77c9ae01 441 #define CMP_SCR_IEF_SHIFT 3
mturner5 0:0d6b77c9ae01 442 #define CMP_SCR_IER_MASK 0x10u
mturner5 0:0d6b77c9ae01 443 #define CMP_SCR_IER_SHIFT 4
mturner5 0:0d6b77c9ae01 444 #define CMP_SCR_DMAEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 445 #define CMP_SCR_DMAEN_SHIFT 6
mturner5 0:0d6b77c9ae01 446 /* DACCR Bit Fields */
mturner5 0:0d6b77c9ae01 447 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 448 #define CMP_DACCR_VOSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 449 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mturner5 0:0d6b77c9ae01 450 #define CMP_DACCR_VRSEL_MASK 0x40u
mturner5 0:0d6b77c9ae01 451 #define CMP_DACCR_VRSEL_SHIFT 6
mturner5 0:0d6b77c9ae01 452 #define CMP_DACCR_DACEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 453 #define CMP_DACCR_DACEN_SHIFT 7
mturner5 0:0d6b77c9ae01 454 /* MUXCR Bit Fields */
mturner5 0:0d6b77c9ae01 455 #define CMP_MUXCR_MSEL_MASK 0x7u
mturner5 0:0d6b77c9ae01 456 #define CMP_MUXCR_MSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 457 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mturner5 0:0d6b77c9ae01 458 #define CMP_MUXCR_PSEL_MASK 0x38u
mturner5 0:0d6b77c9ae01 459 #define CMP_MUXCR_PSEL_SHIFT 3
mturner5 0:0d6b77c9ae01 460 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mturner5 0:0d6b77c9ae01 461 #define CMP_MUXCR_PSTM_MASK 0x80u
mturner5 0:0d6b77c9ae01 462 #define CMP_MUXCR_PSTM_SHIFT 7
mturner5 0:0d6b77c9ae01 463
mturner5 0:0d6b77c9ae01 464 /*!
mturner5 0:0d6b77c9ae01 465 * @}
mturner5 0:0d6b77c9ae01 466 */ /* end of group CMP_Register_Masks */
mturner5 0:0d6b77c9ae01 467
mturner5 0:0d6b77c9ae01 468
mturner5 0:0d6b77c9ae01 469 /* CMP - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 470 /** Peripheral CMP0 base address */
mturner5 0:0d6b77c9ae01 471 #define CMP0_BASE (0x40073000u)
mturner5 0:0d6b77c9ae01 472 /** Peripheral CMP0 base pointer */
mturner5 0:0d6b77c9ae01 473 #define CMP0 ((CMP_Type *)CMP0_BASE)
mturner5 0:0d6b77c9ae01 474 /** Array initializer of CMP peripheral base pointers */
mturner5 0:0d6b77c9ae01 475 #define CMP_BASES { CMP0 }
mturner5 0:0d6b77c9ae01 476
mturner5 0:0d6b77c9ae01 477 /*!
mturner5 0:0d6b77c9ae01 478 * @}
mturner5 0:0d6b77c9ae01 479 */ /* end of group CMP_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 480
mturner5 0:0d6b77c9ae01 481
mturner5 0:0d6b77c9ae01 482 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 483 -- DAC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 484 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 485
mturner5 0:0d6b77c9ae01 486 /*!
mturner5 0:0d6b77c9ae01 487 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 488 * @{
mturner5 0:0d6b77c9ae01 489 */
mturner5 0:0d6b77c9ae01 490
mturner5 0:0d6b77c9ae01 491 /** DAC - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 492 typedef struct {
mturner5 0:0d6b77c9ae01 493 struct { /* offset: 0x0, array step: 0x2 */
mturner5 0:0d6b77c9ae01 494 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mturner5 0:0d6b77c9ae01 495 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mturner5 0:0d6b77c9ae01 496 } DAT[2];
mturner5 0:0d6b77c9ae01 497 uint8_t RESERVED_0[28];
mturner5 0:0d6b77c9ae01 498 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mturner5 0:0d6b77c9ae01 499 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mturner5 0:0d6b77c9ae01 500 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mturner5 0:0d6b77c9ae01 501 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mturner5 0:0d6b77c9ae01 502 } DAC_Type;
mturner5 0:0d6b77c9ae01 503
mturner5 0:0d6b77c9ae01 504 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 505 -- DAC Register Masks
mturner5 0:0d6b77c9ae01 506 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 507
mturner5 0:0d6b77c9ae01 508 /*!
mturner5 0:0d6b77c9ae01 509 * @addtogroup DAC_Register_Masks DAC Register Masks
mturner5 0:0d6b77c9ae01 510 * @{
mturner5 0:0d6b77c9ae01 511 */
mturner5 0:0d6b77c9ae01 512
mturner5 0:0d6b77c9ae01 513 /* DATL Bit Fields */
mturner5 0:0d6b77c9ae01 514 #define DAC_DATL_DATA0_MASK 0xFFu
mturner5 0:0d6b77c9ae01 515 #define DAC_DATL_DATA0_SHIFT 0
mturner5 0:0d6b77c9ae01 516 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mturner5 0:0d6b77c9ae01 517 /* DATH Bit Fields */
mturner5 0:0d6b77c9ae01 518 #define DAC_DATH_DATA1_MASK 0xFu
mturner5 0:0d6b77c9ae01 519 #define DAC_DATH_DATA1_SHIFT 0
mturner5 0:0d6b77c9ae01 520 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mturner5 0:0d6b77c9ae01 521 /* SR Bit Fields */
mturner5 0:0d6b77c9ae01 522 #define DAC_SR_DACBFRPBF_MASK 0x1u
mturner5 0:0d6b77c9ae01 523 #define DAC_SR_DACBFRPBF_SHIFT 0
mturner5 0:0d6b77c9ae01 524 #define DAC_SR_DACBFRPTF_MASK 0x2u
mturner5 0:0d6b77c9ae01 525 #define DAC_SR_DACBFRPTF_SHIFT 1
mturner5 0:0d6b77c9ae01 526 /* C0 Bit Fields */
mturner5 0:0d6b77c9ae01 527 #define DAC_C0_DACBBIEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 528 #define DAC_C0_DACBBIEN_SHIFT 0
mturner5 0:0d6b77c9ae01 529 #define DAC_C0_DACBTIEN_MASK 0x2u
mturner5 0:0d6b77c9ae01 530 #define DAC_C0_DACBTIEN_SHIFT 1
mturner5 0:0d6b77c9ae01 531 #define DAC_C0_LPEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 532 #define DAC_C0_LPEN_SHIFT 3
mturner5 0:0d6b77c9ae01 533 #define DAC_C0_DACSWTRG_MASK 0x10u
mturner5 0:0d6b77c9ae01 534 #define DAC_C0_DACSWTRG_SHIFT 4
mturner5 0:0d6b77c9ae01 535 #define DAC_C0_DACTRGSEL_MASK 0x20u
mturner5 0:0d6b77c9ae01 536 #define DAC_C0_DACTRGSEL_SHIFT 5
mturner5 0:0d6b77c9ae01 537 #define DAC_C0_DACRFS_MASK 0x40u
mturner5 0:0d6b77c9ae01 538 #define DAC_C0_DACRFS_SHIFT 6
mturner5 0:0d6b77c9ae01 539 #define DAC_C0_DACEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 540 #define DAC_C0_DACEN_SHIFT 7
mturner5 0:0d6b77c9ae01 541 /* C1 Bit Fields */
mturner5 0:0d6b77c9ae01 542 #define DAC_C1_DACBFEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 543 #define DAC_C1_DACBFEN_SHIFT 0
mturner5 0:0d6b77c9ae01 544 #define DAC_C1_DACBFMD_MASK 0x4u
mturner5 0:0d6b77c9ae01 545 #define DAC_C1_DACBFMD_SHIFT 2
mturner5 0:0d6b77c9ae01 546 #define DAC_C1_DMAEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 547 #define DAC_C1_DMAEN_SHIFT 7
mturner5 0:0d6b77c9ae01 548 /* C2 Bit Fields */
mturner5 0:0d6b77c9ae01 549 #define DAC_C2_DACBFUP_MASK 0x1u
mturner5 0:0d6b77c9ae01 550 #define DAC_C2_DACBFUP_SHIFT 0
mturner5 0:0d6b77c9ae01 551 #define DAC_C2_DACBFRP_MASK 0x10u
mturner5 0:0d6b77c9ae01 552 #define DAC_C2_DACBFRP_SHIFT 4
mturner5 0:0d6b77c9ae01 553
mturner5 0:0d6b77c9ae01 554 /*!
mturner5 0:0d6b77c9ae01 555 * @}
mturner5 0:0d6b77c9ae01 556 */ /* end of group DAC_Register_Masks */
mturner5 0:0d6b77c9ae01 557
mturner5 0:0d6b77c9ae01 558
mturner5 0:0d6b77c9ae01 559 /* DAC - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 560 /** Peripheral DAC0 base address */
mturner5 0:0d6b77c9ae01 561 #define DAC0_BASE (0x4003F000u)
mturner5 0:0d6b77c9ae01 562 /** Peripheral DAC0 base pointer */
mturner5 0:0d6b77c9ae01 563 #define DAC0 ((DAC_Type *)DAC0_BASE)
mturner5 0:0d6b77c9ae01 564 /** Array initializer of DAC peripheral base pointers */
mturner5 0:0d6b77c9ae01 565 #define DAC_BASES { DAC0 }
mturner5 0:0d6b77c9ae01 566
mturner5 0:0d6b77c9ae01 567 /*!
mturner5 0:0d6b77c9ae01 568 * @}
mturner5 0:0d6b77c9ae01 569 */ /* end of group DAC_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 570
mturner5 0:0d6b77c9ae01 571
mturner5 0:0d6b77c9ae01 572 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 573 -- DMA Peripheral Access Layer
mturner5 0:0d6b77c9ae01 574 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 575
mturner5 0:0d6b77c9ae01 576 /*!
mturner5 0:0d6b77c9ae01 577 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mturner5 0:0d6b77c9ae01 578 * @{
mturner5 0:0d6b77c9ae01 579 */
mturner5 0:0d6b77c9ae01 580
mturner5 0:0d6b77c9ae01 581 /** DMA - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 582 typedef struct {
mturner5 0:0d6b77c9ae01 583 uint8_t RESERVED_0[256];
mturner5 0:0d6b77c9ae01 584 struct { /* offset: 0x100, array step: 0x10 */
mturner5 0:0d6b77c9ae01 585 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
mturner5 0:0d6b77c9ae01 586 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
mturner5 0:0d6b77c9ae01 587 union { /* offset: 0x108, array step: 0x10 */
mturner5 0:0d6b77c9ae01 588 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
mturner5 0:0d6b77c9ae01 589 struct { /* offset: 0x108, array step: 0x10 */
mturner5 0:0d6b77c9ae01 590 uint8_t RESERVED_0[3];
mturner5 0:0d6b77c9ae01 591 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
mturner5 0:0d6b77c9ae01 592 } DMA_DSR_ACCESS8BIT;
mturner5 0:0d6b77c9ae01 593 };
mturner5 0:0d6b77c9ae01 594 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
mturner5 0:0d6b77c9ae01 595 } DMA[4];
mturner5 0:0d6b77c9ae01 596 } DMA_Type;
mturner5 0:0d6b77c9ae01 597
mturner5 0:0d6b77c9ae01 598 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 599 -- DMA Register Masks
mturner5 0:0d6b77c9ae01 600 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 601
mturner5 0:0d6b77c9ae01 602 /*!
mturner5 0:0d6b77c9ae01 603 * @addtogroup DMA_Register_Masks DMA Register Masks
mturner5 0:0d6b77c9ae01 604 * @{
mturner5 0:0d6b77c9ae01 605 */
mturner5 0:0d6b77c9ae01 606
mturner5 0:0d6b77c9ae01 607 /* SAR Bit Fields */
mturner5 0:0d6b77c9ae01 608 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 609 #define DMA_SAR_SAR_SHIFT 0
mturner5 0:0d6b77c9ae01 610 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
mturner5 0:0d6b77c9ae01 611 /* DAR Bit Fields */
mturner5 0:0d6b77c9ae01 612 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 613 #define DMA_DAR_DAR_SHIFT 0
mturner5 0:0d6b77c9ae01 614 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
mturner5 0:0d6b77c9ae01 615 /* DSR_BCR Bit Fields */
mturner5 0:0d6b77c9ae01 616 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
mturner5 0:0d6b77c9ae01 617 #define DMA_DSR_BCR_BCR_SHIFT 0
mturner5 0:0d6b77c9ae01 618 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
mturner5 0:0d6b77c9ae01 619 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 620 #define DMA_DSR_BCR_DONE_SHIFT 24
mturner5 0:0d6b77c9ae01 621 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 622 #define DMA_DSR_BCR_BSY_SHIFT 25
mturner5 0:0d6b77c9ae01 623 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
mturner5 0:0d6b77c9ae01 624 #define DMA_DSR_BCR_REQ_SHIFT 26
mturner5 0:0d6b77c9ae01 625 #define DMA_DSR_BCR_BED_MASK 0x10000000u
mturner5 0:0d6b77c9ae01 626 #define DMA_DSR_BCR_BED_SHIFT 28
mturner5 0:0d6b77c9ae01 627 #define DMA_DSR_BCR_BES_MASK 0x20000000u
mturner5 0:0d6b77c9ae01 628 #define DMA_DSR_BCR_BES_SHIFT 29
mturner5 0:0d6b77c9ae01 629 #define DMA_DSR_BCR_CE_MASK 0x40000000u
mturner5 0:0d6b77c9ae01 630 #define DMA_DSR_BCR_CE_SHIFT 30
mturner5 0:0d6b77c9ae01 631 /* DCR Bit Fields */
mturner5 0:0d6b77c9ae01 632 #define DMA_DCR_LCH2_MASK 0x3u
mturner5 0:0d6b77c9ae01 633 #define DMA_DCR_LCH2_SHIFT 0
mturner5 0:0d6b77c9ae01 634 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
mturner5 0:0d6b77c9ae01 635 #define DMA_DCR_LCH1_MASK 0xCu
mturner5 0:0d6b77c9ae01 636 #define DMA_DCR_LCH1_SHIFT 2
mturner5 0:0d6b77c9ae01 637 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
mturner5 0:0d6b77c9ae01 638 #define DMA_DCR_LINKCC_MASK 0x30u
mturner5 0:0d6b77c9ae01 639 #define DMA_DCR_LINKCC_SHIFT 4
mturner5 0:0d6b77c9ae01 640 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
mturner5 0:0d6b77c9ae01 641 #define DMA_DCR_D_REQ_MASK 0x80u
mturner5 0:0d6b77c9ae01 642 #define DMA_DCR_D_REQ_SHIFT 7
mturner5 0:0d6b77c9ae01 643 #define DMA_DCR_DMOD_MASK 0xF00u
mturner5 0:0d6b77c9ae01 644 #define DMA_DCR_DMOD_SHIFT 8
mturner5 0:0d6b77c9ae01 645 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
mturner5 0:0d6b77c9ae01 646 #define DMA_DCR_SMOD_MASK 0xF000u
mturner5 0:0d6b77c9ae01 647 #define DMA_DCR_SMOD_SHIFT 12
mturner5 0:0d6b77c9ae01 648 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
mturner5 0:0d6b77c9ae01 649 #define DMA_DCR_START_MASK 0x10000u
mturner5 0:0d6b77c9ae01 650 #define DMA_DCR_START_SHIFT 16
mturner5 0:0d6b77c9ae01 651 #define DMA_DCR_DSIZE_MASK 0x60000u
mturner5 0:0d6b77c9ae01 652 #define DMA_DCR_DSIZE_SHIFT 17
mturner5 0:0d6b77c9ae01 653 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
mturner5 0:0d6b77c9ae01 654 #define DMA_DCR_DINC_MASK 0x80000u
mturner5 0:0d6b77c9ae01 655 #define DMA_DCR_DINC_SHIFT 19
mturner5 0:0d6b77c9ae01 656 #define DMA_DCR_SSIZE_MASK 0x300000u
mturner5 0:0d6b77c9ae01 657 #define DMA_DCR_SSIZE_SHIFT 20
mturner5 0:0d6b77c9ae01 658 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
mturner5 0:0d6b77c9ae01 659 #define DMA_DCR_SINC_MASK 0x400000u
mturner5 0:0d6b77c9ae01 660 #define DMA_DCR_SINC_SHIFT 22
mturner5 0:0d6b77c9ae01 661 #define DMA_DCR_EADREQ_MASK 0x800000u
mturner5 0:0d6b77c9ae01 662 #define DMA_DCR_EADREQ_SHIFT 23
mturner5 0:0d6b77c9ae01 663 #define DMA_DCR_AA_MASK 0x10000000u
mturner5 0:0d6b77c9ae01 664 #define DMA_DCR_AA_SHIFT 28
mturner5 0:0d6b77c9ae01 665 #define DMA_DCR_CS_MASK 0x20000000u
mturner5 0:0d6b77c9ae01 666 #define DMA_DCR_CS_SHIFT 29
mturner5 0:0d6b77c9ae01 667 #define DMA_DCR_ERQ_MASK 0x40000000u
mturner5 0:0d6b77c9ae01 668 #define DMA_DCR_ERQ_SHIFT 30
mturner5 0:0d6b77c9ae01 669 #define DMA_DCR_EINT_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 670 #define DMA_DCR_EINT_SHIFT 31
mturner5 0:0d6b77c9ae01 671
mturner5 0:0d6b77c9ae01 672 /*!
mturner5 0:0d6b77c9ae01 673 * @}
mturner5 0:0d6b77c9ae01 674 */ /* end of group DMA_Register_Masks */
mturner5 0:0d6b77c9ae01 675
mturner5 0:0d6b77c9ae01 676
mturner5 0:0d6b77c9ae01 677 /* DMA - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 678 /** Peripheral DMA base address */
mturner5 0:0d6b77c9ae01 679 #define DMA_BASE (0x40008000u)
mturner5 0:0d6b77c9ae01 680 /** Peripheral DMA base pointer */
mturner5 0:0d6b77c9ae01 681 #define DMA0 ((DMA_Type *)DMA_BASE)
mturner5 0:0d6b77c9ae01 682 /** Array initializer of DMA peripheral base pointers */
mturner5 0:0d6b77c9ae01 683 #define DMA_BASES { DMA0 }
mturner5 0:0d6b77c9ae01 684
mturner5 0:0d6b77c9ae01 685 /*!
mturner5 0:0d6b77c9ae01 686 * @}
mturner5 0:0d6b77c9ae01 687 */ /* end of group DMA_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 688
mturner5 0:0d6b77c9ae01 689
mturner5 0:0d6b77c9ae01 690 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 691 -- DMAMUX Peripheral Access Layer
mturner5 0:0d6b77c9ae01 692 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 693
mturner5 0:0d6b77c9ae01 694 /*!
mturner5 0:0d6b77c9ae01 695 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mturner5 0:0d6b77c9ae01 696 * @{
mturner5 0:0d6b77c9ae01 697 */
mturner5 0:0d6b77c9ae01 698
mturner5 0:0d6b77c9ae01 699 /** DMAMUX - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 700 typedef struct {
mturner5 0:0d6b77c9ae01 701 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mturner5 0:0d6b77c9ae01 702 } DMAMUX_Type;
mturner5 0:0d6b77c9ae01 703
mturner5 0:0d6b77c9ae01 704 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 705 -- DMAMUX Register Masks
mturner5 0:0d6b77c9ae01 706 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 707
mturner5 0:0d6b77c9ae01 708 /*!
mturner5 0:0d6b77c9ae01 709 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mturner5 0:0d6b77c9ae01 710 * @{
mturner5 0:0d6b77c9ae01 711 */
mturner5 0:0d6b77c9ae01 712
mturner5 0:0d6b77c9ae01 713 /* CHCFG Bit Fields */
mturner5 0:0d6b77c9ae01 714 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 715 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mturner5 0:0d6b77c9ae01 716 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mturner5 0:0d6b77c9ae01 717 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mturner5 0:0d6b77c9ae01 718 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mturner5 0:0d6b77c9ae01 719 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mturner5 0:0d6b77c9ae01 720 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mturner5 0:0d6b77c9ae01 721
mturner5 0:0d6b77c9ae01 722 /*!
mturner5 0:0d6b77c9ae01 723 * @}
mturner5 0:0d6b77c9ae01 724 */ /* end of group DMAMUX_Register_Masks */
mturner5 0:0d6b77c9ae01 725
mturner5 0:0d6b77c9ae01 726
mturner5 0:0d6b77c9ae01 727 /* DMAMUX - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 728 /** Peripheral DMAMUX0 base address */
mturner5 0:0d6b77c9ae01 729 #define DMAMUX0_BASE (0x40021000u)
mturner5 0:0d6b77c9ae01 730 /** Peripheral DMAMUX0 base pointer */
mturner5 0:0d6b77c9ae01 731 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
mturner5 0:0d6b77c9ae01 732 /** Array initializer of DMAMUX peripheral base pointers */
mturner5 0:0d6b77c9ae01 733 #define DMAMUX_BASES { DMAMUX0 }
mturner5 0:0d6b77c9ae01 734
mturner5 0:0d6b77c9ae01 735 /*!
mturner5 0:0d6b77c9ae01 736 * @}
mturner5 0:0d6b77c9ae01 737 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 738
mturner5 0:0d6b77c9ae01 739
mturner5 0:0d6b77c9ae01 740 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 741 -- FGPIO Peripheral Access Layer
mturner5 0:0d6b77c9ae01 742 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 743
mturner5 0:0d6b77c9ae01 744 /*!
mturner5 0:0d6b77c9ae01 745 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
mturner5 0:0d6b77c9ae01 746 * @{
mturner5 0:0d6b77c9ae01 747 */
mturner5 0:0d6b77c9ae01 748
mturner5 0:0d6b77c9ae01 749 /** FGPIO - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 750 typedef struct {
mturner5 0:0d6b77c9ae01 751 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 752 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 753 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 754 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 755 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mturner5 0:0d6b77c9ae01 756 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mturner5 0:0d6b77c9ae01 757 } FGPIO_Type;
mturner5 0:0d6b77c9ae01 758
mturner5 0:0d6b77c9ae01 759 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 760 -- FGPIO Register Masks
mturner5 0:0d6b77c9ae01 761 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 762
mturner5 0:0d6b77c9ae01 763 /*!
mturner5 0:0d6b77c9ae01 764 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
mturner5 0:0d6b77c9ae01 765 * @{
mturner5 0:0d6b77c9ae01 766 */
mturner5 0:0d6b77c9ae01 767
mturner5 0:0d6b77c9ae01 768 /* PDOR Bit Fields */
mturner5 0:0d6b77c9ae01 769 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 770 #define FGPIO_PDOR_PDO_SHIFT 0
mturner5 0:0d6b77c9ae01 771 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
mturner5 0:0d6b77c9ae01 772 /* PSOR Bit Fields */
mturner5 0:0d6b77c9ae01 773 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 774 #define FGPIO_PSOR_PTSO_SHIFT 0
mturner5 0:0d6b77c9ae01 775 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
mturner5 0:0d6b77c9ae01 776 /* PCOR Bit Fields */
mturner5 0:0d6b77c9ae01 777 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 778 #define FGPIO_PCOR_PTCO_SHIFT 0
mturner5 0:0d6b77c9ae01 779 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
mturner5 0:0d6b77c9ae01 780 /* PTOR Bit Fields */
mturner5 0:0d6b77c9ae01 781 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 782 #define FGPIO_PTOR_PTTO_SHIFT 0
mturner5 0:0d6b77c9ae01 783 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
mturner5 0:0d6b77c9ae01 784 /* PDIR Bit Fields */
mturner5 0:0d6b77c9ae01 785 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 786 #define FGPIO_PDIR_PDI_SHIFT 0
mturner5 0:0d6b77c9ae01 787 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
mturner5 0:0d6b77c9ae01 788 /* PDDR Bit Fields */
mturner5 0:0d6b77c9ae01 789 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 790 #define FGPIO_PDDR_PDD_SHIFT 0
mturner5 0:0d6b77c9ae01 791 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
mturner5 0:0d6b77c9ae01 792
mturner5 0:0d6b77c9ae01 793 /*!
mturner5 0:0d6b77c9ae01 794 * @}
mturner5 0:0d6b77c9ae01 795 */ /* end of group FGPIO_Register_Masks */
mturner5 0:0d6b77c9ae01 796
mturner5 0:0d6b77c9ae01 797
mturner5 0:0d6b77c9ae01 798 /* FGPIO - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 799 /** Peripheral FPTA base address */
mturner5 0:0d6b77c9ae01 800 #define FPTA_BASE (0xF80FF000u)
mturner5 0:0d6b77c9ae01 801 /** Peripheral FPTA base pointer */
mturner5 0:0d6b77c9ae01 802 #define FPTA ((FGPIO_Type *)FPTA_BASE)
mturner5 0:0d6b77c9ae01 803 /** Peripheral FPTB base address */
mturner5 0:0d6b77c9ae01 804 #define FPTB_BASE (0xF80FF040u)
mturner5 0:0d6b77c9ae01 805 /** Peripheral FPTB base pointer */
mturner5 0:0d6b77c9ae01 806 #define FPTB ((FGPIO_Type *)FPTB_BASE)
mturner5 0:0d6b77c9ae01 807 /** Peripheral FPTC base address */
mturner5 0:0d6b77c9ae01 808 #define FPTC_BASE (0xF80FF080u)
mturner5 0:0d6b77c9ae01 809 /** Peripheral FPTC base pointer */
mturner5 0:0d6b77c9ae01 810 #define FPTC ((FGPIO_Type *)FPTC_BASE)
mturner5 0:0d6b77c9ae01 811 /** Peripheral FPTD base address */
mturner5 0:0d6b77c9ae01 812 #define FPTD_BASE (0xF80FF0C0u)
mturner5 0:0d6b77c9ae01 813 /** Peripheral FPTD base pointer */
mturner5 0:0d6b77c9ae01 814 #define FPTD ((FGPIO_Type *)FPTD_BASE)
mturner5 0:0d6b77c9ae01 815 /** Peripheral FPTE base address */
mturner5 0:0d6b77c9ae01 816 #define FPTE_BASE (0xF80FF100u)
mturner5 0:0d6b77c9ae01 817 /** Peripheral FPTE base pointer */
mturner5 0:0d6b77c9ae01 818 #define FPTE ((FGPIO_Type *)FPTE_BASE)
mturner5 0:0d6b77c9ae01 819 /** Array initializer of FGPIO peripheral base pointers */
mturner5 0:0d6b77c9ae01 820 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
mturner5 0:0d6b77c9ae01 821
mturner5 0:0d6b77c9ae01 822 /*!
mturner5 0:0d6b77c9ae01 823 * @}
mturner5 0:0d6b77c9ae01 824 */ /* end of group FGPIO_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 825
mturner5 0:0d6b77c9ae01 826
mturner5 0:0d6b77c9ae01 827 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 828 -- FTFA Peripheral Access Layer
mturner5 0:0d6b77c9ae01 829 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 830
mturner5 0:0d6b77c9ae01 831 /*!
mturner5 0:0d6b77c9ae01 832 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
mturner5 0:0d6b77c9ae01 833 * @{
mturner5 0:0d6b77c9ae01 834 */
mturner5 0:0d6b77c9ae01 835
mturner5 0:0d6b77c9ae01 836 /** FTFA - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 837 typedef struct {
mturner5 0:0d6b77c9ae01 838 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 839 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 840 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mturner5 0:0d6b77c9ae01 841 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mturner5 0:0d6b77c9ae01 842 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mturner5 0:0d6b77c9ae01 843 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mturner5 0:0d6b77c9ae01 844 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mturner5 0:0d6b77c9ae01 845 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mturner5 0:0d6b77c9ae01 846 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mturner5 0:0d6b77c9ae01 847 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mturner5 0:0d6b77c9ae01 848 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mturner5 0:0d6b77c9ae01 849 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mturner5 0:0d6b77c9ae01 850 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mturner5 0:0d6b77c9ae01 851 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mturner5 0:0d6b77c9ae01 852 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mturner5 0:0d6b77c9ae01 853 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mturner5 0:0d6b77c9ae01 854 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mturner5 0:0d6b77c9ae01 855 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mturner5 0:0d6b77c9ae01 856 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mturner5 0:0d6b77c9ae01 857 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mturner5 0:0d6b77c9ae01 858 } FTFA_Type;
mturner5 0:0d6b77c9ae01 859
mturner5 0:0d6b77c9ae01 860 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 861 -- FTFA Register Masks
mturner5 0:0d6b77c9ae01 862 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 863
mturner5 0:0d6b77c9ae01 864 /*!
mturner5 0:0d6b77c9ae01 865 * @addtogroup FTFA_Register_Masks FTFA Register Masks
mturner5 0:0d6b77c9ae01 866 * @{
mturner5 0:0d6b77c9ae01 867 */
mturner5 0:0d6b77c9ae01 868
mturner5 0:0d6b77c9ae01 869 /* FSTAT Bit Fields */
mturner5 0:0d6b77c9ae01 870 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
mturner5 0:0d6b77c9ae01 871 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
mturner5 0:0d6b77c9ae01 872 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
mturner5 0:0d6b77c9ae01 873 #define FTFA_FSTAT_FPVIOL_SHIFT 4
mturner5 0:0d6b77c9ae01 874 #define FTFA_FSTAT_ACCERR_MASK 0x20u
mturner5 0:0d6b77c9ae01 875 #define FTFA_FSTAT_ACCERR_SHIFT 5
mturner5 0:0d6b77c9ae01 876 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
mturner5 0:0d6b77c9ae01 877 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
mturner5 0:0d6b77c9ae01 878 #define FTFA_FSTAT_CCIF_MASK 0x80u
mturner5 0:0d6b77c9ae01 879 #define FTFA_FSTAT_CCIF_SHIFT 7
mturner5 0:0d6b77c9ae01 880 /* FCNFG Bit Fields */
mturner5 0:0d6b77c9ae01 881 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
mturner5 0:0d6b77c9ae01 882 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
mturner5 0:0d6b77c9ae01 883 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
mturner5 0:0d6b77c9ae01 884 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
mturner5 0:0d6b77c9ae01 885 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 886 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
mturner5 0:0d6b77c9ae01 887 #define FTFA_FCNFG_CCIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 888 #define FTFA_FCNFG_CCIE_SHIFT 7
mturner5 0:0d6b77c9ae01 889 /* FSEC Bit Fields */
mturner5 0:0d6b77c9ae01 890 #define FTFA_FSEC_SEC_MASK 0x3u
mturner5 0:0d6b77c9ae01 891 #define FTFA_FSEC_SEC_SHIFT 0
mturner5 0:0d6b77c9ae01 892 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
mturner5 0:0d6b77c9ae01 893 #define FTFA_FSEC_FSLACC_MASK 0xCu
mturner5 0:0d6b77c9ae01 894 #define FTFA_FSEC_FSLACC_SHIFT 2
mturner5 0:0d6b77c9ae01 895 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
mturner5 0:0d6b77c9ae01 896 #define FTFA_FSEC_MEEN_MASK 0x30u
mturner5 0:0d6b77c9ae01 897 #define FTFA_FSEC_MEEN_SHIFT 4
mturner5 0:0d6b77c9ae01 898 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
mturner5 0:0d6b77c9ae01 899 #define FTFA_FSEC_KEYEN_MASK 0xC0u
mturner5 0:0d6b77c9ae01 900 #define FTFA_FSEC_KEYEN_SHIFT 6
mturner5 0:0d6b77c9ae01 901 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
mturner5 0:0d6b77c9ae01 902 /* FOPT Bit Fields */
mturner5 0:0d6b77c9ae01 903 #define FTFA_FOPT_OPT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 904 #define FTFA_FOPT_OPT_SHIFT 0
mturner5 0:0d6b77c9ae01 905 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
mturner5 0:0d6b77c9ae01 906 /* FCCOB3 Bit Fields */
mturner5 0:0d6b77c9ae01 907 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 908 #define FTFA_FCCOB3_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 909 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 910 /* FCCOB2 Bit Fields */
mturner5 0:0d6b77c9ae01 911 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 912 #define FTFA_FCCOB2_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 913 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 914 /* FCCOB1 Bit Fields */
mturner5 0:0d6b77c9ae01 915 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 916 #define FTFA_FCCOB1_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 917 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 918 /* FCCOB0 Bit Fields */
mturner5 0:0d6b77c9ae01 919 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 920 #define FTFA_FCCOB0_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 921 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 922 /* FCCOB7 Bit Fields */
mturner5 0:0d6b77c9ae01 923 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 924 #define FTFA_FCCOB7_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 925 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 926 /* FCCOB6 Bit Fields */
mturner5 0:0d6b77c9ae01 927 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 928 #define FTFA_FCCOB6_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 929 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 930 /* FCCOB5 Bit Fields */
mturner5 0:0d6b77c9ae01 931 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 932 #define FTFA_FCCOB5_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 933 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 934 /* FCCOB4 Bit Fields */
mturner5 0:0d6b77c9ae01 935 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 936 #define FTFA_FCCOB4_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 937 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 938 /* FCCOBB Bit Fields */
mturner5 0:0d6b77c9ae01 939 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 940 #define FTFA_FCCOBB_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 941 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 942 /* FCCOBA Bit Fields */
mturner5 0:0d6b77c9ae01 943 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 944 #define FTFA_FCCOBA_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 945 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 946 /* FCCOB9 Bit Fields */
mturner5 0:0d6b77c9ae01 947 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 948 #define FTFA_FCCOB9_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 949 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 950 /* FCCOB8 Bit Fields */
mturner5 0:0d6b77c9ae01 951 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
mturner5 0:0d6b77c9ae01 952 #define FTFA_FCCOB8_CCOBn_SHIFT 0
mturner5 0:0d6b77c9ae01 953 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
mturner5 0:0d6b77c9ae01 954 /* FPROT3 Bit Fields */
mturner5 0:0d6b77c9ae01 955 #define FTFA_FPROT3_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 956 #define FTFA_FPROT3_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 957 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
mturner5 0:0d6b77c9ae01 958 /* FPROT2 Bit Fields */
mturner5 0:0d6b77c9ae01 959 #define FTFA_FPROT2_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 960 #define FTFA_FPROT2_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 961 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
mturner5 0:0d6b77c9ae01 962 /* FPROT1 Bit Fields */
mturner5 0:0d6b77c9ae01 963 #define FTFA_FPROT1_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 964 #define FTFA_FPROT1_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 965 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
mturner5 0:0d6b77c9ae01 966 /* FPROT0 Bit Fields */
mturner5 0:0d6b77c9ae01 967 #define FTFA_FPROT0_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 968 #define FTFA_FPROT0_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 969 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
mturner5 0:0d6b77c9ae01 970
mturner5 0:0d6b77c9ae01 971 /*!
mturner5 0:0d6b77c9ae01 972 * @}
mturner5 0:0d6b77c9ae01 973 */ /* end of group FTFA_Register_Masks */
mturner5 0:0d6b77c9ae01 974
mturner5 0:0d6b77c9ae01 975
mturner5 0:0d6b77c9ae01 976 /* FTFA - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 977 /** Peripheral FTFA base address */
mturner5 0:0d6b77c9ae01 978 #define FTFA_BASE (0x40020000u)
mturner5 0:0d6b77c9ae01 979 /** Peripheral FTFA base pointer */
mturner5 0:0d6b77c9ae01 980 #define FTFA ((FTFA_Type *)FTFA_BASE)
mturner5 0:0d6b77c9ae01 981 /** Array initializer of FTFA peripheral base pointers */
mturner5 0:0d6b77c9ae01 982 #define FTFA_BASES { FTFA }
mturner5 0:0d6b77c9ae01 983
mturner5 0:0d6b77c9ae01 984 /*!
mturner5 0:0d6b77c9ae01 985 * @}
mturner5 0:0d6b77c9ae01 986 */ /* end of group FTFA_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 987
mturner5 0:0d6b77c9ae01 988
mturner5 0:0d6b77c9ae01 989 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 990 -- GPIO Peripheral Access Layer
mturner5 0:0d6b77c9ae01 991 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 992
mturner5 0:0d6b77c9ae01 993 /*!
mturner5 0:0d6b77c9ae01 994 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mturner5 0:0d6b77c9ae01 995 * @{
mturner5 0:0d6b77c9ae01 996 */
mturner5 0:0d6b77c9ae01 997
mturner5 0:0d6b77c9ae01 998 /** GPIO - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 999 typedef struct {
mturner5 0:0d6b77c9ae01 1000 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 1001 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 1002 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 1003 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 1004 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mturner5 0:0d6b77c9ae01 1005 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mturner5 0:0d6b77c9ae01 1006 } GPIO_Type;
mturner5 0:0d6b77c9ae01 1007
mturner5 0:0d6b77c9ae01 1008 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1009 -- GPIO Register Masks
mturner5 0:0d6b77c9ae01 1010 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1011
mturner5 0:0d6b77c9ae01 1012 /*!
mturner5 0:0d6b77c9ae01 1013 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mturner5 0:0d6b77c9ae01 1014 * @{
mturner5 0:0d6b77c9ae01 1015 */
mturner5 0:0d6b77c9ae01 1016
mturner5 0:0d6b77c9ae01 1017 /* PDOR Bit Fields */
mturner5 0:0d6b77c9ae01 1018 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1019 #define GPIO_PDOR_PDO_SHIFT 0
mturner5 0:0d6b77c9ae01 1020 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mturner5 0:0d6b77c9ae01 1021 /* PSOR Bit Fields */
mturner5 0:0d6b77c9ae01 1022 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1023 #define GPIO_PSOR_PTSO_SHIFT 0
mturner5 0:0d6b77c9ae01 1024 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mturner5 0:0d6b77c9ae01 1025 /* PCOR Bit Fields */
mturner5 0:0d6b77c9ae01 1026 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1027 #define GPIO_PCOR_PTCO_SHIFT 0
mturner5 0:0d6b77c9ae01 1028 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mturner5 0:0d6b77c9ae01 1029 /* PTOR Bit Fields */
mturner5 0:0d6b77c9ae01 1030 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1031 #define GPIO_PTOR_PTTO_SHIFT 0
mturner5 0:0d6b77c9ae01 1032 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mturner5 0:0d6b77c9ae01 1033 /* PDIR Bit Fields */
mturner5 0:0d6b77c9ae01 1034 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1035 #define GPIO_PDIR_PDI_SHIFT 0
mturner5 0:0d6b77c9ae01 1036 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mturner5 0:0d6b77c9ae01 1037 /* PDDR Bit Fields */
mturner5 0:0d6b77c9ae01 1038 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1039 #define GPIO_PDDR_PDD_SHIFT 0
mturner5 0:0d6b77c9ae01 1040 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mturner5 0:0d6b77c9ae01 1041
mturner5 0:0d6b77c9ae01 1042 /*!
mturner5 0:0d6b77c9ae01 1043 * @}
mturner5 0:0d6b77c9ae01 1044 */ /* end of group GPIO_Register_Masks */
mturner5 0:0d6b77c9ae01 1045
mturner5 0:0d6b77c9ae01 1046
mturner5 0:0d6b77c9ae01 1047 /* GPIO - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 1048 /** Peripheral PTA base address */
mturner5 0:0d6b77c9ae01 1049 #define PTA_BASE (0x400FF000u)
mturner5 0:0d6b77c9ae01 1050 /** Peripheral PTA base pointer */
mturner5 0:0d6b77c9ae01 1051 #define PTA ((GPIO_Type *)PTA_BASE)
mturner5 0:0d6b77c9ae01 1052 /** Peripheral PTB base address */
mturner5 0:0d6b77c9ae01 1053 #define PTB_BASE (0x400FF040u)
mturner5 0:0d6b77c9ae01 1054 /** Peripheral PTB base pointer */
mturner5 0:0d6b77c9ae01 1055 #define PTB ((GPIO_Type *)PTB_BASE)
mturner5 0:0d6b77c9ae01 1056 /** Peripheral PTC base address */
mturner5 0:0d6b77c9ae01 1057 #define PTC_BASE (0x400FF080u)
mturner5 0:0d6b77c9ae01 1058 /** Peripheral PTC base pointer */
mturner5 0:0d6b77c9ae01 1059 #define PTC ((GPIO_Type *)PTC_BASE)
mturner5 0:0d6b77c9ae01 1060 /** Peripheral PTD base address */
mturner5 0:0d6b77c9ae01 1061 #define PTD_BASE (0x400FF0C0u)
mturner5 0:0d6b77c9ae01 1062 /** Peripheral PTD base pointer */
mturner5 0:0d6b77c9ae01 1063 #define PTD ((GPIO_Type *)PTD_BASE)
mturner5 0:0d6b77c9ae01 1064 /** Peripheral PTE base address */
mturner5 0:0d6b77c9ae01 1065 #define PTE_BASE (0x400FF100u)
mturner5 0:0d6b77c9ae01 1066 /** Peripheral PTE base pointer */
mturner5 0:0d6b77c9ae01 1067 #define PTE ((GPIO_Type *)PTE_BASE)
mturner5 0:0d6b77c9ae01 1068 /** Array initializer of GPIO peripheral base pointers */
mturner5 0:0d6b77c9ae01 1069 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
mturner5 0:0d6b77c9ae01 1070
mturner5 0:0d6b77c9ae01 1071 /*!
mturner5 0:0d6b77c9ae01 1072 * @}
mturner5 0:0d6b77c9ae01 1073 */ /* end of group GPIO_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 1074
mturner5 0:0d6b77c9ae01 1075
mturner5 0:0d6b77c9ae01 1076 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1077 -- I2C Peripheral Access Layer
mturner5 0:0d6b77c9ae01 1078 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1079
mturner5 0:0d6b77c9ae01 1080 /*!
mturner5 0:0d6b77c9ae01 1081 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mturner5 0:0d6b77c9ae01 1082 * @{
mturner5 0:0d6b77c9ae01 1083 */
mturner5 0:0d6b77c9ae01 1084
mturner5 0:0d6b77c9ae01 1085 /** I2C - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 1086 typedef struct {
mturner5 0:0d6b77c9ae01 1087 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mturner5 0:0d6b77c9ae01 1088 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 1089 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mturner5 0:0d6b77c9ae01 1090 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mturner5 0:0d6b77c9ae01 1091 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 1092 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mturner5 0:0d6b77c9ae01 1093 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mturner5 0:0d6b77c9ae01 1094 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mturner5 0:0d6b77c9ae01 1095 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 1096 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mturner5 0:0d6b77c9ae01 1097 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mturner5 0:0d6b77c9ae01 1098 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mturner5 0:0d6b77c9ae01 1099 } I2C_Type;
mturner5 0:0d6b77c9ae01 1100
mturner5 0:0d6b77c9ae01 1101 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1102 -- I2C Register Masks
mturner5 0:0d6b77c9ae01 1103 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1104
mturner5 0:0d6b77c9ae01 1105 /*!
mturner5 0:0d6b77c9ae01 1106 * @addtogroup I2C_Register_Masks I2C Register Masks
mturner5 0:0d6b77c9ae01 1107 * @{
mturner5 0:0d6b77c9ae01 1108 */
mturner5 0:0d6b77c9ae01 1109
mturner5 0:0d6b77c9ae01 1110 /* A1 Bit Fields */
mturner5 0:0d6b77c9ae01 1111 #define I2C_A1_AD_MASK 0xFEu
mturner5 0:0d6b77c9ae01 1112 #define I2C_A1_AD_SHIFT 1
mturner5 0:0d6b77c9ae01 1113 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mturner5 0:0d6b77c9ae01 1114 /* F Bit Fields */
mturner5 0:0d6b77c9ae01 1115 #define I2C_F_ICR_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 1116 #define I2C_F_ICR_SHIFT 0
mturner5 0:0d6b77c9ae01 1117 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mturner5 0:0d6b77c9ae01 1118 #define I2C_F_MULT_MASK 0xC0u
mturner5 0:0d6b77c9ae01 1119 #define I2C_F_MULT_SHIFT 6
mturner5 0:0d6b77c9ae01 1120 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mturner5 0:0d6b77c9ae01 1121 /* C1 Bit Fields */
mturner5 0:0d6b77c9ae01 1122 #define I2C_C1_DMAEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 1123 #define I2C_C1_DMAEN_SHIFT 0
mturner5 0:0d6b77c9ae01 1124 #define I2C_C1_WUEN_MASK 0x2u
mturner5 0:0d6b77c9ae01 1125 #define I2C_C1_WUEN_SHIFT 1
mturner5 0:0d6b77c9ae01 1126 #define I2C_C1_RSTA_MASK 0x4u
mturner5 0:0d6b77c9ae01 1127 #define I2C_C1_RSTA_SHIFT 2
mturner5 0:0d6b77c9ae01 1128 #define I2C_C1_TXAK_MASK 0x8u
mturner5 0:0d6b77c9ae01 1129 #define I2C_C1_TXAK_SHIFT 3
mturner5 0:0d6b77c9ae01 1130 #define I2C_C1_TX_MASK 0x10u
mturner5 0:0d6b77c9ae01 1131 #define I2C_C1_TX_SHIFT 4
mturner5 0:0d6b77c9ae01 1132 #define I2C_C1_MST_MASK 0x20u
mturner5 0:0d6b77c9ae01 1133 #define I2C_C1_MST_SHIFT 5
mturner5 0:0d6b77c9ae01 1134 #define I2C_C1_IICIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 1135 #define I2C_C1_IICIE_SHIFT 6
mturner5 0:0d6b77c9ae01 1136 #define I2C_C1_IICEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 1137 #define I2C_C1_IICEN_SHIFT 7
mturner5 0:0d6b77c9ae01 1138 /* S Bit Fields */
mturner5 0:0d6b77c9ae01 1139 #define I2C_S_RXAK_MASK 0x1u
mturner5 0:0d6b77c9ae01 1140 #define I2C_S_RXAK_SHIFT 0
mturner5 0:0d6b77c9ae01 1141 #define I2C_S_IICIF_MASK 0x2u
mturner5 0:0d6b77c9ae01 1142 #define I2C_S_IICIF_SHIFT 1
mturner5 0:0d6b77c9ae01 1143 #define I2C_S_SRW_MASK 0x4u
mturner5 0:0d6b77c9ae01 1144 #define I2C_S_SRW_SHIFT 2
mturner5 0:0d6b77c9ae01 1145 #define I2C_S_RAM_MASK 0x8u
mturner5 0:0d6b77c9ae01 1146 #define I2C_S_RAM_SHIFT 3
mturner5 0:0d6b77c9ae01 1147 #define I2C_S_ARBL_MASK 0x10u
mturner5 0:0d6b77c9ae01 1148 #define I2C_S_ARBL_SHIFT 4
mturner5 0:0d6b77c9ae01 1149 #define I2C_S_BUSY_MASK 0x20u
mturner5 0:0d6b77c9ae01 1150 #define I2C_S_BUSY_SHIFT 5
mturner5 0:0d6b77c9ae01 1151 #define I2C_S_IAAS_MASK 0x40u
mturner5 0:0d6b77c9ae01 1152 #define I2C_S_IAAS_SHIFT 6
mturner5 0:0d6b77c9ae01 1153 #define I2C_S_TCF_MASK 0x80u
mturner5 0:0d6b77c9ae01 1154 #define I2C_S_TCF_SHIFT 7
mturner5 0:0d6b77c9ae01 1155 /* D Bit Fields */
mturner5 0:0d6b77c9ae01 1156 #define I2C_D_DATA_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1157 #define I2C_D_DATA_SHIFT 0
mturner5 0:0d6b77c9ae01 1158 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mturner5 0:0d6b77c9ae01 1159 /* C2 Bit Fields */
mturner5 0:0d6b77c9ae01 1160 #define I2C_C2_AD_MASK 0x7u
mturner5 0:0d6b77c9ae01 1161 #define I2C_C2_AD_SHIFT 0
mturner5 0:0d6b77c9ae01 1162 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mturner5 0:0d6b77c9ae01 1163 #define I2C_C2_RMEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 1164 #define I2C_C2_RMEN_SHIFT 3
mturner5 0:0d6b77c9ae01 1165 #define I2C_C2_SBRC_MASK 0x10u
mturner5 0:0d6b77c9ae01 1166 #define I2C_C2_SBRC_SHIFT 4
mturner5 0:0d6b77c9ae01 1167 #define I2C_C2_HDRS_MASK 0x20u
mturner5 0:0d6b77c9ae01 1168 #define I2C_C2_HDRS_SHIFT 5
mturner5 0:0d6b77c9ae01 1169 #define I2C_C2_ADEXT_MASK 0x40u
mturner5 0:0d6b77c9ae01 1170 #define I2C_C2_ADEXT_SHIFT 6
mturner5 0:0d6b77c9ae01 1171 #define I2C_C2_GCAEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 1172 #define I2C_C2_GCAEN_SHIFT 7
mturner5 0:0d6b77c9ae01 1173 /* FLT Bit Fields */
mturner5 0:0d6b77c9ae01 1174 #define I2C_FLT_FLT_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 1175 #define I2C_FLT_FLT_SHIFT 0
mturner5 0:0d6b77c9ae01 1176 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mturner5 0:0d6b77c9ae01 1177 #define I2C_FLT_STOPIE_MASK 0x20u
mturner5 0:0d6b77c9ae01 1178 #define I2C_FLT_STOPIE_SHIFT 5
mturner5 0:0d6b77c9ae01 1179 #define I2C_FLT_STOPF_MASK 0x40u
mturner5 0:0d6b77c9ae01 1180 #define I2C_FLT_STOPF_SHIFT 6
mturner5 0:0d6b77c9ae01 1181 #define I2C_FLT_SHEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 1182 #define I2C_FLT_SHEN_SHIFT 7
mturner5 0:0d6b77c9ae01 1183 /* RA Bit Fields */
mturner5 0:0d6b77c9ae01 1184 #define I2C_RA_RAD_MASK 0xFEu
mturner5 0:0d6b77c9ae01 1185 #define I2C_RA_RAD_SHIFT 1
mturner5 0:0d6b77c9ae01 1186 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mturner5 0:0d6b77c9ae01 1187 /* SMB Bit Fields */
mturner5 0:0d6b77c9ae01 1188 #define I2C_SMB_SHTF2IE_MASK 0x1u
mturner5 0:0d6b77c9ae01 1189 #define I2C_SMB_SHTF2IE_SHIFT 0
mturner5 0:0d6b77c9ae01 1190 #define I2C_SMB_SHTF2_MASK 0x2u
mturner5 0:0d6b77c9ae01 1191 #define I2C_SMB_SHTF2_SHIFT 1
mturner5 0:0d6b77c9ae01 1192 #define I2C_SMB_SHTF1_MASK 0x4u
mturner5 0:0d6b77c9ae01 1193 #define I2C_SMB_SHTF1_SHIFT 2
mturner5 0:0d6b77c9ae01 1194 #define I2C_SMB_SLTF_MASK 0x8u
mturner5 0:0d6b77c9ae01 1195 #define I2C_SMB_SLTF_SHIFT 3
mturner5 0:0d6b77c9ae01 1196 #define I2C_SMB_TCKSEL_MASK 0x10u
mturner5 0:0d6b77c9ae01 1197 #define I2C_SMB_TCKSEL_SHIFT 4
mturner5 0:0d6b77c9ae01 1198 #define I2C_SMB_SIICAEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 1199 #define I2C_SMB_SIICAEN_SHIFT 5
mturner5 0:0d6b77c9ae01 1200 #define I2C_SMB_ALERTEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 1201 #define I2C_SMB_ALERTEN_SHIFT 6
mturner5 0:0d6b77c9ae01 1202 #define I2C_SMB_FACK_MASK 0x80u
mturner5 0:0d6b77c9ae01 1203 #define I2C_SMB_FACK_SHIFT 7
mturner5 0:0d6b77c9ae01 1204 /* A2 Bit Fields */
mturner5 0:0d6b77c9ae01 1205 #define I2C_A2_SAD_MASK 0xFEu
mturner5 0:0d6b77c9ae01 1206 #define I2C_A2_SAD_SHIFT 1
mturner5 0:0d6b77c9ae01 1207 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mturner5 0:0d6b77c9ae01 1208 /* SLTH Bit Fields */
mturner5 0:0d6b77c9ae01 1209 #define I2C_SLTH_SSLT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1210 #define I2C_SLTH_SSLT_SHIFT 0
mturner5 0:0d6b77c9ae01 1211 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mturner5 0:0d6b77c9ae01 1212 /* SLTL Bit Fields */
mturner5 0:0d6b77c9ae01 1213 #define I2C_SLTL_SSLT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1214 #define I2C_SLTL_SSLT_SHIFT 0
mturner5 0:0d6b77c9ae01 1215 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mturner5 0:0d6b77c9ae01 1216
mturner5 0:0d6b77c9ae01 1217 /*!
mturner5 0:0d6b77c9ae01 1218 * @}
mturner5 0:0d6b77c9ae01 1219 */ /* end of group I2C_Register_Masks */
mturner5 0:0d6b77c9ae01 1220
mturner5 0:0d6b77c9ae01 1221
mturner5 0:0d6b77c9ae01 1222 /* I2C - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 1223 /** Peripheral I2C0 base address */
mturner5 0:0d6b77c9ae01 1224 #define I2C0_BASE (0x40066000u)
mturner5 0:0d6b77c9ae01 1225 /** Peripheral I2C0 base pointer */
mturner5 0:0d6b77c9ae01 1226 #define I2C0 ((I2C_Type *)I2C0_BASE)
mturner5 0:0d6b77c9ae01 1227 /** Peripheral I2C1 base address */
mturner5 0:0d6b77c9ae01 1228 #define I2C1_BASE (0x40067000u)
mturner5 0:0d6b77c9ae01 1229 /** Peripheral I2C1 base pointer */
mturner5 0:0d6b77c9ae01 1230 #define I2C1 ((I2C_Type *)I2C1_BASE)
mturner5 0:0d6b77c9ae01 1231 /** Array initializer of I2C peripheral base pointers */
mturner5 0:0d6b77c9ae01 1232 #define I2C_BASES { I2C0, I2C1 }
mturner5 0:0d6b77c9ae01 1233
mturner5 0:0d6b77c9ae01 1234 /*!
mturner5 0:0d6b77c9ae01 1235 * @}
mturner5 0:0d6b77c9ae01 1236 */ /* end of group I2C_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 1237
mturner5 0:0d6b77c9ae01 1238
mturner5 0:0d6b77c9ae01 1239 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1240 -- I2S Peripheral Access Layer
mturner5 0:0d6b77c9ae01 1241 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1242
mturner5 0:0d6b77c9ae01 1243 /*!
mturner5 0:0d6b77c9ae01 1244 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mturner5 0:0d6b77c9ae01 1245 * @{
mturner5 0:0d6b77c9ae01 1246 */
mturner5 0:0d6b77c9ae01 1247
mturner5 0:0d6b77c9ae01 1248 /** I2S - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 1249 typedef struct {
mturner5 0:0d6b77c9ae01 1250 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 1251 uint8_t RESERVED_0[4];
mturner5 0:0d6b77c9ae01 1252 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 1253 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 1254 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mturner5 0:0d6b77c9ae01 1255 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mturner5 0:0d6b77c9ae01 1256 uint8_t RESERVED_1[8];
mturner5 0:0d6b77c9ae01 1257 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mturner5 0:0d6b77c9ae01 1258 uint8_t RESERVED_2[60];
mturner5 0:0d6b77c9ae01 1259 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mturner5 0:0d6b77c9ae01 1260 uint8_t RESERVED_3[28];
mturner5 0:0d6b77c9ae01 1261 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mturner5 0:0d6b77c9ae01 1262 uint8_t RESERVED_4[4];
mturner5 0:0d6b77c9ae01 1263 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mturner5 0:0d6b77c9ae01 1264 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mturner5 0:0d6b77c9ae01 1265 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mturner5 0:0d6b77c9ae01 1266 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mturner5 0:0d6b77c9ae01 1267 uint8_t RESERVED_5[8];
mturner5 0:0d6b77c9ae01 1268 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 1269 uint8_t RESERVED_6[60];
mturner5 0:0d6b77c9ae01 1270 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mturner5 0:0d6b77c9ae01 1271 uint8_t RESERVED_7[28];
mturner5 0:0d6b77c9ae01 1272 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mturner5 0:0d6b77c9ae01 1273 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
mturner5 0:0d6b77c9ae01 1274 } I2S_Type;
mturner5 0:0d6b77c9ae01 1275
mturner5 0:0d6b77c9ae01 1276 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1277 -- I2S Register Masks
mturner5 0:0d6b77c9ae01 1278 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1279
mturner5 0:0d6b77c9ae01 1280 /*!
mturner5 0:0d6b77c9ae01 1281 * @addtogroup I2S_Register_Masks I2S Register Masks
mturner5 0:0d6b77c9ae01 1282 * @{
mturner5 0:0d6b77c9ae01 1283 */
mturner5 0:0d6b77c9ae01 1284
mturner5 0:0d6b77c9ae01 1285 /* TCSR Bit Fields */
mturner5 0:0d6b77c9ae01 1286 #define I2S_TCSR_FWDE_MASK 0x2u
mturner5 0:0d6b77c9ae01 1287 #define I2S_TCSR_FWDE_SHIFT 1
mturner5 0:0d6b77c9ae01 1288 #define I2S_TCSR_FWIE_MASK 0x200u
mturner5 0:0d6b77c9ae01 1289 #define I2S_TCSR_FWIE_SHIFT 9
mturner5 0:0d6b77c9ae01 1290 #define I2S_TCSR_FEIE_MASK 0x400u
mturner5 0:0d6b77c9ae01 1291 #define I2S_TCSR_FEIE_SHIFT 10
mturner5 0:0d6b77c9ae01 1292 #define I2S_TCSR_SEIE_MASK 0x800u
mturner5 0:0d6b77c9ae01 1293 #define I2S_TCSR_SEIE_SHIFT 11
mturner5 0:0d6b77c9ae01 1294 #define I2S_TCSR_WSIE_MASK 0x1000u
mturner5 0:0d6b77c9ae01 1295 #define I2S_TCSR_WSIE_SHIFT 12
mturner5 0:0d6b77c9ae01 1296 #define I2S_TCSR_FWF_MASK 0x20000u
mturner5 0:0d6b77c9ae01 1297 #define I2S_TCSR_FWF_SHIFT 17
mturner5 0:0d6b77c9ae01 1298 #define I2S_TCSR_FEF_MASK 0x40000u
mturner5 0:0d6b77c9ae01 1299 #define I2S_TCSR_FEF_SHIFT 18
mturner5 0:0d6b77c9ae01 1300 #define I2S_TCSR_SEF_MASK 0x80000u
mturner5 0:0d6b77c9ae01 1301 #define I2S_TCSR_SEF_SHIFT 19
mturner5 0:0d6b77c9ae01 1302 #define I2S_TCSR_WSF_MASK 0x100000u
mturner5 0:0d6b77c9ae01 1303 #define I2S_TCSR_WSF_SHIFT 20
mturner5 0:0d6b77c9ae01 1304 #define I2S_TCSR_SR_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 1305 #define I2S_TCSR_SR_SHIFT 24
mturner5 0:0d6b77c9ae01 1306 #define I2S_TCSR_FR_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 1307 #define I2S_TCSR_FR_SHIFT 25
mturner5 0:0d6b77c9ae01 1308 #define I2S_TCSR_BCE_MASK 0x10000000u
mturner5 0:0d6b77c9ae01 1309 #define I2S_TCSR_BCE_SHIFT 28
mturner5 0:0d6b77c9ae01 1310 #define I2S_TCSR_DBGE_MASK 0x20000000u
mturner5 0:0d6b77c9ae01 1311 #define I2S_TCSR_DBGE_SHIFT 29
mturner5 0:0d6b77c9ae01 1312 #define I2S_TCSR_STOPE_MASK 0x40000000u
mturner5 0:0d6b77c9ae01 1313 #define I2S_TCSR_STOPE_SHIFT 30
mturner5 0:0d6b77c9ae01 1314 #define I2S_TCSR_TE_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 1315 #define I2S_TCSR_TE_SHIFT 31
mturner5 0:0d6b77c9ae01 1316 /* TCR2 Bit Fields */
mturner5 0:0d6b77c9ae01 1317 #define I2S_TCR2_DIV_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1318 #define I2S_TCR2_DIV_SHIFT 0
mturner5 0:0d6b77c9ae01 1319 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mturner5 0:0d6b77c9ae01 1320 #define I2S_TCR2_BCD_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 1321 #define I2S_TCR2_BCD_SHIFT 24
mturner5 0:0d6b77c9ae01 1322 #define I2S_TCR2_BCP_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 1323 #define I2S_TCR2_BCP_SHIFT 25
mturner5 0:0d6b77c9ae01 1324 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
mturner5 0:0d6b77c9ae01 1325 #define I2S_TCR2_CLKMODE_SHIFT 26
mturner5 0:0d6b77c9ae01 1326 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
mturner5 0:0d6b77c9ae01 1327 /* TCR3 Bit Fields */
mturner5 0:0d6b77c9ae01 1328 #define I2S_TCR3_WDFL_MASK 0x1u
mturner5 0:0d6b77c9ae01 1329 #define I2S_TCR3_WDFL_SHIFT 0
mturner5 0:0d6b77c9ae01 1330 #define I2S_TCR3_TCE_MASK 0x10000u
mturner5 0:0d6b77c9ae01 1331 #define I2S_TCR3_TCE_SHIFT 16
mturner5 0:0d6b77c9ae01 1332 /* TCR4 Bit Fields */
mturner5 0:0d6b77c9ae01 1333 #define I2S_TCR4_FSD_MASK 0x1u
mturner5 0:0d6b77c9ae01 1334 #define I2S_TCR4_FSD_SHIFT 0
mturner5 0:0d6b77c9ae01 1335 #define I2S_TCR4_FSP_MASK 0x2u
mturner5 0:0d6b77c9ae01 1336 #define I2S_TCR4_FSP_SHIFT 1
mturner5 0:0d6b77c9ae01 1337 #define I2S_TCR4_FSE_MASK 0x8u
mturner5 0:0d6b77c9ae01 1338 #define I2S_TCR4_FSE_SHIFT 3
mturner5 0:0d6b77c9ae01 1339 #define I2S_TCR4_MF_MASK 0x10u
mturner5 0:0d6b77c9ae01 1340 #define I2S_TCR4_MF_SHIFT 4
mturner5 0:0d6b77c9ae01 1341 #define I2S_TCR4_SYWD_MASK 0x1F00u
mturner5 0:0d6b77c9ae01 1342 #define I2S_TCR4_SYWD_SHIFT 8
mturner5 0:0d6b77c9ae01 1343 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mturner5 0:0d6b77c9ae01 1344 #define I2S_TCR4_FRSZ_MASK 0x10000u
mturner5 0:0d6b77c9ae01 1345 #define I2S_TCR4_FRSZ_SHIFT 16
mturner5 0:0d6b77c9ae01 1346 /* TCR5 Bit Fields */
mturner5 0:0d6b77c9ae01 1347 #define I2S_TCR5_FBT_MASK 0x1F00u
mturner5 0:0d6b77c9ae01 1348 #define I2S_TCR5_FBT_SHIFT 8
mturner5 0:0d6b77c9ae01 1349 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mturner5 0:0d6b77c9ae01 1350 #define I2S_TCR5_W0W_MASK 0x1F0000u
mturner5 0:0d6b77c9ae01 1351 #define I2S_TCR5_W0W_SHIFT 16
mturner5 0:0d6b77c9ae01 1352 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mturner5 0:0d6b77c9ae01 1353 #define I2S_TCR5_WNW_MASK 0x1F000000u
mturner5 0:0d6b77c9ae01 1354 #define I2S_TCR5_WNW_SHIFT 24
mturner5 0:0d6b77c9ae01 1355 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mturner5 0:0d6b77c9ae01 1356 /* TDR Bit Fields */
mturner5 0:0d6b77c9ae01 1357 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1358 #define I2S_TDR_TDR_SHIFT 0
mturner5 0:0d6b77c9ae01 1359 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mturner5 0:0d6b77c9ae01 1360 /* TMR Bit Fields */
mturner5 0:0d6b77c9ae01 1361 #define I2S_TMR_TWM_MASK 0x3u
mturner5 0:0d6b77c9ae01 1362 #define I2S_TMR_TWM_SHIFT 0
mturner5 0:0d6b77c9ae01 1363 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mturner5 0:0d6b77c9ae01 1364 /* RCSR Bit Fields */
mturner5 0:0d6b77c9ae01 1365 #define I2S_RCSR_FWDE_MASK 0x2u
mturner5 0:0d6b77c9ae01 1366 #define I2S_RCSR_FWDE_SHIFT 1
mturner5 0:0d6b77c9ae01 1367 #define I2S_RCSR_FWIE_MASK 0x200u
mturner5 0:0d6b77c9ae01 1368 #define I2S_RCSR_FWIE_SHIFT 9
mturner5 0:0d6b77c9ae01 1369 #define I2S_RCSR_FEIE_MASK 0x400u
mturner5 0:0d6b77c9ae01 1370 #define I2S_RCSR_FEIE_SHIFT 10
mturner5 0:0d6b77c9ae01 1371 #define I2S_RCSR_SEIE_MASK 0x800u
mturner5 0:0d6b77c9ae01 1372 #define I2S_RCSR_SEIE_SHIFT 11
mturner5 0:0d6b77c9ae01 1373 #define I2S_RCSR_WSIE_MASK 0x1000u
mturner5 0:0d6b77c9ae01 1374 #define I2S_RCSR_WSIE_SHIFT 12
mturner5 0:0d6b77c9ae01 1375 #define I2S_RCSR_FWF_MASK 0x20000u
mturner5 0:0d6b77c9ae01 1376 #define I2S_RCSR_FWF_SHIFT 17
mturner5 0:0d6b77c9ae01 1377 #define I2S_RCSR_FEF_MASK 0x40000u
mturner5 0:0d6b77c9ae01 1378 #define I2S_RCSR_FEF_SHIFT 18
mturner5 0:0d6b77c9ae01 1379 #define I2S_RCSR_SEF_MASK 0x80000u
mturner5 0:0d6b77c9ae01 1380 #define I2S_RCSR_SEF_SHIFT 19
mturner5 0:0d6b77c9ae01 1381 #define I2S_RCSR_WSF_MASK 0x100000u
mturner5 0:0d6b77c9ae01 1382 #define I2S_RCSR_WSF_SHIFT 20
mturner5 0:0d6b77c9ae01 1383 #define I2S_RCSR_SR_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 1384 #define I2S_RCSR_SR_SHIFT 24
mturner5 0:0d6b77c9ae01 1385 #define I2S_RCSR_FR_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 1386 #define I2S_RCSR_FR_SHIFT 25
mturner5 0:0d6b77c9ae01 1387 #define I2S_RCSR_BCE_MASK 0x10000000u
mturner5 0:0d6b77c9ae01 1388 #define I2S_RCSR_BCE_SHIFT 28
mturner5 0:0d6b77c9ae01 1389 #define I2S_RCSR_DBGE_MASK 0x20000000u
mturner5 0:0d6b77c9ae01 1390 #define I2S_RCSR_DBGE_SHIFT 29
mturner5 0:0d6b77c9ae01 1391 #define I2S_RCSR_STOPE_MASK 0x40000000u
mturner5 0:0d6b77c9ae01 1392 #define I2S_RCSR_STOPE_SHIFT 30
mturner5 0:0d6b77c9ae01 1393 #define I2S_RCSR_RE_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 1394 #define I2S_RCSR_RE_SHIFT 31
mturner5 0:0d6b77c9ae01 1395 /* RCR2 Bit Fields */
mturner5 0:0d6b77c9ae01 1396 #define I2S_RCR2_DIV_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1397 #define I2S_RCR2_DIV_SHIFT 0
mturner5 0:0d6b77c9ae01 1398 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mturner5 0:0d6b77c9ae01 1399 #define I2S_RCR2_BCD_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 1400 #define I2S_RCR2_BCD_SHIFT 24
mturner5 0:0d6b77c9ae01 1401 #define I2S_RCR2_BCP_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 1402 #define I2S_RCR2_BCP_SHIFT 25
mturner5 0:0d6b77c9ae01 1403 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
mturner5 0:0d6b77c9ae01 1404 #define I2S_RCR2_CLKMODE_SHIFT 26
mturner5 0:0d6b77c9ae01 1405 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
mturner5 0:0d6b77c9ae01 1406 /* RCR3 Bit Fields */
mturner5 0:0d6b77c9ae01 1407 #define I2S_RCR3_WDFL_MASK 0x1u
mturner5 0:0d6b77c9ae01 1408 #define I2S_RCR3_WDFL_SHIFT 0
mturner5 0:0d6b77c9ae01 1409 #define I2S_RCR3_RCE_MASK 0x10000u
mturner5 0:0d6b77c9ae01 1410 #define I2S_RCR3_RCE_SHIFT 16
mturner5 0:0d6b77c9ae01 1411 /* RCR4 Bit Fields */
mturner5 0:0d6b77c9ae01 1412 #define I2S_RCR4_FSD_MASK 0x1u
mturner5 0:0d6b77c9ae01 1413 #define I2S_RCR4_FSD_SHIFT 0
mturner5 0:0d6b77c9ae01 1414 #define I2S_RCR4_FSP_MASK 0x2u
mturner5 0:0d6b77c9ae01 1415 #define I2S_RCR4_FSP_SHIFT 1
mturner5 0:0d6b77c9ae01 1416 #define I2S_RCR4_FSE_MASK 0x8u
mturner5 0:0d6b77c9ae01 1417 #define I2S_RCR4_FSE_SHIFT 3
mturner5 0:0d6b77c9ae01 1418 #define I2S_RCR4_MF_MASK 0x10u
mturner5 0:0d6b77c9ae01 1419 #define I2S_RCR4_MF_SHIFT 4
mturner5 0:0d6b77c9ae01 1420 #define I2S_RCR4_SYWD_MASK 0x1F00u
mturner5 0:0d6b77c9ae01 1421 #define I2S_RCR4_SYWD_SHIFT 8
mturner5 0:0d6b77c9ae01 1422 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mturner5 0:0d6b77c9ae01 1423 #define I2S_RCR4_FRSZ_MASK 0x10000u
mturner5 0:0d6b77c9ae01 1424 #define I2S_RCR4_FRSZ_SHIFT 16
mturner5 0:0d6b77c9ae01 1425 /* RCR5 Bit Fields */
mturner5 0:0d6b77c9ae01 1426 #define I2S_RCR5_FBT_MASK 0x1F00u
mturner5 0:0d6b77c9ae01 1427 #define I2S_RCR5_FBT_SHIFT 8
mturner5 0:0d6b77c9ae01 1428 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mturner5 0:0d6b77c9ae01 1429 #define I2S_RCR5_W0W_MASK 0x1F0000u
mturner5 0:0d6b77c9ae01 1430 #define I2S_RCR5_W0W_SHIFT 16
mturner5 0:0d6b77c9ae01 1431 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mturner5 0:0d6b77c9ae01 1432 #define I2S_RCR5_WNW_MASK 0x1F000000u
mturner5 0:0d6b77c9ae01 1433 #define I2S_RCR5_WNW_SHIFT 24
mturner5 0:0d6b77c9ae01 1434 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mturner5 0:0d6b77c9ae01 1435 /* RDR Bit Fields */
mturner5 0:0d6b77c9ae01 1436 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1437 #define I2S_RDR_RDR_SHIFT 0
mturner5 0:0d6b77c9ae01 1438 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mturner5 0:0d6b77c9ae01 1439 /* RMR Bit Fields */
mturner5 0:0d6b77c9ae01 1440 #define I2S_RMR_RWM_MASK 0x3u
mturner5 0:0d6b77c9ae01 1441 #define I2S_RMR_RWM_SHIFT 0
mturner5 0:0d6b77c9ae01 1442 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mturner5 0:0d6b77c9ae01 1443 /* MCR Bit Fields */
mturner5 0:0d6b77c9ae01 1444 #define I2S_MCR_MICS_MASK 0x3000000u
mturner5 0:0d6b77c9ae01 1445 #define I2S_MCR_MICS_SHIFT 24
mturner5 0:0d6b77c9ae01 1446 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mturner5 0:0d6b77c9ae01 1447 #define I2S_MCR_MOE_MASK 0x40000000u
mturner5 0:0d6b77c9ae01 1448 #define I2S_MCR_MOE_SHIFT 30
mturner5 0:0d6b77c9ae01 1449 #define I2S_MCR_DUF_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 1450 #define I2S_MCR_DUF_SHIFT 31
mturner5 0:0d6b77c9ae01 1451 /* MDR Bit Fields */
mturner5 0:0d6b77c9ae01 1452 #define I2S_MDR_DIVIDE_MASK 0xFFFu
mturner5 0:0d6b77c9ae01 1453 #define I2S_MDR_DIVIDE_SHIFT 0
mturner5 0:0d6b77c9ae01 1454 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
mturner5 0:0d6b77c9ae01 1455 #define I2S_MDR_FRACT_MASK 0xFF000u
mturner5 0:0d6b77c9ae01 1456 #define I2S_MDR_FRACT_SHIFT 12
mturner5 0:0d6b77c9ae01 1457 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
mturner5 0:0d6b77c9ae01 1458
mturner5 0:0d6b77c9ae01 1459 /*!
mturner5 0:0d6b77c9ae01 1460 * @}
mturner5 0:0d6b77c9ae01 1461 */ /* end of group I2S_Register_Masks */
mturner5 0:0d6b77c9ae01 1462
mturner5 0:0d6b77c9ae01 1463
mturner5 0:0d6b77c9ae01 1464 /* I2S - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 1465 /** Peripheral I2S0 base address */
mturner5 0:0d6b77c9ae01 1466 #define I2S0_BASE (0x4002F000u)
mturner5 0:0d6b77c9ae01 1467 /** Peripheral I2S0 base pointer */
mturner5 0:0d6b77c9ae01 1468 #define I2S0 ((I2S_Type *)I2S0_BASE)
mturner5 0:0d6b77c9ae01 1469 /** Array initializer of I2S peripheral base pointers */
mturner5 0:0d6b77c9ae01 1470 #define I2S_BASES { I2S0 }
mturner5 0:0d6b77c9ae01 1471
mturner5 0:0d6b77c9ae01 1472 /*!
mturner5 0:0d6b77c9ae01 1473 * @}
mturner5 0:0d6b77c9ae01 1474 */ /* end of group I2S_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 1475
mturner5 0:0d6b77c9ae01 1476
mturner5 0:0d6b77c9ae01 1477 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1478 -- LCD Peripheral Access Layer
mturner5 0:0d6b77c9ae01 1479 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1480
mturner5 0:0d6b77c9ae01 1481 /*!
mturner5 0:0d6b77c9ae01 1482 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
mturner5 0:0d6b77c9ae01 1483 * @{
mturner5 0:0d6b77c9ae01 1484 */
mturner5 0:0d6b77c9ae01 1485
mturner5 0:0d6b77c9ae01 1486 /** LCD - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 1487 typedef struct {
mturner5 0:0d6b77c9ae01 1488 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 1489 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 1490 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 1491 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 1492 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
mturner5 0:0d6b77c9ae01 1493 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
mturner5 0:0d6b77c9ae01 1494 union { /* offset: 0x20 */
mturner5 0:0d6b77c9ae01 1495 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
mturner5 0:0d6b77c9ae01 1496 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
mturner5 0:0d6b77c9ae01 1497 };
mturner5 0:0d6b77c9ae01 1498 } LCD_Type;
mturner5 0:0d6b77c9ae01 1499
mturner5 0:0d6b77c9ae01 1500 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 1501 -- LCD Register Masks
mturner5 0:0d6b77c9ae01 1502 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 1503
mturner5 0:0d6b77c9ae01 1504 /*!
mturner5 0:0d6b77c9ae01 1505 * @addtogroup LCD_Register_Masks LCD Register Masks
mturner5 0:0d6b77c9ae01 1506 * @{
mturner5 0:0d6b77c9ae01 1507 */
mturner5 0:0d6b77c9ae01 1508
mturner5 0:0d6b77c9ae01 1509 /* GCR Bit Fields */
mturner5 0:0d6b77c9ae01 1510 #define LCD_GCR_DUTY_MASK 0x7u
mturner5 0:0d6b77c9ae01 1511 #define LCD_GCR_DUTY_SHIFT 0
mturner5 0:0d6b77c9ae01 1512 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
mturner5 0:0d6b77c9ae01 1513 #define LCD_GCR_LCLK_MASK 0x38u
mturner5 0:0d6b77c9ae01 1514 #define LCD_GCR_LCLK_SHIFT 3
mturner5 0:0d6b77c9ae01 1515 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
mturner5 0:0d6b77c9ae01 1516 #define LCD_GCR_SOURCE_MASK 0x40u
mturner5 0:0d6b77c9ae01 1517 #define LCD_GCR_SOURCE_SHIFT 6
mturner5 0:0d6b77c9ae01 1518 #define LCD_GCR_LCDEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 1519 #define LCD_GCR_LCDEN_SHIFT 7
mturner5 0:0d6b77c9ae01 1520 #define LCD_GCR_LCDSTP_MASK 0x100u
mturner5 0:0d6b77c9ae01 1521 #define LCD_GCR_LCDSTP_SHIFT 8
mturner5 0:0d6b77c9ae01 1522 #define LCD_GCR_LCDDOZE_MASK 0x200u
mturner5 0:0d6b77c9ae01 1523 #define LCD_GCR_LCDDOZE_SHIFT 9
mturner5 0:0d6b77c9ae01 1524 #define LCD_GCR_FFR_MASK 0x400u
mturner5 0:0d6b77c9ae01 1525 #define LCD_GCR_FFR_SHIFT 10
mturner5 0:0d6b77c9ae01 1526 #define LCD_GCR_ALTSOURCE_MASK 0x800u
mturner5 0:0d6b77c9ae01 1527 #define LCD_GCR_ALTSOURCE_SHIFT 11
mturner5 0:0d6b77c9ae01 1528 #define LCD_GCR_ALTDIV_MASK 0x3000u
mturner5 0:0d6b77c9ae01 1529 #define LCD_GCR_ALTDIV_SHIFT 12
mturner5 0:0d6b77c9ae01 1530 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
mturner5 0:0d6b77c9ae01 1531 #define LCD_GCR_FDCIEN_MASK 0x4000u
mturner5 0:0d6b77c9ae01 1532 #define LCD_GCR_FDCIEN_SHIFT 14
mturner5 0:0d6b77c9ae01 1533 #define LCD_GCR_PADSAFE_MASK 0x8000u
mturner5 0:0d6b77c9ae01 1534 #define LCD_GCR_PADSAFE_SHIFT 15
mturner5 0:0d6b77c9ae01 1535 #define LCD_GCR_VSUPPLY_MASK 0x20000u
mturner5 0:0d6b77c9ae01 1536 #define LCD_GCR_VSUPPLY_SHIFT 17
mturner5 0:0d6b77c9ae01 1537 #define LCD_GCR_LADJ_MASK 0x300000u
mturner5 0:0d6b77c9ae01 1538 #define LCD_GCR_LADJ_SHIFT 20
mturner5 0:0d6b77c9ae01 1539 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
mturner5 0:0d6b77c9ae01 1540 #define LCD_GCR_CPSEL_MASK 0x800000u
mturner5 0:0d6b77c9ae01 1541 #define LCD_GCR_CPSEL_SHIFT 23
mturner5 0:0d6b77c9ae01 1542 #define LCD_GCR_RVTRIM_MASK 0xF000000u
mturner5 0:0d6b77c9ae01 1543 #define LCD_GCR_RVTRIM_SHIFT 24
mturner5 0:0d6b77c9ae01 1544 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
mturner5 0:0d6b77c9ae01 1545 #define LCD_GCR_RVEN_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 1546 #define LCD_GCR_RVEN_SHIFT 31
mturner5 0:0d6b77c9ae01 1547 /* AR Bit Fields */
mturner5 0:0d6b77c9ae01 1548 #define LCD_AR_BRATE_MASK 0x7u
mturner5 0:0d6b77c9ae01 1549 #define LCD_AR_BRATE_SHIFT 0
mturner5 0:0d6b77c9ae01 1550 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
mturner5 0:0d6b77c9ae01 1551 #define LCD_AR_BMODE_MASK 0x8u
mturner5 0:0d6b77c9ae01 1552 #define LCD_AR_BMODE_SHIFT 3
mturner5 0:0d6b77c9ae01 1553 #define LCD_AR_BLANK_MASK 0x20u
mturner5 0:0d6b77c9ae01 1554 #define LCD_AR_BLANK_SHIFT 5
mturner5 0:0d6b77c9ae01 1555 #define LCD_AR_ALT_MASK 0x40u
mturner5 0:0d6b77c9ae01 1556 #define LCD_AR_ALT_SHIFT 6
mturner5 0:0d6b77c9ae01 1557 #define LCD_AR_BLINK_MASK 0x80u
mturner5 0:0d6b77c9ae01 1558 #define LCD_AR_BLINK_SHIFT 7
mturner5 0:0d6b77c9ae01 1559 /* FDCR Bit Fields */
mturner5 0:0d6b77c9ae01 1560 #define LCD_FDCR_FDPINID_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 1561 #define LCD_FDCR_FDPINID_SHIFT 0
mturner5 0:0d6b77c9ae01 1562 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
mturner5 0:0d6b77c9ae01 1563 #define LCD_FDCR_FDBPEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 1564 #define LCD_FDCR_FDBPEN_SHIFT 6
mturner5 0:0d6b77c9ae01 1565 #define LCD_FDCR_FDEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 1566 #define LCD_FDCR_FDEN_SHIFT 7
mturner5 0:0d6b77c9ae01 1567 #define LCD_FDCR_FDSWW_MASK 0xE00u
mturner5 0:0d6b77c9ae01 1568 #define LCD_FDCR_FDSWW_SHIFT 9
mturner5 0:0d6b77c9ae01 1569 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
mturner5 0:0d6b77c9ae01 1570 #define LCD_FDCR_FDPRS_MASK 0x7000u
mturner5 0:0d6b77c9ae01 1571 #define LCD_FDCR_FDPRS_SHIFT 12
mturner5 0:0d6b77c9ae01 1572 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
mturner5 0:0d6b77c9ae01 1573 /* FDSR Bit Fields */
mturner5 0:0d6b77c9ae01 1574 #define LCD_FDSR_FDCNT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1575 #define LCD_FDSR_FDCNT_SHIFT 0
mturner5 0:0d6b77c9ae01 1576 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
mturner5 0:0d6b77c9ae01 1577 #define LCD_FDSR_FDCF_MASK 0x8000u
mturner5 0:0d6b77c9ae01 1578 #define LCD_FDSR_FDCF_SHIFT 15
mturner5 0:0d6b77c9ae01 1579 /* PEN Bit Fields */
mturner5 0:0d6b77c9ae01 1580 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1581 #define LCD_PEN_PEN_SHIFT 0
mturner5 0:0d6b77c9ae01 1582 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
mturner5 0:0d6b77c9ae01 1583 /* BPEN Bit Fields */
mturner5 0:0d6b77c9ae01 1584 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 1585 #define LCD_BPEN_BPEN_SHIFT 0
mturner5 0:0d6b77c9ae01 1586 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
mturner5 0:0d6b77c9ae01 1587 /* WF Bit Fields */
mturner5 0:0d6b77c9ae01 1588 #define LCD_WF_WF0_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1589 #define LCD_WF_WF0_SHIFT 0
mturner5 0:0d6b77c9ae01 1590 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
mturner5 0:0d6b77c9ae01 1591 #define LCD_WF_WF60_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1592 #define LCD_WF_WF60_SHIFT 0
mturner5 0:0d6b77c9ae01 1593 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
mturner5 0:0d6b77c9ae01 1594 #define LCD_WF_WF56_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1595 #define LCD_WF_WF56_SHIFT 0
mturner5 0:0d6b77c9ae01 1596 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
mturner5 0:0d6b77c9ae01 1597 #define LCD_WF_WF52_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1598 #define LCD_WF_WF52_SHIFT 0
mturner5 0:0d6b77c9ae01 1599 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
mturner5 0:0d6b77c9ae01 1600 #define LCD_WF_WF4_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1601 #define LCD_WF_WF4_SHIFT 0
mturner5 0:0d6b77c9ae01 1602 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
mturner5 0:0d6b77c9ae01 1603 #define LCD_WF_WF48_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1604 #define LCD_WF_WF48_SHIFT 0
mturner5 0:0d6b77c9ae01 1605 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
mturner5 0:0d6b77c9ae01 1606 #define LCD_WF_WF44_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1607 #define LCD_WF_WF44_SHIFT 0
mturner5 0:0d6b77c9ae01 1608 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
mturner5 0:0d6b77c9ae01 1609 #define LCD_WF_WF40_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1610 #define LCD_WF_WF40_SHIFT 0
mturner5 0:0d6b77c9ae01 1611 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
mturner5 0:0d6b77c9ae01 1612 #define LCD_WF_WF8_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1613 #define LCD_WF_WF8_SHIFT 0
mturner5 0:0d6b77c9ae01 1614 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
mturner5 0:0d6b77c9ae01 1615 #define LCD_WF_WF36_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1616 #define LCD_WF_WF36_SHIFT 0
mturner5 0:0d6b77c9ae01 1617 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
mturner5 0:0d6b77c9ae01 1618 #define LCD_WF_WF32_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1619 #define LCD_WF_WF32_SHIFT 0
mturner5 0:0d6b77c9ae01 1620 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
mturner5 0:0d6b77c9ae01 1621 #define LCD_WF_WF28_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1622 #define LCD_WF_WF28_SHIFT 0
mturner5 0:0d6b77c9ae01 1623 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
mturner5 0:0d6b77c9ae01 1624 #define LCD_WF_WF12_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1625 #define LCD_WF_WF12_SHIFT 0
mturner5 0:0d6b77c9ae01 1626 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
mturner5 0:0d6b77c9ae01 1627 #define LCD_WF_WF24_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1628 #define LCD_WF_WF24_SHIFT 0
mturner5 0:0d6b77c9ae01 1629 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
mturner5 0:0d6b77c9ae01 1630 #define LCD_WF_WF20_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1631 #define LCD_WF_WF20_SHIFT 0
mturner5 0:0d6b77c9ae01 1632 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
mturner5 0:0d6b77c9ae01 1633 #define LCD_WF_WF16_MASK 0xFFu
mturner5 0:0d6b77c9ae01 1634 #define LCD_WF_WF16_SHIFT 0
mturner5 0:0d6b77c9ae01 1635 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
mturner5 0:0d6b77c9ae01 1636 #define LCD_WF_WF5_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1637 #define LCD_WF_WF5_SHIFT 8
mturner5 0:0d6b77c9ae01 1638 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
mturner5 0:0d6b77c9ae01 1639 #define LCD_WF_WF49_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1640 #define LCD_WF_WF49_SHIFT 8
mturner5 0:0d6b77c9ae01 1641 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
mturner5 0:0d6b77c9ae01 1642 #define LCD_WF_WF45_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1643 #define LCD_WF_WF45_SHIFT 8
mturner5 0:0d6b77c9ae01 1644 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
mturner5 0:0d6b77c9ae01 1645 #define LCD_WF_WF61_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1646 #define LCD_WF_WF61_SHIFT 8
mturner5 0:0d6b77c9ae01 1647 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
mturner5 0:0d6b77c9ae01 1648 #define LCD_WF_WF25_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1649 #define LCD_WF_WF25_SHIFT 8
mturner5 0:0d6b77c9ae01 1650 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
mturner5 0:0d6b77c9ae01 1651 #define LCD_WF_WF17_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1652 #define LCD_WF_WF17_SHIFT 8
mturner5 0:0d6b77c9ae01 1653 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
mturner5 0:0d6b77c9ae01 1654 #define LCD_WF_WF41_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1655 #define LCD_WF_WF41_SHIFT 8
mturner5 0:0d6b77c9ae01 1656 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
mturner5 0:0d6b77c9ae01 1657 #define LCD_WF_WF13_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1658 #define LCD_WF_WF13_SHIFT 8
mturner5 0:0d6b77c9ae01 1659 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
mturner5 0:0d6b77c9ae01 1660 #define LCD_WF_WF57_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1661 #define LCD_WF_WF57_SHIFT 8
mturner5 0:0d6b77c9ae01 1662 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
mturner5 0:0d6b77c9ae01 1663 #define LCD_WF_WF53_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1664 #define LCD_WF_WF53_SHIFT 8
mturner5 0:0d6b77c9ae01 1665 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
mturner5 0:0d6b77c9ae01 1666 #define LCD_WF_WF37_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1667 #define LCD_WF_WF37_SHIFT 8
mturner5 0:0d6b77c9ae01 1668 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
mturner5 0:0d6b77c9ae01 1669 #define LCD_WF_WF9_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1670 #define LCD_WF_WF9_SHIFT 8
mturner5 0:0d6b77c9ae01 1671 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
mturner5 0:0d6b77c9ae01 1672 #define LCD_WF_WF1_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1673 #define LCD_WF_WF1_SHIFT 8
mturner5 0:0d6b77c9ae01 1674 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
mturner5 0:0d6b77c9ae01 1675 #define LCD_WF_WF29_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1676 #define LCD_WF_WF29_SHIFT 8
mturner5 0:0d6b77c9ae01 1677 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
mturner5 0:0d6b77c9ae01 1678 #define LCD_WF_WF33_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1679 #define LCD_WF_WF33_SHIFT 8
mturner5 0:0d6b77c9ae01 1680 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
mturner5 0:0d6b77c9ae01 1681 #define LCD_WF_WF21_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 1682 #define LCD_WF_WF21_SHIFT 8
mturner5 0:0d6b77c9ae01 1683 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
mturner5 0:0d6b77c9ae01 1684 #define LCD_WF_WF26_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1685 #define LCD_WF_WF26_SHIFT 16
mturner5 0:0d6b77c9ae01 1686 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
mturner5 0:0d6b77c9ae01 1687 #define LCD_WF_WF46_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1688 #define LCD_WF_WF46_SHIFT 16
mturner5 0:0d6b77c9ae01 1689 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
mturner5 0:0d6b77c9ae01 1690 #define LCD_WF_WF6_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1691 #define LCD_WF_WF6_SHIFT 16
mturner5 0:0d6b77c9ae01 1692 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
mturner5 0:0d6b77c9ae01 1693 #define LCD_WF_WF42_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1694 #define LCD_WF_WF42_SHIFT 16
mturner5 0:0d6b77c9ae01 1695 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
mturner5 0:0d6b77c9ae01 1696 #define LCD_WF_WF18_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1697 #define LCD_WF_WF18_SHIFT 16
mturner5 0:0d6b77c9ae01 1698 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
mturner5 0:0d6b77c9ae01 1699 #define LCD_WF_WF38_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1700 #define LCD_WF_WF38_SHIFT 16
mturner5 0:0d6b77c9ae01 1701 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
mturner5 0:0d6b77c9ae01 1702 #define LCD_WF_WF22_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1703 #define LCD_WF_WF22_SHIFT 16
mturner5 0:0d6b77c9ae01 1704 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
mturner5 0:0d6b77c9ae01 1705 #define LCD_WF_WF34_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1706 #define LCD_WF_WF34_SHIFT 16
mturner5 0:0d6b77c9ae01 1707 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
mturner5 0:0d6b77c9ae01 1708 #define LCD_WF_WF50_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1709 #define LCD_WF_WF50_SHIFT 16
mturner5 0:0d6b77c9ae01 1710 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
mturner5 0:0d6b77c9ae01 1711 #define LCD_WF_WF14_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1712 #define LCD_WF_WF14_SHIFT 16
mturner5 0:0d6b77c9ae01 1713 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
mturner5 0:0d6b77c9ae01 1714 #define LCD_WF_WF54_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1715 #define LCD_WF_WF54_SHIFT 16
mturner5 0:0d6b77c9ae01 1716 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
mturner5 0:0d6b77c9ae01 1717 #define LCD_WF_WF2_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1718 #define LCD_WF_WF2_SHIFT 16
mturner5 0:0d6b77c9ae01 1719 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
mturner5 0:0d6b77c9ae01 1720 #define LCD_WF_WF58_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1721 #define LCD_WF_WF58_SHIFT 16
mturner5 0:0d6b77c9ae01 1722 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
mturner5 0:0d6b77c9ae01 1723 #define LCD_WF_WF30_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1724 #define LCD_WF_WF30_SHIFT 16
mturner5 0:0d6b77c9ae01 1725 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
mturner5 0:0d6b77c9ae01 1726 #define LCD_WF_WF62_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1727 #define LCD_WF_WF62_SHIFT 16
mturner5 0:0d6b77c9ae01 1728 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
mturner5 0:0d6b77c9ae01 1729 #define LCD_WF_WF10_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 1730 #define LCD_WF_WF10_SHIFT 16
mturner5 0:0d6b77c9ae01 1731 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
mturner5 0:0d6b77c9ae01 1732 #define LCD_WF_WF63_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1733 #define LCD_WF_WF63_SHIFT 24
mturner5 0:0d6b77c9ae01 1734 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
mturner5 0:0d6b77c9ae01 1735 #define LCD_WF_WF59_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1736 #define LCD_WF_WF59_SHIFT 24
mturner5 0:0d6b77c9ae01 1737 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
mturner5 0:0d6b77c9ae01 1738 #define LCD_WF_WF55_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1739 #define LCD_WF_WF55_SHIFT 24
mturner5 0:0d6b77c9ae01 1740 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
mturner5 0:0d6b77c9ae01 1741 #define LCD_WF_WF3_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1742 #define LCD_WF_WF3_SHIFT 24
mturner5 0:0d6b77c9ae01 1743 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
mturner5 0:0d6b77c9ae01 1744 #define LCD_WF_WF51_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1745 #define LCD_WF_WF51_SHIFT 24
mturner5 0:0d6b77c9ae01 1746 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
mturner5 0:0d6b77c9ae01 1747 #define LCD_WF_WF47_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1748 #define LCD_WF_WF47_SHIFT 24
mturner5 0:0d6b77c9ae01 1749 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
mturner5 0:0d6b77c9ae01 1750 #define LCD_WF_WF43_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1751 #define LCD_WF_WF43_SHIFT 24
mturner5 0:0d6b77c9ae01 1752 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
mturner5 0:0d6b77c9ae01 1753 #define LCD_WF_WF7_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1754 #define LCD_WF_WF7_SHIFT 24
mturner5 0:0d6b77c9ae01 1755 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
mturner5 0:0d6b77c9ae01 1756 #define LCD_WF_WF39_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1757 #define LCD_WF_WF39_SHIFT 24
mturner5 0:0d6b77c9ae01 1758 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
mturner5 0:0d6b77c9ae01 1759 #define LCD_WF_WF35_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1760 #define LCD_WF_WF35_SHIFT 24
mturner5 0:0d6b77c9ae01 1761 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
mturner5 0:0d6b77c9ae01 1762 #define LCD_WF_WF31_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1763 #define LCD_WF_WF31_SHIFT 24
mturner5 0:0d6b77c9ae01 1764 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
mturner5 0:0d6b77c9ae01 1765 #define LCD_WF_WF11_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1766 #define LCD_WF_WF11_SHIFT 24
mturner5 0:0d6b77c9ae01 1767 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
mturner5 0:0d6b77c9ae01 1768 #define LCD_WF_WF27_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1769 #define LCD_WF_WF27_SHIFT 24
mturner5 0:0d6b77c9ae01 1770 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
mturner5 0:0d6b77c9ae01 1771 #define LCD_WF_WF23_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1772 #define LCD_WF_WF23_SHIFT 24
mturner5 0:0d6b77c9ae01 1773 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
mturner5 0:0d6b77c9ae01 1774 #define LCD_WF_WF19_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1775 #define LCD_WF_WF19_SHIFT 24
mturner5 0:0d6b77c9ae01 1776 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
mturner5 0:0d6b77c9ae01 1777 #define LCD_WF_WF15_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 1778 #define LCD_WF_WF15_SHIFT 24
mturner5 0:0d6b77c9ae01 1779 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
mturner5 0:0d6b77c9ae01 1780 /* WF8B Bit Fields */
mturner5 0:0d6b77c9ae01 1781 #define LCD_WF8B_BPALCD0_MASK 0x1u
mturner5 0:0d6b77c9ae01 1782 #define LCD_WF8B_BPALCD0_SHIFT 0
mturner5 0:0d6b77c9ae01 1783 #define LCD_WF8B_BPALCD63_MASK 0x1u
mturner5 0:0d6b77c9ae01 1784 #define LCD_WF8B_BPALCD63_SHIFT 0
mturner5 0:0d6b77c9ae01 1785 #define LCD_WF8B_BPALCD62_MASK 0x1u
mturner5 0:0d6b77c9ae01 1786 #define LCD_WF8B_BPALCD62_SHIFT 0
mturner5 0:0d6b77c9ae01 1787 #define LCD_WF8B_BPALCD61_MASK 0x1u
mturner5 0:0d6b77c9ae01 1788 #define LCD_WF8B_BPALCD61_SHIFT 0
mturner5 0:0d6b77c9ae01 1789 #define LCD_WF8B_BPALCD60_MASK 0x1u
mturner5 0:0d6b77c9ae01 1790 #define LCD_WF8B_BPALCD60_SHIFT 0
mturner5 0:0d6b77c9ae01 1791 #define LCD_WF8B_BPALCD59_MASK 0x1u
mturner5 0:0d6b77c9ae01 1792 #define LCD_WF8B_BPALCD59_SHIFT 0
mturner5 0:0d6b77c9ae01 1793 #define LCD_WF8B_BPALCD58_MASK 0x1u
mturner5 0:0d6b77c9ae01 1794 #define LCD_WF8B_BPALCD58_SHIFT 0
mturner5 0:0d6b77c9ae01 1795 #define LCD_WF8B_BPALCD57_MASK 0x1u
mturner5 0:0d6b77c9ae01 1796 #define LCD_WF8B_BPALCD57_SHIFT 0
mturner5 0:0d6b77c9ae01 1797 #define LCD_WF8B_BPALCD1_MASK 0x1u
mturner5 0:0d6b77c9ae01 1798 #define LCD_WF8B_BPALCD1_SHIFT 0
mturner5 0:0d6b77c9ae01 1799 #define LCD_WF8B_BPALCD56_MASK 0x1u
mturner5 0:0d6b77c9ae01 1800 #define LCD_WF8B_BPALCD56_SHIFT 0
mturner5 0:0d6b77c9ae01 1801 #define LCD_WF8B_BPALCD55_MASK 0x1u
mturner5 0:0d6b77c9ae01 1802 #define LCD_WF8B_BPALCD55_SHIFT 0
mturner5 0:0d6b77c9ae01 1803 #define LCD_WF8B_BPALCD54_MASK 0x1u
mturner5 0:0d6b77c9ae01 1804 #define LCD_WF8B_BPALCD54_SHIFT 0
mturner5 0:0d6b77c9ae01 1805 #define LCD_WF8B_BPALCD53_MASK 0x1u
mturner5 0:0d6b77c9ae01 1806 #define LCD_WF8B_BPALCD53_SHIFT 0
mturner5 0:0d6b77c9ae01 1807 #define LCD_WF8B_BPALCD52_MASK 0x1u
mturner5 0:0d6b77c9ae01 1808 #define LCD_WF8B_BPALCD52_SHIFT 0
mturner5 0:0d6b77c9ae01 1809 #define LCD_WF8B_BPALCD51_MASK 0x1u
mturner5 0:0d6b77c9ae01 1810 #define LCD_WF8B_BPALCD51_SHIFT 0
mturner5 0:0d6b77c9ae01 1811 #define LCD_WF8B_BPALCD50_MASK 0x1u
mturner5 0:0d6b77c9ae01 1812 #define LCD_WF8B_BPALCD50_SHIFT 0
mturner5 0:0d6b77c9ae01 1813 #define LCD_WF8B_BPALCD2_MASK 0x1u
mturner5 0:0d6b77c9ae01 1814 #define LCD_WF8B_BPALCD2_SHIFT 0
mturner5 0:0d6b77c9ae01 1815 #define LCD_WF8B_BPALCD49_MASK 0x1u
mturner5 0:0d6b77c9ae01 1816 #define LCD_WF8B_BPALCD49_SHIFT 0
mturner5 0:0d6b77c9ae01 1817 #define LCD_WF8B_BPALCD48_MASK 0x1u
mturner5 0:0d6b77c9ae01 1818 #define LCD_WF8B_BPALCD48_SHIFT 0
mturner5 0:0d6b77c9ae01 1819 #define LCD_WF8B_BPALCD47_MASK 0x1u
mturner5 0:0d6b77c9ae01 1820 #define LCD_WF8B_BPALCD47_SHIFT 0
mturner5 0:0d6b77c9ae01 1821 #define LCD_WF8B_BPALCD46_MASK 0x1u
mturner5 0:0d6b77c9ae01 1822 #define LCD_WF8B_BPALCD46_SHIFT 0
mturner5 0:0d6b77c9ae01 1823 #define LCD_WF8B_BPALCD45_MASK 0x1u
mturner5 0:0d6b77c9ae01 1824 #define LCD_WF8B_BPALCD45_SHIFT 0
mturner5 0:0d6b77c9ae01 1825 #define LCD_WF8B_BPALCD44_MASK 0x1u
mturner5 0:0d6b77c9ae01 1826 #define LCD_WF8B_BPALCD44_SHIFT 0
mturner5 0:0d6b77c9ae01 1827 #define LCD_WF8B_BPALCD43_MASK 0x1u
mturner5 0:0d6b77c9ae01 1828 #define LCD_WF8B_BPALCD43_SHIFT 0
mturner5 0:0d6b77c9ae01 1829 #define LCD_WF8B_BPALCD3_MASK 0x1u
mturner5 0:0d6b77c9ae01 1830 #define LCD_WF8B_BPALCD3_SHIFT 0
mturner5 0:0d6b77c9ae01 1831 #define LCD_WF8B_BPALCD42_MASK 0x1u
mturner5 0:0d6b77c9ae01 1832 #define LCD_WF8B_BPALCD42_SHIFT 0
mturner5 0:0d6b77c9ae01 1833 #define LCD_WF8B_BPALCD41_MASK 0x1u
mturner5 0:0d6b77c9ae01 1834 #define LCD_WF8B_BPALCD41_SHIFT 0
mturner5 0:0d6b77c9ae01 1835 #define LCD_WF8B_BPALCD40_MASK 0x1u
mturner5 0:0d6b77c9ae01 1836 #define LCD_WF8B_BPALCD40_SHIFT 0
mturner5 0:0d6b77c9ae01 1837 #define LCD_WF8B_BPALCD39_MASK 0x1u
mturner5 0:0d6b77c9ae01 1838 #define LCD_WF8B_BPALCD39_SHIFT 0
mturner5 0:0d6b77c9ae01 1839 #define LCD_WF8B_BPALCD38_MASK 0x1u
mturner5 0:0d6b77c9ae01 1840 #define LCD_WF8B_BPALCD38_SHIFT 0
mturner5 0:0d6b77c9ae01 1841 #define LCD_WF8B_BPALCD37_MASK 0x1u
mturner5 0:0d6b77c9ae01 1842 #define LCD_WF8B_BPALCD37_SHIFT 0
mturner5 0:0d6b77c9ae01 1843 #define LCD_WF8B_BPALCD36_MASK 0x1u
mturner5 0:0d6b77c9ae01 1844 #define LCD_WF8B_BPALCD36_SHIFT 0
mturner5 0:0d6b77c9ae01 1845 #define LCD_WF8B_BPALCD4_MASK 0x1u
mturner5 0:0d6b77c9ae01 1846 #define LCD_WF8B_BPALCD4_SHIFT 0
mturner5 0:0d6b77c9ae01 1847 #define LCD_WF8B_BPALCD35_MASK 0x1u
mturner5 0:0d6b77c9ae01 1848 #define LCD_WF8B_BPALCD35_SHIFT 0
mturner5 0:0d6b77c9ae01 1849 #define LCD_WF8B_BPALCD34_MASK 0x1u
mturner5 0:0d6b77c9ae01 1850 #define LCD_WF8B_BPALCD34_SHIFT 0
mturner5 0:0d6b77c9ae01 1851 #define LCD_WF8B_BPALCD33_MASK 0x1u
mturner5 0:0d6b77c9ae01 1852 #define LCD_WF8B_BPALCD33_SHIFT 0
mturner5 0:0d6b77c9ae01 1853 #define LCD_WF8B_BPALCD32_MASK 0x1u
mturner5 0:0d6b77c9ae01 1854 #define LCD_WF8B_BPALCD32_SHIFT 0
mturner5 0:0d6b77c9ae01 1855 #define LCD_WF8B_BPALCD31_MASK 0x1u
mturner5 0:0d6b77c9ae01 1856 #define LCD_WF8B_BPALCD31_SHIFT 0
mturner5 0:0d6b77c9ae01 1857 #define LCD_WF8B_BPALCD30_MASK 0x1u
mturner5 0:0d6b77c9ae01 1858 #define LCD_WF8B_BPALCD30_SHIFT 0
mturner5 0:0d6b77c9ae01 1859 #define LCD_WF8B_BPALCD29_MASK 0x1u
mturner5 0:0d6b77c9ae01 1860 #define LCD_WF8B_BPALCD29_SHIFT 0
mturner5 0:0d6b77c9ae01 1861 #define LCD_WF8B_BPALCD5_MASK 0x1u
mturner5 0:0d6b77c9ae01 1862 #define LCD_WF8B_BPALCD5_SHIFT 0
mturner5 0:0d6b77c9ae01 1863 #define LCD_WF8B_BPALCD28_MASK 0x1u
mturner5 0:0d6b77c9ae01 1864 #define LCD_WF8B_BPALCD28_SHIFT 0
mturner5 0:0d6b77c9ae01 1865 #define LCD_WF8B_BPALCD27_MASK 0x1u
mturner5 0:0d6b77c9ae01 1866 #define LCD_WF8B_BPALCD27_SHIFT 0
mturner5 0:0d6b77c9ae01 1867 #define LCD_WF8B_BPALCD26_MASK 0x1u
mturner5 0:0d6b77c9ae01 1868 #define LCD_WF8B_BPALCD26_SHIFT 0
mturner5 0:0d6b77c9ae01 1869 #define LCD_WF8B_BPALCD25_MASK 0x1u
mturner5 0:0d6b77c9ae01 1870 #define LCD_WF8B_BPALCD25_SHIFT 0
mturner5 0:0d6b77c9ae01 1871 #define LCD_WF8B_BPALCD24_MASK 0x1u
mturner5 0:0d6b77c9ae01 1872 #define LCD_WF8B_BPALCD24_SHIFT 0
mturner5 0:0d6b77c9ae01 1873 #define LCD_WF8B_BPALCD23_MASK 0x1u
mturner5 0:0d6b77c9ae01 1874 #define LCD_WF8B_BPALCD23_SHIFT 0
mturner5 0:0d6b77c9ae01 1875 #define LCD_WF8B_BPALCD22_MASK 0x1u
mturner5 0:0d6b77c9ae01 1876 #define LCD_WF8B_BPALCD22_SHIFT 0
mturner5 0:0d6b77c9ae01 1877 #define LCD_WF8B_BPALCD6_MASK 0x1u
mturner5 0:0d6b77c9ae01 1878 #define LCD_WF8B_BPALCD6_SHIFT 0
mturner5 0:0d6b77c9ae01 1879 #define LCD_WF8B_BPALCD21_MASK 0x1u
mturner5 0:0d6b77c9ae01 1880 #define LCD_WF8B_BPALCD21_SHIFT 0
mturner5 0:0d6b77c9ae01 1881 #define LCD_WF8B_BPALCD20_MASK 0x1u
mturner5 0:0d6b77c9ae01 1882 #define LCD_WF8B_BPALCD20_SHIFT 0
mturner5 0:0d6b77c9ae01 1883 #define LCD_WF8B_BPALCD19_MASK 0x1u
mturner5 0:0d6b77c9ae01 1884 #define LCD_WF8B_BPALCD19_SHIFT 0
mturner5 0:0d6b77c9ae01 1885 #define LCD_WF8B_BPALCD18_MASK 0x1u
mturner5 0:0d6b77c9ae01 1886 #define LCD_WF8B_BPALCD18_SHIFT 0
mturner5 0:0d6b77c9ae01 1887 #define LCD_WF8B_BPALCD17_MASK 0x1u
mturner5 0:0d6b77c9ae01 1888 #define LCD_WF8B_BPALCD17_SHIFT 0
mturner5 0:0d6b77c9ae01 1889 #define LCD_WF8B_BPALCD16_MASK 0x1u
mturner5 0:0d6b77c9ae01 1890 #define LCD_WF8B_BPALCD16_SHIFT 0
mturner5 0:0d6b77c9ae01 1891 #define LCD_WF8B_BPALCD15_MASK 0x1u
mturner5 0:0d6b77c9ae01 1892 #define LCD_WF8B_BPALCD15_SHIFT 0
mturner5 0:0d6b77c9ae01 1893 #define LCD_WF8B_BPALCD7_MASK 0x1u
mturner5 0:0d6b77c9ae01 1894 #define LCD_WF8B_BPALCD7_SHIFT 0
mturner5 0:0d6b77c9ae01 1895 #define LCD_WF8B_BPALCD14_MASK 0x1u
mturner5 0:0d6b77c9ae01 1896 #define LCD_WF8B_BPALCD14_SHIFT 0
mturner5 0:0d6b77c9ae01 1897 #define LCD_WF8B_BPALCD13_MASK 0x1u
mturner5 0:0d6b77c9ae01 1898 #define LCD_WF8B_BPALCD13_SHIFT 0
mturner5 0:0d6b77c9ae01 1899 #define LCD_WF8B_BPALCD12_MASK 0x1u
mturner5 0:0d6b77c9ae01 1900 #define LCD_WF8B_BPALCD12_SHIFT 0
mturner5 0:0d6b77c9ae01 1901 #define LCD_WF8B_BPALCD11_MASK 0x1u
mturner5 0:0d6b77c9ae01 1902 #define LCD_WF8B_BPALCD11_SHIFT 0
mturner5 0:0d6b77c9ae01 1903 #define LCD_WF8B_BPALCD10_MASK 0x1u
mturner5 0:0d6b77c9ae01 1904 #define LCD_WF8B_BPALCD10_SHIFT 0
mturner5 0:0d6b77c9ae01 1905 #define LCD_WF8B_BPALCD9_MASK 0x1u
mturner5 0:0d6b77c9ae01 1906 #define LCD_WF8B_BPALCD9_SHIFT 0
mturner5 0:0d6b77c9ae01 1907 #define LCD_WF8B_BPALCD8_MASK 0x1u
mturner5 0:0d6b77c9ae01 1908 #define LCD_WF8B_BPALCD8_SHIFT 0
mturner5 0:0d6b77c9ae01 1909 #define LCD_WF8B_BPBLCD1_MASK 0x2u
mturner5 0:0d6b77c9ae01 1910 #define LCD_WF8B_BPBLCD1_SHIFT 1
mturner5 0:0d6b77c9ae01 1911 #define LCD_WF8B_BPBLCD32_MASK 0x2u
mturner5 0:0d6b77c9ae01 1912 #define LCD_WF8B_BPBLCD32_SHIFT 1
mturner5 0:0d6b77c9ae01 1913 #define LCD_WF8B_BPBLCD30_MASK 0x2u
mturner5 0:0d6b77c9ae01 1914 #define LCD_WF8B_BPBLCD30_SHIFT 1
mturner5 0:0d6b77c9ae01 1915 #define LCD_WF8B_BPBLCD60_MASK 0x2u
mturner5 0:0d6b77c9ae01 1916 #define LCD_WF8B_BPBLCD60_SHIFT 1
mturner5 0:0d6b77c9ae01 1917 #define LCD_WF8B_BPBLCD24_MASK 0x2u
mturner5 0:0d6b77c9ae01 1918 #define LCD_WF8B_BPBLCD24_SHIFT 1
mturner5 0:0d6b77c9ae01 1919 #define LCD_WF8B_BPBLCD28_MASK 0x2u
mturner5 0:0d6b77c9ae01 1920 #define LCD_WF8B_BPBLCD28_SHIFT 1
mturner5 0:0d6b77c9ae01 1921 #define LCD_WF8B_BPBLCD23_MASK 0x2u
mturner5 0:0d6b77c9ae01 1922 #define LCD_WF8B_BPBLCD23_SHIFT 1
mturner5 0:0d6b77c9ae01 1923 #define LCD_WF8B_BPBLCD48_MASK 0x2u
mturner5 0:0d6b77c9ae01 1924 #define LCD_WF8B_BPBLCD48_SHIFT 1
mturner5 0:0d6b77c9ae01 1925 #define LCD_WF8B_BPBLCD10_MASK 0x2u
mturner5 0:0d6b77c9ae01 1926 #define LCD_WF8B_BPBLCD10_SHIFT 1
mturner5 0:0d6b77c9ae01 1927 #define LCD_WF8B_BPBLCD15_MASK 0x2u
mturner5 0:0d6b77c9ae01 1928 #define LCD_WF8B_BPBLCD15_SHIFT 1
mturner5 0:0d6b77c9ae01 1929 #define LCD_WF8B_BPBLCD36_MASK 0x2u
mturner5 0:0d6b77c9ae01 1930 #define LCD_WF8B_BPBLCD36_SHIFT 1
mturner5 0:0d6b77c9ae01 1931 #define LCD_WF8B_BPBLCD44_MASK 0x2u
mturner5 0:0d6b77c9ae01 1932 #define LCD_WF8B_BPBLCD44_SHIFT 1
mturner5 0:0d6b77c9ae01 1933 #define LCD_WF8B_BPBLCD62_MASK 0x2u
mturner5 0:0d6b77c9ae01 1934 #define LCD_WF8B_BPBLCD62_SHIFT 1
mturner5 0:0d6b77c9ae01 1935 #define LCD_WF8B_BPBLCD53_MASK 0x2u
mturner5 0:0d6b77c9ae01 1936 #define LCD_WF8B_BPBLCD53_SHIFT 1
mturner5 0:0d6b77c9ae01 1937 #define LCD_WF8B_BPBLCD22_MASK 0x2u
mturner5 0:0d6b77c9ae01 1938 #define LCD_WF8B_BPBLCD22_SHIFT 1
mturner5 0:0d6b77c9ae01 1939 #define LCD_WF8B_BPBLCD47_MASK 0x2u
mturner5 0:0d6b77c9ae01 1940 #define LCD_WF8B_BPBLCD47_SHIFT 1
mturner5 0:0d6b77c9ae01 1941 #define LCD_WF8B_BPBLCD33_MASK 0x2u
mturner5 0:0d6b77c9ae01 1942 #define LCD_WF8B_BPBLCD33_SHIFT 1
mturner5 0:0d6b77c9ae01 1943 #define LCD_WF8B_BPBLCD2_MASK 0x2u
mturner5 0:0d6b77c9ae01 1944 #define LCD_WF8B_BPBLCD2_SHIFT 1
mturner5 0:0d6b77c9ae01 1945 #define LCD_WF8B_BPBLCD49_MASK 0x2u
mturner5 0:0d6b77c9ae01 1946 #define LCD_WF8B_BPBLCD49_SHIFT 1
mturner5 0:0d6b77c9ae01 1947 #define LCD_WF8B_BPBLCD0_MASK 0x2u
mturner5 0:0d6b77c9ae01 1948 #define LCD_WF8B_BPBLCD0_SHIFT 1
mturner5 0:0d6b77c9ae01 1949 #define LCD_WF8B_BPBLCD55_MASK 0x2u
mturner5 0:0d6b77c9ae01 1950 #define LCD_WF8B_BPBLCD55_SHIFT 1
mturner5 0:0d6b77c9ae01 1951 #define LCD_WF8B_BPBLCD56_MASK 0x2u
mturner5 0:0d6b77c9ae01 1952 #define LCD_WF8B_BPBLCD56_SHIFT 1
mturner5 0:0d6b77c9ae01 1953 #define LCD_WF8B_BPBLCD21_MASK 0x2u
mturner5 0:0d6b77c9ae01 1954 #define LCD_WF8B_BPBLCD21_SHIFT 1
mturner5 0:0d6b77c9ae01 1955 #define LCD_WF8B_BPBLCD6_MASK 0x2u
mturner5 0:0d6b77c9ae01 1956 #define LCD_WF8B_BPBLCD6_SHIFT 1
mturner5 0:0d6b77c9ae01 1957 #define LCD_WF8B_BPBLCD29_MASK 0x2u
mturner5 0:0d6b77c9ae01 1958 #define LCD_WF8B_BPBLCD29_SHIFT 1
mturner5 0:0d6b77c9ae01 1959 #define LCD_WF8B_BPBLCD25_MASK 0x2u
mturner5 0:0d6b77c9ae01 1960 #define LCD_WF8B_BPBLCD25_SHIFT 1
mturner5 0:0d6b77c9ae01 1961 #define LCD_WF8B_BPBLCD8_MASK 0x2u
mturner5 0:0d6b77c9ae01 1962 #define LCD_WF8B_BPBLCD8_SHIFT 1
mturner5 0:0d6b77c9ae01 1963 #define LCD_WF8B_BPBLCD54_MASK 0x2u
mturner5 0:0d6b77c9ae01 1964 #define LCD_WF8B_BPBLCD54_SHIFT 1
mturner5 0:0d6b77c9ae01 1965 #define LCD_WF8B_BPBLCD38_MASK 0x2u
mturner5 0:0d6b77c9ae01 1966 #define LCD_WF8B_BPBLCD38_SHIFT 1
mturner5 0:0d6b77c9ae01 1967 #define LCD_WF8B_BPBLCD43_MASK 0x2u
mturner5 0:0d6b77c9ae01 1968 #define LCD_WF8B_BPBLCD43_SHIFT 1
mturner5 0:0d6b77c9ae01 1969 #define LCD_WF8B_BPBLCD20_MASK 0x2u
mturner5 0:0d6b77c9ae01 1970 #define LCD_WF8B_BPBLCD20_SHIFT 1
mturner5 0:0d6b77c9ae01 1971 #define LCD_WF8B_BPBLCD9_MASK 0x2u
mturner5 0:0d6b77c9ae01 1972 #define LCD_WF8B_BPBLCD9_SHIFT 1
mturner5 0:0d6b77c9ae01 1973 #define LCD_WF8B_BPBLCD7_MASK 0x2u
mturner5 0:0d6b77c9ae01 1974 #define LCD_WF8B_BPBLCD7_SHIFT 1
mturner5 0:0d6b77c9ae01 1975 #define LCD_WF8B_BPBLCD50_MASK 0x2u
mturner5 0:0d6b77c9ae01 1976 #define LCD_WF8B_BPBLCD50_SHIFT 1
mturner5 0:0d6b77c9ae01 1977 #define LCD_WF8B_BPBLCD40_MASK 0x2u
mturner5 0:0d6b77c9ae01 1978 #define LCD_WF8B_BPBLCD40_SHIFT 1
mturner5 0:0d6b77c9ae01 1979 #define LCD_WF8B_BPBLCD63_MASK 0x2u
mturner5 0:0d6b77c9ae01 1980 #define LCD_WF8B_BPBLCD63_SHIFT 1
mturner5 0:0d6b77c9ae01 1981 #define LCD_WF8B_BPBLCD26_MASK 0x2u
mturner5 0:0d6b77c9ae01 1982 #define LCD_WF8B_BPBLCD26_SHIFT 1
mturner5 0:0d6b77c9ae01 1983 #define LCD_WF8B_BPBLCD12_MASK 0x2u
mturner5 0:0d6b77c9ae01 1984 #define LCD_WF8B_BPBLCD12_SHIFT 1
mturner5 0:0d6b77c9ae01 1985 #define LCD_WF8B_BPBLCD19_MASK 0x2u
mturner5 0:0d6b77c9ae01 1986 #define LCD_WF8B_BPBLCD19_SHIFT 1
mturner5 0:0d6b77c9ae01 1987 #define LCD_WF8B_BPBLCD34_MASK 0x2u
mturner5 0:0d6b77c9ae01 1988 #define LCD_WF8B_BPBLCD34_SHIFT 1
mturner5 0:0d6b77c9ae01 1989 #define LCD_WF8B_BPBLCD39_MASK 0x2u
mturner5 0:0d6b77c9ae01 1990 #define LCD_WF8B_BPBLCD39_SHIFT 1
mturner5 0:0d6b77c9ae01 1991 #define LCD_WF8B_BPBLCD59_MASK 0x2u
mturner5 0:0d6b77c9ae01 1992 #define LCD_WF8B_BPBLCD59_SHIFT 1
mturner5 0:0d6b77c9ae01 1993 #define LCD_WF8B_BPBLCD61_MASK 0x2u
mturner5 0:0d6b77c9ae01 1994 #define LCD_WF8B_BPBLCD61_SHIFT 1
mturner5 0:0d6b77c9ae01 1995 #define LCD_WF8B_BPBLCD37_MASK 0x2u
mturner5 0:0d6b77c9ae01 1996 #define LCD_WF8B_BPBLCD37_SHIFT 1
mturner5 0:0d6b77c9ae01 1997 #define LCD_WF8B_BPBLCD31_MASK 0x2u
mturner5 0:0d6b77c9ae01 1998 #define LCD_WF8B_BPBLCD31_SHIFT 1
mturner5 0:0d6b77c9ae01 1999 #define LCD_WF8B_BPBLCD58_MASK 0x2u
mturner5 0:0d6b77c9ae01 2000 #define LCD_WF8B_BPBLCD58_SHIFT 1
mturner5 0:0d6b77c9ae01 2001 #define LCD_WF8B_BPBLCD18_MASK 0x2u
mturner5 0:0d6b77c9ae01 2002 #define LCD_WF8B_BPBLCD18_SHIFT 1
mturner5 0:0d6b77c9ae01 2003 #define LCD_WF8B_BPBLCD45_MASK 0x2u
mturner5 0:0d6b77c9ae01 2004 #define LCD_WF8B_BPBLCD45_SHIFT 1
mturner5 0:0d6b77c9ae01 2005 #define LCD_WF8B_BPBLCD27_MASK 0x2u
mturner5 0:0d6b77c9ae01 2006 #define LCD_WF8B_BPBLCD27_SHIFT 1
mturner5 0:0d6b77c9ae01 2007 #define LCD_WF8B_BPBLCD14_MASK 0x2u
mturner5 0:0d6b77c9ae01 2008 #define LCD_WF8B_BPBLCD14_SHIFT 1
mturner5 0:0d6b77c9ae01 2009 #define LCD_WF8B_BPBLCD51_MASK 0x2u
mturner5 0:0d6b77c9ae01 2010 #define LCD_WF8B_BPBLCD51_SHIFT 1
mturner5 0:0d6b77c9ae01 2011 #define LCD_WF8B_BPBLCD52_MASK 0x2u
mturner5 0:0d6b77c9ae01 2012 #define LCD_WF8B_BPBLCD52_SHIFT 1
mturner5 0:0d6b77c9ae01 2013 #define LCD_WF8B_BPBLCD4_MASK 0x2u
mturner5 0:0d6b77c9ae01 2014 #define LCD_WF8B_BPBLCD4_SHIFT 1
mturner5 0:0d6b77c9ae01 2015 #define LCD_WF8B_BPBLCD35_MASK 0x2u
mturner5 0:0d6b77c9ae01 2016 #define LCD_WF8B_BPBLCD35_SHIFT 1
mturner5 0:0d6b77c9ae01 2017 #define LCD_WF8B_BPBLCD17_MASK 0x2u
mturner5 0:0d6b77c9ae01 2018 #define LCD_WF8B_BPBLCD17_SHIFT 1
mturner5 0:0d6b77c9ae01 2019 #define LCD_WF8B_BPBLCD41_MASK 0x2u
mturner5 0:0d6b77c9ae01 2020 #define LCD_WF8B_BPBLCD41_SHIFT 1
mturner5 0:0d6b77c9ae01 2021 #define LCD_WF8B_BPBLCD11_MASK 0x2u
mturner5 0:0d6b77c9ae01 2022 #define LCD_WF8B_BPBLCD11_SHIFT 1
mturner5 0:0d6b77c9ae01 2023 #define LCD_WF8B_BPBLCD46_MASK 0x2u
mturner5 0:0d6b77c9ae01 2024 #define LCD_WF8B_BPBLCD46_SHIFT 1
mturner5 0:0d6b77c9ae01 2025 #define LCD_WF8B_BPBLCD57_MASK 0x2u
mturner5 0:0d6b77c9ae01 2026 #define LCD_WF8B_BPBLCD57_SHIFT 1
mturner5 0:0d6b77c9ae01 2027 #define LCD_WF8B_BPBLCD42_MASK 0x2u
mturner5 0:0d6b77c9ae01 2028 #define LCD_WF8B_BPBLCD42_SHIFT 1
mturner5 0:0d6b77c9ae01 2029 #define LCD_WF8B_BPBLCD5_MASK 0x2u
mturner5 0:0d6b77c9ae01 2030 #define LCD_WF8B_BPBLCD5_SHIFT 1
mturner5 0:0d6b77c9ae01 2031 #define LCD_WF8B_BPBLCD3_MASK 0x2u
mturner5 0:0d6b77c9ae01 2032 #define LCD_WF8B_BPBLCD3_SHIFT 1
mturner5 0:0d6b77c9ae01 2033 #define LCD_WF8B_BPBLCD16_MASK 0x2u
mturner5 0:0d6b77c9ae01 2034 #define LCD_WF8B_BPBLCD16_SHIFT 1
mturner5 0:0d6b77c9ae01 2035 #define LCD_WF8B_BPBLCD13_MASK 0x2u
mturner5 0:0d6b77c9ae01 2036 #define LCD_WF8B_BPBLCD13_SHIFT 1
mturner5 0:0d6b77c9ae01 2037 #define LCD_WF8B_BPCLCD10_MASK 0x4u
mturner5 0:0d6b77c9ae01 2038 #define LCD_WF8B_BPCLCD10_SHIFT 2
mturner5 0:0d6b77c9ae01 2039 #define LCD_WF8B_BPCLCD55_MASK 0x4u
mturner5 0:0d6b77c9ae01 2040 #define LCD_WF8B_BPCLCD55_SHIFT 2
mturner5 0:0d6b77c9ae01 2041 #define LCD_WF8B_BPCLCD2_MASK 0x4u
mturner5 0:0d6b77c9ae01 2042 #define LCD_WF8B_BPCLCD2_SHIFT 2
mturner5 0:0d6b77c9ae01 2043 #define LCD_WF8B_BPCLCD23_MASK 0x4u
mturner5 0:0d6b77c9ae01 2044 #define LCD_WF8B_BPCLCD23_SHIFT 2
mturner5 0:0d6b77c9ae01 2045 #define LCD_WF8B_BPCLCD48_MASK 0x4u
mturner5 0:0d6b77c9ae01 2046 #define LCD_WF8B_BPCLCD48_SHIFT 2
mturner5 0:0d6b77c9ae01 2047 #define LCD_WF8B_BPCLCD24_MASK 0x4u
mturner5 0:0d6b77c9ae01 2048 #define LCD_WF8B_BPCLCD24_SHIFT 2
mturner5 0:0d6b77c9ae01 2049 #define LCD_WF8B_BPCLCD60_MASK 0x4u
mturner5 0:0d6b77c9ae01 2050 #define LCD_WF8B_BPCLCD60_SHIFT 2
mturner5 0:0d6b77c9ae01 2051 #define LCD_WF8B_BPCLCD47_MASK 0x4u
mturner5 0:0d6b77c9ae01 2052 #define LCD_WF8B_BPCLCD47_SHIFT 2
mturner5 0:0d6b77c9ae01 2053 #define LCD_WF8B_BPCLCD22_MASK 0x4u
mturner5 0:0d6b77c9ae01 2054 #define LCD_WF8B_BPCLCD22_SHIFT 2
mturner5 0:0d6b77c9ae01 2055 #define LCD_WF8B_BPCLCD8_MASK 0x4u
mturner5 0:0d6b77c9ae01 2056 #define LCD_WF8B_BPCLCD8_SHIFT 2
mturner5 0:0d6b77c9ae01 2057 #define LCD_WF8B_BPCLCD21_MASK 0x4u
mturner5 0:0d6b77c9ae01 2058 #define LCD_WF8B_BPCLCD21_SHIFT 2
mturner5 0:0d6b77c9ae01 2059 #define LCD_WF8B_BPCLCD49_MASK 0x4u
mturner5 0:0d6b77c9ae01 2060 #define LCD_WF8B_BPCLCD49_SHIFT 2
mturner5 0:0d6b77c9ae01 2061 #define LCD_WF8B_BPCLCD25_MASK 0x4u
mturner5 0:0d6b77c9ae01 2062 #define LCD_WF8B_BPCLCD25_SHIFT 2
mturner5 0:0d6b77c9ae01 2063 #define LCD_WF8B_BPCLCD1_MASK 0x4u
mturner5 0:0d6b77c9ae01 2064 #define LCD_WF8B_BPCLCD1_SHIFT 2
mturner5 0:0d6b77c9ae01 2065 #define LCD_WF8B_BPCLCD20_MASK 0x4u
mturner5 0:0d6b77c9ae01 2066 #define LCD_WF8B_BPCLCD20_SHIFT 2
mturner5 0:0d6b77c9ae01 2067 #define LCD_WF8B_BPCLCD50_MASK 0x4u
mturner5 0:0d6b77c9ae01 2068 #define LCD_WF8B_BPCLCD50_SHIFT 2
mturner5 0:0d6b77c9ae01 2069 #define LCD_WF8B_BPCLCD19_MASK 0x4u
mturner5 0:0d6b77c9ae01 2070 #define LCD_WF8B_BPCLCD19_SHIFT 2
mturner5 0:0d6b77c9ae01 2071 #define LCD_WF8B_BPCLCD26_MASK 0x4u
mturner5 0:0d6b77c9ae01 2072 #define LCD_WF8B_BPCLCD26_SHIFT 2
mturner5 0:0d6b77c9ae01 2073 #define LCD_WF8B_BPCLCD59_MASK 0x4u
mturner5 0:0d6b77c9ae01 2074 #define LCD_WF8B_BPCLCD59_SHIFT 2
mturner5 0:0d6b77c9ae01 2075 #define LCD_WF8B_BPCLCD61_MASK 0x4u
mturner5 0:0d6b77c9ae01 2076 #define LCD_WF8B_BPCLCD61_SHIFT 2
mturner5 0:0d6b77c9ae01 2077 #define LCD_WF8B_BPCLCD46_MASK 0x4u
mturner5 0:0d6b77c9ae01 2078 #define LCD_WF8B_BPCLCD46_SHIFT 2
mturner5 0:0d6b77c9ae01 2079 #define LCD_WF8B_BPCLCD18_MASK 0x4u
mturner5 0:0d6b77c9ae01 2080 #define LCD_WF8B_BPCLCD18_SHIFT 2
mturner5 0:0d6b77c9ae01 2081 #define LCD_WF8B_BPCLCD5_MASK 0x4u
mturner5 0:0d6b77c9ae01 2082 #define LCD_WF8B_BPCLCD5_SHIFT 2
mturner5 0:0d6b77c9ae01 2083 #define LCD_WF8B_BPCLCD63_MASK 0x4u
mturner5 0:0d6b77c9ae01 2084 #define LCD_WF8B_BPCLCD63_SHIFT 2
mturner5 0:0d6b77c9ae01 2085 #define LCD_WF8B_BPCLCD27_MASK 0x4u
mturner5 0:0d6b77c9ae01 2086 #define LCD_WF8B_BPCLCD27_SHIFT 2
mturner5 0:0d6b77c9ae01 2087 #define LCD_WF8B_BPCLCD17_MASK 0x4u
mturner5 0:0d6b77c9ae01 2088 #define LCD_WF8B_BPCLCD17_SHIFT 2
mturner5 0:0d6b77c9ae01 2089 #define LCD_WF8B_BPCLCD51_MASK 0x4u
mturner5 0:0d6b77c9ae01 2090 #define LCD_WF8B_BPCLCD51_SHIFT 2
mturner5 0:0d6b77c9ae01 2091 #define LCD_WF8B_BPCLCD9_MASK 0x4u
mturner5 0:0d6b77c9ae01 2092 #define LCD_WF8B_BPCLCD9_SHIFT 2
mturner5 0:0d6b77c9ae01 2093 #define LCD_WF8B_BPCLCD54_MASK 0x4u
mturner5 0:0d6b77c9ae01 2094 #define LCD_WF8B_BPCLCD54_SHIFT 2
mturner5 0:0d6b77c9ae01 2095 #define LCD_WF8B_BPCLCD15_MASK 0x4u
mturner5 0:0d6b77c9ae01 2096 #define LCD_WF8B_BPCLCD15_SHIFT 2
mturner5 0:0d6b77c9ae01 2097 #define LCD_WF8B_BPCLCD16_MASK 0x4u
mturner5 0:0d6b77c9ae01 2098 #define LCD_WF8B_BPCLCD16_SHIFT 2
mturner5 0:0d6b77c9ae01 2099 #define LCD_WF8B_BPCLCD14_MASK 0x4u
mturner5 0:0d6b77c9ae01 2100 #define LCD_WF8B_BPCLCD14_SHIFT 2
mturner5 0:0d6b77c9ae01 2101 #define LCD_WF8B_BPCLCD32_MASK 0x4u
mturner5 0:0d6b77c9ae01 2102 #define LCD_WF8B_BPCLCD32_SHIFT 2
mturner5 0:0d6b77c9ae01 2103 #define LCD_WF8B_BPCLCD28_MASK 0x4u
mturner5 0:0d6b77c9ae01 2104 #define LCD_WF8B_BPCLCD28_SHIFT 2
mturner5 0:0d6b77c9ae01 2105 #define LCD_WF8B_BPCLCD53_MASK 0x4u
mturner5 0:0d6b77c9ae01 2106 #define LCD_WF8B_BPCLCD53_SHIFT 2
mturner5 0:0d6b77c9ae01 2107 #define LCD_WF8B_BPCLCD33_MASK 0x4u
mturner5 0:0d6b77c9ae01 2108 #define LCD_WF8B_BPCLCD33_SHIFT 2
mturner5 0:0d6b77c9ae01 2109 #define LCD_WF8B_BPCLCD0_MASK 0x4u
mturner5 0:0d6b77c9ae01 2110 #define LCD_WF8B_BPCLCD0_SHIFT 2
mturner5 0:0d6b77c9ae01 2111 #define LCD_WF8B_BPCLCD43_MASK 0x4u
mturner5 0:0d6b77c9ae01 2112 #define LCD_WF8B_BPCLCD43_SHIFT 2
mturner5 0:0d6b77c9ae01 2113 #define LCD_WF8B_BPCLCD7_MASK 0x4u
mturner5 0:0d6b77c9ae01 2114 #define LCD_WF8B_BPCLCD7_SHIFT 2
mturner5 0:0d6b77c9ae01 2115 #define LCD_WF8B_BPCLCD4_MASK 0x4u
mturner5 0:0d6b77c9ae01 2116 #define LCD_WF8B_BPCLCD4_SHIFT 2
mturner5 0:0d6b77c9ae01 2117 #define LCD_WF8B_BPCLCD34_MASK 0x4u
mturner5 0:0d6b77c9ae01 2118 #define LCD_WF8B_BPCLCD34_SHIFT 2
mturner5 0:0d6b77c9ae01 2119 #define LCD_WF8B_BPCLCD29_MASK 0x4u
mturner5 0:0d6b77c9ae01 2120 #define LCD_WF8B_BPCLCD29_SHIFT 2
mturner5 0:0d6b77c9ae01 2121 #define LCD_WF8B_BPCLCD45_MASK 0x4u
mturner5 0:0d6b77c9ae01 2122 #define LCD_WF8B_BPCLCD45_SHIFT 2
mturner5 0:0d6b77c9ae01 2123 #define LCD_WF8B_BPCLCD57_MASK 0x4u
mturner5 0:0d6b77c9ae01 2124 #define LCD_WF8B_BPCLCD57_SHIFT 2
mturner5 0:0d6b77c9ae01 2125 #define LCD_WF8B_BPCLCD42_MASK 0x4u
mturner5 0:0d6b77c9ae01 2126 #define LCD_WF8B_BPCLCD42_SHIFT 2
mturner5 0:0d6b77c9ae01 2127 #define LCD_WF8B_BPCLCD35_MASK 0x4u
mturner5 0:0d6b77c9ae01 2128 #define LCD_WF8B_BPCLCD35_SHIFT 2
mturner5 0:0d6b77c9ae01 2129 #define LCD_WF8B_BPCLCD13_MASK 0x4u
mturner5 0:0d6b77c9ae01 2130 #define LCD_WF8B_BPCLCD13_SHIFT 2
mturner5 0:0d6b77c9ae01 2131 #define LCD_WF8B_BPCLCD36_MASK 0x4u
mturner5 0:0d6b77c9ae01 2132 #define LCD_WF8B_BPCLCD36_SHIFT 2
mturner5 0:0d6b77c9ae01 2133 #define LCD_WF8B_BPCLCD30_MASK 0x4u
mturner5 0:0d6b77c9ae01 2134 #define LCD_WF8B_BPCLCD30_SHIFT 2
mturner5 0:0d6b77c9ae01 2135 #define LCD_WF8B_BPCLCD52_MASK 0x4u
mturner5 0:0d6b77c9ae01 2136 #define LCD_WF8B_BPCLCD52_SHIFT 2
mturner5 0:0d6b77c9ae01 2137 #define LCD_WF8B_BPCLCD58_MASK 0x4u
mturner5 0:0d6b77c9ae01 2138 #define LCD_WF8B_BPCLCD58_SHIFT 2
mturner5 0:0d6b77c9ae01 2139 #define LCD_WF8B_BPCLCD41_MASK 0x4u
mturner5 0:0d6b77c9ae01 2140 #define LCD_WF8B_BPCLCD41_SHIFT 2
mturner5 0:0d6b77c9ae01 2141 #define LCD_WF8B_BPCLCD37_MASK 0x4u
mturner5 0:0d6b77c9ae01 2142 #define LCD_WF8B_BPCLCD37_SHIFT 2
mturner5 0:0d6b77c9ae01 2143 #define LCD_WF8B_BPCLCD3_MASK 0x4u
mturner5 0:0d6b77c9ae01 2144 #define LCD_WF8B_BPCLCD3_SHIFT 2
mturner5 0:0d6b77c9ae01 2145 #define LCD_WF8B_BPCLCD12_MASK 0x4u
mturner5 0:0d6b77c9ae01 2146 #define LCD_WF8B_BPCLCD12_SHIFT 2
mturner5 0:0d6b77c9ae01 2147 #define LCD_WF8B_BPCLCD11_MASK 0x4u
mturner5 0:0d6b77c9ae01 2148 #define LCD_WF8B_BPCLCD11_SHIFT 2
mturner5 0:0d6b77c9ae01 2149 #define LCD_WF8B_BPCLCD38_MASK 0x4u
mturner5 0:0d6b77c9ae01 2150 #define LCD_WF8B_BPCLCD38_SHIFT 2
mturner5 0:0d6b77c9ae01 2151 #define LCD_WF8B_BPCLCD44_MASK 0x4u
mturner5 0:0d6b77c9ae01 2152 #define LCD_WF8B_BPCLCD44_SHIFT 2
mturner5 0:0d6b77c9ae01 2153 #define LCD_WF8B_BPCLCD31_MASK 0x4u
mturner5 0:0d6b77c9ae01 2154 #define LCD_WF8B_BPCLCD31_SHIFT 2
mturner5 0:0d6b77c9ae01 2155 #define LCD_WF8B_BPCLCD40_MASK 0x4u
mturner5 0:0d6b77c9ae01 2156 #define LCD_WF8B_BPCLCD40_SHIFT 2
mturner5 0:0d6b77c9ae01 2157 #define LCD_WF8B_BPCLCD62_MASK 0x4u
mturner5 0:0d6b77c9ae01 2158 #define LCD_WF8B_BPCLCD62_SHIFT 2
mturner5 0:0d6b77c9ae01 2159 #define LCD_WF8B_BPCLCD56_MASK 0x4u
mturner5 0:0d6b77c9ae01 2160 #define LCD_WF8B_BPCLCD56_SHIFT 2
mturner5 0:0d6b77c9ae01 2161 #define LCD_WF8B_BPCLCD39_MASK 0x4u
mturner5 0:0d6b77c9ae01 2162 #define LCD_WF8B_BPCLCD39_SHIFT 2
mturner5 0:0d6b77c9ae01 2163 #define LCD_WF8B_BPCLCD6_MASK 0x4u
mturner5 0:0d6b77c9ae01 2164 #define LCD_WF8B_BPCLCD6_SHIFT 2
mturner5 0:0d6b77c9ae01 2165 #define LCD_WF8B_BPDLCD47_MASK 0x8u
mturner5 0:0d6b77c9ae01 2166 #define LCD_WF8B_BPDLCD47_SHIFT 3
mturner5 0:0d6b77c9ae01 2167 #define LCD_WF8B_BPDLCD23_MASK 0x8u
mturner5 0:0d6b77c9ae01 2168 #define LCD_WF8B_BPDLCD23_SHIFT 3
mturner5 0:0d6b77c9ae01 2169 #define LCD_WF8B_BPDLCD48_MASK 0x8u
mturner5 0:0d6b77c9ae01 2170 #define LCD_WF8B_BPDLCD48_SHIFT 3
mturner5 0:0d6b77c9ae01 2171 #define LCD_WF8B_BPDLCD24_MASK 0x8u
mturner5 0:0d6b77c9ae01 2172 #define LCD_WF8B_BPDLCD24_SHIFT 3
mturner5 0:0d6b77c9ae01 2173 #define LCD_WF8B_BPDLCD15_MASK 0x8u
mturner5 0:0d6b77c9ae01 2174 #define LCD_WF8B_BPDLCD15_SHIFT 3
mturner5 0:0d6b77c9ae01 2175 #define LCD_WF8B_BPDLCD22_MASK 0x8u
mturner5 0:0d6b77c9ae01 2176 #define LCD_WF8B_BPDLCD22_SHIFT 3
mturner5 0:0d6b77c9ae01 2177 #define LCD_WF8B_BPDLCD60_MASK 0x8u
mturner5 0:0d6b77c9ae01 2178 #define LCD_WF8B_BPDLCD60_SHIFT 3
mturner5 0:0d6b77c9ae01 2179 #define LCD_WF8B_BPDLCD10_MASK 0x8u
mturner5 0:0d6b77c9ae01 2180 #define LCD_WF8B_BPDLCD10_SHIFT 3
mturner5 0:0d6b77c9ae01 2181 #define LCD_WF8B_BPDLCD21_MASK 0x8u
mturner5 0:0d6b77c9ae01 2182 #define LCD_WF8B_BPDLCD21_SHIFT 3
mturner5 0:0d6b77c9ae01 2183 #define LCD_WF8B_BPDLCD49_MASK 0x8u
mturner5 0:0d6b77c9ae01 2184 #define LCD_WF8B_BPDLCD49_SHIFT 3
mturner5 0:0d6b77c9ae01 2185 #define LCD_WF8B_BPDLCD1_MASK 0x8u
mturner5 0:0d6b77c9ae01 2186 #define LCD_WF8B_BPDLCD1_SHIFT 3
mturner5 0:0d6b77c9ae01 2187 #define LCD_WF8B_BPDLCD25_MASK 0x8u
mturner5 0:0d6b77c9ae01 2188 #define LCD_WF8B_BPDLCD25_SHIFT 3
mturner5 0:0d6b77c9ae01 2189 #define LCD_WF8B_BPDLCD20_MASK 0x8u
mturner5 0:0d6b77c9ae01 2190 #define LCD_WF8B_BPDLCD20_SHIFT 3
mturner5 0:0d6b77c9ae01 2191 #define LCD_WF8B_BPDLCD2_MASK 0x8u
mturner5 0:0d6b77c9ae01 2192 #define LCD_WF8B_BPDLCD2_SHIFT 3
mturner5 0:0d6b77c9ae01 2193 #define LCD_WF8B_BPDLCD55_MASK 0x8u
mturner5 0:0d6b77c9ae01 2194 #define LCD_WF8B_BPDLCD55_SHIFT 3
mturner5 0:0d6b77c9ae01 2195 #define LCD_WF8B_BPDLCD59_MASK 0x8u
mturner5 0:0d6b77c9ae01 2196 #define LCD_WF8B_BPDLCD59_SHIFT 3
mturner5 0:0d6b77c9ae01 2197 #define LCD_WF8B_BPDLCD5_MASK 0x8u
mturner5 0:0d6b77c9ae01 2198 #define LCD_WF8B_BPDLCD5_SHIFT 3
mturner5 0:0d6b77c9ae01 2199 #define LCD_WF8B_BPDLCD19_MASK 0x8u
mturner5 0:0d6b77c9ae01 2200 #define LCD_WF8B_BPDLCD19_SHIFT 3
mturner5 0:0d6b77c9ae01 2201 #define LCD_WF8B_BPDLCD6_MASK 0x8u
mturner5 0:0d6b77c9ae01 2202 #define LCD_WF8B_BPDLCD6_SHIFT 3
mturner5 0:0d6b77c9ae01 2203 #define LCD_WF8B_BPDLCD26_MASK 0x8u
mturner5 0:0d6b77c9ae01 2204 #define LCD_WF8B_BPDLCD26_SHIFT 3
mturner5 0:0d6b77c9ae01 2205 #define LCD_WF8B_BPDLCD0_MASK 0x8u
mturner5 0:0d6b77c9ae01 2206 #define LCD_WF8B_BPDLCD0_SHIFT 3
mturner5 0:0d6b77c9ae01 2207 #define LCD_WF8B_BPDLCD50_MASK 0x8u
mturner5 0:0d6b77c9ae01 2208 #define LCD_WF8B_BPDLCD50_SHIFT 3
mturner5 0:0d6b77c9ae01 2209 #define LCD_WF8B_BPDLCD46_MASK 0x8u
mturner5 0:0d6b77c9ae01 2210 #define LCD_WF8B_BPDLCD46_SHIFT 3
mturner5 0:0d6b77c9ae01 2211 #define LCD_WF8B_BPDLCD18_MASK 0x8u
mturner5 0:0d6b77c9ae01 2212 #define LCD_WF8B_BPDLCD18_SHIFT 3
mturner5 0:0d6b77c9ae01 2213 #define LCD_WF8B_BPDLCD61_MASK 0x8u
mturner5 0:0d6b77c9ae01 2214 #define LCD_WF8B_BPDLCD61_SHIFT 3
mturner5 0:0d6b77c9ae01 2215 #define LCD_WF8B_BPDLCD9_MASK 0x8u
mturner5 0:0d6b77c9ae01 2216 #define LCD_WF8B_BPDLCD9_SHIFT 3
mturner5 0:0d6b77c9ae01 2217 #define LCD_WF8B_BPDLCD17_MASK 0x8u
mturner5 0:0d6b77c9ae01 2218 #define LCD_WF8B_BPDLCD17_SHIFT 3
mturner5 0:0d6b77c9ae01 2219 #define LCD_WF8B_BPDLCD27_MASK 0x8u
mturner5 0:0d6b77c9ae01 2220 #define LCD_WF8B_BPDLCD27_SHIFT 3
mturner5 0:0d6b77c9ae01 2221 #define LCD_WF8B_BPDLCD53_MASK 0x8u
mturner5 0:0d6b77c9ae01 2222 #define LCD_WF8B_BPDLCD53_SHIFT 3
mturner5 0:0d6b77c9ae01 2223 #define LCD_WF8B_BPDLCD51_MASK 0x8u
mturner5 0:0d6b77c9ae01 2224 #define LCD_WF8B_BPDLCD51_SHIFT 3
mturner5 0:0d6b77c9ae01 2225 #define LCD_WF8B_BPDLCD54_MASK 0x8u
mturner5 0:0d6b77c9ae01 2226 #define LCD_WF8B_BPDLCD54_SHIFT 3
mturner5 0:0d6b77c9ae01 2227 #define LCD_WF8B_BPDLCD13_MASK 0x8u
mturner5 0:0d6b77c9ae01 2228 #define LCD_WF8B_BPDLCD13_SHIFT 3
mturner5 0:0d6b77c9ae01 2229 #define LCD_WF8B_BPDLCD16_MASK 0x8u
mturner5 0:0d6b77c9ae01 2230 #define LCD_WF8B_BPDLCD16_SHIFT 3
mturner5 0:0d6b77c9ae01 2231 #define LCD_WF8B_BPDLCD32_MASK 0x8u
mturner5 0:0d6b77c9ae01 2232 #define LCD_WF8B_BPDLCD32_SHIFT 3
mturner5 0:0d6b77c9ae01 2233 #define LCD_WF8B_BPDLCD14_MASK 0x8u
mturner5 0:0d6b77c9ae01 2234 #define LCD_WF8B_BPDLCD14_SHIFT 3
mturner5 0:0d6b77c9ae01 2235 #define LCD_WF8B_BPDLCD28_MASK 0x8u
mturner5 0:0d6b77c9ae01 2236 #define LCD_WF8B_BPDLCD28_SHIFT 3
mturner5 0:0d6b77c9ae01 2237 #define LCD_WF8B_BPDLCD43_MASK 0x8u
mturner5 0:0d6b77c9ae01 2238 #define LCD_WF8B_BPDLCD43_SHIFT 3
mturner5 0:0d6b77c9ae01 2239 #define LCD_WF8B_BPDLCD4_MASK 0x8u
mturner5 0:0d6b77c9ae01 2240 #define LCD_WF8B_BPDLCD4_SHIFT 3
mturner5 0:0d6b77c9ae01 2241 #define LCD_WF8B_BPDLCD45_MASK 0x8u
mturner5 0:0d6b77c9ae01 2242 #define LCD_WF8B_BPDLCD45_SHIFT 3
mturner5 0:0d6b77c9ae01 2243 #define LCD_WF8B_BPDLCD8_MASK 0x8u
mturner5 0:0d6b77c9ae01 2244 #define LCD_WF8B_BPDLCD8_SHIFT 3
mturner5 0:0d6b77c9ae01 2245 #define LCD_WF8B_BPDLCD62_MASK 0x8u
mturner5 0:0d6b77c9ae01 2246 #define LCD_WF8B_BPDLCD62_SHIFT 3
mturner5 0:0d6b77c9ae01 2247 #define LCD_WF8B_BPDLCD33_MASK 0x8u
mturner5 0:0d6b77c9ae01 2248 #define LCD_WF8B_BPDLCD33_SHIFT 3
mturner5 0:0d6b77c9ae01 2249 #define LCD_WF8B_BPDLCD34_MASK 0x8u
mturner5 0:0d6b77c9ae01 2250 #define LCD_WF8B_BPDLCD34_SHIFT 3
mturner5 0:0d6b77c9ae01 2251 #define LCD_WF8B_BPDLCD29_MASK 0x8u
mturner5 0:0d6b77c9ae01 2252 #define LCD_WF8B_BPDLCD29_SHIFT 3
mturner5 0:0d6b77c9ae01 2253 #define LCD_WF8B_BPDLCD58_MASK 0x8u
mturner5 0:0d6b77c9ae01 2254 #define LCD_WF8B_BPDLCD58_SHIFT 3
mturner5 0:0d6b77c9ae01 2255 #define LCD_WF8B_BPDLCD57_MASK 0x8u
mturner5 0:0d6b77c9ae01 2256 #define LCD_WF8B_BPDLCD57_SHIFT 3
mturner5 0:0d6b77c9ae01 2257 #define LCD_WF8B_BPDLCD42_MASK 0x8u
mturner5 0:0d6b77c9ae01 2258 #define LCD_WF8B_BPDLCD42_SHIFT 3
mturner5 0:0d6b77c9ae01 2259 #define LCD_WF8B_BPDLCD35_MASK 0x8u
mturner5 0:0d6b77c9ae01 2260 #define LCD_WF8B_BPDLCD35_SHIFT 3
mturner5 0:0d6b77c9ae01 2261 #define LCD_WF8B_BPDLCD52_MASK 0x8u
mturner5 0:0d6b77c9ae01 2262 #define LCD_WF8B_BPDLCD52_SHIFT 3
mturner5 0:0d6b77c9ae01 2263 #define LCD_WF8B_BPDLCD7_MASK 0x8u
mturner5 0:0d6b77c9ae01 2264 #define LCD_WF8B_BPDLCD7_SHIFT 3
mturner5 0:0d6b77c9ae01 2265 #define LCD_WF8B_BPDLCD36_MASK 0x8u
mturner5 0:0d6b77c9ae01 2266 #define LCD_WF8B_BPDLCD36_SHIFT 3
mturner5 0:0d6b77c9ae01 2267 #define LCD_WF8B_BPDLCD30_MASK 0x8u
mturner5 0:0d6b77c9ae01 2268 #define LCD_WF8B_BPDLCD30_SHIFT 3
mturner5 0:0d6b77c9ae01 2269 #define LCD_WF8B_BPDLCD41_MASK 0x8u
mturner5 0:0d6b77c9ae01 2270 #define LCD_WF8B_BPDLCD41_SHIFT 3
mturner5 0:0d6b77c9ae01 2271 #define LCD_WF8B_BPDLCD37_MASK 0x8u
mturner5 0:0d6b77c9ae01 2272 #define LCD_WF8B_BPDLCD37_SHIFT 3
mturner5 0:0d6b77c9ae01 2273 #define LCD_WF8B_BPDLCD44_MASK 0x8u
mturner5 0:0d6b77c9ae01 2274 #define LCD_WF8B_BPDLCD44_SHIFT 3
mturner5 0:0d6b77c9ae01 2275 #define LCD_WF8B_BPDLCD63_MASK 0x8u
mturner5 0:0d6b77c9ae01 2276 #define LCD_WF8B_BPDLCD63_SHIFT 3
mturner5 0:0d6b77c9ae01 2277 #define LCD_WF8B_BPDLCD38_MASK 0x8u
mturner5 0:0d6b77c9ae01 2278 #define LCD_WF8B_BPDLCD38_SHIFT 3
mturner5 0:0d6b77c9ae01 2279 #define LCD_WF8B_BPDLCD56_MASK 0x8u
mturner5 0:0d6b77c9ae01 2280 #define LCD_WF8B_BPDLCD56_SHIFT 3
mturner5 0:0d6b77c9ae01 2281 #define LCD_WF8B_BPDLCD40_MASK 0x8u
mturner5 0:0d6b77c9ae01 2282 #define LCD_WF8B_BPDLCD40_SHIFT 3
mturner5 0:0d6b77c9ae01 2283 #define LCD_WF8B_BPDLCD31_MASK 0x8u
mturner5 0:0d6b77c9ae01 2284 #define LCD_WF8B_BPDLCD31_SHIFT 3
mturner5 0:0d6b77c9ae01 2285 #define LCD_WF8B_BPDLCD12_MASK 0x8u
mturner5 0:0d6b77c9ae01 2286 #define LCD_WF8B_BPDLCD12_SHIFT 3
mturner5 0:0d6b77c9ae01 2287 #define LCD_WF8B_BPDLCD39_MASK 0x8u
mturner5 0:0d6b77c9ae01 2288 #define LCD_WF8B_BPDLCD39_SHIFT 3
mturner5 0:0d6b77c9ae01 2289 #define LCD_WF8B_BPDLCD3_MASK 0x8u
mturner5 0:0d6b77c9ae01 2290 #define LCD_WF8B_BPDLCD3_SHIFT 3
mturner5 0:0d6b77c9ae01 2291 #define LCD_WF8B_BPDLCD11_MASK 0x8u
mturner5 0:0d6b77c9ae01 2292 #define LCD_WF8B_BPDLCD11_SHIFT 3
mturner5 0:0d6b77c9ae01 2293 #define LCD_WF8B_BPELCD12_MASK 0x10u
mturner5 0:0d6b77c9ae01 2294 #define LCD_WF8B_BPELCD12_SHIFT 4
mturner5 0:0d6b77c9ae01 2295 #define LCD_WF8B_BPELCD39_MASK 0x10u
mturner5 0:0d6b77c9ae01 2296 #define LCD_WF8B_BPELCD39_SHIFT 4
mturner5 0:0d6b77c9ae01 2297 #define LCD_WF8B_BPELCD3_MASK 0x10u
mturner5 0:0d6b77c9ae01 2298 #define LCD_WF8B_BPELCD3_SHIFT 4
mturner5 0:0d6b77c9ae01 2299 #define LCD_WF8B_BPELCD38_MASK 0x10u
mturner5 0:0d6b77c9ae01 2300 #define LCD_WF8B_BPELCD38_SHIFT 4
mturner5 0:0d6b77c9ae01 2301 #define LCD_WF8B_BPELCD40_MASK 0x10u
mturner5 0:0d6b77c9ae01 2302 #define LCD_WF8B_BPELCD40_SHIFT 4
mturner5 0:0d6b77c9ae01 2303 #define LCD_WF8B_BPELCD37_MASK 0x10u
mturner5 0:0d6b77c9ae01 2304 #define LCD_WF8B_BPELCD37_SHIFT 4
mturner5 0:0d6b77c9ae01 2305 #define LCD_WF8B_BPELCD41_MASK 0x10u
mturner5 0:0d6b77c9ae01 2306 #define LCD_WF8B_BPELCD41_SHIFT 4
mturner5 0:0d6b77c9ae01 2307 #define LCD_WF8B_BPELCD36_MASK 0x10u
mturner5 0:0d6b77c9ae01 2308 #define LCD_WF8B_BPELCD36_SHIFT 4
mturner5 0:0d6b77c9ae01 2309 #define LCD_WF8B_BPELCD8_MASK 0x10u
mturner5 0:0d6b77c9ae01 2310 #define LCD_WF8B_BPELCD8_SHIFT 4
mturner5 0:0d6b77c9ae01 2311 #define LCD_WF8B_BPELCD35_MASK 0x10u
mturner5 0:0d6b77c9ae01 2312 #define LCD_WF8B_BPELCD35_SHIFT 4
mturner5 0:0d6b77c9ae01 2313 #define LCD_WF8B_BPELCD42_MASK 0x10u
mturner5 0:0d6b77c9ae01 2314 #define LCD_WF8B_BPELCD42_SHIFT 4
mturner5 0:0d6b77c9ae01 2315 #define LCD_WF8B_BPELCD34_MASK 0x10u
mturner5 0:0d6b77c9ae01 2316 #define LCD_WF8B_BPELCD34_SHIFT 4
mturner5 0:0d6b77c9ae01 2317 #define LCD_WF8B_BPELCD33_MASK 0x10u
mturner5 0:0d6b77c9ae01 2318 #define LCD_WF8B_BPELCD33_SHIFT 4
mturner5 0:0d6b77c9ae01 2319 #define LCD_WF8B_BPELCD11_MASK 0x10u
mturner5 0:0d6b77c9ae01 2320 #define LCD_WF8B_BPELCD11_SHIFT 4
mturner5 0:0d6b77c9ae01 2321 #define LCD_WF8B_BPELCD43_MASK 0x10u
mturner5 0:0d6b77c9ae01 2322 #define LCD_WF8B_BPELCD43_SHIFT 4
mturner5 0:0d6b77c9ae01 2323 #define LCD_WF8B_BPELCD32_MASK 0x10u
mturner5 0:0d6b77c9ae01 2324 #define LCD_WF8B_BPELCD32_SHIFT 4
mturner5 0:0d6b77c9ae01 2325 #define LCD_WF8B_BPELCD31_MASK 0x10u
mturner5 0:0d6b77c9ae01 2326 #define LCD_WF8B_BPELCD31_SHIFT 4
mturner5 0:0d6b77c9ae01 2327 #define LCD_WF8B_BPELCD44_MASK 0x10u
mturner5 0:0d6b77c9ae01 2328 #define LCD_WF8B_BPELCD44_SHIFT 4
mturner5 0:0d6b77c9ae01 2329 #define LCD_WF8B_BPELCD30_MASK 0x10u
mturner5 0:0d6b77c9ae01 2330 #define LCD_WF8B_BPELCD30_SHIFT 4
mturner5 0:0d6b77c9ae01 2331 #define LCD_WF8B_BPELCD29_MASK 0x10u
mturner5 0:0d6b77c9ae01 2332 #define LCD_WF8B_BPELCD29_SHIFT 4
mturner5 0:0d6b77c9ae01 2333 #define LCD_WF8B_BPELCD7_MASK 0x10u
mturner5 0:0d6b77c9ae01 2334 #define LCD_WF8B_BPELCD7_SHIFT 4
mturner5 0:0d6b77c9ae01 2335 #define LCD_WF8B_BPELCD45_MASK 0x10u
mturner5 0:0d6b77c9ae01 2336 #define LCD_WF8B_BPELCD45_SHIFT 4
mturner5 0:0d6b77c9ae01 2337 #define LCD_WF8B_BPELCD28_MASK 0x10u
mturner5 0:0d6b77c9ae01 2338 #define LCD_WF8B_BPELCD28_SHIFT 4
mturner5 0:0d6b77c9ae01 2339 #define LCD_WF8B_BPELCD2_MASK 0x10u
mturner5 0:0d6b77c9ae01 2340 #define LCD_WF8B_BPELCD2_SHIFT 4
mturner5 0:0d6b77c9ae01 2341 #define LCD_WF8B_BPELCD27_MASK 0x10u
mturner5 0:0d6b77c9ae01 2342 #define LCD_WF8B_BPELCD27_SHIFT 4
mturner5 0:0d6b77c9ae01 2343 #define LCD_WF8B_BPELCD46_MASK 0x10u
mturner5 0:0d6b77c9ae01 2344 #define LCD_WF8B_BPELCD46_SHIFT 4
mturner5 0:0d6b77c9ae01 2345 #define LCD_WF8B_BPELCD26_MASK 0x10u
mturner5 0:0d6b77c9ae01 2346 #define LCD_WF8B_BPELCD26_SHIFT 4
mturner5 0:0d6b77c9ae01 2347 #define LCD_WF8B_BPELCD10_MASK 0x10u
mturner5 0:0d6b77c9ae01 2348 #define LCD_WF8B_BPELCD10_SHIFT 4
mturner5 0:0d6b77c9ae01 2349 #define LCD_WF8B_BPELCD13_MASK 0x10u
mturner5 0:0d6b77c9ae01 2350 #define LCD_WF8B_BPELCD13_SHIFT 4
mturner5 0:0d6b77c9ae01 2351 #define LCD_WF8B_BPELCD25_MASK 0x10u
mturner5 0:0d6b77c9ae01 2352 #define LCD_WF8B_BPELCD25_SHIFT 4
mturner5 0:0d6b77c9ae01 2353 #define LCD_WF8B_BPELCD5_MASK 0x10u
mturner5 0:0d6b77c9ae01 2354 #define LCD_WF8B_BPELCD5_SHIFT 4
mturner5 0:0d6b77c9ae01 2355 #define LCD_WF8B_BPELCD24_MASK 0x10u
mturner5 0:0d6b77c9ae01 2356 #define LCD_WF8B_BPELCD24_SHIFT 4
mturner5 0:0d6b77c9ae01 2357 #define LCD_WF8B_BPELCD47_MASK 0x10u
mturner5 0:0d6b77c9ae01 2358 #define LCD_WF8B_BPELCD47_SHIFT 4
mturner5 0:0d6b77c9ae01 2359 #define LCD_WF8B_BPELCD23_MASK 0x10u
mturner5 0:0d6b77c9ae01 2360 #define LCD_WF8B_BPELCD23_SHIFT 4
mturner5 0:0d6b77c9ae01 2361 #define LCD_WF8B_BPELCD22_MASK 0x10u
mturner5 0:0d6b77c9ae01 2362 #define LCD_WF8B_BPELCD22_SHIFT 4
mturner5 0:0d6b77c9ae01 2363 #define LCD_WF8B_BPELCD48_MASK 0x10u
mturner5 0:0d6b77c9ae01 2364 #define LCD_WF8B_BPELCD48_SHIFT 4
mturner5 0:0d6b77c9ae01 2365 #define LCD_WF8B_BPELCD21_MASK 0x10u
mturner5 0:0d6b77c9ae01 2366 #define LCD_WF8B_BPELCD21_SHIFT 4
mturner5 0:0d6b77c9ae01 2367 #define LCD_WF8B_BPELCD49_MASK 0x10u
mturner5 0:0d6b77c9ae01 2368 #define LCD_WF8B_BPELCD49_SHIFT 4
mturner5 0:0d6b77c9ae01 2369 #define LCD_WF8B_BPELCD20_MASK 0x10u
mturner5 0:0d6b77c9ae01 2370 #define LCD_WF8B_BPELCD20_SHIFT 4
mturner5 0:0d6b77c9ae01 2371 #define LCD_WF8B_BPELCD19_MASK 0x10u
mturner5 0:0d6b77c9ae01 2372 #define LCD_WF8B_BPELCD19_SHIFT 4
mturner5 0:0d6b77c9ae01 2373 #define LCD_WF8B_BPELCD9_MASK 0x10u
mturner5 0:0d6b77c9ae01 2374 #define LCD_WF8B_BPELCD9_SHIFT 4
mturner5 0:0d6b77c9ae01 2375 #define LCD_WF8B_BPELCD50_MASK 0x10u
mturner5 0:0d6b77c9ae01 2376 #define LCD_WF8B_BPELCD50_SHIFT 4
mturner5 0:0d6b77c9ae01 2377 #define LCD_WF8B_BPELCD18_MASK 0x10u
mturner5 0:0d6b77c9ae01 2378 #define LCD_WF8B_BPELCD18_SHIFT 4
mturner5 0:0d6b77c9ae01 2379 #define LCD_WF8B_BPELCD6_MASK 0x10u
mturner5 0:0d6b77c9ae01 2380 #define LCD_WF8B_BPELCD6_SHIFT 4
mturner5 0:0d6b77c9ae01 2381 #define LCD_WF8B_BPELCD17_MASK 0x10u
mturner5 0:0d6b77c9ae01 2382 #define LCD_WF8B_BPELCD17_SHIFT 4
mturner5 0:0d6b77c9ae01 2383 #define LCD_WF8B_BPELCD51_MASK 0x10u
mturner5 0:0d6b77c9ae01 2384 #define LCD_WF8B_BPELCD51_SHIFT 4
mturner5 0:0d6b77c9ae01 2385 #define LCD_WF8B_BPELCD16_MASK 0x10u
mturner5 0:0d6b77c9ae01 2386 #define LCD_WF8B_BPELCD16_SHIFT 4
mturner5 0:0d6b77c9ae01 2387 #define LCD_WF8B_BPELCD56_MASK 0x10u
mturner5 0:0d6b77c9ae01 2388 #define LCD_WF8B_BPELCD56_SHIFT 4
mturner5 0:0d6b77c9ae01 2389 #define LCD_WF8B_BPELCD57_MASK 0x10u
mturner5 0:0d6b77c9ae01 2390 #define LCD_WF8B_BPELCD57_SHIFT 4
mturner5 0:0d6b77c9ae01 2391 #define LCD_WF8B_BPELCD52_MASK 0x10u
mturner5 0:0d6b77c9ae01 2392 #define LCD_WF8B_BPELCD52_SHIFT 4
mturner5 0:0d6b77c9ae01 2393 #define LCD_WF8B_BPELCD1_MASK 0x10u
mturner5 0:0d6b77c9ae01 2394 #define LCD_WF8B_BPELCD1_SHIFT 4
mturner5 0:0d6b77c9ae01 2395 #define LCD_WF8B_BPELCD58_MASK 0x10u
mturner5 0:0d6b77c9ae01 2396 #define LCD_WF8B_BPELCD58_SHIFT 4
mturner5 0:0d6b77c9ae01 2397 #define LCD_WF8B_BPELCD59_MASK 0x10u
mturner5 0:0d6b77c9ae01 2398 #define LCD_WF8B_BPELCD59_SHIFT 4
mturner5 0:0d6b77c9ae01 2399 #define LCD_WF8B_BPELCD53_MASK 0x10u
mturner5 0:0d6b77c9ae01 2400 #define LCD_WF8B_BPELCD53_SHIFT 4
mturner5 0:0d6b77c9ae01 2401 #define LCD_WF8B_BPELCD14_MASK 0x10u
mturner5 0:0d6b77c9ae01 2402 #define LCD_WF8B_BPELCD14_SHIFT 4
mturner5 0:0d6b77c9ae01 2403 #define LCD_WF8B_BPELCD0_MASK 0x10u
mturner5 0:0d6b77c9ae01 2404 #define LCD_WF8B_BPELCD0_SHIFT 4
mturner5 0:0d6b77c9ae01 2405 #define LCD_WF8B_BPELCD60_MASK 0x10u
mturner5 0:0d6b77c9ae01 2406 #define LCD_WF8B_BPELCD60_SHIFT 4
mturner5 0:0d6b77c9ae01 2407 #define LCD_WF8B_BPELCD15_MASK 0x10u
mturner5 0:0d6b77c9ae01 2408 #define LCD_WF8B_BPELCD15_SHIFT 4
mturner5 0:0d6b77c9ae01 2409 #define LCD_WF8B_BPELCD61_MASK 0x10u
mturner5 0:0d6b77c9ae01 2410 #define LCD_WF8B_BPELCD61_SHIFT 4
mturner5 0:0d6b77c9ae01 2411 #define LCD_WF8B_BPELCD54_MASK 0x10u
mturner5 0:0d6b77c9ae01 2412 #define LCD_WF8B_BPELCD54_SHIFT 4
mturner5 0:0d6b77c9ae01 2413 #define LCD_WF8B_BPELCD62_MASK 0x10u
mturner5 0:0d6b77c9ae01 2414 #define LCD_WF8B_BPELCD62_SHIFT 4
mturner5 0:0d6b77c9ae01 2415 #define LCD_WF8B_BPELCD63_MASK 0x10u
mturner5 0:0d6b77c9ae01 2416 #define LCD_WF8B_BPELCD63_SHIFT 4
mturner5 0:0d6b77c9ae01 2417 #define LCD_WF8B_BPELCD55_MASK 0x10u
mturner5 0:0d6b77c9ae01 2418 #define LCD_WF8B_BPELCD55_SHIFT 4
mturner5 0:0d6b77c9ae01 2419 #define LCD_WF8B_BPELCD4_MASK 0x10u
mturner5 0:0d6b77c9ae01 2420 #define LCD_WF8B_BPELCD4_SHIFT 4
mturner5 0:0d6b77c9ae01 2421 #define LCD_WF8B_BPFLCD13_MASK 0x20u
mturner5 0:0d6b77c9ae01 2422 #define LCD_WF8B_BPFLCD13_SHIFT 5
mturner5 0:0d6b77c9ae01 2423 #define LCD_WF8B_BPFLCD39_MASK 0x20u
mturner5 0:0d6b77c9ae01 2424 #define LCD_WF8B_BPFLCD39_SHIFT 5
mturner5 0:0d6b77c9ae01 2425 #define LCD_WF8B_BPFLCD55_MASK 0x20u
mturner5 0:0d6b77c9ae01 2426 #define LCD_WF8B_BPFLCD55_SHIFT 5
mturner5 0:0d6b77c9ae01 2427 #define LCD_WF8B_BPFLCD47_MASK 0x20u
mturner5 0:0d6b77c9ae01 2428 #define LCD_WF8B_BPFLCD47_SHIFT 5
mturner5 0:0d6b77c9ae01 2429 #define LCD_WF8B_BPFLCD63_MASK 0x20u
mturner5 0:0d6b77c9ae01 2430 #define LCD_WF8B_BPFLCD63_SHIFT 5
mturner5 0:0d6b77c9ae01 2431 #define LCD_WF8B_BPFLCD43_MASK 0x20u
mturner5 0:0d6b77c9ae01 2432 #define LCD_WF8B_BPFLCD43_SHIFT 5
mturner5 0:0d6b77c9ae01 2433 #define LCD_WF8B_BPFLCD5_MASK 0x20u
mturner5 0:0d6b77c9ae01 2434 #define LCD_WF8B_BPFLCD5_SHIFT 5
mturner5 0:0d6b77c9ae01 2435 #define LCD_WF8B_BPFLCD62_MASK 0x20u
mturner5 0:0d6b77c9ae01 2436 #define LCD_WF8B_BPFLCD62_SHIFT 5
mturner5 0:0d6b77c9ae01 2437 #define LCD_WF8B_BPFLCD14_MASK 0x20u
mturner5 0:0d6b77c9ae01 2438 #define LCD_WF8B_BPFLCD14_SHIFT 5
mturner5 0:0d6b77c9ae01 2439 #define LCD_WF8B_BPFLCD24_MASK 0x20u
mturner5 0:0d6b77c9ae01 2440 #define LCD_WF8B_BPFLCD24_SHIFT 5
mturner5 0:0d6b77c9ae01 2441 #define LCD_WF8B_BPFLCD54_MASK 0x20u
mturner5 0:0d6b77c9ae01 2442 #define LCD_WF8B_BPFLCD54_SHIFT 5
mturner5 0:0d6b77c9ae01 2443 #define LCD_WF8B_BPFLCD15_MASK 0x20u
mturner5 0:0d6b77c9ae01 2444 #define LCD_WF8B_BPFLCD15_SHIFT 5
mturner5 0:0d6b77c9ae01 2445 #define LCD_WF8B_BPFLCD32_MASK 0x20u
mturner5 0:0d6b77c9ae01 2446 #define LCD_WF8B_BPFLCD32_SHIFT 5
mturner5 0:0d6b77c9ae01 2447 #define LCD_WF8B_BPFLCD61_MASK 0x20u
mturner5 0:0d6b77c9ae01 2448 #define LCD_WF8B_BPFLCD61_SHIFT 5
mturner5 0:0d6b77c9ae01 2449 #define LCD_WF8B_BPFLCD25_MASK 0x20u
mturner5 0:0d6b77c9ae01 2450 #define LCD_WF8B_BPFLCD25_SHIFT 5
mturner5 0:0d6b77c9ae01 2451 #define LCD_WF8B_BPFLCD60_MASK 0x20u
mturner5 0:0d6b77c9ae01 2452 #define LCD_WF8B_BPFLCD60_SHIFT 5
mturner5 0:0d6b77c9ae01 2453 #define LCD_WF8B_BPFLCD41_MASK 0x20u
mturner5 0:0d6b77c9ae01 2454 #define LCD_WF8B_BPFLCD41_SHIFT 5
mturner5 0:0d6b77c9ae01 2455 #define LCD_WF8B_BPFLCD33_MASK 0x20u
mturner5 0:0d6b77c9ae01 2456 #define LCD_WF8B_BPFLCD33_SHIFT 5
mturner5 0:0d6b77c9ae01 2457 #define LCD_WF8B_BPFLCD53_MASK 0x20u
mturner5 0:0d6b77c9ae01 2458 #define LCD_WF8B_BPFLCD53_SHIFT 5
mturner5 0:0d6b77c9ae01 2459 #define LCD_WF8B_BPFLCD59_MASK 0x20u
mturner5 0:0d6b77c9ae01 2460 #define LCD_WF8B_BPFLCD59_SHIFT 5
mturner5 0:0d6b77c9ae01 2461 #define LCD_WF8B_BPFLCD0_MASK 0x20u
mturner5 0:0d6b77c9ae01 2462 #define LCD_WF8B_BPFLCD0_SHIFT 5
mturner5 0:0d6b77c9ae01 2463 #define LCD_WF8B_BPFLCD46_MASK 0x20u
mturner5 0:0d6b77c9ae01 2464 #define LCD_WF8B_BPFLCD46_SHIFT 5
mturner5 0:0d6b77c9ae01 2465 #define LCD_WF8B_BPFLCD58_MASK 0x20u
mturner5 0:0d6b77c9ae01 2466 #define LCD_WF8B_BPFLCD58_SHIFT 5
mturner5 0:0d6b77c9ae01 2467 #define LCD_WF8B_BPFLCD26_MASK 0x20u
mturner5 0:0d6b77c9ae01 2468 #define LCD_WF8B_BPFLCD26_SHIFT 5
mturner5 0:0d6b77c9ae01 2469 #define LCD_WF8B_BPFLCD36_MASK 0x20u
mturner5 0:0d6b77c9ae01 2470 #define LCD_WF8B_BPFLCD36_SHIFT 5
mturner5 0:0d6b77c9ae01 2471 #define LCD_WF8B_BPFLCD10_MASK 0x20u
mturner5 0:0d6b77c9ae01 2472 #define LCD_WF8B_BPFLCD10_SHIFT 5
mturner5 0:0d6b77c9ae01 2473 #define LCD_WF8B_BPFLCD52_MASK 0x20u
mturner5 0:0d6b77c9ae01 2474 #define LCD_WF8B_BPFLCD52_SHIFT 5
mturner5 0:0d6b77c9ae01 2475 #define LCD_WF8B_BPFLCD57_MASK 0x20u
mturner5 0:0d6b77c9ae01 2476 #define LCD_WF8B_BPFLCD57_SHIFT 5
mturner5 0:0d6b77c9ae01 2477 #define LCD_WF8B_BPFLCD27_MASK 0x20u
mturner5 0:0d6b77c9ae01 2478 #define LCD_WF8B_BPFLCD27_SHIFT 5
mturner5 0:0d6b77c9ae01 2479 #define LCD_WF8B_BPFLCD11_MASK 0x20u
mturner5 0:0d6b77c9ae01 2480 #define LCD_WF8B_BPFLCD11_SHIFT 5
mturner5 0:0d6b77c9ae01 2481 #define LCD_WF8B_BPFLCD56_MASK 0x20u
mturner5 0:0d6b77c9ae01 2482 #define LCD_WF8B_BPFLCD56_SHIFT 5
mturner5 0:0d6b77c9ae01 2483 #define LCD_WF8B_BPFLCD1_MASK 0x20u
mturner5 0:0d6b77c9ae01 2484 #define LCD_WF8B_BPFLCD1_SHIFT 5
mturner5 0:0d6b77c9ae01 2485 #define LCD_WF8B_BPFLCD8_MASK 0x20u
mturner5 0:0d6b77c9ae01 2486 #define LCD_WF8B_BPFLCD8_SHIFT 5
mturner5 0:0d6b77c9ae01 2487 #define LCD_WF8B_BPFLCD40_MASK 0x20u
mturner5 0:0d6b77c9ae01 2488 #define LCD_WF8B_BPFLCD40_SHIFT 5
mturner5 0:0d6b77c9ae01 2489 #define LCD_WF8B_BPFLCD51_MASK 0x20u
mturner5 0:0d6b77c9ae01 2490 #define LCD_WF8B_BPFLCD51_SHIFT 5
mturner5 0:0d6b77c9ae01 2491 #define LCD_WF8B_BPFLCD16_MASK 0x20u
mturner5 0:0d6b77c9ae01 2492 #define LCD_WF8B_BPFLCD16_SHIFT 5
mturner5 0:0d6b77c9ae01 2493 #define LCD_WF8B_BPFLCD45_MASK 0x20u
mturner5 0:0d6b77c9ae01 2494 #define LCD_WF8B_BPFLCD45_SHIFT 5
mturner5 0:0d6b77c9ae01 2495 #define LCD_WF8B_BPFLCD6_MASK 0x20u
mturner5 0:0d6b77c9ae01 2496 #define LCD_WF8B_BPFLCD6_SHIFT 5
mturner5 0:0d6b77c9ae01 2497 #define LCD_WF8B_BPFLCD17_MASK 0x20u
mturner5 0:0d6b77c9ae01 2498 #define LCD_WF8B_BPFLCD17_SHIFT 5
mturner5 0:0d6b77c9ae01 2499 #define LCD_WF8B_BPFLCD28_MASK 0x20u
mturner5 0:0d6b77c9ae01 2500 #define LCD_WF8B_BPFLCD28_SHIFT 5
mturner5 0:0d6b77c9ae01 2501 #define LCD_WF8B_BPFLCD42_MASK 0x20u
mturner5 0:0d6b77c9ae01 2502 #define LCD_WF8B_BPFLCD42_SHIFT 5
mturner5 0:0d6b77c9ae01 2503 #define LCD_WF8B_BPFLCD29_MASK 0x20u
mturner5 0:0d6b77c9ae01 2504 #define LCD_WF8B_BPFLCD29_SHIFT 5
mturner5 0:0d6b77c9ae01 2505 #define LCD_WF8B_BPFLCD50_MASK 0x20u
mturner5 0:0d6b77c9ae01 2506 #define LCD_WF8B_BPFLCD50_SHIFT 5
mturner5 0:0d6b77c9ae01 2507 #define LCD_WF8B_BPFLCD18_MASK 0x20u
mturner5 0:0d6b77c9ae01 2508 #define LCD_WF8B_BPFLCD18_SHIFT 5
mturner5 0:0d6b77c9ae01 2509 #define LCD_WF8B_BPFLCD34_MASK 0x20u
mturner5 0:0d6b77c9ae01 2510 #define LCD_WF8B_BPFLCD34_SHIFT 5
mturner5 0:0d6b77c9ae01 2511 #define LCD_WF8B_BPFLCD19_MASK 0x20u
mturner5 0:0d6b77c9ae01 2512 #define LCD_WF8B_BPFLCD19_SHIFT 5
mturner5 0:0d6b77c9ae01 2513 #define LCD_WF8B_BPFLCD2_MASK 0x20u
mturner5 0:0d6b77c9ae01 2514 #define LCD_WF8B_BPFLCD2_SHIFT 5
mturner5 0:0d6b77c9ae01 2515 #define LCD_WF8B_BPFLCD9_MASK 0x20u
mturner5 0:0d6b77c9ae01 2516 #define LCD_WF8B_BPFLCD9_SHIFT 5
mturner5 0:0d6b77c9ae01 2517 #define LCD_WF8B_BPFLCD3_MASK 0x20u
mturner5 0:0d6b77c9ae01 2518 #define LCD_WF8B_BPFLCD3_SHIFT 5
mturner5 0:0d6b77c9ae01 2519 #define LCD_WF8B_BPFLCD37_MASK 0x20u
mturner5 0:0d6b77c9ae01 2520 #define LCD_WF8B_BPFLCD37_SHIFT 5
mturner5 0:0d6b77c9ae01 2521 #define LCD_WF8B_BPFLCD49_MASK 0x20u
mturner5 0:0d6b77c9ae01 2522 #define LCD_WF8B_BPFLCD49_SHIFT 5
mturner5 0:0d6b77c9ae01 2523 #define LCD_WF8B_BPFLCD20_MASK 0x20u
mturner5 0:0d6b77c9ae01 2524 #define LCD_WF8B_BPFLCD20_SHIFT 5
mturner5 0:0d6b77c9ae01 2525 #define LCD_WF8B_BPFLCD44_MASK 0x20u
mturner5 0:0d6b77c9ae01 2526 #define LCD_WF8B_BPFLCD44_SHIFT 5
mturner5 0:0d6b77c9ae01 2527 #define LCD_WF8B_BPFLCD30_MASK 0x20u
mturner5 0:0d6b77c9ae01 2528 #define LCD_WF8B_BPFLCD30_SHIFT 5
mturner5 0:0d6b77c9ae01 2529 #define LCD_WF8B_BPFLCD21_MASK 0x20u
mturner5 0:0d6b77c9ae01 2530 #define LCD_WF8B_BPFLCD21_SHIFT 5
mturner5 0:0d6b77c9ae01 2531 #define LCD_WF8B_BPFLCD35_MASK 0x20u
mturner5 0:0d6b77c9ae01 2532 #define LCD_WF8B_BPFLCD35_SHIFT 5
mturner5 0:0d6b77c9ae01 2533 #define LCD_WF8B_BPFLCD4_MASK 0x20u
mturner5 0:0d6b77c9ae01 2534 #define LCD_WF8B_BPFLCD4_SHIFT 5
mturner5 0:0d6b77c9ae01 2535 #define LCD_WF8B_BPFLCD31_MASK 0x20u
mturner5 0:0d6b77c9ae01 2536 #define LCD_WF8B_BPFLCD31_SHIFT 5
mturner5 0:0d6b77c9ae01 2537 #define LCD_WF8B_BPFLCD48_MASK 0x20u
mturner5 0:0d6b77c9ae01 2538 #define LCD_WF8B_BPFLCD48_SHIFT 5
mturner5 0:0d6b77c9ae01 2539 #define LCD_WF8B_BPFLCD7_MASK 0x20u
mturner5 0:0d6b77c9ae01 2540 #define LCD_WF8B_BPFLCD7_SHIFT 5
mturner5 0:0d6b77c9ae01 2541 #define LCD_WF8B_BPFLCD22_MASK 0x20u
mturner5 0:0d6b77c9ae01 2542 #define LCD_WF8B_BPFLCD22_SHIFT 5
mturner5 0:0d6b77c9ae01 2543 #define LCD_WF8B_BPFLCD38_MASK 0x20u
mturner5 0:0d6b77c9ae01 2544 #define LCD_WF8B_BPFLCD38_SHIFT 5
mturner5 0:0d6b77c9ae01 2545 #define LCD_WF8B_BPFLCD12_MASK 0x20u
mturner5 0:0d6b77c9ae01 2546 #define LCD_WF8B_BPFLCD12_SHIFT 5
mturner5 0:0d6b77c9ae01 2547 #define LCD_WF8B_BPFLCD23_MASK 0x20u
mturner5 0:0d6b77c9ae01 2548 #define LCD_WF8B_BPFLCD23_SHIFT 5
mturner5 0:0d6b77c9ae01 2549 #define LCD_WF8B_BPGLCD14_MASK 0x40u
mturner5 0:0d6b77c9ae01 2550 #define LCD_WF8B_BPGLCD14_SHIFT 6
mturner5 0:0d6b77c9ae01 2551 #define LCD_WF8B_BPGLCD55_MASK 0x40u
mturner5 0:0d6b77c9ae01 2552 #define LCD_WF8B_BPGLCD55_SHIFT 6
mturner5 0:0d6b77c9ae01 2553 #define LCD_WF8B_BPGLCD63_MASK 0x40u
mturner5 0:0d6b77c9ae01 2554 #define LCD_WF8B_BPGLCD63_SHIFT 6
mturner5 0:0d6b77c9ae01 2555 #define LCD_WF8B_BPGLCD15_MASK 0x40u
mturner5 0:0d6b77c9ae01 2556 #define LCD_WF8B_BPGLCD15_SHIFT 6
mturner5 0:0d6b77c9ae01 2557 #define LCD_WF8B_BPGLCD62_MASK 0x40u
mturner5 0:0d6b77c9ae01 2558 #define LCD_WF8B_BPGLCD62_SHIFT 6
mturner5 0:0d6b77c9ae01 2559 #define LCD_WF8B_BPGLCD54_MASK 0x40u
mturner5 0:0d6b77c9ae01 2560 #define LCD_WF8B_BPGLCD54_SHIFT 6
mturner5 0:0d6b77c9ae01 2561 #define LCD_WF8B_BPGLCD61_MASK 0x40u
mturner5 0:0d6b77c9ae01 2562 #define LCD_WF8B_BPGLCD61_SHIFT 6
mturner5 0:0d6b77c9ae01 2563 #define LCD_WF8B_BPGLCD60_MASK 0x40u
mturner5 0:0d6b77c9ae01 2564 #define LCD_WF8B_BPGLCD60_SHIFT 6
mturner5 0:0d6b77c9ae01 2565 #define LCD_WF8B_BPGLCD59_MASK 0x40u
mturner5 0:0d6b77c9ae01 2566 #define LCD_WF8B_BPGLCD59_SHIFT 6
mturner5 0:0d6b77c9ae01 2567 #define LCD_WF8B_BPGLCD53_MASK 0x40u
mturner5 0:0d6b77c9ae01 2568 #define LCD_WF8B_BPGLCD53_SHIFT 6
mturner5 0:0d6b77c9ae01 2569 #define LCD_WF8B_BPGLCD58_MASK 0x40u
mturner5 0:0d6b77c9ae01 2570 #define LCD_WF8B_BPGLCD58_SHIFT 6
mturner5 0:0d6b77c9ae01 2571 #define LCD_WF8B_BPGLCD0_MASK 0x40u
mturner5 0:0d6b77c9ae01 2572 #define LCD_WF8B_BPGLCD0_SHIFT 6
mturner5 0:0d6b77c9ae01 2573 #define LCD_WF8B_BPGLCD57_MASK 0x40u
mturner5 0:0d6b77c9ae01 2574 #define LCD_WF8B_BPGLCD57_SHIFT 6
mturner5 0:0d6b77c9ae01 2575 #define LCD_WF8B_BPGLCD52_MASK 0x40u
mturner5 0:0d6b77c9ae01 2576 #define LCD_WF8B_BPGLCD52_SHIFT 6
mturner5 0:0d6b77c9ae01 2577 #define LCD_WF8B_BPGLCD7_MASK 0x40u
mturner5 0:0d6b77c9ae01 2578 #define LCD_WF8B_BPGLCD7_SHIFT 6
mturner5 0:0d6b77c9ae01 2579 #define LCD_WF8B_BPGLCD56_MASK 0x40u
mturner5 0:0d6b77c9ae01 2580 #define LCD_WF8B_BPGLCD56_SHIFT 6
mturner5 0:0d6b77c9ae01 2581 #define LCD_WF8B_BPGLCD6_MASK 0x40u
mturner5 0:0d6b77c9ae01 2582 #define LCD_WF8B_BPGLCD6_SHIFT 6
mturner5 0:0d6b77c9ae01 2583 #define LCD_WF8B_BPGLCD51_MASK 0x40u
mturner5 0:0d6b77c9ae01 2584 #define LCD_WF8B_BPGLCD51_SHIFT 6
mturner5 0:0d6b77c9ae01 2585 #define LCD_WF8B_BPGLCD16_MASK 0x40u
mturner5 0:0d6b77c9ae01 2586 #define LCD_WF8B_BPGLCD16_SHIFT 6
mturner5 0:0d6b77c9ae01 2587 #define LCD_WF8B_BPGLCD1_MASK 0x40u
mturner5 0:0d6b77c9ae01 2588 #define LCD_WF8B_BPGLCD1_SHIFT 6
mturner5 0:0d6b77c9ae01 2589 #define LCD_WF8B_BPGLCD17_MASK 0x40u
mturner5 0:0d6b77c9ae01 2590 #define LCD_WF8B_BPGLCD17_SHIFT 6
mturner5 0:0d6b77c9ae01 2591 #define LCD_WF8B_BPGLCD50_MASK 0x40u
mturner5 0:0d6b77c9ae01 2592 #define LCD_WF8B_BPGLCD50_SHIFT 6
mturner5 0:0d6b77c9ae01 2593 #define LCD_WF8B_BPGLCD18_MASK 0x40u
mturner5 0:0d6b77c9ae01 2594 #define LCD_WF8B_BPGLCD18_SHIFT 6
mturner5 0:0d6b77c9ae01 2595 #define LCD_WF8B_BPGLCD19_MASK 0x40u
mturner5 0:0d6b77c9ae01 2596 #define LCD_WF8B_BPGLCD19_SHIFT 6
mturner5 0:0d6b77c9ae01 2597 #define LCD_WF8B_BPGLCD8_MASK 0x40u
mturner5 0:0d6b77c9ae01 2598 #define LCD_WF8B_BPGLCD8_SHIFT 6
mturner5 0:0d6b77c9ae01 2599 #define LCD_WF8B_BPGLCD49_MASK 0x40u
mturner5 0:0d6b77c9ae01 2600 #define LCD_WF8B_BPGLCD49_SHIFT 6
mturner5 0:0d6b77c9ae01 2601 #define LCD_WF8B_BPGLCD20_MASK 0x40u
mturner5 0:0d6b77c9ae01 2602 #define LCD_WF8B_BPGLCD20_SHIFT 6
mturner5 0:0d6b77c9ae01 2603 #define LCD_WF8B_BPGLCD9_MASK 0x40u
mturner5 0:0d6b77c9ae01 2604 #define LCD_WF8B_BPGLCD9_SHIFT 6
mturner5 0:0d6b77c9ae01 2605 #define LCD_WF8B_BPGLCD21_MASK 0x40u
mturner5 0:0d6b77c9ae01 2606 #define LCD_WF8B_BPGLCD21_SHIFT 6
mturner5 0:0d6b77c9ae01 2607 #define LCD_WF8B_BPGLCD13_MASK 0x40u
mturner5 0:0d6b77c9ae01 2608 #define LCD_WF8B_BPGLCD13_SHIFT 6
mturner5 0:0d6b77c9ae01 2609 #define LCD_WF8B_BPGLCD48_MASK 0x40u
mturner5 0:0d6b77c9ae01 2610 #define LCD_WF8B_BPGLCD48_SHIFT 6
mturner5 0:0d6b77c9ae01 2611 #define LCD_WF8B_BPGLCD22_MASK 0x40u
mturner5 0:0d6b77c9ae01 2612 #define LCD_WF8B_BPGLCD22_SHIFT 6
mturner5 0:0d6b77c9ae01 2613 #define LCD_WF8B_BPGLCD5_MASK 0x40u
mturner5 0:0d6b77c9ae01 2614 #define LCD_WF8B_BPGLCD5_SHIFT 6
mturner5 0:0d6b77c9ae01 2615 #define LCD_WF8B_BPGLCD47_MASK 0x40u
mturner5 0:0d6b77c9ae01 2616 #define LCD_WF8B_BPGLCD47_SHIFT 6
mturner5 0:0d6b77c9ae01 2617 #define LCD_WF8B_BPGLCD23_MASK 0x40u
mturner5 0:0d6b77c9ae01 2618 #define LCD_WF8B_BPGLCD23_SHIFT 6
mturner5 0:0d6b77c9ae01 2619 #define LCD_WF8B_BPGLCD24_MASK 0x40u
mturner5 0:0d6b77c9ae01 2620 #define LCD_WF8B_BPGLCD24_SHIFT 6
mturner5 0:0d6b77c9ae01 2621 #define LCD_WF8B_BPGLCD25_MASK 0x40u
mturner5 0:0d6b77c9ae01 2622 #define LCD_WF8B_BPGLCD25_SHIFT 6
mturner5 0:0d6b77c9ae01 2623 #define LCD_WF8B_BPGLCD46_MASK 0x40u
mturner5 0:0d6b77c9ae01 2624 #define LCD_WF8B_BPGLCD46_SHIFT 6
mturner5 0:0d6b77c9ae01 2625 #define LCD_WF8B_BPGLCD26_MASK 0x40u
mturner5 0:0d6b77c9ae01 2626 #define LCD_WF8B_BPGLCD26_SHIFT 6
mturner5 0:0d6b77c9ae01 2627 #define LCD_WF8B_BPGLCD27_MASK 0x40u
mturner5 0:0d6b77c9ae01 2628 #define LCD_WF8B_BPGLCD27_SHIFT 6
mturner5 0:0d6b77c9ae01 2629 #define LCD_WF8B_BPGLCD10_MASK 0x40u
mturner5 0:0d6b77c9ae01 2630 #define LCD_WF8B_BPGLCD10_SHIFT 6
mturner5 0:0d6b77c9ae01 2631 #define LCD_WF8B_BPGLCD45_MASK 0x40u
mturner5 0:0d6b77c9ae01 2632 #define LCD_WF8B_BPGLCD45_SHIFT 6
mturner5 0:0d6b77c9ae01 2633 #define LCD_WF8B_BPGLCD28_MASK 0x40u
mturner5 0:0d6b77c9ae01 2634 #define LCD_WF8B_BPGLCD28_SHIFT 6
mturner5 0:0d6b77c9ae01 2635 #define LCD_WF8B_BPGLCD29_MASK 0x40u
mturner5 0:0d6b77c9ae01 2636 #define LCD_WF8B_BPGLCD29_SHIFT 6
mturner5 0:0d6b77c9ae01 2637 #define LCD_WF8B_BPGLCD4_MASK 0x40u
mturner5 0:0d6b77c9ae01 2638 #define LCD_WF8B_BPGLCD4_SHIFT 6
mturner5 0:0d6b77c9ae01 2639 #define LCD_WF8B_BPGLCD44_MASK 0x40u
mturner5 0:0d6b77c9ae01 2640 #define LCD_WF8B_BPGLCD44_SHIFT 6
mturner5 0:0d6b77c9ae01 2641 #define LCD_WF8B_BPGLCD30_MASK 0x40u
mturner5 0:0d6b77c9ae01 2642 #define LCD_WF8B_BPGLCD30_SHIFT 6
mturner5 0:0d6b77c9ae01 2643 #define LCD_WF8B_BPGLCD2_MASK 0x40u
mturner5 0:0d6b77c9ae01 2644 #define LCD_WF8B_BPGLCD2_SHIFT 6
mturner5 0:0d6b77c9ae01 2645 #define LCD_WF8B_BPGLCD31_MASK 0x40u
mturner5 0:0d6b77c9ae01 2646 #define LCD_WF8B_BPGLCD31_SHIFT 6
mturner5 0:0d6b77c9ae01 2647 #define LCD_WF8B_BPGLCD43_MASK 0x40u
mturner5 0:0d6b77c9ae01 2648 #define LCD_WF8B_BPGLCD43_SHIFT 6
mturner5 0:0d6b77c9ae01 2649 #define LCD_WF8B_BPGLCD32_MASK 0x40u
mturner5 0:0d6b77c9ae01 2650 #define LCD_WF8B_BPGLCD32_SHIFT 6
mturner5 0:0d6b77c9ae01 2651 #define LCD_WF8B_BPGLCD33_MASK 0x40u
mturner5 0:0d6b77c9ae01 2652 #define LCD_WF8B_BPGLCD33_SHIFT 6
mturner5 0:0d6b77c9ae01 2653 #define LCD_WF8B_BPGLCD42_MASK 0x40u
mturner5 0:0d6b77c9ae01 2654 #define LCD_WF8B_BPGLCD42_SHIFT 6
mturner5 0:0d6b77c9ae01 2655 #define LCD_WF8B_BPGLCD34_MASK 0x40u
mturner5 0:0d6b77c9ae01 2656 #define LCD_WF8B_BPGLCD34_SHIFT 6
mturner5 0:0d6b77c9ae01 2657 #define LCD_WF8B_BPGLCD11_MASK 0x40u
mturner5 0:0d6b77c9ae01 2658 #define LCD_WF8B_BPGLCD11_SHIFT 6
mturner5 0:0d6b77c9ae01 2659 #define LCD_WF8B_BPGLCD35_MASK 0x40u
mturner5 0:0d6b77c9ae01 2660 #define LCD_WF8B_BPGLCD35_SHIFT 6
mturner5 0:0d6b77c9ae01 2661 #define LCD_WF8B_BPGLCD12_MASK 0x40u
mturner5 0:0d6b77c9ae01 2662 #define LCD_WF8B_BPGLCD12_SHIFT 6
mturner5 0:0d6b77c9ae01 2663 #define LCD_WF8B_BPGLCD41_MASK 0x40u
mturner5 0:0d6b77c9ae01 2664 #define LCD_WF8B_BPGLCD41_SHIFT 6
mturner5 0:0d6b77c9ae01 2665 #define LCD_WF8B_BPGLCD36_MASK 0x40u
mturner5 0:0d6b77c9ae01 2666 #define LCD_WF8B_BPGLCD36_SHIFT 6
mturner5 0:0d6b77c9ae01 2667 #define LCD_WF8B_BPGLCD3_MASK 0x40u
mturner5 0:0d6b77c9ae01 2668 #define LCD_WF8B_BPGLCD3_SHIFT 6
mturner5 0:0d6b77c9ae01 2669 #define LCD_WF8B_BPGLCD37_MASK 0x40u
mturner5 0:0d6b77c9ae01 2670 #define LCD_WF8B_BPGLCD37_SHIFT 6
mturner5 0:0d6b77c9ae01 2671 #define LCD_WF8B_BPGLCD40_MASK 0x40u
mturner5 0:0d6b77c9ae01 2672 #define LCD_WF8B_BPGLCD40_SHIFT 6
mturner5 0:0d6b77c9ae01 2673 #define LCD_WF8B_BPGLCD38_MASK 0x40u
mturner5 0:0d6b77c9ae01 2674 #define LCD_WF8B_BPGLCD38_SHIFT 6
mturner5 0:0d6b77c9ae01 2675 #define LCD_WF8B_BPGLCD39_MASK 0x40u
mturner5 0:0d6b77c9ae01 2676 #define LCD_WF8B_BPGLCD39_SHIFT 6
mturner5 0:0d6b77c9ae01 2677 #define LCD_WF8B_BPHLCD63_MASK 0x80u
mturner5 0:0d6b77c9ae01 2678 #define LCD_WF8B_BPHLCD63_SHIFT 7
mturner5 0:0d6b77c9ae01 2679 #define LCD_WF8B_BPHLCD62_MASK 0x80u
mturner5 0:0d6b77c9ae01 2680 #define LCD_WF8B_BPHLCD62_SHIFT 7
mturner5 0:0d6b77c9ae01 2681 #define LCD_WF8B_BPHLCD61_MASK 0x80u
mturner5 0:0d6b77c9ae01 2682 #define LCD_WF8B_BPHLCD61_SHIFT 7
mturner5 0:0d6b77c9ae01 2683 #define LCD_WF8B_BPHLCD60_MASK 0x80u
mturner5 0:0d6b77c9ae01 2684 #define LCD_WF8B_BPHLCD60_SHIFT 7
mturner5 0:0d6b77c9ae01 2685 #define LCD_WF8B_BPHLCD59_MASK 0x80u
mturner5 0:0d6b77c9ae01 2686 #define LCD_WF8B_BPHLCD59_SHIFT 7
mturner5 0:0d6b77c9ae01 2687 #define LCD_WF8B_BPHLCD58_MASK 0x80u
mturner5 0:0d6b77c9ae01 2688 #define LCD_WF8B_BPHLCD58_SHIFT 7
mturner5 0:0d6b77c9ae01 2689 #define LCD_WF8B_BPHLCD57_MASK 0x80u
mturner5 0:0d6b77c9ae01 2690 #define LCD_WF8B_BPHLCD57_SHIFT 7
mturner5 0:0d6b77c9ae01 2691 #define LCD_WF8B_BPHLCD0_MASK 0x80u
mturner5 0:0d6b77c9ae01 2692 #define LCD_WF8B_BPHLCD0_SHIFT 7
mturner5 0:0d6b77c9ae01 2693 #define LCD_WF8B_BPHLCD56_MASK 0x80u
mturner5 0:0d6b77c9ae01 2694 #define LCD_WF8B_BPHLCD56_SHIFT 7
mturner5 0:0d6b77c9ae01 2695 #define LCD_WF8B_BPHLCD55_MASK 0x80u
mturner5 0:0d6b77c9ae01 2696 #define LCD_WF8B_BPHLCD55_SHIFT 7
mturner5 0:0d6b77c9ae01 2697 #define LCD_WF8B_BPHLCD54_MASK 0x80u
mturner5 0:0d6b77c9ae01 2698 #define LCD_WF8B_BPHLCD54_SHIFT 7
mturner5 0:0d6b77c9ae01 2699 #define LCD_WF8B_BPHLCD53_MASK 0x80u
mturner5 0:0d6b77c9ae01 2700 #define LCD_WF8B_BPHLCD53_SHIFT 7
mturner5 0:0d6b77c9ae01 2701 #define LCD_WF8B_BPHLCD52_MASK 0x80u
mturner5 0:0d6b77c9ae01 2702 #define LCD_WF8B_BPHLCD52_SHIFT 7
mturner5 0:0d6b77c9ae01 2703 #define LCD_WF8B_BPHLCD51_MASK 0x80u
mturner5 0:0d6b77c9ae01 2704 #define LCD_WF8B_BPHLCD51_SHIFT 7
mturner5 0:0d6b77c9ae01 2705 #define LCD_WF8B_BPHLCD50_MASK 0x80u
mturner5 0:0d6b77c9ae01 2706 #define LCD_WF8B_BPHLCD50_SHIFT 7
mturner5 0:0d6b77c9ae01 2707 #define LCD_WF8B_BPHLCD1_MASK 0x80u
mturner5 0:0d6b77c9ae01 2708 #define LCD_WF8B_BPHLCD1_SHIFT 7
mturner5 0:0d6b77c9ae01 2709 #define LCD_WF8B_BPHLCD49_MASK 0x80u
mturner5 0:0d6b77c9ae01 2710 #define LCD_WF8B_BPHLCD49_SHIFT 7
mturner5 0:0d6b77c9ae01 2711 #define LCD_WF8B_BPHLCD48_MASK 0x80u
mturner5 0:0d6b77c9ae01 2712 #define LCD_WF8B_BPHLCD48_SHIFT 7
mturner5 0:0d6b77c9ae01 2713 #define LCD_WF8B_BPHLCD47_MASK 0x80u
mturner5 0:0d6b77c9ae01 2714 #define LCD_WF8B_BPHLCD47_SHIFT 7
mturner5 0:0d6b77c9ae01 2715 #define LCD_WF8B_BPHLCD46_MASK 0x80u
mturner5 0:0d6b77c9ae01 2716 #define LCD_WF8B_BPHLCD46_SHIFT 7
mturner5 0:0d6b77c9ae01 2717 #define LCD_WF8B_BPHLCD45_MASK 0x80u
mturner5 0:0d6b77c9ae01 2718 #define LCD_WF8B_BPHLCD45_SHIFT 7
mturner5 0:0d6b77c9ae01 2719 #define LCD_WF8B_BPHLCD44_MASK 0x80u
mturner5 0:0d6b77c9ae01 2720 #define LCD_WF8B_BPHLCD44_SHIFT 7
mturner5 0:0d6b77c9ae01 2721 #define LCD_WF8B_BPHLCD43_MASK 0x80u
mturner5 0:0d6b77c9ae01 2722 #define LCD_WF8B_BPHLCD43_SHIFT 7
mturner5 0:0d6b77c9ae01 2723 #define LCD_WF8B_BPHLCD2_MASK 0x80u
mturner5 0:0d6b77c9ae01 2724 #define LCD_WF8B_BPHLCD2_SHIFT 7
mturner5 0:0d6b77c9ae01 2725 #define LCD_WF8B_BPHLCD42_MASK 0x80u
mturner5 0:0d6b77c9ae01 2726 #define LCD_WF8B_BPHLCD42_SHIFT 7
mturner5 0:0d6b77c9ae01 2727 #define LCD_WF8B_BPHLCD41_MASK 0x80u
mturner5 0:0d6b77c9ae01 2728 #define LCD_WF8B_BPHLCD41_SHIFT 7
mturner5 0:0d6b77c9ae01 2729 #define LCD_WF8B_BPHLCD40_MASK 0x80u
mturner5 0:0d6b77c9ae01 2730 #define LCD_WF8B_BPHLCD40_SHIFT 7
mturner5 0:0d6b77c9ae01 2731 #define LCD_WF8B_BPHLCD39_MASK 0x80u
mturner5 0:0d6b77c9ae01 2732 #define LCD_WF8B_BPHLCD39_SHIFT 7
mturner5 0:0d6b77c9ae01 2733 #define LCD_WF8B_BPHLCD38_MASK 0x80u
mturner5 0:0d6b77c9ae01 2734 #define LCD_WF8B_BPHLCD38_SHIFT 7
mturner5 0:0d6b77c9ae01 2735 #define LCD_WF8B_BPHLCD37_MASK 0x80u
mturner5 0:0d6b77c9ae01 2736 #define LCD_WF8B_BPHLCD37_SHIFT 7
mturner5 0:0d6b77c9ae01 2737 #define LCD_WF8B_BPHLCD36_MASK 0x80u
mturner5 0:0d6b77c9ae01 2738 #define LCD_WF8B_BPHLCD36_SHIFT 7
mturner5 0:0d6b77c9ae01 2739 #define LCD_WF8B_BPHLCD3_MASK 0x80u
mturner5 0:0d6b77c9ae01 2740 #define LCD_WF8B_BPHLCD3_SHIFT 7
mturner5 0:0d6b77c9ae01 2741 #define LCD_WF8B_BPHLCD35_MASK 0x80u
mturner5 0:0d6b77c9ae01 2742 #define LCD_WF8B_BPHLCD35_SHIFT 7
mturner5 0:0d6b77c9ae01 2743 #define LCD_WF8B_BPHLCD34_MASK 0x80u
mturner5 0:0d6b77c9ae01 2744 #define LCD_WF8B_BPHLCD34_SHIFT 7
mturner5 0:0d6b77c9ae01 2745 #define LCD_WF8B_BPHLCD33_MASK 0x80u
mturner5 0:0d6b77c9ae01 2746 #define LCD_WF8B_BPHLCD33_SHIFT 7
mturner5 0:0d6b77c9ae01 2747 #define LCD_WF8B_BPHLCD32_MASK 0x80u
mturner5 0:0d6b77c9ae01 2748 #define LCD_WF8B_BPHLCD32_SHIFT 7
mturner5 0:0d6b77c9ae01 2749 #define LCD_WF8B_BPHLCD31_MASK 0x80u
mturner5 0:0d6b77c9ae01 2750 #define LCD_WF8B_BPHLCD31_SHIFT 7
mturner5 0:0d6b77c9ae01 2751 #define LCD_WF8B_BPHLCD30_MASK 0x80u
mturner5 0:0d6b77c9ae01 2752 #define LCD_WF8B_BPHLCD30_SHIFT 7
mturner5 0:0d6b77c9ae01 2753 #define LCD_WF8B_BPHLCD29_MASK 0x80u
mturner5 0:0d6b77c9ae01 2754 #define LCD_WF8B_BPHLCD29_SHIFT 7
mturner5 0:0d6b77c9ae01 2755 #define LCD_WF8B_BPHLCD4_MASK 0x80u
mturner5 0:0d6b77c9ae01 2756 #define LCD_WF8B_BPHLCD4_SHIFT 7
mturner5 0:0d6b77c9ae01 2757 #define LCD_WF8B_BPHLCD28_MASK 0x80u
mturner5 0:0d6b77c9ae01 2758 #define LCD_WF8B_BPHLCD28_SHIFT 7
mturner5 0:0d6b77c9ae01 2759 #define LCD_WF8B_BPHLCD27_MASK 0x80u
mturner5 0:0d6b77c9ae01 2760 #define LCD_WF8B_BPHLCD27_SHIFT 7
mturner5 0:0d6b77c9ae01 2761 #define LCD_WF8B_BPHLCD26_MASK 0x80u
mturner5 0:0d6b77c9ae01 2762 #define LCD_WF8B_BPHLCD26_SHIFT 7
mturner5 0:0d6b77c9ae01 2763 #define LCD_WF8B_BPHLCD25_MASK 0x80u
mturner5 0:0d6b77c9ae01 2764 #define LCD_WF8B_BPHLCD25_SHIFT 7
mturner5 0:0d6b77c9ae01 2765 #define LCD_WF8B_BPHLCD24_MASK 0x80u
mturner5 0:0d6b77c9ae01 2766 #define LCD_WF8B_BPHLCD24_SHIFT 7
mturner5 0:0d6b77c9ae01 2767 #define LCD_WF8B_BPHLCD23_MASK 0x80u
mturner5 0:0d6b77c9ae01 2768 #define LCD_WF8B_BPHLCD23_SHIFT 7
mturner5 0:0d6b77c9ae01 2769 #define LCD_WF8B_BPHLCD22_MASK 0x80u
mturner5 0:0d6b77c9ae01 2770 #define LCD_WF8B_BPHLCD22_SHIFT 7
mturner5 0:0d6b77c9ae01 2771 #define LCD_WF8B_BPHLCD5_MASK 0x80u
mturner5 0:0d6b77c9ae01 2772 #define LCD_WF8B_BPHLCD5_SHIFT 7
mturner5 0:0d6b77c9ae01 2773 #define LCD_WF8B_BPHLCD21_MASK 0x80u
mturner5 0:0d6b77c9ae01 2774 #define LCD_WF8B_BPHLCD21_SHIFT 7
mturner5 0:0d6b77c9ae01 2775 #define LCD_WF8B_BPHLCD20_MASK 0x80u
mturner5 0:0d6b77c9ae01 2776 #define LCD_WF8B_BPHLCD20_SHIFT 7
mturner5 0:0d6b77c9ae01 2777 #define LCD_WF8B_BPHLCD19_MASK 0x80u
mturner5 0:0d6b77c9ae01 2778 #define LCD_WF8B_BPHLCD19_SHIFT 7
mturner5 0:0d6b77c9ae01 2779 #define LCD_WF8B_BPHLCD18_MASK 0x80u
mturner5 0:0d6b77c9ae01 2780 #define LCD_WF8B_BPHLCD18_SHIFT 7
mturner5 0:0d6b77c9ae01 2781 #define LCD_WF8B_BPHLCD17_MASK 0x80u
mturner5 0:0d6b77c9ae01 2782 #define LCD_WF8B_BPHLCD17_SHIFT 7
mturner5 0:0d6b77c9ae01 2783 #define LCD_WF8B_BPHLCD16_MASK 0x80u
mturner5 0:0d6b77c9ae01 2784 #define LCD_WF8B_BPHLCD16_SHIFT 7
mturner5 0:0d6b77c9ae01 2785 #define LCD_WF8B_BPHLCD15_MASK 0x80u
mturner5 0:0d6b77c9ae01 2786 #define LCD_WF8B_BPHLCD15_SHIFT 7
mturner5 0:0d6b77c9ae01 2787 #define LCD_WF8B_BPHLCD6_MASK 0x80u
mturner5 0:0d6b77c9ae01 2788 #define LCD_WF8B_BPHLCD6_SHIFT 7
mturner5 0:0d6b77c9ae01 2789 #define LCD_WF8B_BPHLCD14_MASK 0x80u
mturner5 0:0d6b77c9ae01 2790 #define LCD_WF8B_BPHLCD14_SHIFT 7
mturner5 0:0d6b77c9ae01 2791 #define LCD_WF8B_BPHLCD13_MASK 0x80u
mturner5 0:0d6b77c9ae01 2792 #define LCD_WF8B_BPHLCD13_SHIFT 7
mturner5 0:0d6b77c9ae01 2793 #define LCD_WF8B_BPHLCD12_MASK 0x80u
mturner5 0:0d6b77c9ae01 2794 #define LCD_WF8B_BPHLCD12_SHIFT 7
mturner5 0:0d6b77c9ae01 2795 #define LCD_WF8B_BPHLCD11_MASK 0x80u
mturner5 0:0d6b77c9ae01 2796 #define LCD_WF8B_BPHLCD11_SHIFT 7
mturner5 0:0d6b77c9ae01 2797 #define LCD_WF8B_BPHLCD10_MASK 0x80u
mturner5 0:0d6b77c9ae01 2798 #define LCD_WF8B_BPHLCD10_SHIFT 7
mturner5 0:0d6b77c9ae01 2799 #define LCD_WF8B_BPHLCD9_MASK 0x80u
mturner5 0:0d6b77c9ae01 2800 #define LCD_WF8B_BPHLCD9_SHIFT 7
mturner5 0:0d6b77c9ae01 2801 #define LCD_WF8B_BPHLCD8_MASK 0x80u
mturner5 0:0d6b77c9ae01 2802 #define LCD_WF8B_BPHLCD8_SHIFT 7
mturner5 0:0d6b77c9ae01 2803 #define LCD_WF8B_BPHLCD7_MASK 0x80u
mturner5 0:0d6b77c9ae01 2804 #define LCD_WF8B_BPHLCD7_SHIFT 7
mturner5 0:0d6b77c9ae01 2805
mturner5 0:0d6b77c9ae01 2806 /*!
mturner5 0:0d6b77c9ae01 2807 * @}
mturner5 0:0d6b77c9ae01 2808 */ /* end of group LCD_Register_Masks */
mturner5 0:0d6b77c9ae01 2809
mturner5 0:0d6b77c9ae01 2810
mturner5 0:0d6b77c9ae01 2811 /* LCD - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 2812 /** Peripheral LCD base address */
mturner5 0:0d6b77c9ae01 2813 #define LCD_BASE (0x40053000u)
mturner5 0:0d6b77c9ae01 2814 /** Peripheral LCD base pointer */
mturner5 0:0d6b77c9ae01 2815 #define LCD ((LCD_Type *)LCD_BASE)
mturner5 0:0d6b77c9ae01 2816 /** Array initializer of LCD peripheral base pointers */
mturner5 0:0d6b77c9ae01 2817 #define LCD_BASES { LCD }
mturner5 0:0d6b77c9ae01 2818
mturner5 0:0d6b77c9ae01 2819 /*!
mturner5 0:0d6b77c9ae01 2820 * @}
mturner5 0:0d6b77c9ae01 2821 */ /* end of group LCD_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 2822
mturner5 0:0d6b77c9ae01 2823
mturner5 0:0d6b77c9ae01 2824 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 2825 -- LLWU Peripheral Access Layer
mturner5 0:0d6b77c9ae01 2826 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 2827
mturner5 0:0d6b77c9ae01 2828 /*!
mturner5 0:0d6b77c9ae01 2829 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mturner5 0:0d6b77c9ae01 2830 * @{
mturner5 0:0d6b77c9ae01 2831 */
mturner5 0:0d6b77c9ae01 2832
mturner5 0:0d6b77c9ae01 2833 /** LLWU - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 2834 typedef struct {
mturner5 0:0d6b77c9ae01 2835 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 2836 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 2837 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mturner5 0:0d6b77c9ae01 2838 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mturner5 0:0d6b77c9ae01 2839 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 2840 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mturner5 0:0d6b77c9ae01 2841 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mturner5 0:0d6b77c9ae01 2842 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mturner5 0:0d6b77c9ae01 2843 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 2844 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mturner5 0:0d6b77c9ae01 2845 } LLWU_Type;
mturner5 0:0d6b77c9ae01 2846
mturner5 0:0d6b77c9ae01 2847 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 2848 -- LLWU Register Masks
mturner5 0:0d6b77c9ae01 2849 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 2850
mturner5 0:0d6b77c9ae01 2851 /*!
mturner5 0:0d6b77c9ae01 2852 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mturner5 0:0d6b77c9ae01 2853 * @{
mturner5 0:0d6b77c9ae01 2854 */
mturner5 0:0d6b77c9ae01 2855
mturner5 0:0d6b77c9ae01 2856 /* PE1 Bit Fields */
mturner5 0:0d6b77c9ae01 2857 #define LLWU_PE1_WUPE0_MASK 0x3u
mturner5 0:0d6b77c9ae01 2858 #define LLWU_PE1_WUPE0_SHIFT 0
mturner5 0:0d6b77c9ae01 2859 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mturner5 0:0d6b77c9ae01 2860 #define LLWU_PE1_WUPE1_MASK 0xCu
mturner5 0:0d6b77c9ae01 2861 #define LLWU_PE1_WUPE1_SHIFT 2
mturner5 0:0d6b77c9ae01 2862 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mturner5 0:0d6b77c9ae01 2863 #define LLWU_PE1_WUPE2_MASK 0x30u
mturner5 0:0d6b77c9ae01 2864 #define LLWU_PE1_WUPE2_SHIFT 4
mturner5 0:0d6b77c9ae01 2865 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mturner5 0:0d6b77c9ae01 2866 #define LLWU_PE1_WUPE3_MASK 0xC0u
mturner5 0:0d6b77c9ae01 2867 #define LLWU_PE1_WUPE3_SHIFT 6
mturner5 0:0d6b77c9ae01 2868 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mturner5 0:0d6b77c9ae01 2869 /* PE2 Bit Fields */
mturner5 0:0d6b77c9ae01 2870 #define LLWU_PE2_WUPE4_MASK 0x3u
mturner5 0:0d6b77c9ae01 2871 #define LLWU_PE2_WUPE4_SHIFT 0
mturner5 0:0d6b77c9ae01 2872 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mturner5 0:0d6b77c9ae01 2873 #define LLWU_PE2_WUPE5_MASK 0xCu
mturner5 0:0d6b77c9ae01 2874 #define LLWU_PE2_WUPE5_SHIFT 2
mturner5 0:0d6b77c9ae01 2875 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mturner5 0:0d6b77c9ae01 2876 #define LLWU_PE2_WUPE6_MASK 0x30u
mturner5 0:0d6b77c9ae01 2877 #define LLWU_PE2_WUPE6_SHIFT 4
mturner5 0:0d6b77c9ae01 2878 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mturner5 0:0d6b77c9ae01 2879 #define LLWU_PE2_WUPE7_MASK 0xC0u
mturner5 0:0d6b77c9ae01 2880 #define LLWU_PE2_WUPE7_SHIFT 6
mturner5 0:0d6b77c9ae01 2881 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mturner5 0:0d6b77c9ae01 2882 /* PE3 Bit Fields */
mturner5 0:0d6b77c9ae01 2883 #define LLWU_PE3_WUPE8_MASK 0x3u
mturner5 0:0d6b77c9ae01 2884 #define LLWU_PE3_WUPE8_SHIFT 0
mturner5 0:0d6b77c9ae01 2885 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mturner5 0:0d6b77c9ae01 2886 #define LLWU_PE3_WUPE9_MASK 0xCu
mturner5 0:0d6b77c9ae01 2887 #define LLWU_PE3_WUPE9_SHIFT 2
mturner5 0:0d6b77c9ae01 2888 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mturner5 0:0d6b77c9ae01 2889 #define LLWU_PE3_WUPE10_MASK 0x30u
mturner5 0:0d6b77c9ae01 2890 #define LLWU_PE3_WUPE10_SHIFT 4
mturner5 0:0d6b77c9ae01 2891 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mturner5 0:0d6b77c9ae01 2892 #define LLWU_PE3_WUPE11_MASK 0xC0u
mturner5 0:0d6b77c9ae01 2893 #define LLWU_PE3_WUPE11_SHIFT 6
mturner5 0:0d6b77c9ae01 2894 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mturner5 0:0d6b77c9ae01 2895 /* PE4 Bit Fields */
mturner5 0:0d6b77c9ae01 2896 #define LLWU_PE4_WUPE12_MASK 0x3u
mturner5 0:0d6b77c9ae01 2897 #define LLWU_PE4_WUPE12_SHIFT 0
mturner5 0:0d6b77c9ae01 2898 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mturner5 0:0d6b77c9ae01 2899 #define LLWU_PE4_WUPE13_MASK 0xCu
mturner5 0:0d6b77c9ae01 2900 #define LLWU_PE4_WUPE13_SHIFT 2
mturner5 0:0d6b77c9ae01 2901 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mturner5 0:0d6b77c9ae01 2902 #define LLWU_PE4_WUPE14_MASK 0x30u
mturner5 0:0d6b77c9ae01 2903 #define LLWU_PE4_WUPE14_SHIFT 4
mturner5 0:0d6b77c9ae01 2904 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mturner5 0:0d6b77c9ae01 2905 #define LLWU_PE4_WUPE15_MASK 0xC0u
mturner5 0:0d6b77c9ae01 2906 #define LLWU_PE4_WUPE15_SHIFT 6
mturner5 0:0d6b77c9ae01 2907 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mturner5 0:0d6b77c9ae01 2908 /* ME Bit Fields */
mturner5 0:0d6b77c9ae01 2909 #define LLWU_ME_WUME0_MASK 0x1u
mturner5 0:0d6b77c9ae01 2910 #define LLWU_ME_WUME0_SHIFT 0
mturner5 0:0d6b77c9ae01 2911 #define LLWU_ME_WUME1_MASK 0x2u
mturner5 0:0d6b77c9ae01 2912 #define LLWU_ME_WUME1_SHIFT 1
mturner5 0:0d6b77c9ae01 2913 #define LLWU_ME_WUME2_MASK 0x4u
mturner5 0:0d6b77c9ae01 2914 #define LLWU_ME_WUME2_SHIFT 2
mturner5 0:0d6b77c9ae01 2915 #define LLWU_ME_WUME3_MASK 0x8u
mturner5 0:0d6b77c9ae01 2916 #define LLWU_ME_WUME3_SHIFT 3
mturner5 0:0d6b77c9ae01 2917 #define LLWU_ME_WUME4_MASK 0x10u
mturner5 0:0d6b77c9ae01 2918 #define LLWU_ME_WUME4_SHIFT 4
mturner5 0:0d6b77c9ae01 2919 #define LLWU_ME_WUME5_MASK 0x20u
mturner5 0:0d6b77c9ae01 2920 #define LLWU_ME_WUME5_SHIFT 5
mturner5 0:0d6b77c9ae01 2921 #define LLWU_ME_WUME6_MASK 0x40u
mturner5 0:0d6b77c9ae01 2922 #define LLWU_ME_WUME6_SHIFT 6
mturner5 0:0d6b77c9ae01 2923 #define LLWU_ME_WUME7_MASK 0x80u
mturner5 0:0d6b77c9ae01 2924 #define LLWU_ME_WUME7_SHIFT 7
mturner5 0:0d6b77c9ae01 2925 /* F1 Bit Fields */
mturner5 0:0d6b77c9ae01 2926 #define LLWU_F1_WUF0_MASK 0x1u
mturner5 0:0d6b77c9ae01 2927 #define LLWU_F1_WUF0_SHIFT 0
mturner5 0:0d6b77c9ae01 2928 #define LLWU_F1_WUF1_MASK 0x2u
mturner5 0:0d6b77c9ae01 2929 #define LLWU_F1_WUF1_SHIFT 1
mturner5 0:0d6b77c9ae01 2930 #define LLWU_F1_WUF2_MASK 0x4u
mturner5 0:0d6b77c9ae01 2931 #define LLWU_F1_WUF2_SHIFT 2
mturner5 0:0d6b77c9ae01 2932 #define LLWU_F1_WUF3_MASK 0x8u
mturner5 0:0d6b77c9ae01 2933 #define LLWU_F1_WUF3_SHIFT 3
mturner5 0:0d6b77c9ae01 2934 #define LLWU_F1_WUF4_MASK 0x10u
mturner5 0:0d6b77c9ae01 2935 #define LLWU_F1_WUF4_SHIFT 4
mturner5 0:0d6b77c9ae01 2936 #define LLWU_F1_WUF5_MASK 0x20u
mturner5 0:0d6b77c9ae01 2937 #define LLWU_F1_WUF5_SHIFT 5
mturner5 0:0d6b77c9ae01 2938 #define LLWU_F1_WUF6_MASK 0x40u
mturner5 0:0d6b77c9ae01 2939 #define LLWU_F1_WUF6_SHIFT 6
mturner5 0:0d6b77c9ae01 2940 #define LLWU_F1_WUF7_MASK 0x80u
mturner5 0:0d6b77c9ae01 2941 #define LLWU_F1_WUF7_SHIFT 7
mturner5 0:0d6b77c9ae01 2942 /* F2 Bit Fields */
mturner5 0:0d6b77c9ae01 2943 #define LLWU_F2_WUF8_MASK 0x1u
mturner5 0:0d6b77c9ae01 2944 #define LLWU_F2_WUF8_SHIFT 0
mturner5 0:0d6b77c9ae01 2945 #define LLWU_F2_WUF9_MASK 0x2u
mturner5 0:0d6b77c9ae01 2946 #define LLWU_F2_WUF9_SHIFT 1
mturner5 0:0d6b77c9ae01 2947 #define LLWU_F2_WUF10_MASK 0x4u
mturner5 0:0d6b77c9ae01 2948 #define LLWU_F2_WUF10_SHIFT 2
mturner5 0:0d6b77c9ae01 2949 #define LLWU_F2_WUF11_MASK 0x8u
mturner5 0:0d6b77c9ae01 2950 #define LLWU_F2_WUF11_SHIFT 3
mturner5 0:0d6b77c9ae01 2951 #define LLWU_F2_WUF12_MASK 0x10u
mturner5 0:0d6b77c9ae01 2952 #define LLWU_F2_WUF12_SHIFT 4
mturner5 0:0d6b77c9ae01 2953 #define LLWU_F2_WUF13_MASK 0x20u
mturner5 0:0d6b77c9ae01 2954 #define LLWU_F2_WUF13_SHIFT 5
mturner5 0:0d6b77c9ae01 2955 #define LLWU_F2_WUF14_MASK 0x40u
mturner5 0:0d6b77c9ae01 2956 #define LLWU_F2_WUF14_SHIFT 6
mturner5 0:0d6b77c9ae01 2957 #define LLWU_F2_WUF15_MASK 0x80u
mturner5 0:0d6b77c9ae01 2958 #define LLWU_F2_WUF15_SHIFT 7
mturner5 0:0d6b77c9ae01 2959 /* F3 Bit Fields */
mturner5 0:0d6b77c9ae01 2960 #define LLWU_F3_MWUF0_MASK 0x1u
mturner5 0:0d6b77c9ae01 2961 #define LLWU_F3_MWUF0_SHIFT 0
mturner5 0:0d6b77c9ae01 2962 #define LLWU_F3_MWUF1_MASK 0x2u
mturner5 0:0d6b77c9ae01 2963 #define LLWU_F3_MWUF1_SHIFT 1
mturner5 0:0d6b77c9ae01 2964 #define LLWU_F3_MWUF2_MASK 0x4u
mturner5 0:0d6b77c9ae01 2965 #define LLWU_F3_MWUF2_SHIFT 2
mturner5 0:0d6b77c9ae01 2966 #define LLWU_F3_MWUF3_MASK 0x8u
mturner5 0:0d6b77c9ae01 2967 #define LLWU_F3_MWUF3_SHIFT 3
mturner5 0:0d6b77c9ae01 2968 #define LLWU_F3_MWUF4_MASK 0x10u
mturner5 0:0d6b77c9ae01 2969 #define LLWU_F3_MWUF4_SHIFT 4
mturner5 0:0d6b77c9ae01 2970 #define LLWU_F3_MWUF5_MASK 0x20u
mturner5 0:0d6b77c9ae01 2971 #define LLWU_F3_MWUF5_SHIFT 5
mturner5 0:0d6b77c9ae01 2972 #define LLWU_F3_MWUF6_MASK 0x40u
mturner5 0:0d6b77c9ae01 2973 #define LLWU_F3_MWUF6_SHIFT 6
mturner5 0:0d6b77c9ae01 2974 #define LLWU_F3_MWUF7_MASK 0x80u
mturner5 0:0d6b77c9ae01 2975 #define LLWU_F3_MWUF7_SHIFT 7
mturner5 0:0d6b77c9ae01 2976 /* FILT1 Bit Fields */
mturner5 0:0d6b77c9ae01 2977 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mturner5 0:0d6b77c9ae01 2978 #define LLWU_FILT1_FILTSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 2979 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mturner5 0:0d6b77c9ae01 2980 #define LLWU_FILT1_FILTE_MASK 0x60u
mturner5 0:0d6b77c9ae01 2981 #define LLWU_FILT1_FILTE_SHIFT 5
mturner5 0:0d6b77c9ae01 2982 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mturner5 0:0d6b77c9ae01 2983 #define LLWU_FILT1_FILTF_MASK 0x80u
mturner5 0:0d6b77c9ae01 2984 #define LLWU_FILT1_FILTF_SHIFT 7
mturner5 0:0d6b77c9ae01 2985 /* FILT2 Bit Fields */
mturner5 0:0d6b77c9ae01 2986 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mturner5 0:0d6b77c9ae01 2987 #define LLWU_FILT2_FILTSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 2988 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mturner5 0:0d6b77c9ae01 2989 #define LLWU_FILT2_FILTE_MASK 0x60u
mturner5 0:0d6b77c9ae01 2990 #define LLWU_FILT2_FILTE_SHIFT 5
mturner5 0:0d6b77c9ae01 2991 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mturner5 0:0d6b77c9ae01 2992 #define LLWU_FILT2_FILTF_MASK 0x80u
mturner5 0:0d6b77c9ae01 2993 #define LLWU_FILT2_FILTF_SHIFT 7
mturner5 0:0d6b77c9ae01 2994
mturner5 0:0d6b77c9ae01 2995 /*!
mturner5 0:0d6b77c9ae01 2996 * @}
mturner5 0:0d6b77c9ae01 2997 */ /* end of group LLWU_Register_Masks */
mturner5 0:0d6b77c9ae01 2998
mturner5 0:0d6b77c9ae01 2999
mturner5 0:0d6b77c9ae01 3000 /* LLWU - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3001 /** Peripheral LLWU base address */
mturner5 0:0d6b77c9ae01 3002 #define LLWU_BASE (0x4007C000u)
mturner5 0:0d6b77c9ae01 3003 /** Peripheral LLWU base pointer */
mturner5 0:0d6b77c9ae01 3004 #define LLWU ((LLWU_Type *)LLWU_BASE)
mturner5 0:0d6b77c9ae01 3005 /** Array initializer of LLWU peripheral base pointers */
mturner5 0:0d6b77c9ae01 3006 #define LLWU_BASES { LLWU }
mturner5 0:0d6b77c9ae01 3007
mturner5 0:0d6b77c9ae01 3008 /*!
mturner5 0:0d6b77c9ae01 3009 * @}
mturner5 0:0d6b77c9ae01 3010 */ /* end of group LLWU_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3011
mturner5 0:0d6b77c9ae01 3012
mturner5 0:0d6b77c9ae01 3013 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3014 -- LPTMR Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3015 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3016
mturner5 0:0d6b77c9ae01 3017 /*!
mturner5 0:0d6b77c9ae01 3018 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3019 * @{
mturner5 0:0d6b77c9ae01 3020 */
mturner5 0:0d6b77c9ae01 3021
mturner5 0:0d6b77c9ae01 3022 /** LPTMR - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3023 typedef struct {
mturner5 0:0d6b77c9ae01 3024 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3025 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 3026 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 3027 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 3028 } LPTMR_Type;
mturner5 0:0d6b77c9ae01 3029
mturner5 0:0d6b77c9ae01 3030 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3031 -- LPTMR Register Masks
mturner5 0:0d6b77c9ae01 3032 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3033
mturner5 0:0d6b77c9ae01 3034 /*!
mturner5 0:0d6b77c9ae01 3035 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mturner5 0:0d6b77c9ae01 3036 * @{
mturner5 0:0d6b77c9ae01 3037 */
mturner5 0:0d6b77c9ae01 3038
mturner5 0:0d6b77c9ae01 3039 /* CSR Bit Fields */
mturner5 0:0d6b77c9ae01 3040 #define LPTMR_CSR_TEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 3041 #define LPTMR_CSR_TEN_SHIFT 0
mturner5 0:0d6b77c9ae01 3042 #define LPTMR_CSR_TMS_MASK 0x2u
mturner5 0:0d6b77c9ae01 3043 #define LPTMR_CSR_TMS_SHIFT 1
mturner5 0:0d6b77c9ae01 3044 #define LPTMR_CSR_TFC_MASK 0x4u
mturner5 0:0d6b77c9ae01 3045 #define LPTMR_CSR_TFC_SHIFT 2
mturner5 0:0d6b77c9ae01 3046 #define LPTMR_CSR_TPP_MASK 0x8u
mturner5 0:0d6b77c9ae01 3047 #define LPTMR_CSR_TPP_SHIFT 3
mturner5 0:0d6b77c9ae01 3048 #define LPTMR_CSR_TPS_MASK 0x30u
mturner5 0:0d6b77c9ae01 3049 #define LPTMR_CSR_TPS_SHIFT 4
mturner5 0:0d6b77c9ae01 3050 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mturner5 0:0d6b77c9ae01 3051 #define LPTMR_CSR_TIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 3052 #define LPTMR_CSR_TIE_SHIFT 6
mturner5 0:0d6b77c9ae01 3053 #define LPTMR_CSR_TCF_MASK 0x80u
mturner5 0:0d6b77c9ae01 3054 #define LPTMR_CSR_TCF_SHIFT 7
mturner5 0:0d6b77c9ae01 3055 /* PSR Bit Fields */
mturner5 0:0d6b77c9ae01 3056 #define LPTMR_PSR_PCS_MASK 0x3u
mturner5 0:0d6b77c9ae01 3057 #define LPTMR_PSR_PCS_SHIFT 0
mturner5 0:0d6b77c9ae01 3058 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mturner5 0:0d6b77c9ae01 3059 #define LPTMR_PSR_PBYP_MASK 0x4u
mturner5 0:0d6b77c9ae01 3060 #define LPTMR_PSR_PBYP_SHIFT 2
mturner5 0:0d6b77c9ae01 3061 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mturner5 0:0d6b77c9ae01 3062 #define LPTMR_PSR_PRESCALE_SHIFT 3
mturner5 0:0d6b77c9ae01 3063 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mturner5 0:0d6b77c9ae01 3064 /* CMR Bit Fields */
mturner5 0:0d6b77c9ae01 3065 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 3066 #define LPTMR_CMR_COMPARE_SHIFT 0
mturner5 0:0d6b77c9ae01 3067 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mturner5 0:0d6b77c9ae01 3068 /* CNR Bit Fields */
mturner5 0:0d6b77c9ae01 3069 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 3070 #define LPTMR_CNR_COUNTER_SHIFT 0
mturner5 0:0d6b77c9ae01 3071 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mturner5 0:0d6b77c9ae01 3072
mturner5 0:0d6b77c9ae01 3073 /*!
mturner5 0:0d6b77c9ae01 3074 * @}
mturner5 0:0d6b77c9ae01 3075 */ /* end of group LPTMR_Register_Masks */
mturner5 0:0d6b77c9ae01 3076
mturner5 0:0d6b77c9ae01 3077
mturner5 0:0d6b77c9ae01 3078 /* LPTMR - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3079 /** Peripheral LPTMR0 base address */
mturner5 0:0d6b77c9ae01 3080 #define LPTMR0_BASE (0x40040000u)
mturner5 0:0d6b77c9ae01 3081 /** Peripheral LPTMR0 base pointer */
mturner5 0:0d6b77c9ae01 3082 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mturner5 0:0d6b77c9ae01 3083 /** Array initializer of LPTMR peripheral base pointers */
mturner5 0:0d6b77c9ae01 3084 #define LPTMR_BASES { LPTMR0 }
mturner5 0:0d6b77c9ae01 3085
mturner5 0:0d6b77c9ae01 3086 /*!
mturner5 0:0d6b77c9ae01 3087 * @}
mturner5 0:0d6b77c9ae01 3088 */ /* end of group LPTMR_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3089
mturner5 0:0d6b77c9ae01 3090
mturner5 0:0d6b77c9ae01 3091 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3092 -- MCG Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3093 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3094
mturner5 0:0d6b77c9ae01 3095 /*!
mturner5 0:0d6b77c9ae01 3096 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3097 * @{
mturner5 0:0d6b77c9ae01 3098 */
mturner5 0:0d6b77c9ae01 3099
mturner5 0:0d6b77c9ae01 3100 /** MCG - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3101 typedef struct {
mturner5 0:0d6b77c9ae01 3102 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3103 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 3104 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mturner5 0:0d6b77c9ae01 3105 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mturner5 0:0d6b77c9ae01 3106 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 3107 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mturner5 0:0d6b77c9ae01 3108 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
mturner5 0:0d6b77c9ae01 3109 uint8_t RESERVED_0[1];
mturner5 0:0d6b77c9ae01 3110 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 3111 uint8_t RESERVED_1[1];
mturner5 0:0d6b77c9ae01 3112 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mturner5 0:0d6b77c9ae01 3113 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mturner5 0:0d6b77c9ae01 3114 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 3115 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mturner5 0:0d6b77c9ae01 3116 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
mturner5 0:0d6b77c9ae01 3117 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
mturner5 0:0d6b77c9ae01 3118 } MCG_Type;
mturner5 0:0d6b77c9ae01 3119
mturner5 0:0d6b77c9ae01 3120 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3121 -- MCG Register Masks
mturner5 0:0d6b77c9ae01 3122 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3123
mturner5 0:0d6b77c9ae01 3124 /*!
mturner5 0:0d6b77c9ae01 3125 * @addtogroup MCG_Register_Masks MCG Register Masks
mturner5 0:0d6b77c9ae01 3126 * @{
mturner5 0:0d6b77c9ae01 3127 */
mturner5 0:0d6b77c9ae01 3128
mturner5 0:0d6b77c9ae01 3129 /* C1 Bit Fields */
mturner5 0:0d6b77c9ae01 3130 #define MCG_C1_IREFSTEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 3131 #define MCG_C1_IREFSTEN_SHIFT 0
mturner5 0:0d6b77c9ae01 3132 #define MCG_C1_IRCLKEN_MASK 0x2u
mturner5 0:0d6b77c9ae01 3133 #define MCG_C1_IRCLKEN_SHIFT 1
mturner5 0:0d6b77c9ae01 3134 #define MCG_C1_IREFS_MASK 0x4u
mturner5 0:0d6b77c9ae01 3135 #define MCG_C1_IREFS_SHIFT 2
mturner5 0:0d6b77c9ae01 3136 #define MCG_C1_FRDIV_MASK 0x38u
mturner5 0:0d6b77c9ae01 3137 #define MCG_C1_FRDIV_SHIFT 3
mturner5 0:0d6b77c9ae01 3138 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mturner5 0:0d6b77c9ae01 3139 #define MCG_C1_CLKS_MASK 0xC0u
mturner5 0:0d6b77c9ae01 3140 #define MCG_C1_CLKS_SHIFT 6
mturner5 0:0d6b77c9ae01 3141 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mturner5 0:0d6b77c9ae01 3142 /* C2 Bit Fields */
mturner5 0:0d6b77c9ae01 3143 #define MCG_C2_IRCS_MASK 0x1u
mturner5 0:0d6b77c9ae01 3144 #define MCG_C2_IRCS_SHIFT 0
mturner5 0:0d6b77c9ae01 3145 #define MCG_C2_LP_MASK 0x2u
mturner5 0:0d6b77c9ae01 3146 #define MCG_C2_LP_SHIFT 1
mturner5 0:0d6b77c9ae01 3147 #define MCG_C2_EREFS0_MASK 0x4u
mturner5 0:0d6b77c9ae01 3148 #define MCG_C2_EREFS0_SHIFT 2
mturner5 0:0d6b77c9ae01 3149 #define MCG_C2_HGO0_MASK 0x8u
mturner5 0:0d6b77c9ae01 3150 #define MCG_C2_HGO0_SHIFT 3
mturner5 0:0d6b77c9ae01 3151 #define MCG_C2_RANGE0_MASK 0x30u
mturner5 0:0d6b77c9ae01 3152 #define MCG_C2_RANGE0_SHIFT 4
mturner5 0:0d6b77c9ae01 3153 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
mturner5 0:0d6b77c9ae01 3154 #define MCG_C2_FCFTRIM_MASK 0x40u
mturner5 0:0d6b77c9ae01 3155 #define MCG_C2_FCFTRIM_SHIFT 6
mturner5 0:0d6b77c9ae01 3156 #define MCG_C2_LOCRE0_MASK 0x80u
mturner5 0:0d6b77c9ae01 3157 #define MCG_C2_LOCRE0_SHIFT 7
mturner5 0:0d6b77c9ae01 3158 /* C3 Bit Fields */
mturner5 0:0d6b77c9ae01 3159 #define MCG_C3_SCTRIM_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3160 #define MCG_C3_SCTRIM_SHIFT 0
mturner5 0:0d6b77c9ae01 3161 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mturner5 0:0d6b77c9ae01 3162 /* C4 Bit Fields */
mturner5 0:0d6b77c9ae01 3163 #define MCG_C4_SCFTRIM_MASK 0x1u
mturner5 0:0d6b77c9ae01 3164 #define MCG_C4_SCFTRIM_SHIFT 0
mturner5 0:0d6b77c9ae01 3165 #define MCG_C4_FCTRIM_MASK 0x1Eu
mturner5 0:0d6b77c9ae01 3166 #define MCG_C4_FCTRIM_SHIFT 1
mturner5 0:0d6b77c9ae01 3167 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mturner5 0:0d6b77c9ae01 3168 #define MCG_C4_DRST_DRS_MASK 0x60u
mturner5 0:0d6b77c9ae01 3169 #define MCG_C4_DRST_DRS_SHIFT 5
mturner5 0:0d6b77c9ae01 3170 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mturner5 0:0d6b77c9ae01 3171 #define MCG_C4_DMX32_MASK 0x80u
mturner5 0:0d6b77c9ae01 3172 #define MCG_C4_DMX32_SHIFT 7
mturner5 0:0d6b77c9ae01 3173 /* C5 Bit Fields */
mturner5 0:0d6b77c9ae01 3174 #define MCG_C5_PRDIV0_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 3175 #define MCG_C5_PRDIV0_SHIFT 0
mturner5 0:0d6b77c9ae01 3176 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
mturner5 0:0d6b77c9ae01 3177 #define MCG_C5_PLLSTEN0_MASK 0x20u
mturner5 0:0d6b77c9ae01 3178 #define MCG_C5_PLLSTEN0_SHIFT 5
mturner5 0:0d6b77c9ae01 3179 #define MCG_C5_PLLCLKEN0_MASK 0x40u
mturner5 0:0d6b77c9ae01 3180 #define MCG_C5_PLLCLKEN0_SHIFT 6
mturner5 0:0d6b77c9ae01 3181 /* C6 Bit Fields */
mturner5 0:0d6b77c9ae01 3182 #define MCG_C6_VDIV0_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 3183 #define MCG_C6_VDIV0_SHIFT 0
mturner5 0:0d6b77c9ae01 3184 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
mturner5 0:0d6b77c9ae01 3185 #define MCG_C6_CME0_MASK 0x20u
mturner5 0:0d6b77c9ae01 3186 #define MCG_C6_CME0_SHIFT 5
mturner5 0:0d6b77c9ae01 3187 #define MCG_C6_PLLS_MASK 0x40u
mturner5 0:0d6b77c9ae01 3188 #define MCG_C6_PLLS_SHIFT 6
mturner5 0:0d6b77c9ae01 3189 #define MCG_C6_LOLIE0_MASK 0x80u
mturner5 0:0d6b77c9ae01 3190 #define MCG_C6_LOLIE0_SHIFT 7
mturner5 0:0d6b77c9ae01 3191 /* S Bit Fields */
mturner5 0:0d6b77c9ae01 3192 #define MCG_S_IRCST_MASK 0x1u
mturner5 0:0d6b77c9ae01 3193 #define MCG_S_IRCST_SHIFT 0
mturner5 0:0d6b77c9ae01 3194 #define MCG_S_OSCINIT0_MASK 0x2u
mturner5 0:0d6b77c9ae01 3195 #define MCG_S_OSCINIT0_SHIFT 1
mturner5 0:0d6b77c9ae01 3196 #define MCG_S_CLKST_MASK 0xCu
mturner5 0:0d6b77c9ae01 3197 #define MCG_S_CLKST_SHIFT 2
mturner5 0:0d6b77c9ae01 3198 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mturner5 0:0d6b77c9ae01 3199 #define MCG_S_IREFST_MASK 0x10u
mturner5 0:0d6b77c9ae01 3200 #define MCG_S_IREFST_SHIFT 4
mturner5 0:0d6b77c9ae01 3201 #define MCG_S_PLLST_MASK 0x20u
mturner5 0:0d6b77c9ae01 3202 #define MCG_S_PLLST_SHIFT 5
mturner5 0:0d6b77c9ae01 3203 #define MCG_S_LOCK0_MASK 0x40u
mturner5 0:0d6b77c9ae01 3204 #define MCG_S_LOCK0_SHIFT 6
mturner5 0:0d6b77c9ae01 3205 #define MCG_S_LOLS_MASK 0x80u
mturner5 0:0d6b77c9ae01 3206 #define MCG_S_LOLS_SHIFT 7
mturner5 0:0d6b77c9ae01 3207 /* SC Bit Fields */
mturner5 0:0d6b77c9ae01 3208 #define MCG_SC_LOCS0_MASK 0x1u
mturner5 0:0d6b77c9ae01 3209 #define MCG_SC_LOCS0_SHIFT 0
mturner5 0:0d6b77c9ae01 3210 #define MCG_SC_FCRDIV_MASK 0xEu
mturner5 0:0d6b77c9ae01 3211 #define MCG_SC_FCRDIV_SHIFT 1
mturner5 0:0d6b77c9ae01 3212 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mturner5 0:0d6b77c9ae01 3213 #define MCG_SC_FLTPRSRV_MASK 0x10u
mturner5 0:0d6b77c9ae01 3214 #define MCG_SC_FLTPRSRV_SHIFT 4
mturner5 0:0d6b77c9ae01 3215 #define MCG_SC_ATMF_MASK 0x20u
mturner5 0:0d6b77c9ae01 3216 #define MCG_SC_ATMF_SHIFT 5
mturner5 0:0d6b77c9ae01 3217 #define MCG_SC_ATMS_MASK 0x40u
mturner5 0:0d6b77c9ae01 3218 #define MCG_SC_ATMS_SHIFT 6
mturner5 0:0d6b77c9ae01 3219 #define MCG_SC_ATME_MASK 0x80u
mturner5 0:0d6b77c9ae01 3220 #define MCG_SC_ATME_SHIFT 7
mturner5 0:0d6b77c9ae01 3221 /* ATCVH Bit Fields */
mturner5 0:0d6b77c9ae01 3222 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3223 #define MCG_ATCVH_ATCVH_SHIFT 0
mturner5 0:0d6b77c9ae01 3224 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mturner5 0:0d6b77c9ae01 3225 /* ATCVL Bit Fields */
mturner5 0:0d6b77c9ae01 3226 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3227 #define MCG_ATCVL_ATCVL_SHIFT 0
mturner5 0:0d6b77c9ae01 3228 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mturner5 0:0d6b77c9ae01 3229 /* C8 Bit Fields */
mturner5 0:0d6b77c9ae01 3230 #define MCG_C8_LOLRE_MASK 0x40u
mturner5 0:0d6b77c9ae01 3231 #define MCG_C8_LOLRE_SHIFT 6
mturner5 0:0d6b77c9ae01 3232
mturner5 0:0d6b77c9ae01 3233 /*!
mturner5 0:0d6b77c9ae01 3234 * @}
mturner5 0:0d6b77c9ae01 3235 */ /* end of group MCG_Register_Masks */
mturner5 0:0d6b77c9ae01 3236
mturner5 0:0d6b77c9ae01 3237
mturner5 0:0d6b77c9ae01 3238 /* MCG - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3239 /** Peripheral MCG base address */
mturner5 0:0d6b77c9ae01 3240 #define MCG_BASE (0x40064000u)
mturner5 0:0d6b77c9ae01 3241 /** Peripheral MCG base pointer */
mturner5 0:0d6b77c9ae01 3242 #define MCG ((MCG_Type *)MCG_BASE)
mturner5 0:0d6b77c9ae01 3243 /** Array initializer of MCG peripheral base pointers */
mturner5 0:0d6b77c9ae01 3244 #define MCG_BASES { MCG }
mturner5 0:0d6b77c9ae01 3245
mturner5 0:0d6b77c9ae01 3246 /*!
mturner5 0:0d6b77c9ae01 3247 * @}
mturner5 0:0d6b77c9ae01 3248 */ /* end of group MCG_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3249
mturner5 0:0d6b77c9ae01 3250
mturner5 0:0d6b77c9ae01 3251 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3252 -- MCM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3253 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3254
mturner5 0:0d6b77c9ae01 3255 /*!
mturner5 0:0d6b77c9ae01 3256 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3257 * @{
mturner5 0:0d6b77c9ae01 3258 */
mturner5 0:0d6b77c9ae01 3259
mturner5 0:0d6b77c9ae01 3260 /** MCM - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3261 typedef struct {
mturner5 0:0d6b77c9ae01 3262 uint8_t RESERVED_0[8];
mturner5 0:0d6b77c9ae01 3263 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mturner5 0:0d6b77c9ae01 3264 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mturner5 0:0d6b77c9ae01 3265 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 3266 uint8_t RESERVED_1[48];
mturner5 0:0d6b77c9ae01 3267 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
mturner5 0:0d6b77c9ae01 3268 } MCM_Type;
mturner5 0:0d6b77c9ae01 3269
mturner5 0:0d6b77c9ae01 3270 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3271 -- MCM Register Masks
mturner5 0:0d6b77c9ae01 3272 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3273
mturner5 0:0d6b77c9ae01 3274 /*!
mturner5 0:0d6b77c9ae01 3275 * @addtogroup MCM_Register_Masks MCM Register Masks
mturner5 0:0d6b77c9ae01 3276 * @{
mturner5 0:0d6b77c9ae01 3277 */
mturner5 0:0d6b77c9ae01 3278
mturner5 0:0d6b77c9ae01 3279 /* PLASC Bit Fields */
mturner5 0:0d6b77c9ae01 3280 #define MCM_PLASC_ASC_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3281 #define MCM_PLASC_ASC_SHIFT 0
mturner5 0:0d6b77c9ae01 3282 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mturner5 0:0d6b77c9ae01 3283 /* PLAMC Bit Fields */
mturner5 0:0d6b77c9ae01 3284 #define MCM_PLAMC_AMC_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3285 #define MCM_PLAMC_AMC_SHIFT 0
mturner5 0:0d6b77c9ae01 3286 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mturner5 0:0d6b77c9ae01 3287 /* PLACR Bit Fields */
mturner5 0:0d6b77c9ae01 3288 #define MCM_PLACR_ARB_MASK 0x200u
mturner5 0:0d6b77c9ae01 3289 #define MCM_PLACR_ARB_SHIFT 9
mturner5 0:0d6b77c9ae01 3290 #define MCM_PLACR_CFCC_MASK 0x400u
mturner5 0:0d6b77c9ae01 3291 #define MCM_PLACR_CFCC_SHIFT 10
mturner5 0:0d6b77c9ae01 3292 #define MCM_PLACR_DFCDA_MASK 0x800u
mturner5 0:0d6b77c9ae01 3293 #define MCM_PLACR_DFCDA_SHIFT 11
mturner5 0:0d6b77c9ae01 3294 #define MCM_PLACR_DFCIC_MASK 0x1000u
mturner5 0:0d6b77c9ae01 3295 #define MCM_PLACR_DFCIC_SHIFT 12
mturner5 0:0d6b77c9ae01 3296 #define MCM_PLACR_DFCC_MASK 0x2000u
mturner5 0:0d6b77c9ae01 3297 #define MCM_PLACR_DFCC_SHIFT 13
mturner5 0:0d6b77c9ae01 3298 #define MCM_PLACR_EFDS_MASK 0x4000u
mturner5 0:0d6b77c9ae01 3299 #define MCM_PLACR_EFDS_SHIFT 14
mturner5 0:0d6b77c9ae01 3300 #define MCM_PLACR_DFCS_MASK 0x8000u
mturner5 0:0d6b77c9ae01 3301 #define MCM_PLACR_DFCS_SHIFT 15
mturner5 0:0d6b77c9ae01 3302 #define MCM_PLACR_ESFC_MASK 0x10000u
mturner5 0:0d6b77c9ae01 3303 #define MCM_PLACR_ESFC_SHIFT 16
mturner5 0:0d6b77c9ae01 3304 /* CPO Bit Fields */
mturner5 0:0d6b77c9ae01 3305 #define MCM_CPO_CPOREQ_MASK 0x1u
mturner5 0:0d6b77c9ae01 3306 #define MCM_CPO_CPOREQ_SHIFT 0
mturner5 0:0d6b77c9ae01 3307 #define MCM_CPO_CPOACK_MASK 0x2u
mturner5 0:0d6b77c9ae01 3308 #define MCM_CPO_CPOACK_SHIFT 1
mturner5 0:0d6b77c9ae01 3309 #define MCM_CPO_CPOWOI_MASK 0x4u
mturner5 0:0d6b77c9ae01 3310 #define MCM_CPO_CPOWOI_SHIFT 2
mturner5 0:0d6b77c9ae01 3311
mturner5 0:0d6b77c9ae01 3312 /*!
mturner5 0:0d6b77c9ae01 3313 * @}
mturner5 0:0d6b77c9ae01 3314 */ /* end of group MCM_Register_Masks */
mturner5 0:0d6b77c9ae01 3315
mturner5 0:0d6b77c9ae01 3316
mturner5 0:0d6b77c9ae01 3317 /* MCM - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3318 /** Peripheral MCM base address */
mturner5 0:0d6b77c9ae01 3319 #define MCM_BASE (0xF0003000u)
mturner5 0:0d6b77c9ae01 3320 /** Peripheral MCM base pointer */
mturner5 0:0d6b77c9ae01 3321 #define MCM ((MCM_Type *)MCM_BASE)
mturner5 0:0d6b77c9ae01 3322 /** Array initializer of MCM peripheral base pointers */
mturner5 0:0d6b77c9ae01 3323 #define MCM_BASES { MCM }
mturner5 0:0d6b77c9ae01 3324
mturner5 0:0d6b77c9ae01 3325 /*!
mturner5 0:0d6b77c9ae01 3326 * @}
mturner5 0:0d6b77c9ae01 3327 */ /* end of group MCM_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3328
mturner5 0:0d6b77c9ae01 3329
mturner5 0:0d6b77c9ae01 3330 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3331 -- MTB Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3332 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3333
mturner5 0:0d6b77c9ae01 3334 /*!
mturner5 0:0d6b77c9ae01 3335 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3336 * @{
mturner5 0:0d6b77c9ae01 3337 */
mturner5 0:0d6b77c9ae01 3338
mturner5 0:0d6b77c9ae01 3339 /** MTB - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3340 typedef struct {
mturner5 0:0d6b77c9ae01 3341 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3342 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 3343 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 3344 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 3345 uint8_t RESERVED_0[3824];
mturner5 0:0d6b77c9ae01 3346 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
mturner5 0:0d6b77c9ae01 3347 uint8_t RESERVED_1[156];
mturner5 0:0d6b77c9ae01 3348 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
mturner5 0:0d6b77c9ae01 3349 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
mturner5 0:0d6b77c9ae01 3350 uint8_t RESERVED_2[8];
mturner5 0:0d6b77c9ae01 3351 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
mturner5 0:0d6b77c9ae01 3352 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
mturner5 0:0d6b77c9ae01 3353 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
mturner5 0:0d6b77c9ae01 3354 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
mturner5 0:0d6b77c9ae01 3355 uint8_t RESERVED_3[8];
mturner5 0:0d6b77c9ae01 3356 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mturner5 0:0d6b77c9ae01 3357 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mturner5 0:0d6b77c9ae01 3358 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 3359 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 3360 } MTB_Type;
mturner5 0:0d6b77c9ae01 3361
mturner5 0:0d6b77c9ae01 3362 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3363 -- MTB Register Masks
mturner5 0:0d6b77c9ae01 3364 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3365
mturner5 0:0d6b77c9ae01 3366 /*!
mturner5 0:0d6b77c9ae01 3367 * @addtogroup MTB_Register_Masks MTB Register Masks
mturner5 0:0d6b77c9ae01 3368 * @{
mturner5 0:0d6b77c9ae01 3369 */
mturner5 0:0d6b77c9ae01 3370
mturner5 0:0d6b77c9ae01 3371 /* POSITION Bit Fields */
mturner5 0:0d6b77c9ae01 3372 #define MTB_POSITION_WRAP_MASK 0x4u
mturner5 0:0d6b77c9ae01 3373 #define MTB_POSITION_WRAP_SHIFT 2
mturner5 0:0d6b77c9ae01 3374 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
mturner5 0:0d6b77c9ae01 3375 #define MTB_POSITION_POINTER_SHIFT 3
mturner5 0:0d6b77c9ae01 3376 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
mturner5 0:0d6b77c9ae01 3377 /* MASTER Bit Fields */
mturner5 0:0d6b77c9ae01 3378 #define MTB_MASTER_MASK_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 3379 #define MTB_MASTER_MASK_SHIFT 0
mturner5 0:0d6b77c9ae01 3380 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
mturner5 0:0d6b77c9ae01 3381 #define MTB_MASTER_TSTARTEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 3382 #define MTB_MASTER_TSTARTEN_SHIFT 5
mturner5 0:0d6b77c9ae01 3383 #define MTB_MASTER_TSTOPEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 3384 #define MTB_MASTER_TSTOPEN_SHIFT 6
mturner5 0:0d6b77c9ae01 3385 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
mturner5 0:0d6b77c9ae01 3386 #define MTB_MASTER_SFRWPRIV_SHIFT 7
mturner5 0:0d6b77c9ae01 3387 #define MTB_MASTER_RAMPRIV_MASK 0x100u
mturner5 0:0d6b77c9ae01 3388 #define MTB_MASTER_RAMPRIV_SHIFT 8
mturner5 0:0d6b77c9ae01 3389 #define MTB_MASTER_HALTREQ_MASK 0x200u
mturner5 0:0d6b77c9ae01 3390 #define MTB_MASTER_HALTREQ_SHIFT 9
mturner5 0:0d6b77c9ae01 3391 #define MTB_MASTER_EN_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 3392 #define MTB_MASTER_EN_SHIFT 31
mturner5 0:0d6b77c9ae01 3393 /* FLOW Bit Fields */
mturner5 0:0d6b77c9ae01 3394 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
mturner5 0:0d6b77c9ae01 3395 #define MTB_FLOW_AUTOSTOP_SHIFT 0
mturner5 0:0d6b77c9ae01 3396 #define MTB_FLOW_AUTOHALT_MASK 0x2u
mturner5 0:0d6b77c9ae01 3397 #define MTB_FLOW_AUTOHALT_SHIFT 1
mturner5 0:0d6b77c9ae01 3398 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
mturner5 0:0d6b77c9ae01 3399 #define MTB_FLOW_WATERMARK_SHIFT 3
mturner5 0:0d6b77c9ae01 3400 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
mturner5 0:0d6b77c9ae01 3401 /* BASE Bit Fields */
mturner5 0:0d6b77c9ae01 3402 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3403 #define MTB_BASE_BASEADDR_SHIFT 0
mturner5 0:0d6b77c9ae01 3404 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
mturner5 0:0d6b77c9ae01 3405 /* MODECTRL Bit Fields */
mturner5 0:0d6b77c9ae01 3406 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3407 #define MTB_MODECTRL_MODECTRL_SHIFT 0
mturner5 0:0d6b77c9ae01 3408 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
mturner5 0:0d6b77c9ae01 3409 /* TAGSET Bit Fields */
mturner5 0:0d6b77c9ae01 3410 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3411 #define MTB_TAGSET_TAGSET_SHIFT 0
mturner5 0:0d6b77c9ae01 3412 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
mturner5 0:0d6b77c9ae01 3413 /* TAGCLEAR Bit Fields */
mturner5 0:0d6b77c9ae01 3414 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3415 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
mturner5 0:0d6b77c9ae01 3416 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
mturner5 0:0d6b77c9ae01 3417 /* LOCKACCESS Bit Fields */
mturner5 0:0d6b77c9ae01 3418 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3419 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
mturner5 0:0d6b77c9ae01 3420 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
mturner5 0:0d6b77c9ae01 3421 /* LOCKSTAT Bit Fields */
mturner5 0:0d6b77c9ae01 3422 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3423 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
mturner5 0:0d6b77c9ae01 3424 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
mturner5 0:0d6b77c9ae01 3425 /* AUTHSTAT Bit Fields */
mturner5 0:0d6b77c9ae01 3426 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
mturner5 0:0d6b77c9ae01 3427 #define MTB_AUTHSTAT_BIT0_SHIFT 0
mturner5 0:0d6b77c9ae01 3428 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
mturner5 0:0d6b77c9ae01 3429 #define MTB_AUTHSTAT_BIT1_SHIFT 1
mturner5 0:0d6b77c9ae01 3430 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
mturner5 0:0d6b77c9ae01 3431 #define MTB_AUTHSTAT_BIT2_SHIFT 2
mturner5 0:0d6b77c9ae01 3432 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
mturner5 0:0d6b77c9ae01 3433 #define MTB_AUTHSTAT_BIT3_SHIFT 3
mturner5 0:0d6b77c9ae01 3434 /* DEVICEARCH Bit Fields */
mturner5 0:0d6b77c9ae01 3435 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3436 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
mturner5 0:0d6b77c9ae01 3437 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
mturner5 0:0d6b77c9ae01 3438 /* DEVICECFG Bit Fields */
mturner5 0:0d6b77c9ae01 3439 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3440 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
mturner5 0:0d6b77c9ae01 3441 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
mturner5 0:0d6b77c9ae01 3442 /* DEVICETYPID Bit Fields */
mturner5 0:0d6b77c9ae01 3443 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3444 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
mturner5 0:0d6b77c9ae01 3445 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
mturner5 0:0d6b77c9ae01 3446 /* PERIPHID Bit Fields */
mturner5 0:0d6b77c9ae01 3447 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3448 #define MTB_PERIPHID_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 3449 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 3450 /* COMPID Bit Fields */
mturner5 0:0d6b77c9ae01 3451 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3452 #define MTB_COMPID_COMPID_SHIFT 0
mturner5 0:0d6b77c9ae01 3453 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
mturner5 0:0d6b77c9ae01 3454
mturner5 0:0d6b77c9ae01 3455 /*!
mturner5 0:0d6b77c9ae01 3456 * @}
mturner5 0:0d6b77c9ae01 3457 */ /* end of group MTB_Register_Masks */
mturner5 0:0d6b77c9ae01 3458
mturner5 0:0d6b77c9ae01 3459
mturner5 0:0d6b77c9ae01 3460 /* MTB - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3461 /** Peripheral MTB base address */
mturner5 0:0d6b77c9ae01 3462 #define MTB_BASE (0xF0000000u)
mturner5 0:0d6b77c9ae01 3463 /** Peripheral MTB base pointer */
mturner5 0:0d6b77c9ae01 3464 #define MTB ((MTB_Type *)MTB_BASE)
mturner5 0:0d6b77c9ae01 3465 /** Array initializer of MTB peripheral base pointers */
mturner5 0:0d6b77c9ae01 3466 #define MTB_BASES { MTB }
mturner5 0:0d6b77c9ae01 3467
mturner5 0:0d6b77c9ae01 3468 /*!
mturner5 0:0d6b77c9ae01 3469 * @}
mturner5 0:0d6b77c9ae01 3470 */ /* end of group MTB_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3471
mturner5 0:0d6b77c9ae01 3472
mturner5 0:0d6b77c9ae01 3473 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3474 -- MTBDWT Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3475 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3476
mturner5 0:0d6b77c9ae01 3477 /*!
mturner5 0:0d6b77c9ae01 3478 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3479 * @{
mturner5 0:0d6b77c9ae01 3480 */
mturner5 0:0d6b77c9ae01 3481
mturner5 0:0d6b77c9ae01 3482 /** MTBDWT - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3483 typedef struct {
mturner5 0:0d6b77c9ae01 3484 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3485 uint8_t RESERVED_0[28];
mturner5 0:0d6b77c9ae01 3486 struct { /* offset: 0x20, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3487 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3488 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3489 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3490 uint8_t RESERVED_0[4];
mturner5 0:0d6b77c9ae01 3491 } COMPARATOR[2];
mturner5 0:0d6b77c9ae01 3492 uint8_t RESERVED_1[448];
mturner5 0:0d6b77c9ae01 3493 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
mturner5 0:0d6b77c9ae01 3494 uint8_t RESERVED_2[3524];
mturner5 0:0d6b77c9ae01 3495 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mturner5 0:0d6b77c9ae01 3496 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mturner5 0:0d6b77c9ae01 3497 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 3498 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 3499 } MTBDWT_Type;
mturner5 0:0d6b77c9ae01 3500
mturner5 0:0d6b77c9ae01 3501 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3502 -- MTBDWT Register Masks
mturner5 0:0d6b77c9ae01 3503 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3504
mturner5 0:0d6b77c9ae01 3505 /*!
mturner5 0:0d6b77c9ae01 3506 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
mturner5 0:0d6b77c9ae01 3507 * @{
mturner5 0:0d6b77c9ae01 3508 */
mturner5 0:0d6b77c9ae01 3509
mturner5 0:0d6b77c9ae01 3510 /* CTRL Bit Fields */
mturner5 0:0d6b77c9ae01 3511 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
mturner5 0:0d6b77c9ae01 3512 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
mturner5 0:0d6b77c9ae01 3513 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
mturner5 0:0d6b77c9ae01 3514 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
mturner5 0:0d6b77c9ae01 3515 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
mturner5 0:0d6b77c9ae01 3516 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
mturner5 0:0d6b77c9ae01 3517 /* COMP Bit Fields */
mturner5 0:0d6b77c9ae01 3518 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3519 #define MTBDWT_COMP_COMP_SHIFT 0
mturner5 0:0d6b77c9ae01 3520 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
mturner5 0:0d6b77c9ae01 3521 /* MASK Bit Fields */
mturner5 0:0d6b77c9ae01 3522 #define MTBDWT_MASK_MASK_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 3523 #define MTBDWT_MASK_MASK_SHIFT 0
mturner5 0:0d6b77c9ae01 3524 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
mturner5 0:0d6b77c9ae01 3525 /* FCT Bit Fields */
mturner5 0:0d6b77c9ae01 3526 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
mturner5 0:0d6b77c9ae01 3527 #define MTBDWT_FCT_FUNCTION_SHIFT 0
mturner5 0:0d6b77c9ae01 3528 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
mturner5 0:0d6b77c9ae01 3529 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
mturner5 0:0d6b77c9ae01 3530 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
mturner5 0:0d6b77c9ae01 3531 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
mturner5 0:0d6b77c9ae01 3532 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
mturner5 0:0d6b77c9ae01 3533 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
mturner5 0:0d6b77c9ae01 3534 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
mturner5 0:0d6b77c9ae01 3535 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
mturner5 0:0d6b77c9ae01 3536 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
mturner5 0:0d6b77c9ae01 3537 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 3538 #define MTBDWT_FCT_MATCHED_SHIFT 24
mturner5 0:0d6b77c9ae01 3539 /* TBCTRL Bit Fields */
mturner5 0:0d6b77c9ae01 3540 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
mturner5 0:0d6b77c9ae01 3541 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
mturner5 0:0d6b77c9ae01 3542 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
mturner5 0:0d6b77c9ae01 3543 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
mturner5 0:0d6b77c9ae01 3544 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
mturner5 0:0d6b77c9ae01 3545 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
mturner5 0:0d6b77c9ae01 3546 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
mturner5 0:0d6b77c9ae01 3547 /* DEVICECFG Bit Fields */
mturner5 0:0d6b77c9ae01 3548 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3549 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
mturner5 0:0d6b77c9ae01 3550 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
mturner5 0:0d6b77c9ae01 3551 /* DEVICETYPID Bit Fields */
mturner5 0:0d6b77c9ae01 3552 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3553 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
mturner5 0:0d6b77c9ae01 3554 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
mturner5 0:0d6b77c9ae01 3555 /* PERIPHID Bit Fields */
mturner5 0:0d6b77c9ae01 3556 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3557 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 3558 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 3559 /* COMPID Bit Fields */
mturner5 0:0d6b77c9ae01 3560 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3561 #define MTBDWT_COMPID_COMPID_SHIFT 0
mturner5 0:0d6b77c9ae01 3562 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
mturner5 0:0d6b77c9ae01 3563
mturner5 0:0d6b77c9ae01 3564 /*!
mturner5 0:0d6b77c9ae01 3565 * @}
mturner5 0:0d6b77c9ae01 3566 */ /* end of group MTBDWT_Register_Masks */
mturner5 0:0d6b77c9ae01 3567
mturner5 0:0d6b77c9ae01 3568
mturner5 0:0d6b77c9ae01 3569 /* MTBDWT - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3570 /** Peripheral MTBDWT base address */
mturner5 0:0d6b77c9ae01 3571 #define MTBDWT_BASE (0xF0001000u)
mturner5 0:0d6b77c9ae01 3572 /** Peripheral MTBDWT base pointer */
mturner5 0:0d6b77c9ae01 3573 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
mturner5 0:0d6b77c9ae01 3574 /** Array initializer of MTBDWT peripheral base pointers */
mturner5 0:0d6b77c9ae01 3575 #define MTBDWT_BASES { MTBDWT }
mturner5 0:0d6b77c9ae01 3576
mturner5 0:0d6b77c9ae01 3577 /*!
mturner5 0:0d6b77c9ae01 3578 * @}
mturner5 0:0d6b77c9ae01 3579 */ /* end of group MTBDWT_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3580
mturner5 0:0d6b77c9ae01 3581
mturner5 0:0d6b77c9ae01 3582 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3583 -- NV Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3584 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3585
mturner5 0:0d6b77c9ae01 3586 /*!
mturner5 0:0d6b77c9ae01 3587 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3588 * @{
mturner5 0:0d6b77c9ae01 3589 */
mturner5 0:0d6b77c9ae01 3590
mturner5 0:0d6b77c9ae01 3591 /** NV - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3592 typedef struct {
mturner5 0:0d6b77c9ae01 3593 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mturner5 0:0d6b77c9ae01 3594 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mturner5 0:0d6b77c9ae01 3595 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mturner5 0:0d6b77c9ae01 3596 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mturner5 0:0d6b77c9ae01 3597 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mturner5 0:0d6b77c9ae01 3598 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mturner5 0:0d6b77c9ae01 3599 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mturner5 0:0d6b77c9ae01 3600 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mturner5 0:0d6b77c9ae01 3601 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 3602 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mturner5 0:0d6b77c9ae01 3603 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mturner5 0:0d6b77c9ae01 3604 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mturner5 0:0d6b77c9ae01 3605 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 3606 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mturner5 0:0d6b77c9ae01 3607 } NV_Type;
mturner5 0:0d6b77c9ae01 3608
mturner5 0:0d6b77c9ae01 3609 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3610 -- NV Register Masks
mturner5 0:0d6b77c9ae01 3611 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3612
mturner5 0:0d6b77c9ae01 3613 /*!
mturner5 0:0d6b77c9ae01 3614 * @addtogroup NV_Register_Masks NV Register Masks
mturner5 0:0d6b77c9ae01 3615 * @{
mturner5 0:0d6b77c9ae01 3616 */
mturner5 0:0d6b77c9ae01 3617
mturner5 0:0d6b77c9ae01 3618 /* BACKKEY3 Bit Fields */
mturner5 0:0d6b77c9ae01 3619 #define NV_BACKKEY3_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3620 #define NV_BACKKEY3_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3621 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mturner5 0:0d6b77c9ae01 3622 /* BACKKEY2 Bit Fields */
mturner5 0:0d6b77c9ae01 3623 #define NV_BACKKEY2_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3624 #define NV_BACKKEY2_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3625 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mturner5 0:0d6b77c9ae01 3626 /* BACKKEY1 Bit Fields */
mturner5 0:0d6b77c9ae01 3627 #define NV_BACKKEY1_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3628 #define NV_BACKKEY1_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3629 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mturner5 0:0d6b77c9ae01 3630 /* BACKKEY0 Bit Fields */
mturner5 0:0d6b77c9ae01 3631 #define NV_BACKKEY0_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3632 #define NV_BACKKEY0_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3633 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mturner5 0:0d6b77c9ae01 3634 /* BACKKEY7 Bit Fields */
mturner5 0:0d6b77c9ae01 3635 #define NV_BACKKEY7_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3636 #define NV_BACKKEY7_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3637 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mturner5 0:0d6b77c9ae01 3638 /* BACKKEY6 Bit Fields */
mturner5 0:0d6b77c9ae01 3639 #define NV_BACKKEY6_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3640 #define NV_BACKKEY6_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3641 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mturner5 0:0d6b77c9ae01 3642 /* BACKKEY5 Bit Fields */
mturner5 0:0d6b77c9ae01 3643 #define NV_BACKKEY5_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3644 #define NV_BACKKEY5_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3645 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mturner5 0:0d6b77c9ae01 3646 /* BACKKEY4 Bit Fields */
mturner5 0:0d6b77c9ae01 3647 #define NV_BACKKEY4_KEY_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3648 #define NV_BACKKEY4_KEY_SHIFT 0
mturner5 0:0d6b77c9ae01 3649 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mturner5 0:0d6b77c9ae01 3650 /* FPROT3 Bit Fields */
mturner5 0:0d6b77c9ae01 3651 #define NV_FPROT3_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3652 #define NV_FPROT3_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 3653 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mturner5 0:0d6b77c9ae01 3654 /* FPROT2 Bit Fields */
mturner5 0:0d6b77c9ae01 3655 #define NV_FPROT2_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3656 #define NV_FPROT2_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 3657 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mturner5 0:0d6b77c9ae01 3658 /* FPROT1 Bit Fields */
mturner5 0:0d6b77c9ae01 3659 #define NV_FPROT1_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3660 #define NV_FPROT1_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 3661 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mturner5 0:0d6b77c9ae01 3662 /* FPROT0 Bit Fields */
mturner5 0:0d6b77c9ae01 3663 #define NV_FPROT0_PROT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 3664 #define NV_FPROT0_PROT_SHIFT 0
mturner5 0:0d6b77c9ae01 3665 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mturner5 0:0d6b77c9ae01 3666 /* FSEC Bit Fields */
mturner5 0:0d6b77c9ae01 3667 #define NV_FSEC_SEC_MASK 0x3u
mturner5 0:0d6b77c9ae01 3668 #define NV_FSEC_SEC_SHIFT 0
mturner5 0:0d6b77c9ae01 3669 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mturner5 0:0d6b77c9ae01 3670 #define NV_FSEC_FSLACC_MASK 0xCu
mturner5 0:0d6b77c9ae01 3671 #define NV_FSEC_FSLACC_SHIFT 2
mturner5 0:0d6b77c9ae01 3672 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mturner5 0:0d6b77c9ae01 3673 #define NV_FSEC_MEEN_MASK 0x30u
mturner5 0:0d6b77c9ae01 3674 #define NV_FSEC_MEEN_SHIFT 4
mturner5 0:0d6b77c9ae01 3675 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mturner5 0:0d6b77c9ae01 3676 #define NV_FSEC_KEYEN_MASK 0xC0u
mturner5 0:0d6b77c9ae01 3677 #define NV_FSEC_KEYEN_SHIFT 6
mturner5 0:0d6b77c9ae01 3678 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mturner5 0:0d6b77c9ae01 3679 /* FOPT Bit Fields */
mturner5 0:0d6b77c9ae01 3680 #define NV_FOPT_LPBOOT0_MASK 0x1u
mturner5 0:0d6b77c9ae01 3681 #define NV_FOPT_LPBOOT0_SHIFT 0
mturner5 0:0d6b77c9ae01 3682 #define NV_FOPT_NMI_DIS_MASK 0x4u
mturner5 0:0d6b77c9ae01 3683 #define NV_FOPT_NMI_DIS_SHIFT 2
mturner5 0:0d6b77c9ae01 3684 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
mturner5 0:0d6b77c9ae01 3685 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
mturner5 0:0d6b77c9ae01 3686 #define NV_FOPT_LPBOOT1_MASK 0x10u
mturner5 0:0d6b77c9ae01 3687 #define NV_FOPT_LPBOOT1_SHIFT 4
mturner5 0:0d6b77c9ae01 3688 #define NV_FOPT_FAST_INIT_MASK 0x20u
mturner5 0:0d6b77c9ae01 3689 #define NV_FOPT_FAST_INIT_SHIFT 5
mturner5 0:0d6b77c9ae01 3690
mturner5 0:0d6b77c9ae01 3691 /*!
mturner5 0:0d6b77c9ae01 3692 * @}
mturner5 0:0d6b77c9ae01 3693 */ /* end of group NV_Register_Masks */
mturner5 0:0d6b77c9ae01 3694
mturner5 0:0d6b77c9ae01 3695
mturner5 0:0d6b77c9ae01 3696 /* NV - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3697 /** Peripheral FTFA_FlashConfig base address */
mturner5 0:0d6b77c9ae01 3698 #define FTFA_FlashConfig_BASE (0x400u)
mturner5 0:0d6b77c9ae01 3699 /** Peripheral FTFA_FlashConfig base pointer */
mturner5 0:0d6b77c9ae01 3700 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
mturner5 0:0d6b77c9ae01 3701 /** Array initializer of NV peripheral base pointers */
mturner5 0:0d6b77c9ae01 3702 #define NV_BASES { FTFA_FlashConfig }
mturner5 0:0d6b77c9ae01 3703
mturner5 0:0d6b77c9ae01 3704 /*!
mturner5 0:0d6b77c9ae01 3705 * @}
mturner5 0:0d6b77c9ae01 3706 */ /* end of group NV_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3707
mturner5 0:0d6b77c9ae01 3708
mturner5 0:0d6b77c9ae01 3709 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3710 -- OSC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3711 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3712
mturner5 0:0d6b77c9ae01 3713 /*!
mturner5 0:0d6b77c9ae01 3714 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3715 * @{
mturner5 0:0d6b77c9ae01 3716 */
mturner5 0:0d6b77c9ae01 3717
mturner5 0:0d6b77c9ae01 3718 /** OSC - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3719 typedef struct {
mturner5 0:0d6b77c9ae01 3720 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3721 } OSC_Type;
mturner5 0:0d6b77c9ae01 3722
mturner5 0:0d6b77c9ae01 3723 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3724 -- OSC Register Masks
mturner5 0:0d6b77c9ae01 3725 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3726
mturner5 0:0d6b77c9ae01 3727 /*!
mturner5 0:0d6b77c9ae01 3728 * @addtogroup OSC_Register_Masks OSC Register Masks
mturner5 0:0d6b77c9ae01 3729 * @{
mturner5 0:0d6b77c9ae01 3730 */
mturner5 0:0d6b77c9ae01 3731
mturner5 0:0d6b77c9ae01 3732 /* CR Bit Fields */
mturner5 0:0d6b77c9ae01 3733 #define OSC_CR_SC16P_MASK 0x1u
mturner5 0:0d6b77c9ae01 3734 #define OSC_CR_SC16P_SHIFT 0
mturner5 0:0d6b77c9ae01 3735 #define OSC_CR_SC8P_MASK 0x2u
mturner5 0:0d6b77c9ae01 3736 #define OSC_CR_SC8P_SHIFT 1
mturner5 0:0d6b77c9ae01 3737 #define OSC_CR_SC4P_MASK 0x4u
mturner5 0:0d6b77c9ae01 3738 #define OSC_CR_SC4P_SHIFT 2
mturner5 0:0d6b77c9ae01 3739 #define OSC_CR_SC2P_MASK 0x8u
mturner5 0:0d6b77c9ae01 3740 #define OSC_CR_SC2P_SHIFT 3
mturner5 0:0d6b77c9ae01 3741 #define OSC_CR_EREFSTEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 3742 #define OSC_CR_EREFSTEN_SHIFT 5
mturner5 0:0d6b77c9ae01 3743 #define OSC_CR_ERCLKEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 3744 #define OSC_CR_ERCLKEN_SHIFT 7
mturner5 0:0d6b77c9ae01 3745
mturner5 0:0d6b77c9ae01 3746 /*!
mturner5 0:0d6b77c9ae01 3747 * @}
mturner5 0:0d6b77c9ae01 3748 */ /* end of group OSC_Register_Masks */
mturner5 0:0d6b77c9ae01 3749
mturner5 0:0d6b77c9ae01 3750
mturner5 0:0d6b77c9ae01 3751 /* OSC - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3752 /** Peripheral OSC0 base address */
mturner5 0:0d6b77c9ae01 3753 #define OSC0_BASE (0x40065000u)
mturner5 0:0d6b77c9ae01 3754 /** Peripheral OSC0 base pointer */
mturner5 0:0d6b77c9ae01 3755 #define OSC0 ((OSC_Type *)OSC0_BASE)
mturner5 0:0d6b77c9ae01 3756 /** Array initializer of OSC peripheral base pointers */
mturner5 0:0d6b77c9ae01 3757 #define OSC_BASES { OSC0 }
mturner5 0:0d6b77c9ae01 3758
mturner5 0:0d6b77c9ae01 3759 /*!
mturner5 0:0d6b77c9ae01 3760 * @}
mturner5 0:0d6b77c9ae01 3761 */ /* end of group OSC_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3762
mturner5 0:0d6b77c9ae01 3763
mturner5 0:0d6b77c9ae01 3764 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3765 -- PIT Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3766 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3767
mturner5 0:0d6b77c9ae01 3768 /*!
mturner5 0:0d6b77c9ae01 3769 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3770 * @{
mturner5 0:0d6b77c9ae01 3771 */
mturner5 0:0d6b77c9ae01 3772
mturner5 0:0d6b77c9ae01 3773 /** PIT - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3774 typedef struct {
mturner5 0:0d6b77c9ae01 3775 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3776 uint8_t RESERVED_0[220];
mturner5 0:0d6b77c9ae01 3777 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
mturner5 0:0d6b77c9ae01 3778 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
mturner5 0:0d6b77c9ae01 3779 uint8_t RESERVED_1[24];
mturner5 0:0d6b77c9ae01 3780 struct { /* offset: 0x100, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3781 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3782 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3783 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3784 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mturner5 0:0d6b77c9ae01 3785 } CHANNEL[2];
mturner5 0:0d6b77c9ae01 3786 } PIT_Type;
mturner5 0:0d6b77c9ae01 3787
mturner5 0:0d6b77c9ae01 3788 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3789 -- PIT Register Masks
mturner5 0:0d6b77c9ae01 3790 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3791
mturner5 0:0d6b77c9ae01 3792 /*!
mturner5 0:0d6b77c9ae01 3793 * @addtogroup PIT_Register_Masks PIT Register Masks
mturner5 0:0d6b77c9ae01 3794 * @{
mturner5 0:0d6b77c9ae01 3795 */
mturner5 0:0d6b77c9ae01 3796
mturner5 0:0d6b77c9ae01 3797 /* MCR Bit Fields */
mturner5 0:0d6b77c9ae01 3798 #define PIT_MCR_FRZ_MASK 0x1u
mturner5 0:0d6b77c9ae01 3799 #define PIT_MCR_FRZ_SHIFT 0
mturner5 0:0d6b77c9ae01 3800 #define PIT_MCR_MDIS_MASK 0x2u
mturner5 0:0d6b77c9ae01 3801 #define PIT_MCR_MDIS_SHIFT 1
mturner5 0:0d6b77c9ae01 3802 /* LTMR64H Bit Fields */
mturner5 0:0d6b77c9ae01 3803 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3804 #define PIT_LTMR64H_LTH_SHIFT 0
mturner5 0:0d6b77c9ae01 3805 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
mturner5 0:0d6b77c9ae01 3806 /* LTMR64L Bit Fields */
mturner5 0:0d6b77c9ae01 3807 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3808 #define PIT_LTMR64L_LTL_SHIFT 0
mturner5 0:0d6b77c9ae01 3809 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
mturner5 0:0d6b77c9ae01 3810 /* LDVAL Bit Fields */
mturner5 0:0d6b77c9ae01 3811 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3812 #define PIT_LDVAL_TSV_SHIFT 0
mturner5 0:0d6b77c9ae01 3813 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mturner5 0:0d6b77c9ae01 3814 /* CVAL Bit Fields */
mturner5 0:0d6b77c9ae01 3815 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3816 #define PIT_CVAL_TVL_SHIFT 0
mturner5 0:0d6b77c9ae01 3817 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mturner5 0:0d6b77c9ae01 3818 /* TCTRL Bit Fields */
mturner5 0:0d6b77c9ae01 3819 #define PIT_TCTRL_TEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 3820 #define PIT_TCTRL_TEN_SHIFT 0
mturner5 0:0d6b77c9ae01 3821 #define PIT_TCTRL_TIE_MASK 0x2u
mturner5 0:0d6b77c9ae01 3822 #define PIT_TCTRL_TIE_SHIFT 1
mturner5 0:0d6b77c9ae01 3823 #define PIT_TCTRL_CHN_MASK 0x4u
mturner5 0:0d6b77c9ae01 3824 #define PIT_TCTRL_CHN_SHIFT 2
mturner5 0:0d6b77c9ae01 3825 /* TFLG Bit Fields */
mturner5 0:0d6b77c9ae01 3826 #define PIT_TFLG_TIF_MASK 0x1u
mturner5 0:0d6b77c9ae01 3827 #define PIT_TFLG_TIF_SHIFT 0
mturner5 0:0d6b77c9ae01 3828
mturner5 0:0d6b77c9ae01 3829 /*!
mturner5 0:0d6b77c9ae01 3830 * @}
mturner5 0:0d6b77c9ae01 3831 */ /* end of group PIT_Register_Masks */
mturner5 0:0d6b77c9ae01 3832
mturner5 0:0d6b77c9ae01 3833
mturner5 0:0d6b77c9ae01 3834 /* PIT - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3835 /** Peripheral PIT base address */
mturner5 0:0d6b77c9ae01 3836 #define PIT_BASE (0x40037000u)
mturner5 0:0d6b77c9ae01 3837 /** Peripheral PIT base pointer */
mturner5 0:0d6b77c9ae01 3838 #define PIT ((PIT_Type *)PIT_BASE)
mturner5 0:0d6b77c9ae01 3839 /** Array initializer of PIT peripheral base pointers */
mturner5 0:0d6b77c9ae01 3840 #define PIT_BASES { PIT }
mturner5 0:0d6b77c9ae01 3841
mturner5 0:0d6b77c9ae01 3842 /*!
mturner5 0:0d6b77c9ae01 3843 * @}
mturner5 0:0d6b77c9ae01 3844 */ /* end of group PIT_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3845
mturner5 0:0d6b77c9ae01 3846
mturner5 0:0d6b77c9ae01 3847 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3848 -- PMC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3849 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3850
mturner5 0:0d6b77c9ae01 3851 /*!
mturner5 0:0d6b77c9ae01 3852 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3853 * @{
mturner5 0:0d6b77c9ae01 3854 */
mturner5 0:0d6b77c9ae01 3855
mturner5 0:0d6b77c9ae01 3856 /** PMC - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3857 typedef struct {
mturner5 0:0d6b77c9ae01 3858 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 3859 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 3860 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mturner5 0:0d6b77c9ae01 3861 } PMC_Type;
mturner5 0:0d6b77c9ae01 3862
mturner5 0:0d6b77c9ae01 3863 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3864 -- PMC Register Masks
mturner5 0:0d6b77c9ae01 3865 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3866
mturner5 0:0d6b77c9ae01 3867 /*!
mturner5 0:0d6b77c9ae01 3868 * @addtogroup PMC_Register_Masks PMC Register Masks
mturner5 0:0d6b77c9ae01 3869 * @{
mturner5 0:0d6b77c9ae01 3870 */
mturner5 0:0d6b77c9ae01 3871
mturner5 0:0d6b77c9ae01 3872 /* LVDSC1 Bit Fields */
mturner5 0:0d6b77c9ae01 3873 #define PMC_LVDSC1_LVDV_MASK 0x3u
mturner5 0:0d6b77c9ae01 3874 #define PMC_LVDSC1_LVDV_SHIFT 0
mturner5 0:0d6b77c9ae01 3875 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mturner5 0:0d6b77c9ae01 3876 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mturner5 0:0d6b77c9ae01 3877 #define PMC_LVDSC1_LVDRE_SHIFT 4
mturner5 0:0d6b77c9ae01 3878 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mturner5 0:0d6b77c9ae01 3879 #define PMC_LVDSC1_LVDIE_SHIFT 5
mturner5 0:0d6b77c9ae01 3880 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mturner5 0:0d6b77c9ae01 3881 #define PMC_LVDSC1_LVDACK_SHIFT 6
mturner5 0:0d6b77c9ae01 3882 #define PMC_LVDSC1_LVDF_MASK 0x80u
mturner5 0:0d6b77c9ae01 3883 #define PMC_LVDSC1_LVDF_SHIFT 7
mturner5 0:0d6b77c9ae01 3884 /* LVDSC2 Bit Fields */
mturner5 0:0d6b77c9ae01 3885 #define PMC_LVDSC2_LVWV_MASK 0x3u
mturner5 0:0d6b77c9ae01 3886 #define PMC_LVDSC2_LVWV_SHIFT 0
mturner5 0:0d6b77c9ae01 3887 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mturner5 0:0d6b77c9ae01 3888 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mturner5 0:0d6b77c9ae01 3889 #define PMC_LVDSC2_LVWIE_SHIFT 5
mturner5 0:0d6b77c9ae01 3890 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mturner5 0:0d6b77c9ae01 3891 #define PMC_LVDSC2_LVWACK_SHIFT 6
mturner5 0:0d6b77c9ae01 3892 #define PMC_LVDSC2_LVWF_MASK 0x80u
mturner5 0:0d6b77c9ae01 3893 #define PMC_LVDSC2_LVWF_SHIFT 7
mturner5 0:0d6b77c9ae01 3894 /* REGSC Bit Fields */
mturner5 0:0d6b77c9ae01 3895 #define PMC_REGSC_BGBE_MASK 0x1u
mturner5 0:0d6b77c9ae01 3896 #define PMC_REGSC_BGBE_SHIFT 0
mturner5 0:0d6b77c9ae01 3897 #define PMC_REGSC_REGONS_MASK 0x4u
mturner5 0:0d6b77c9ae01 3898 #define PMC_REGSC_REGONS_SHIFT 2
mturner5 0:0d6b77c9ae01 3899 #define PMC_REGSC_ACKISO_MASK 0x8u
mturner5 0:0d6b77c9ae01 3900 #define PMC_REGSC_ACKISO_SHIFT 3
mturner5 0:0d6b77c9ae01 3901 #define PMC_REGSC_BGEN_MASK 0x10u
mturner5 0:0d6b77c9ae01 3902 #define PMC_REGSC_BGEN_SHIFT 4
mturner5 0:0d6b77c9ae01 3903
mturner5 0:0d6b77c9ae01 3904 /*!
mturner5 0:0d6b77c9ae01 3905 * @}
mturner5 0:0d6b77c9ae01 3906 */ /* end of group PMC_Register_Masks */
mturner5 0:0d6b77c9ae01 3907
mturner5 0:0d6b77c9ae01 3908
mturner5 0:0d6b77c9ae01 3909 /* PMC - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3910 /** Peripheral PMC base address */
mturner5 0:0d6b77c9ae01 3911 #define PMC_BASE (0x4007D000u)
mturner5 0:0d6b77c9ae01 3912 /** Peripheral PMC base pointer */
mturner5 0:0d6b77c9ae01 3913 #define PMC ((PMC_Type *)PMC_BASE)
mturner5 0:0d6b77c9ae01 3914 /** Array initializer of PMC peripheral base pointers */
mturner5 0:0d6b77c9ae01 3915 #define PMC_BASES { PMC }
mturner5 0:0d6b77c9ae01 3916
mturner5 0:0d6b77c9ae01 3917 /*!
mturner5 0:0d6b77c9ae01 3918 * @}
mturner5 0:0d6b77c9ae01 3919 */ /* end of group PMC_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 3920
mturner5 0:0d6b77c9ae01 3921
mturner5 0:0d6b77c9ae01 3922 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3923 -- PORT Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3924 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3925
mturner5 0:0d6b77c9ae01 3926 /*!
mturner5 0:0d6b77c9ae01 3927 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mturner5 0:0d6b77c9ae01 3928 * @{
mturner5 0:0d6b77c9ae01 3929 */
mturner5 0:0d6b77c9ae01 3930
mturner5 0:0d6b77c9ae01 3931 /** PORT - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 3932 typedef struct {
mturner5 0:0d6b77c9ae01 3933 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 3934 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mturner5 0:0d6b77c9ae01 3935 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mturner5 0:0d6b77c9ae01 3936 uint8_t RESERVED_0[24];
mturner5 0:0d6b77c9ae01 3937 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mturner5 0:0d6b77c9ae01 3938 } PORT_Type;
mturner5 0:0d6b77c9ae01 3939
mturner5 0:0d6b77c9ae01 3940 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 3941 -- PORT Register Masks
mturner5 0:0d6b77c9ae01 3942 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 3943
mturner5 0:0d6b77c9ae01 3944 /*!
mturner5 0:0d6b77c9ae01 3945 * @addtogroup PORT_Register_Masks PORT Register Masks
mturner5 0:0d6b77c9ae01 3946 * @{
mturner5 0:0d6b77c9ae01 3947 */
mturner5 0:0d6b77c9ae01 3948
mturner5 0:0d6b77c9ae01 3949 /* PCR Bit Fields */
mturner5 0:0d6b77c9ae01 3950 #define PORT_PCR_PS_MASK 0x1u
mturner5 0:0d6b77c9ae01 3951 #define PORT_PCR_PS_SHIFT 0
mturner5 0:0d6b77c9ae01 3952 #define PORT_PCR_PE_MASK 0x2u
mturner5 0:0d6b77c9ae01 3953 #define PORT_PCR_PE_SHIFT 1
mturner5 0:0d6b77c9ae01 3954 #define PORT_PCR_SRE_MASK 0x4u
mturner5 0:0d6b77c9ae01 3955 #define PORT_PCR_SRE_SHIFT 2
mturner5 0:0d6b77c9ae01 3956 #define PORT_PCR_PFE_MASK 0x10u
mturner5 0:0d6b77c9ae01 3957 #define PORT_PCR_PFE_SHIFT 4
mturner5 0:0d6b77c9ae01 3958 #define PORT_PCR_DSE_MASK 0x40u
mturner5 0:0d6b77c9ae01 3959 #define PORT_PCR_DSE_SHIFT 6
mturner5 0:0d6b77c9ae01 3960 #define PORT_PCR_MUX_MASK 0x700u
mturner5 0:0d6b77c9ae01 3961 #define PORT_PCR_MUX_SHIFT 8
mturner5 0:0d6b77c9ae01 3962 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mturner5 0:0d6b77c9ae01 3963 #define PORT_PCR_IRQC_MASK 0xF0000u
mturner5 0:0d6b77c9ae01 3964 #define PORT_PCR_IRQC_SHIFT 16
mturner5 0:0d6b77c9ae01 3965 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mturner5 0:0d6b77c9ae01 3966 #define PORT_PCR_ISF_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 3967 #define PORT_PCR_ISF_SHIFT 24
mturner5 0:0d6b77c9ae01 3968 /* GPCLR Bit Fields */
mturner5 0:0d6b77c9ae01 3969 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 3970 #define PORT_GPCLR_GPWD_SHIFT 0
mturner5 0:0d6b77c9ae01 3971 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mturner5 0:0d6b77c9ae01 3972 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mturner5 0:0d6b77c9ae01 3973 #define PORT_GPCLR_GPWE_SHIFT 16
mturner5 0:0d6b77c9ae01 3974 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mturner5 0:0d6b77c9ae01 3975 /* GPCHR Bit Fields */
mturner5 0:0d6b77c9ae01 3976 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 3977 #define PORT_GPCHR_GPWD_SHIFT 0
mturner5 0:0d6b77c9ae01 3978 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mturner5 0:0d6b77c9ae01 3979 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mturner5 0:0d6b77c9ae01 3980 #define PORT_GPCHR_GPWE_SHIFT 16
mturner5 0:0d6b77c9ae01 3981 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mturner5 0:0d6b77c9ae01 3982 /* ISFR Bit Fields */
mturner5 0:0d6b77c9ae01 3983 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 3984 #define PORT_ISFR_ISF_SHIFT 0
mturner5 0:0d6b77c9ae01 3985 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mturner5 0:0d6b77c9ae01 3986
mturner5 0:0d6b77c9ae01 3987 /*!
mturner5 0:0d6b77c9ae01 3988 * @}
mturner5 0:0d6b77c9ae01 3989 */ /* end of group PORT_Register_Masks */
mturner5 0:0d6b77c9ae01 3990
mturner5 0:0d6b77c9ae01 3991
mturner5 0:0d6b77c9ae01 3992 /* PORT - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 3993 /** Peripheral PORTA base address */
mturner5 0:0d6b77c9ae01 3994 #define PORTA_BASE (0x40049000u)
mturner5 0:0d6b77c9ae01 3995 /** Peripheral PORTA base pointer */
mturner5 0:0d6b77c9ae01 3996 #define PORTA ((PORT_Type *)PORTA_BASE)
mturner5 0:0d6b77c9ae01 3997 /** Peripheral PORTB base address */
mturner5 0:0d6b77c9ae01 3998 #define PORTB_BASE (0x4004A000u)
mturner5 0:0d6b77c9ae01 3999 /** Peripheral PORTB base pointer */
mturner5 0:0d6b77c9ae01 4000 #define PORTB ((PORT_Type *)PORTB_BASE)
mturner5 0:0d6b77c9ae01 4001 /** Peripheral PORTC base address */
mturner5 0:0d6b77c9ae01 4002 #define PORTC_BASE (0x4004B000u)
mturner5 0:0d6b77c9ae01 4003 /** Peripheral PORTC base pointer */
mturner5 0:0d6b77c9ae01 4004 #define PORTC ((PORT_Type *)PORTC_BASE)
mturner5 0:0d6b77c9ae01 4005 /** Peripheral PORTD base address */
mturner5 0:0d6b77c9ae01 4006 #define PORTD_BASE (0x4004C000u)
mturner5 0:0d6b77c9ae01 4007 /** Peripheral PORTD base pointer */
mturner5 0:0d6b77c9ae01 4008 #define PORTD ((PORT_Type *)PORTD_BASE)
mturner5 0:0d6b77c9ae01 4009 /** Peripheral PORTE base address */
mturner5 0:0d6b77c9ae01 4010 #define PORTE_BASE (0x4004D000u)
mturner5 0:0d6b77c9ae01 4011 /** Peripheral PORTE base pointer */
mturner5 0:0d6b77c9ae01 4012 #define PORTE ((PORT_Type *)PORTE_BASE)
mturner5 0:0d6b77c9ae01 4013 /** Array initializer of PORT peripheral base pointers */
mturner5 0:0d6b77c9ae01 4014 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
mturner5 0:0d6b77c9ae01 4015
mturner5 0:0d6b77c9ae01 4016 /*!
mturner5 0:0d6b77c9ae01 4017 * @}
mturner5 0:0d6b77c9ae01 4018 */ /* end of group PORT_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4019
mturner5 0:0d6b77c9ae01 4020
mturner5 0:0d6b77c9ae01 4021 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4022 -- RCM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4023 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4024
mturner5 0:0d6b77c9ae01 4025 /*!
mturner5 0:0d6b77c9ae01 4026 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4027 * @{
mturner5 0:0d6b77c9ae01 4028 */
mturner5 0:0d6b77c9ae01 4029
mturner5 0:0d6b77c9ae01 4030 /** RCM - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4031 typedef struct {
mturner5 0:0d6b77c9ae01 4032 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4033 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mturner5 0:0d6b77c9ae01 4034 uint8_t RESERVED_0[2];
mturner5 0:0d6b77c9ae01 4035 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 4036 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mturner5 0:0d6b77c9ae01 4037 } RCM_Type;
mturner5 0:0d6b77c9ae01 4038
mturner5 0:0d6b77c9ae01 4039 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4040 -- RCM Register Masks
mturner5 0:0d6b77c9ae01 4041 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4042
mturner5 0:0d6b77c9ae01 4043 /*!
mturner5 0:0d6b77c9ae01 4044 * @addtogroup RCM_Register_Masks RCM Register Masks
mturner5 0:0d6b77c9ae01 4045 * @{
mturner5 0:0d6b77c9ae01 4046 */
mturner5 0:0d6b77c9ae01 4047
mturner5 0:0d6b77c9ae01 4048 /* SRS0 Bit Fields */
mturner5 0:0d6b77c9ae01 4049 #define RCM_SRS0_WAKEUP_MASK 0x1u
mturner5 0:0d6b77c9ae01 4050 #define RCM_SRS0_WAKEUP_SHIFT 0
mturner5 0:0d6b77c9ae01 4051 #define RCM_SRS0_LVD_MASK 0x2u
mturner5 0:0d6b77c9ae01 4052 #define RCM_SRS0_LVD_SHIFT 1
mturner5 0:0d6b77c9ae01 4053 #define RCM_SRS0_LOC_MASK 0x4u
mturner5 0:0d6b77c9ae01 4054 #define RCM_SRS0_LOC_SHIFT 2
mturner5 0:0d6b77c9ae01 4055 #define RCM_SRS0_LOL_MASK 0x8u
mturner5 0:0d6b77c9ae01 4056 #define RCM_SRS0_LOL_SHIFT 3
mturner5 0:0d6b77c9ae01 4057 #define RCM_SRS0_WDOG_MASK 0x20u
mturner5 0:0d6b77c9ae01 4058 #define RCM_SRS0_WDOG_SHIFT 5
mturner5 0:0d6b77c9ae01 4059 #define RCM_SRS0_PIN_MASK 0x40u
mturner5 0:0d6b77c9ae01 4060 #define RCM_SRS0_PIN_SHIFT 6
mturner5 0:0d6b77c9ae01 4061 #define RCM_SRS0_POR_MASK 0x80u
mturner5 0:0d6b77c9ae01 4062 #define RCM_SRS0_POR_SHIFT 7
mturner5 0:0d6b77c9ae01 4063 /* SRS1 Bit Fields */
mturner5 0:0d6b77c9ae01 4064 #define RCM_SRS1_LOCKUP_MASK 0x2u
mturner5 0:0d6b77c9ae01 4065 #define RCM_SRS1_LOCKUP_SHIFT 1
mturner5 0:0d6b77c9ae01 4066 #define RCM_SRS1_SW_MASK 0x4u
mturner5 0:0d6b77c9ae01 4067 #define RCM_SRS1_SW_SHIFT 2
mturner5 0:0d6b77c9ae01 4068 #define RCM_SRS1_MDM_AP_MASK 0x8u
mturner5 0:0d6b77c9ae01 4069 #define RCM_SRS1_MDM_AP_SHIFT 3
mturner5 0:0d6b77c9ae01 4070 #define RCM_SRS1_SACKERR_MASK 0x20u
mturner5 0:0d6b77c9ae01 4071 #define RCM_SRS1_SACKERR_SHIFT 5
mturner5 0:0d6b77c9ae01 4072 /* RPFC Bit Fields */
mturner5 0:0d6b77c9ae01 4073 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mturner5 0:0d6b77c9ae01 4074 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mturner5 0:0d6b77c9ae01 4075 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mturner5 0:0d6b77c9ae01 4076 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mturner5 0:0d6b77c9ae01 4077 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mturner5 0:0d6b77c9ae01 4078 /* RPFW Bit Fields */
mturner5 0:0d6b77c9ae01 4079 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 4080 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 4081 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mturner5 0:0d6b77c9ae01 4082
mturner5 0:0d6b77c9ae01 4083 /*!
mturner5 0:0d6b77c9ae01 4084 * @}
mturner5 0:0d6b77c9ae01 4085 */ /* end of group RCM_Register_Masks */
mturner5 0:0d6b77c9ae01 4086
mturner5 0:0d6b77c9ae01 4087
mturner5 0:0d6b77c9ae01 4088 /* RCM - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4089 /** Peripheral RCM base address */
mturner5 0:0d6b77c9ae01 4090 #define RCM_BASE (0x4007F000u)
mturner5 0:0d6b77c9ae01 4091 /** Peripheral RCM base pointer */
mturner5 0:0d6b77c9ae01 4092 #define RCM ((RCM_Type *)RCM_BASE)
mturner5 0:0d6b77c9ae01 4093 /** Array initializer of RCM peripheral base pointers */
mturner5 0:0d6b77c9ae01 4094 #define RCM_BASES { RCM }
mturner5 0:0d6b77c9ae01 4095
mturner5 0:0d6b77c9ae01 4096 /*!
mturner5 0:0d6b77c9ae01 4097 * @}
mturner5 0:0d6b77c9ae01 4098 */ /* end of group RCM_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4099
mturner5 0:0d6b77c9ae01 4100
mturner5 0:0d6b77c9ae01 4101 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4102 -- ROM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4103 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4104
mturner5 0:0d6b77c9ae01 4105 /*!
mturner5 0:0d6b77c9ae01 4106 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4107 * @{
mturner5 0:0d6b77c9ae01 4108 */
mturner5 0:0d6b77c9ae01 4109
mturner5 0:0d6b77c9ae01 4110 /** ROM - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4111 typedef struct {
mturner5 0:0d6b77c9ae01 4112 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 4113 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 4114 uint8_t RESERVED_0[4028];
mturner5 0:0d6b77c9ae01 4115 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
mturner5 0:0d6b77c9ae01 4116 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
mturner5 0:0d6b77c9ae01 4117 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
mturner5 0:0d6b77c9ae01 4118 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
mturner5 0:0d6b77c9ae01 4119 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
mturner5 0:0d6b77c9ae01 4120 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
mturner5 0:0d6b77c9ae01 4121 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
mturner5 0:0d6b77c9ae01 4122 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
mturner5 0:0d6b77c9ae01 4123 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
mturner5 0:0d6b77c9ae01 4124 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 4125 } ROM_Type;
mturner5 0:0d6b77c9ae01 4126
mturner5 0:0d6b77c9ae01 4127 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4128 -- ROM Register Masks
mturner5 0:0d6b77c9ae01 4129 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4130
mturner5 0:0d6b77c9ae01 4131 /*!
mturner5 0:0d6b77c9ae01 4132 * @addtogroup ROM_Register_Masks ROM Register Masks
mturner5 0:0d6b77c9ae01 4133 * @{
mturner5 0:0d6b77c9ae01 4134 */
mturner5 0:0d6b77c9ae01 4135
mturner5 0:0d6b77c9ae01 4136 /* ENTRY Bit Fields */
mturner5 0:0d6b77c9ae01 4137 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4138 #define ROM_ENTRY_ENTRY_SHIFT 0
mturner5 0:0d6b77c9ae01 4139 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
mturner5 0:0d6b77c9ae01 4140 /* TABLEMARK Bit Fields */
mturner5 0:0d6b77c9ae01 4141 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4142 #define ROM_TABLEMARK_MARK_SHIFT 0
mturner5 0:0d6b77c9ae01 4143 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
mturner5 0:0d6b77c9ae01 4144 /* SYSACCESS Bit Fields */
mturner5 0:0d6b77c9ae01 4145 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4146 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
mturner5 0:0d6b77c9ae01 4147 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
mturner5 0:0d6b77c9ae01 4148 /* PERIPHID4 Bit Fields */
mturner5 0:0d6b77c9ae01 4149 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4150 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4151 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4152 /* PERIPHID5 Bit Fields */
mturner5 0:0d6b77c9ae01 4153 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4154 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4155 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4156 /* PERIPHID6 Bit Fields */
mturner5 0:0d6b77c9ae01 4157 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4158 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4159 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4160 /* PERIPHID7 Bit Fields */
mturner5 0:0d6b77c9ae01 4161 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4162 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4163 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4164 /* PERIPHID0 Bit Fields */
mturner5 0:0d6b77c9ae01 4165 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4166 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4167 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4168 /* PERIPHID1 Bit Fields */
mturner5 0:0d6b77c9ae01 4169 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4170 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4171 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4172 /* PERIPHID2 Bit Fields */
mturner5 0:0d6b77c9ae01 4173 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4174 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4175 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4176 /* PERIPHID3 Bit Fields */
mturner5 0:0d6b77c9ae01 4177 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4178 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
mturner5 0:0d6b77c9ae01 4179 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
mturner5 0:0d6b77c9ae01 4180 /* COMPID Bit Fields */
mturner5 0:0d6b77c9ae01 4181 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4182 #define ROM_COMPID_COMPID_SHIFT 0
mturner5 0:0d6b77c9ae01 4183 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
mturner5 0:0d6b77c9ae01 4184
mturner5 0:0d6b77c9ae01 4185 /*!
mturner5 0:0d6b77c9ae01 4186 * @}
mturner5 0:0d6b77c9ae01 4187 */ /* end of group ROM_Register_Masks */
mturner5 0:0d6b77c9ae01 4188
mturner5 0:0d6b77c9ae01 4189
mturner5 0:0d6b77c9ae01 4190 /* ROM - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4191 /** Peripheral ROM base address */
mturner5 0:0d6b77c9ae01 4192 #define ROM_BASE (0xF0002000u)
mturner5 0:0d6b77c9ae01 4193 /** Peripheral ROM base pointer */
mturner5 0:0d6b77c9ae01 4194 #define ROM ((ROM_Type *)ROM_BASE)
mturner5 0:0d6b77c9ae01 4195 /** Array initializer of ROM peripheral base pointers */
mturner5 0:0d6b77c9ae01 4196 #define ROM_BASES { ROM }
mturner5 0:0d6b77c9ae01 4197
mturner5 0:0d6b77c9ae01 4198 /*!
mturner5 0:0d6b77c9ae01 4199 * @}
mturner5 0:0d6b77c9ae01 4200 */ /* end of group ROM_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4201
mturner5 0:0d6b77c9ae01 4202
mturner5 0:0d6b77c9ae01 4203 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4204 -- RTC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4205 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4206
mturner5 0:0d6b77c9ae01 4207 /*!
mturner5 0:0d6b77c9ae01 4208 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4209 * @{
mturner5 0:0d6b77c9ae01 4210 */
mturner5 0:0d6b77c9ae01 4211
mturner5 0:0d6b77c9ae01 4212 /** RTC - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4213 typedef struct {
mturner5 0:0d6b77c9ae01 4214 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4215 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 4216 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 4217 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mturner5 0:0d6b77c9ae01 4218 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mturner5 0:0d6b77c9ae01 4219 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mturner5 0:0d6b77c9ae01 4220 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mturner5 0:0d6b77c9ae01 4221 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mturner5 0:0d6b77c9ae01 4222 } RTC_Type;
mturner5 0:0d6b77c9ae01 4223
mturner5 0:0d6b77c9ae01 4224 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4225 -- RTC Register Masks
mturner5 0:0d6b77c9ae01 4226 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4227
mturner5 0:0d6b77c9ae01 4228 /*!
mturner5 0:0d6b77c9ae01 4229 * @addtogroup RTC_Register_Masks RTC Register Masks
mturner5 0:0d6b77c9ae01 4230 * @{
mturner5 0:0d6b77c9ae01 4231 */
mturner5 0:0d6b77c9ae01 4232
mturner5 0:0d6b77c9ae01 4233 /* TSR Bit Fields */
mturner5 0:0d6b77c9ae01 4234 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4235 #define RTC_TSR_TSR_SHIFT 0
mturner5 0:0d6b77c9ae01 4236 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mturner5 0:0d6b77c9ae01 4237 /* TPR Bit Fields */
mturner5 0:0d6b77c9ae01 4238 #define RTC_TPR_TPR_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 4239 #define RTC_TPR_TPR_SHIFT 0
mturner5 0:0d6b77c9ae01 4240 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mturner5 0:0d6b77c9ae01 4241 /* TAR Bit Fields */
mturner5 0:0d6b77c9ae01 4242 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4243 #define RTC_TAR_TAR_SHIFT 0
mturner5 0:0d6b77c9ae01 4244 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mturner5 0:0d6b77c9ae01 4245 /* TCR Bit Fields */
mturner5 0:0d6b77c9ae01 4246 #define RTC_TCR_TCR_MASK 0xFFu
mturner5 0:0d6b77c9ae01 4247 #define RTC_TCR_TCR_SHIFT 0
mturner5 0:0d6b77c9ae01 4248 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mturner5 0:0d6b77c9ae01 4249 #define RTC_TCR_CIR_MASK 0xFF00u
mturner5 0:0d6b77c9ae01 4250 #define RTC_TCR_CIR_SHIFT 8
mturner5 0:0d6b77c9ae01 4251 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mturner5 0:0d6b77c9ae01 4252 #define RTC_TCR_TCV_MASK 0xFF0000u
mturner5 0:0d6b77c9ae01 4253 #define RTC_TCR_TCV_SHIFT 16
mturner5 0:0d6b77c9ae01 4254 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mturner5 0:0d6b77c9ae01 4255 #define RTC_TCR_CIC_MASK 0xFF000000u
mturner5 0:0d6b77c9ae01 4256 #define RTC_TCR_CIC_SHIFT 24
mturner5 0:0d6b77c9ae01 4257 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mturner5 0:0d6b77c9ae01 4258 /* CR Bit Fields */
mturner5 0:0d6b77c9ae01 4259 #define RTC_CR_SWR_MASK 0x1u
mturner5 0:0d6b77c9ae01 4260 #define RTC_CR_SWR_SHIFT 0
mturner5 0:0d6b77c9ae01 4261 #define RTC_CR_WPE_MASK 0x2u
mturner5 0:0d6b77c9ae01 4262 #define RTC_CR_WPE_SHIFT 1
mturner5 0:0d6b77c9ae01 4263 #define RTC_CR_SUP_MASK 0x4u
mturner5 0:0d6b77c9ae01 4264 #define RTC_CR_SUP_SHIFT 2
mturner5 0:0d6b77c9ae01 4265 #define RTC_CR_UM_MASK 0x8u
mturner5 0:0d6b77c9ae01 4266 #define RTC_CR_UM_SHIFT 3
mturner5 0:0d6b77c9ae01 4267 #define RTC_CR_OSCE_MASK 0x100u
mturner5 0:0d6b77c9ae01 4268 #define RTC_CR_OSCE_SHIFT 8
mturner5 0:0d6b77c9ae01 4269 #define RTC_CR_CLKO_MASK 0x200u
mturner5 0:0d6b77c9ae01 4270 #define RTC_CR_CLKO_SHIFT 9
mturner5 0:0d6b77c9ae01 4271 #define RTC_CR_SC16P_MASK 0x400u
mturner5 0:0d6b77c9ae01 4272 #define RTC_CR_SC16P_SHIFT 10
mturner5 0:0d6b77c9ae01 4273 #define RTC_CR_SC8P_MASK 0x800u
mturner5 0:0d6b77c9ae01 4274 #define RTC_CR_SC8P_SHIFT 11
mturner5 0:0d6b77c9ae01 4275 #define RTC_CR_SC4P_MASK 0x1000u
mturner5 0:0d6b77c9ae01 4276 #define RTC_CR_SC4P_SHIFT 12
mturner5 0:0d6b77c9ae01 4277 #define RTC_CR_SC2P_MASK 0x2000u
mturner5 0:0d6b77c9ae01 4278 #define RTC_CR_SC2P_SHIFT 13
mturner5 0:0d6b77c9ae01 4279 /* SR Bit Fields */
mturner5 0:0d6b77c9ae01 4280 #define RTC_SR_TIF_MASK 0x1u
mturner5 0:0d6b77c9ae01 4281 #define RTC_SR_TIF_SHIFT 0
mturner5 0:0d6b77c9ae01 4282 #define RTC_SR_TOF_MASK 0x2u
mturner5 0:0d6b77c9ae01 4283 #define RTC_SR_TOF_SHIFT 1
mturner5 0:0d6b77c9ae01 4284 #define RTC_SR_TAF_MASK 0x4u
mturner5 0:0d6b77c9ae01 4285 #define RTC_SR_TAF_SHIFT 2
mturner5 0:0d6b77c9ae01 4286 #define RTC_SR_TCE_MASK 0x10u
mturner5 0:0d6b77c9ae01 4287 #define RTC_SR_TCE_SHIFT 4
mturner5 0:0d6b77c9ae01 4288 /* LR Bit Fields */
mturner5 0:0d6b77c9ae01 4289 #define RTC_LR_TCL_MASK 0x8u
mturner5 0:0d6b77c9ae01 4290 #define RTC_LR_TCL_SHIFT 3
mturner5 0:0d6b77c9ae01 4291 #define RTC_LR_CRL_MASK 0x10u
mturner5 0:0d6b77c9ae01 4292 #define RTC_LR_CRL_SHIFT 4
mturner5 0:0d6b77c9ae01 4293 #define RTC_LR_SRL_MASK 0x20u
mturner5 0:0d6b77c9ae01 4294 #define RTC_LR_SRL_SHIFT 5
mturner5 0:0d6b77c9ae01 4295 #define RTC_LR_LRL_MASK 0x40u
mturner5 0:0d6b77c9ae01 4296 #define RTC_LR_LRL_SHIFT 6
mturner5 0:0d6b77c9ae01 4297 /* IER Bit Fields */
mturner5 0:0d6b77c9ae01 4298 #define RTC_IER_TIIE_MASK 0x1u
mturner5 0:0d6b77c9ae01 4299 #define RTC_IER_TIIE_SHIFT 0
mturner5 0:0d6b77c9ae01 4300 #define RTC_IER_TOIE_MASK 0x2u
mturner5 0:0d6b77c9ae01 4301 #define RTC_IER_TOIE_SHIFT 1
mturner5 0:0d6b77c9ae01 4302 #define RTC_IER_TAIE_MASK 0x4u
mturner5 0:0d6b77c9ae01 4303 #define RTC_IER_TAIE_SHIFT 2
mturner5 0:0d6b77c9ae01 4304 #define RTC_IER_TSIE_MASK 0x10u
mturner5 0:0d6b77c9ae01 4305 #define RTC_IER_TSIE_SHIFT 4
mturner5 0:0d6b77c9ae01 4306 #define RTC_IER_WPON_MASK 0x80u
mturner5 0:0d6b77c9ae01 4307 #define RTC_IER_WPON_SHIFT 7
mturner5 0:0d6b77c9ae01 4308
mturner5 0:0d6b77c9ae01 4309 /*!
mturner5 0:0d6b77c9ae01 4310 * @}
mturner5 0:0d6b77c9ae01 4311 */ /* end of group RTC_Register_Masks */
mturner5 0:0d6b77c9ae01 4312
mturner5 0:0d6b77c9ae01 4313
mturner5 0:0d6b77c9ae01 4314 /* RTC - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4315 /** Peripheral RTC base address */
mturner5 0:0d6b77c9ae01 4316 #define RTC_BASE (0x4003D000u)
mturner5 0:0d6b77c9ae01 4317 /** Peripheral RTC base pointer */
mturner5 0:0d6b77c9ae01 4318 #define RTC ((RTC_Type *)RTC_BASE)
mturner5 0:0d6b77c9ae01 4319 /** Array initializer of RTC peripheral base pointers */
mturner5 0:0d6b77c9ae01 4320 #define RTC_BASES { RTC }
mturner5 0:0d6b77c9ae01 4321
mturner5 0:0d6b77c9ae01 4322 /*!
mturner5 0:0d6b77c9ae01 4323 * @}
mturner5 0:0d6b77c9ae01 4324 */ /* end of group RTC_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4325
mturner5 0:0d6b77c9ae01 4326
mturner5 0:0d6b77c9ae01 4327 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4328 -- SIM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4329 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4330
mturner5 0:0d6b77c9ae01 4331 /*!
mturner5 0:0d6b77c9ae01 4332 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4333 * @{
mturner5 0:0d6b77c9ae01 4334 */
mturner5 0:0d6b77c9ae01 4335
mturner5 0:0d6b77c9ae01 4336 /** SIM - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4337 typedef struct {
mturner5 0:0d6b77c9ae01 4338 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4339 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 4340 uint8_t RESERVED_0[4092];
mturner5 0:0d6b77c9ae01 4341 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mturner5 0:0d6b77c9ae01 4342 uint8_t RESERVED_1[4];
mturner5 0:0d6b77c9ae01 4343 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mturner5 0:0d6b77c9ae01 4344 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mturner5 0:0d6b77c9ae01 4345 uint8_t RESERVED_2[4];
mturner5 0:0d6b77c9ae01 4346 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mturner5 0:0d6b77c9ae01 4347 uint8_t RESERVED_3[8];
mturner5 0:0d6b77c9ae01 4348 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mturner5 0:0d6b77c9ae01 4349 uint8_t RESERVED_4[12];
mturner5 0:0d6b77c9ae01 4350 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mturner5 0:0d6b77c9ae01 4351 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mturner5 0:0d6b77c9ae01 4352 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mturner5 0:0d6b77c9ae01 4353 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mturner5 0:0d6b77c9ae01 4354 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mturner5 0:0d6b77c9ae01 4355 uint8_t RESERVED_5[4];
mturner5 0:0d6b77c9ae01 4356 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mturner5 0:0d6b77c9ae01 4357 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mturner5 0:0d6b77c9ae01 4358 uint8_t RESERVED_6[4];
mturner5 0:0d6b77c9ae01 4359 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mturner5 0:0d6b77c9ae01 4360 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mturner5 0:0d6b77c9ae01 4361 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mturner5 0:0d6b77c9ae01 4362 uint8_t RESERVED_7[156];
mturner5 0:0d6b77c9ae01 4363 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
mturner5 0:0d6b77c9ae01 4364 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
mturner5 0:0d6b77c9ae01 4365 } SIM_Type;
mturner5 0:0d6b77c9ae01 4366
mturner5 0:0d6b77c9ae01 4367 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4368 -- SIM Register Masks
mturner5 0:0d6b77c9ae01 4369 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4370
mturner5 0:0d6b77c9ae01 4371 /*!
mturner5 0:0d6b77c9ae01 4372 * @addtogroup SIM_Register_Masks SIM Register Masks
mturner5 0:0d6b77c9ae01 4373 * @{
mturner5 0:0d6b77c9ae01 4374 */
mturner5 0:0d6b77c9ae01 4375
mturner5 0:0d6b77c9ae01 4376 /* SOPT1 Bit Fields */
mturner5 0:0d6b77c9ae01 4377 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mturner5 0:0d6b77c9ae01 4378 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mturner5 0:0d6b77c9ae01 4379 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mturner5 0:0d6b77c9ae01 4380 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mturner5 0:0d6b77c9ae01 4381 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mturner5 0:0d6b77c9ae01 4382 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mturner5 0:0d6b77c9ae01 4383 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mturner5 0:0d6b77c9ae01 4384 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 4385 #define SIM_SOPT1_USBREGEN_SHIFT 31
mturner5 0:0d6b77c9ae01 4386 /* SOPT1CFG Bit Fields */
mturner5 0:0d6b77c9ae01 4387 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 4388 #define SIM_SOPT1CFG_URWE_SHIFT 24
mturner5 0:0d6b77c9ae01 4389 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 4390 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mturner5 0:0d6b77c9ae01 4391 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mturner5 0:0d6b77c9ae01 4392 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mturner5 0:0d6b77c9ae01 4393 /* SOPT2 Bit Fields */
mturner5 0:0d6b77c9ae01 4394 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mturner5 0:0d6b77c9ae01 4395 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mturner5 0:0d6b77c9ae01 4396 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mturner5 0:0d6b77c9ae01 4397 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mturner5 0:0d6b77c9ae01 4398 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mturner5 0:0d6b77c9ae01 4399 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
mturner5 0:0d6b77c9ae01 4400 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
mturner5 0:0d6b77c9ae01 4401 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mturner5 0:0d6b77c9ae01 4402 #define SIM_SOPT2_USBSRC_SHIFT 18
mturner5 0:0d6b77c9ae01 4403 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
mturner5 0:0d6b77c9ae01 4404 #define SIM_SOPT2_TPMSRC_SHIFT 24
mturner5 0:0d6b77c9ae01 4405 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
mturner5 0:0d6b77c9ae01 4406 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
mturner5 0:0d6b77c9ae01 4407 #define SIM_SOPT2_UART0SRC_SHIFT 26
mturner5 0:0d6b77c9ae01 4408 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
mturner5 0:0d6b77c9ae01 4409 /* SOPT4 Bit Fields */
mturner5 0:0d6b77c9ae01 4410 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
mturner5 0:0d6b77c9ae01 4411 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
mturner5 0:0d6b77c9ae01 4412 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
mturner5 0:0d6b77c9ae01 4413 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
mturner5 0:0d6b77c9ae01 4414 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
mturner5 0:0d6b77c9ae01 4415 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 4416 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
mturner5 0:0d6b77c9ae01 4417 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 4418 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
mturner5 0:0d6b77c9ae01 4419 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
mturner5 0:0d6b77c9ae01 4420 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
mturner5 0:0d6b77c9ae01 4421 /* SOPT5 Bit Fields */
mturner5 0:0d6b77c9ae01 4422 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
mturner5 0:0d6b77c9ae01 4423 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mturner5 0:0d6b77c9ae01 4424 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
mturner5 0:0d6b77c9ae01 4425 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
mturner5 0:0d6b77c9ae01 4426 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mturner5 0:0d6b77c9ae01 4427 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
mturner5 0:0d6b77c9ae01 4428 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
mturner5 0:0d6b77c9ae01 4429 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
mturner5 0:0d6b77c9ae01 4430 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
mturner5 0:0d6b77c9ae01 4431 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
mturner5 0:0d6b77c9ae01 4432 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
mturner5 0:0d6b77c9ae01 4433 #define SIM_SOPT5_UART0ODE_SHIFT 16
mturner5 0:0d6b77c9ae01 4434 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
mturner5 0:0d6b77c9ae01 4435 #define SIM_SOPT5_UART1ODE_SHIFT 17
mturner5 0:0d6b77c9ae01 4436 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
mturner5 0:0d6b77c9ae01 4437 #define SIM_SOPT5_UART2ODE_SHIFT 18
mturner5 0:0d6b77c9ae01 4438 /* SOPT7 Bit Fields */
mturner5 0:0d6b77c9ae01 4439 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mturner5 0:0d6b77c9ae01 4440 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mturner5 0:0d6b77c9ae01 4441 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mturner5 0:0d6b77c9ae01 4442 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mturner5 0:0d6b77c9ae01 4443 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mturner5 0:0d6b77c9ae01 4444 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 4445 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mturner5 0:0d6b77c9ae01 4446 /* SDID Bit Fields */
mturner5 0:0d6b77c9ae01 4447 #define SIM_SDID_PINID_MASK 0xFu
mturner5 0:0d6b77c9ae01 4448 #define SIM_SDID_PINID_SHIFT 0
mturner5 0:0d6b77c9ae01 4449 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mturner5 0:0d6b77c9ae01 4450 #define SIM_SDID_DIEID_MASK 0xF80u
mturner5 0:0d6b77c9ae01 4451 #define SIM_SDID_DIEID_SHIFT 7
mturner5 0:0d6b77c9ae01 4452 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
mturner5 0:0d6b77c9ae01 4453 #define SIM_SDID_REVID_MASK 0xF000u
mturner5 0:0d6b77c9ae01 4454 #define SIM_SDID_REVID_SHIFT 12
mturner5 0:0d6b77c9ae01 4455 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mturner5 0:0d6b77c9ae01 4456 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
mturner5 0:0d6b77c9ae01 4457 #define SIM_SDID_SRAMSIZE_SHIFT 16
mturner5 0:0d6b77c9ae01 4458 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
mturner5 0:0d6b77c9ae01 4459 #define SIM_SDID_SERIESID_MASK 0xF00000u
mturner5 0:0d6b77c9ae01 4460 #define SIM_SDID_SERIESID_SHIFT 20
mturner5 0:0d6b77c9ae01 4461 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mturner5 0:0d6b77c9ae01 4462 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mturner5 0:0d6b77c9ae01 4463 #define SIM_SDID_SUBFAMID_SHIFT 24
mturner5 0:0d6b77c9ae01 4464 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mturner5 0:0d6b77c9ae01 4465 #define SIM_SDID_FAMID_MASK 0xF0000000u
mturner5 0:0d6b77c9ae01 4466 #define SIM_SDID_FAMID_SHIFT 28
mturner5 0:0d6b77c9ae01 4467 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mturner5 0:0d6b77c9ae01 4468 /* SCGC4 Bit Fields */
mturner5 0:0d6b77c9ae01 4469 #define SIM_SCGC4_I2C0_MASK 0x40u
mturner5 0:0d6b77c9ae01 4470 #define SIM_SCGC4_I2C0_SHIFT 6
mturner5 0:0d6b77c9ae01 4471 #define SIM_SCGC4_I2C1_MASK 0x80u
mturner5 0:0d6b77c9ae01 4472 #define SIM_SCGC4_I2C1_SHIFT 7
mturner5 0:0d6b77c9ae01 4473 #define SIM_SCGC4_UART0_MASK 0x400u
mturner5 0:0d6b77c9ae01 4474 #define SIM_SCGC4_UART0_SHIFT 10
mturner5 0:0d6b77c9ae01 4475 #define SIM_SCGC4_UART1_MASK 0x800u
mturner5 0:0d6b77c9ae01 4476 #define SIM_SCGC4_UART1_SHIFT 11
mturner5 0:0d6b77c9ae01 4477 #define SIM_SCGC4_UART2_MASK 0x1000u
mturner5 0:0d6b77c9ae01 4478 #define SIM_SCGC4_UART2_SHIFT 12
mturner5 0:0d6b77c9ae01 4479 #define SIM_SCGC4_USBOTG_MASK 0x40000u
mturner5 0:0d6b77c9ae01 4480 #define SIM_SCGC4_USBOTG_SHIFT 18
mturner5 0:0d6b77c9ae01 4481 #define SIM_SCGC4_CMP_MASK 0x80000u
mturner5 0:0d6b77c9ae01 4482 #define SIM_SCGC4_CMP_SHIFT 19
mturner5 0:0d6b77c9ae01 4483 #define SIM_SCGC4_SPI0_MASK 0x400000u
mturner5 0:0d6b77c9ae01 4484 #define SIM_SCGC4_SPI0_SHIFT 22
mturner5 0:0d6b77c9ae01 4485 #define SIM_SCGC4_SPI1_MASK 0x800000u
mturner5 0:0d6b77c9ae01 4486 #define SIM_SCGC4_SPI1_SHIFT 23
mturner5 0:0d6b77c9ae01 4487 /* SCGC5 Bit Fields */
mturner5 0:0d6b77c9ae01 4488 #define SIM_SCGC5_LPTMR_MASK 0x1u
mturner5 0:0d6b77c9ae01 4489 #define SIM_SCGC5_LPTMR_SHIFT 0
mturner5 0:0d6b77c9ae01 4490 #define SIM_SCGC5_TSI_MASK 0x20u
mturner5 0:0d6b77c9ae01 4491 #define SIM_SCGC5_TSI_SHIFT 5
mturner5 0:0d6b77c9ae01 4492 #define SIM_SCGC5_PORTA_MASK 0x200u
mturner5 0:0d6b77c9ae01 4493 #define SIM_SCGC5_PORTA_SHIFT 9
mturner5 0:0d6b77c9ae01 4494 #define SIM_SCGC5_PORTB_MASK 0x400u
mturner5 0:0d6b77c9ae01 4495 #define SIM_SCGC5_PORTB_SHIFT 10
mturner5 0:0d6b77c9ae01 4496 #define SIM_SCGC5_PORTC_MASK 0x800u
mturner5 0:0d6b77c9ae01 4497 #define SIM_SCGC5_PORTC_SHIFT 11
mturner5 0:0d6b77c9ae01 4498 #define SIM_SCGC5_PORTD_MASK 0x1000u
mturner5 0:0d6b77c9ae01 4499 #define SIM_SCGC5_PORTD_SHIFT 12
mturner5 0:0d6b77c9ae01 4500 #define SIM_SCGC5_PORTE_MASK 0x2000u
mturner5 0:0d6b77c9ae01 4501 #define SIM_SCGC5_PORTE_SHIFT 13
mturner5 0:0d6b77c9ae01 4502 #define SIM_SCGC5_SLCD_MASK 0x80000u
mturner5 0:0d6b77c9ae01 4503 #define SIM_SCGC5_SLCD_SHIFT 19
mturner5 0:0d6b77c9ae01 4504 /* SCGC6 Bit Fields */
mturner5 0:0d6b77c9ae01 4505 #define SIM_SCGC6_FTF_MASK 0x1u
mturner5 0:0d6b77c9ae01 4506 #define SIM_SCGC6_FTF_SHIFT 0
mturner5 0:0d6b77c9ae01 4507 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mturner5 0:0d6b77c9ae01 4508 #define SIM_SCGC6_DMAMUX_SHIFT 1
mturner5 0:0d6b77c9ae01 4509 #define SIM_SCGC6_I2S_MASK 0x8000u
mturner5 0:0d6b77c9ae01 4510 #define SIM_SCGC6_I2S_SHIFT 15
mturner5 0:0d6b77c9ae01 4511 #define SIM_SCGC6_PIT_MASK 0x800000u
mturner5 0:0d6b77c9ae01 4512 #define SIM_SCGC6_PIT_SHIFT 23
mturner5 0:0d6b77c9ae01 4513 #define SIM_SCGC6_TPM0_MASK 0x1000000u
mturner5 0:0d6b77c9ae01 4514 #define SIM_SCGC6_TPM0_SHIFT 24
mturner5 0:0d6b77c9ae01 4515 #define SIM_SCGC6_TPM1_MASK 0x2000000u
mturner5 0:0d6b77c9ae01 4516 #define SIM_SCGC6_TPM1_SHIFT 25
mturner5 0:0d6b77c9ae01 4517 #define SIM_SCGC6_TPM2_MASK 0x4000000u
mturner5 0:0d6b77c9ae01 4518 #define SIM_SCGC6_TPM2_SHIFT 26
mturner5 0:0d6b77c9ae01 4519 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mturner5 0:0d6b77c9ae01 4520 #define SIM_SCGC6_ADC0_SHIFT 27
mturner5 0:0d6b77c9ae01 4521 #define SIM_SCGC6_RTC_MASK 0x20000000u
mturner5 0:0d6b77c9ae01 4522 #define SIM_SCGC6_RTC_SHIFT 29
mturner5 0:0d6b77c9ae01 4523 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 4524 #define SIM_SCGC6_DAC0_SHIFT 31
mturner5 0:0d6b77c9ae01 4525 /* SCGC7 Bit Fields */
mturner5 0:0d6b77c9ae01 4526 #define SIM_SCGC7_DMA_MASK 0x100u
mturner5 0:0d6b77c9ae01 4527 #define SIM_SCGC7_DMA_SHIFT 8
mturner5 0:0d6b77c9ae01 4528 /* CLKDIV1 Bit Fields */
mturner5 0:0d6b77c9ae01 4529 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
mturner5 0:0d6b77c9ae01 4530 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mturner5 0:0d6b77c9ae01 4531 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mturner5 0:0d6b77c9ae01 4532 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mturner5 0:0d6b77c9ae01 4533 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mturner5 0:0d6b77c9ae01 4534 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mturner5 0:0d6b77c9ae01 4535 /* FCFG1 Bit Fields */
mturner5 0:0d6b77c9ae01 4536 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mturner5 0:0d6b77c9ae01 4537 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mturner5 0:0d6b77c9ae01 4538 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mturner5 0:0d6b77c9ae01 4539 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mturner5 0:0d6b77c9ae01 4540 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mturner5 0:0d6b77c9ae01 4541 #define SIM_FCFG1_PFSIZE_SHIFT 24
mturner5 0:0d6b77c9ae01 4542 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mturner5 0:0d6b77c9ae01 4543 /* FCFG2 Bit Fields */
mturner5 0:0d6b77c9ae01 4544 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mturner5 0:0d6b77c9ae01 4545 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mturner5 0:0d6b77c9ae01 4546 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mturner5 0:0d6b77c9ae01 4547 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mturner5 0:0d6b77c9ae01 4548 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mturner5 0:0d6b77c9ae01 4549 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mturner5 0:0d6b77c9ae01 4550 /* UIDMH Bit Fields */
mturner5 0:0d6b77c9ae01 4551 #define SIM_UIDMH_UID_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 4552 #define SIM_UIDMH_UID_SHIFT 0
mturner5 0:0d6b77c9ae01 4553 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mturner5 0:0d6b77c9ae01 4554 /* UIDML Bit Fields */
mturner5 0:0d6b77c9ae01 4555 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4556 #define SIM_UIDML_UID_SHIFT 0
mturner5 0:0d6b77c9ae01 4557 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mturner5 0:0d6b77c9ae01 4558 /* UIDL Bit Fields */
mturner5 0:0d6b77c9ae01 4559 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mturner5 0:0d6b77c9ae01 4560 #define SIM_UIDL_UID_SHIFT 0
mturner5 0:0d6b77c9ae01 4561 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mturner5 0:0d6b77c9ae01 4562 /* COPC Bit Fields */
mturner5 0:0d6b77c9ae01 4563 #define SIM_COPC_COPW_MASK 0x1u
mturner5 0:0d6b77c9ae01 4564 #define SIM_COPC_COPW_SHIFT 0
mturner5 0:0d6b77c9ae01 4565 #define SIM_COPC_COPCLKS_MASK 0x2u
mturner5 0:0d6b77c9ae01 4566 #define SIM_COPC_COPCLKS_SHIFT 1
mturner5 0:0d6b77c9ae01 4567 #define SIM_COPC_COPT_MASK 0xCu
mturner5 0:0d6b77c9ae01 4568 #define SIM_COPC_COPT_SHIFT 2
mturner5 0:0d6b77c9ae01 4569 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
mturner5 0:0d6b77c9ae01 4570 /* SRVCOP Bit Fields */
mturner5 0:0d6b77c9ae01 4571 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
mturner5 0:0d6b77c9ae01 4572 #define SIM_SRVCOP_SRVCOP_SHIFT 0
mturner5 0:0d6b77c9ae01 4573 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
mturner5 0:0d6b77c9ae01 4574
mturner5 0:0d6b77c9ae01 4575 /*!
mturner5 0:0d6b77c9ae01 4576 * @}
mturner5 0:0d6b77c9ae01 4577 */ /* end of group SIM_Register_Masks */
mturner5 0:0d6b77c9ae01 4578
mturner5 0:0d6b77c9ae01 4579
mturner5 0:0d6b77c9ae01 4580 /* SIM - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4581 /** Peripheral SIM base address */
mturner5 0:0d6b77c9ae01 4582 #define SIM_BASE (0x40047000u)
mturner5 0:0d6b77c9ae01 4583 /** Peripheral SIM base pointer */
mturner5 0:0d6b77c9ae01 4584 #define SIM ((SIM_Type *)SIM_BASE)
mturner5 0:0d6b77c9ae01 4585 /** Array initializer of SIM peripheral base pointers */
mturner5 0:0d6b77c9ae01 4586 #define SIM_BASES { SIM }
mturner5 0:0d6b77c9ae01 4587
mturner5 0:0d6b77c9ae01 4588 /*!
mturner5 0:0d6b77c9ae01 4589 * @}
mturner5 0:0d6b77c9ae01 4590 */ /* end of group SIM_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4591
mturner5 0:0d6b77c9ae01 4592
mturner5 0:0d6b77c9ae01 4593 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4594 -- SMC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4595 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4596
mturner5 0:0d6b77c9ae01 4597 /*!
mturner5 0:0d6b77c9ae01 4598 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4599 * @{
mturner5 0:0d6b77c9ae01 4600 */
mturner5 0:0d6b77c9ae01 4601
mturner5 0:0d6b77c9ae01 4602 /** SMC - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4603 typedef struct {
mturner5 0:0d6b77c9ae01 4604 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4605 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 4606 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
mturner5 0:0d6b77c9ae01 4607 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mturner5 0:0d6b77c9ae01 4608 } SMC_Type;
mturner5 0:0d6b77c9ae01 4609
mturner5 0:0d6b77c9ae01 4610 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4611 -- SMC Register Masks
mturner5 0:0d6b77c9ae01 4612 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4613
mturner5 0:0d6b77c9ae01 4614 /*!
mturner5 0:0d6b77c9ae01 4615 * @addtogroup SMC_Register_Masks SMC Register Masks
mturner5 0:0d6b77c9ae01 4616 * @{
mturner5 0:0d6b77c9ae01 4617 */
mturner5 0:0d6b77c9ae01 4618
mturner5 0:0d6b77c9ae01 4619 /* PMPROT Bit Fields */
mturner5 0:0d6b77c9ae01 4620 #define SMC_PMPROT_AVLLS_MASK 0x2u
mturner5 0:0d6b77c9ae01 4621 #define SMC_PMPROT_AVLLS_SHIFT 1
mturner5 0:0d6b77c9ae01 4622 #define SMC_PMPROT_ALLS_MASK 0x8u
mturner5 0:0d6b77c9ae01 4623 #define SMC_PMPROT_ALLS_SHIFT 3
mturner5 0:0d6b77c9ae01 4624 #define SMC_PMPROT_AVLP_MASK 0x20u
mturner5 0:0d6b77c9ae01 4625 #define SMC_PMPROT_AVLP_SHIFT 5
mturner5 0:0d6b77c9ae01 4626 /* PMCTRL Bit Fields */
mturner5 0:0d6b77c9ae01 4627 #define SMC_PMCTRL_STOPM_MASK 0x7u
mturner5 0:0d6b77c9ae01 4628 #define SMC_PMCTRL_STOPM_SHIFT 0
mturner5 0:0d6b77c9ae01 4629 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mturner5 0:0d6b77c9ae01 4630 #define SMC_PMCTRL_STOPA_MASK 0x8u
mturner5 0:0d6b77c9ae01 4631 #define SMC_PMCTRL_STOPA_SHIFT 3
mturner5 0:0d6b77c9ae01 4632 #define SMC_PMCTRL_RUNM_MASK 0x60u
mturner5 0:0d6b77c9ae01 4633 #define SMC_PMCTRL_RUNM_SHIFT 5
mturner5 0:0d6b77c9ae01 4634 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mturner5 0:0d6b77c9ae01 4635 /* STOPCTRL Bit Fields */
mturner5 0:0d6b77c9ae01 4636 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
mturner5 0:0d6b77c9ae01 4637 #define SMC_STOPCTRL_VLLSM_SHIFT 0
mturner5 0:0d6b77c9ae01 4638 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
mturner5 0:0d6b77c9ae01 4639 #define SMC_STOPCTRL_PORPO_MASK 0x20u
mturner5 0:0d6b77c9ae01 4640 #define SMC_STOPCTRL_PORPO_SHIFT 5
mturner5 0:0d6b77c9ae01 4641 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
mturner5 0:0d6b77c9ae01 4642 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
mturner5 0:0d6b77c9ae01 4643 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
mturner5 0:0d6b77c9ae01 4644 /* PMSTAT Bit Fields */
mturner5 0:0d6b77c9ae01 4645 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
mturner5 0:0d6b77c9ae01 4646 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mturner5 0:0d6b77c9ae01 4647 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mturner5 0:0d6b77c9ae01 4648
mturner5 0:0d6b77c9ae01 4649 /*!
mturner5 0:0d6b77c9ae01 4650 * @}
mturner5 0:0d6b77c9ae01 4651 */ /* end of group SMC_Register_Masks */
mturner5 0:0d6b77c9ae01 4652
mturner5 0:0d6b77c9ae01 4653
mturner5 0:0d6b77c9ae01 4654 /* SMC - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4655 /** Peripheral SMC base address */
mturner5 0:0d6b77c9ae01 4656 #define SMC_BASE (0x4007E000u)
mturner5 0:0d6b77c9ae01 4657 /** Peripheral SMC base pointer */
mturner5 0:0d6b77c9ae01 4658 #define SMC ((SMC_Type *)SMC_BASE)
mturner5 0:0d6b77c9ae01 4659 /** Array initializer of SMC peripheral base pointers */
mturner5 0:0d6b77c9ae01 4660 #define SMC_BASES { SMC }
mturner5 0:0d6b77c9ae01 4661
mturner5 0:0d6b77c9ae01 4662 /*!
mturner5 0:0d6b77c9ae01 4663 * @}
mturner5 0:0d6b77c9ae01 4664 */ /* end of group SMC_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4665
mturner5 0:0d6b77c9ae01 4666
mturner5 0:0d6b77c9ae01 4667 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4668 -- SPI Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4669 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4670
mturner5 0:0d6b77c9ae01 4671 /*!
mturner5 0:0d6b77c9ae01 4672 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4673 * @{
mturner5 0:0d6b77c9ae01 4674 */
mturner5 0:0d6b77c9ae01 4675
mturner5 0:0d6b77c9ae01 4676 /** SPI - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4677 typedef struct {
mturner5 0:0d6b77c9ae01 4678 __I uint8_t S; /**< SPI status register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4679 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
mturner5 0:0d6b77c9ae01 4680 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
mturner5 0:0d6b77c9ae01 4681 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
mturner5 0:0d6b77c9ae01 4682 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
mturner5 0:0d6b77c9ae01 4683 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
mturner5 0:0d6b77c9ae01 4684 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
mturner5 0:0d6b77c9ae01 4685 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
mturner5 0:0d6b77c9ae01 4686 uint8_t RESERVED_0[2];
mturner5 0:0d6b77c9ae01 4687 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
mturner5 0:0d6b77c9ae01 4688 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
mturner5 0:0d6b77c9ae01 4689 } SPI_Type;
mturner5 0:0d6b77c9ae01 4690
mturner5 0:0d6b77c9ae01 4691 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4692 -- SPI Register Masks
mturner5 0:0d6b77c9ae01 4693 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4694
mturner5 0:0d6b77c9ae01 4695 /*!
mturner5 0:0d6b77c9ae01 4696 * @addtogroup SPI_Register_Masks SPI Register Masks
mturner5 0:0d6b77c9ae01 4697 * @{
mturner5 0:0d6b77c9ae01 4698 */
mturner5 0:0d6b77c9ae01 4699
mturner5 0:0d6b77c9ae01 4700 /* S Bit Fields */
mturner5 0:0d6b77c9ae01 4701 #define SPI_S_RFIFOEF_MASK 0x1u
mturner5 0:0d6b77c9ae01 4702 #define SPI_S_RFIFOEF_SHIFT 0
mturner5 0:0d6b77c9ae01 4703 #define SPI_S_TXFULLF_MASK 0x2u
mturner5 0:0d6b77c9ae01 4704 #define SPI_S_TXFULLF_SHIFT 1
mturner5 0:0d6b77c9ae01 4705 #define SPI_S_TNEAREF_MASK 0x4u
mturner5 0:0d6b77c9ae01 4706 #define SPI_S_TNEAREF_SHIFT 2
mturner5 0:0d6b77c9ae01 4707 #define SPI_S_RNFULLF_MASK 0x8u
mturner5 0:0d6b77c9ae01 4708 #define SPI_S_RNFULLF_SHIFT 3
mturner5 0:0d6b77c9ae01 4709 #define SPI_S_MODF_MASK 0x10u
mturner5 0:0d6b77c9ae01 4710 #define SPI_S_MODF_SHIFT 4
mturner5 0:0d6b77c9ae01 4711 #define SPI_S_SPTEF_MASK 0x20u
mturner5 0:0d6b77c9ae01 4712 #define SPI_S_SPTEF_SHIFT 5
mturner5 0:0d6b77c9ae01 4713 #define SPI_S_SPMF_MASK 0x40u
mturner5 0:0d6b77c9ae01 4714 #define SPI_S_SPMF_SHIFT 6
mturner5 0:0d6b77c9ae01 4715 #define SPI_S_SPRF_MASK 0x80u
mturner5 0:0d6b77c9ae01 4716 #define SPI_S_SPRF_SHIFT 7
mturner5 0:0d6b77c9ae01 4717 /* BR Bit Fields */
mturner5 0:0d6b77c9ae01 4718 #define SPI_BR_SPR_MASK 0xFu
mturner5 0:0d6b77c9ae01 4719 #define SPI_BR_SPR_SHIFT 0
mturner5 0:0d6b77c9ae01 4720 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
mturner5 0:0d6b77c9ae01 4721 #define SPI_BR_SPPR_MASK 0x70u
mturner5 0:0d6b77c9ae01 4722 #define SPI_BR_SPPR_SHIFT 4
mturner5 0:0d6b77c9ae01 4723 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
mturner5 0:0d6b77c9ae01 4724 /* C2 Bit Fields */
mturner5 0:0d6b77c9ae01 4725 #define SPI_C2_SPC0_MASK 0x1u
mturner5 0:0d6b77c9ae01 4726 #define SPI_C2_SPC0_SHIFT 0
mturner5 0:0d6b77c9ae01 4727 #define SPI_C2_SPISWAI_MASK 0x2u
mturner5 0:0d6b77c9ae01 4728 #define SPI_C2_SPISWAI_SHIFT 1
mturner5 0:0d6b77c9ae01 4729 #define SPI_C2_RXDMAE_MASK 0x4u
mturner5 0:0d6b77c9ae01 4730 #define SPI_C2_RXDMAE_SHIFT 2
mturner5 0:0d6b77c9ae01 4731 #define SPI_C2_BIDIROE_MASK 0x8u
mturner5 0:0d6b77c9ae01 4732 #define SPI_C2_BIDIROE_SHIFT 3
mturner5 0:0d6b77c9ae01 4733 #define SPI_C2_MODFEN_MASK 0x10u
mturner5 0:0d6b77c9ae01 4734 #define SPI_C2_MODFEN_SHIFT 4
mturner5 0:0d6b77c9ae01 4735 #define SPI_C2_TXDMAE_MASK 0x20u
mturner5 0:0d6b77c9ae01 4736 #define SPI_C2_TXDMAE_SHIFT 5
mturner5 0:0d6b77c9ae01 4737 #define SPI_C2_SPIMODE_MASK 0x40u
mturner5 0:0d6b77c9ae01 4738 #define SPI_C2_SPIMODE_SHIFT 6
mturner5 0:0d6b77c9ae01 4739 #define SPI_C2_SPMIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 4740 #define SPI_C2_SPMIE_SHIFT 7
mturner5 0:0d6b77c9ae01 4741 /* C1 Bit Fields */
mturner5 0:0d6b77c9ae01 4742 #define SPI_C1_LSBFE_MASK 0x1u
mturner5 0:0d6b77c9ae01 4743 #define SPI_C1_LSBFE_SHIFT 0
mturner5 0:0d6b77c9ae01 4744 #define SPI_C1_SSOE_MASK 0x2u
mturner5 0:0d6b77c9ae01 4745 #define SPI_C1_SSOE_SHIFT 1
mturner5 0:0d6b77c9ae01 4746 #define SPI_C1_CPHA_MASK 0x4u
mturner5 0:0d6b77c9ae01 4747 #define SPI_C1_CPHA_SHIFT 2
mturner5 0:0d6b77c9ae01 4748 #define SPI_C1_CPOL_MASK 0x8u
mturner5 0:0d6b77c9ae01 4749 #define SPI_C1_CPOL_SHIFT 3
mturner5 0:0d6b77c9ae01 4750 #define SPI_C1_MSTR_MASK 0x10u
mturner5 0:0d6b77c9ae01 4751 #define SPI_C1_MSTR_SHIFT 4
mturner5 0:0d6b77c9ae01 4752 #define SPI_C1_SPTIE_MASK 0x20u
mturner5 0:0d6b77c9ae01 4753 #define SPI_C1_SPTIE_SHIFT 5
mturner5 0:0d6b77c9ae01 4754 #define SPI_C1_SPE_MASK 0x40u
mturner5 0:0d6b77c9ae01 4755 #define SPI_C1_SPE_SHIFT 6
mturner5 0:0d6b77c9ae01 4756 #define SPI_C1_SPIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 4757 #define SPI_C1_SPIE_SHIFT 7
mturner5 0:0d6b77c9ae01 4758 /* ML Bit Fields */
mturner5 0:0d6b77c9ae01 4759 #define SPI_ML_Bits_MASK 0xFFu
mturner5 0:0d6b77c9ae01 4760 #define SPI_ML_Bits_SHIFT 0
mturner5 0:0d6b77c9ae01 4761 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
mturner5 0:0d6b77c9ae01 4762 /* MH Bit Fields */
mturner5 0:0d6b77c9ae01 4763 #define SPI_MH_Bits_MASK 0xFFu
mturner5 0:0d6b77c9ae01 4764 #define SPI_MH_Bits_SHIFT 0
mturner5 0:0d6b77c9ae01 4765 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
mturner5 0:0d6b77c9ae01 4766 /* DL Bit Fields */
mturner5 0:0d6b77c9ae01 4767 #define SPI_DL_Bits_MASK 0xFFu
mturner5 0:0d6b77c9ae01 4768 #define SPI_DL_Bits_SHIFT 0
mturner5 0:0d6b77c9ae01 4769 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
mturner5 0:0d6b77c9ae01 4770 /* DH Bit Fields */
mturner5 0:0d6b77c9ae01 4771 #define SPI_DH_Bits_MASK 0xFFu
mturner5 0:0d6b77c9ae01 4772 #define SPI_DH_Bits_SHIFT 0
mturner5 0:0d6b77c9ae01 4773 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
mturner5 0:0d6b77c9ae01 4774 /* CI Bit Fields */
mturner5 0:0d6b77c9ae01 4775 #define SPI_CI_SPRFCI_MASK 0x1u
mturner5 0:0d6b77c9ae01 4776 #define SPI_CI_SPRFCI_SHIFT 0
mturner5 0:0d6b77c9ae01 4777 #define SPI_CI_SPTEFCI_MASK 0x2u
mturner5 0:0d6b77c9ae01 4778 #define SPI_CI_SPTEFCI_SHIFT 1
mturner5 0:0d6b77c9ae01 4779 #define SPI_CI_RNFULLFCI_MASK 0x4u
mturner5 0:0d6b77c9ae01 4780 #define SPI_CI_RNFULLFCI_SHIFT 2
mturner5 0:0d6b77c9ae01 4781 #define SPI_CI_TNEAREFCI_MASK 0x8u
mturner5 0:0d6b77c9ae01 4782 #define SPI_CI_TNEAREFCI_SHIFT 3
mturner5 0:0d6b77c9ae01 4783 #define SPI_CI_RXFOF_MASK 0x10u
mturner5 0:0d6b77c9ae01 4784 #define SPI_CI_RXFOF_SHIFT 4
mturner5 0:0d6b77c9ae01 4785 #define SPI_CI_TXFOF_MASK 0x20u
mturner5 0:0d6b77c9ae01 4786 #define SPI_CI_TXFOF_SHIFT 5
mturner5 0:0d6b77c9ae01 4787 #define SPI_CI_RXFERR_MASK 0x40u
mturner5 0:0d6b77c9ae01 4788 #define SPI_CI_RXFERR_SHIFT 6
mturner5 0:0d6b77c9ae01 4789 #define SPI_CI_TXFERR_MASK 0x80u
mturner5 0:0d6b77c9ae01 4790 #define SPI_CI_TXFERR_SHIFT 7
mturner5 0:0d6b77c9ae01 4791 /* C3 Bit Fields */
mturner5 0:0d6b77c9ae01 4792 #define SPI_C3_FIFOMODE_MASK 0x1u
mturner5 0:0d6b77c9ae01 4793 #define SPI_C3_FIFOMODE_SHIFT 0
mturner5 0:0d6b77c9ae01 4794 #define SPI_C3_RNFULLIEN_MASK 0x2u
mturner5 0:0d6b77c9ae01 4795 #define SPI_C3_RNFULLIEN_SHIFT 1
mturner5 0:0d6b77c9ae01 4796 #define SPI_C3_TNEARIEN_MASK 0x4u
mturner5 0:0d6b77c9ae01 4797 #define SPI_C3_TNEARIEN_SHIFT 2
mturner5 0:0d6b77c9ae01 4798 #define SPI_C3_INTCLR_MASK 0x8u
mturner5 0:0d6b77c9ae01 4799 #define SPI_C3_INTCLR_SHIFT 3
mturner5 0:0d6b77c9ae01 4800 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
mturner5 0:0d6b77c9ae01 4801 #define SPI_C3_RNFULLF_MARK_SHIFT 4
mturner5 0:0d6b77c9ae01 4802 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
mturner5 0:0d6b77c9ae01 4803 #define SPI_C3_TNEAREF_MARK_SHIFT 5
mturner5 0:0d6b77c9ae01 4804
mturner5 0:0d6b77c9ae01 4805 /*!
mturner5 0:0d6b77c9ae01 4806 * @}
mturner5 0:0d6b77c9ae01 4807 */ /* end of group SPI_Register_Masks */
mturner5 0:0d6b77c9ae01 4808
mturner5 0:0d6b77c9ae01 4809
mturner5 0:0d6b77c9ae01 4810 /* SPI - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4811 /** Peripheral SPI0 base address */
mturner5 0:0d6b77c9ae01 4812 #define SPI0_BASE (0x40076000u)
mturner5 0:0d6b77c9ae01 4813 /** Peripheral SPI0 base pointer */
mturner5 0:0d6b77c9ae01 4814 #define SPI0 ((SPI_Type *)SPI0_BASE)
mturner5 0:0d6b77c9ae01 4815 /** Peripheral SPI1 base address */
mturner5 0:0d6b77c9ae01 4816 #define SPI1_BASE (0x40077000u)
mturner5 0:0d6b77c9ae01 4817 /** Peripheral SPI1 base pointer */
mturner5 0:0d6b77c9ae01 4818 #define SPI1 ((SPI_Type *)SPI1_BASE)
mturner5 0:0d6b77c9ae01 4819 /** Array initializer of SPI peripheral base pointers */
mturner5 0:0d6b77c9ae01 4820 #define SPI_BASES { SPI0, SPI1 }
mturner5 0:0d6b77c9ae01 4821
mturner5 0:0d6b77c9ae01 4822 /*!
mturner5 0:0d6b77c9ae01 4823 * @}
mturner5 0:0d6b77c9ae01 4824 */ /* end of group SPI_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4825
mturner5 0:0d6b77c9ae01 4826
mturner5 0:0d6b77c9ae01 4827 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4828 -- TPM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4829 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4830
mturner5 0:0d6b77c9ae01 4831 /*!
mturner5 0:0d6b77c9ae01 4832 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4833 * @{
mturner5 0:0d6b77c9ae01 4834 */
mturner5 0:0d6b77c9ae01 4835
mturner5 0:0d6b77c9ae01 4836 /** TPM - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4837 typedef struct {
mturner5 0:0d6b77c9ae01 4838 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4839 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mturner5 0:0d6b77c9ae01 4840 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mturner5 0:0d6b77c9ae01 4841 struct { /* offset: 0xC, array step: 0x8 */
mturner5 0:0d6b77c9ae01 4842 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
mturner5 0:0d6b77c9ae01 4843 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mturner5 0:0d6b77c9ae01 4844 } CONTROLS[6];
mturner5 0:0d6b77c9ae01 4845 uint8_t RESERVED_0[20];
mturner5 0:0d6b77c9ae01 4846 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
mturner5 0:0d6b77c9ae01 4847 uint8_t RESERVED_1[48];
mturner5 0:0d6b77c9ae01 4848 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mturner5 0:0d6b77c9ae01 4849 } TPM_Type;
mturner5 0:0d6b77c9ae01 4850
mturner5 0:0d6b77c9ae01 4851 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4852 -- TPM Register Masks
mturner5 0:0d6b77c9ae01 4853 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4854
mturner5 0:0d6b77c9ae01 4855 /*!
mturner5 0:0d6b77c9ae01 4856 * @addtogroup TPM_Register_Masks TPM Register Masks
mturner5 0:0d6b77c9ae01 4857 * @{
mturner5 0:0d6b77c9ae01 4858 */
mturner5 0:0d6b77c9ae01 4859
mturner5 0:0d6b77c9ae01 4860 /* SC Bit Fields */
mturner5 0:0d6b77c9ae01 4861 #define TPM_SC_PS_MASK 0x7u
mturner5 0:0d6b77c9ae01 4862 #define TPM_SC_PS_SHIFT 0
mturner5 0:0d6b77c9ae01 4863 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
mturner5 0:0d6b77c9ae01 4864 #define TPM_SC_CMOD_MASK 0x18u
mturner5 0:0d6b77c9ae01 4865 #define TPM_SC_CMOD_SHIFT 3
mturner5 0:0d6b77c9ae01 4866 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
mturner5 0:0d6b77c9ae01 4867 #define TPM_SC_CPWMS_MASK 0x20u
mturner5 0:0d6b77c9ae01 4868 #define TPM_SC_CPWMS_SHIFT 5
mturner5 0:0d6b77c9ae01 4869 #define TPM_SC_TOIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 4870 #define TPM_SC_TOIE_SHIFT 6
mturner5 0:0d6b77c9ae01 4871 #define TPM_SC_TOF_MASK 0x80u
mturner5 0:0d6b77c9ae01 4872 #define TPM_SC_TOF_SHIFT 7
mturner5 0:0d6b77c9ae01 4873 #define TPM_SC_DMA_MASK 0x100u
mturner5 0:0d6b77c9ae01 4874 #define TPM_SC_DMA_SHIFT 8
mturner5 0:0d6b77c9ae01 4875 /* CNT Bit Fields */
mturner5 0:0d6b77c9ae01 4876 #define TPM_CNT_COUNT_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 4877 #define TPM_CNT_COUNT_SHIFT 0
mturner5 0:0d6b77c9ae01 4878 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
mturner5 0:0d6b77c9ae01 4879 /* MOD Bit Fields */
mturner5 0:0d6b77c9ae01 4880 #define TPM_MOD_MOD_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 4881 #define TPM_MOD_MOD_SHIFT 0
mturner5 0:0d6b77c9ae01 4882 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
mturner5 0:0d6b77c9ae01 4883 /* CnSC Bit Fields */
mturner5 0:0d6b77c9ae01 4884 #define TPM_CnSC_DMA_MASK 0x1u
mturner5 0:0d6b77c9ae01 4885 #define TPM_CnSC_DMA_SHIFT 0
mturner5 0:0d6b77c9ae01 4886 #define TPM_CnSC_ELSA_MASK 0x4u
mturner5 0:0d6b77c9ae01 4887 #define TPM_CnSC_ELSA_SHIFT 2
mturner5 0:0d6b77c9ae01 4888 #define TPM_CnSC_ELSB_MASK 0x8u
mturner5 0:0d6b77c9ae01 4889 #define TPM_CnSC_ELSB_SHIFT 3
mturner5 0:0d6b77c9ae01 4890 #define TPM_CnSC_MSA_MASK 0x10u
mturner5 0:0d6b77c9ae01 4891 #define TPM_CnSC_MSA_SHIFT 4
mturner5 0:0d6b77c9ae01 4892 #define TPM_CnSC_MSB_MASK 0x20u
mturner5 0:0d6b77c9ae01 4893 #define TPM_CnSC_MSB_SHIFT 5
mturner5 0:0d6b77c9ae01 4894 #define TPM_CnSC_CHIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 4895 #define TPM_CnSC_CHIE_SHIFT 6
mturner5 0:0d6b77c9ae01 4896 #define TPM_CnSC_CHF_MASK 0x80u
mturner5 0:0d6b77c9ae01 4897 #define TPM_CnSC_CHF_SHIFT 7
mturner5 0:0d6b77c9ae01 4898 /* CnV Bit Fields */
mturner5 0:0d6b77c9ae01 4899 #define TPM_CnV_VAL_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 4900 #define TPM_CnV_VAL_SHIFT 0
mturner5 0:0d6b77c9ae01 4901 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
mturner5 0:0d6b77c9ae01 4902 /* STATUS Bit Fields */
mturner5 0:0d6b77c9ae01 4903 #define TPM_STATUS_CH0F_MASK 0x1u
mturner5 0:0d6b77c9ae01 4904 #define TPM_STATUS_CH0F_SHIFT 0
mturner5 0:0d6b77c9ae01 4905 #define TPM_STATUS_CH1F_MASK 0x2u
mturner5 0:0d6b77c9ae01 4906 #define TPM_STATUS_CH1F_SHIFT 1
mturner5 0:0d6b77c9ae01 4907 #define TPM_STATUS_CH2F_MASK 0x4u
mturner5 0:0d6b77c9ae01 4908 #define TPM_STATUS_CH2F_SHIFT 2
mturner5 0:0d6b77c9ae01 4909 #define TPM_STATUS_CH3F_MASK 0x8u
mturner5 0:0d6b77c9ae01 4910 #define TPM_STATUS_CH3F_SHIFT 3
mturner5 0:0d6b77c9ae01 4911 #define TPM_STATUS_CH4F_MASK 0x10u
mturner5 0:0d6b77c9ae01 4912 #define TPM_STATUS_CH4F_SHIFT 4
mturner5 0:0d6b77c9ae01 4913 #define TPM_STATUS_CH5F_MASK 0x20u
mturner5 0:0d6b77c9ae01 4914 #define TPM_STATUS_CH5F_SHIFT 5
mturner5 0:0d6b77c9ae01 4915 #define TPM_STATUS_TOF_MASK 0x100u
mturner5 0:0d6b77c9ae01 4916 #define TPM_STATUS_TOF_SHIFT 8
mturner5 0:0d6b77c9ae01 4917 /* CONF Bit Fields */
mturner5 0:0d6b77c9ae01 4918 #define TPM_CONF_DOZEEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 4919 #define TPM_CONF_DOZEEN_SHIFT 5
mturner5 0:0d6b77c9ae01 4920 #define TPM_CONF_DBGMODE_MASK 0xC0u
mturner5 0:0d6b77c9ae01 4921 #define TPM_CONF_DBGMODE_SHIFT 6
mturner5 0:0d6b77c9ae01 4922 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
mturner5 0:0d6b77c9ae01 4923 #define TPM_CONF_GTBEEN_MASK 0x200u
mturner5 0:0d6b77c9ae01 4924 #define TPM_CONF_GTBEEN_SHIFT 9
mturner5 0:0d6b77c9ae01 4925 #define TPM_CONF_CSOT_MASK 0x10000u
mturner5 0:0d6b77c9ae01 4926 #define TPM_CONF_CSOT_SHIFT 16
mturner5 0:0d6b77c9ae01 4927 #define TPM_CONF_CSOO_MASK 0x20000u
mturner5 0:0d6b77c9ae01 4928 #define TPM_CONF_CSOO_SHIFT 17
mturner5 0:0d6b77c9ae01 4929 #define TPM_CONF_CROT_MASK 0x40000u
mturner5 0:0d6b77c9ae01 4930 #define TPM_CONF_CROT_SHIFT 18
mturner5 0:0d6b77c9ae01 4931 #define TPM_CONF_TRGSEL_MASK 0xF000000u
mturner5 0:0d6b77c9ae01 4932 #define TPM_CONF_TRGSEL_SHIFT 24
mturner5 0:0d6b77c9ae01 4933 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
mturner5 0:0d6b77c9ae01 4934
mturner5 0:0d6b77c9ae01 4935 /*!
mturner5 0:0d6b77c9ae01 4936 * @}
mturner5 0:0d6b77c9ae01 4937 */ /* end of group TPM_Register_Masks */
mturner5 0:0d6b77c9ae01 4938
mturner5 0:0d6b77c9ae01 4939
mturner5 0:0d6b77c9ae01 4940 /* TPM - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 4941 /** Peripheral TPM0 base address */
mturner5 0:0d6b77c9ae01 4942 #define TPM0_BASE (0x40038000u)
mturner5 0:0d6b77c9ae01 4943 /** Peripheral TPM0 base pointer */
mturner5 0:0d6b77c9ae01 4944 #define TPM0 ((TPM_Type *)TPM0_BASE)
mturner5 0:0d6b77c9ae01 4945 /** Peripheral TPM1 base address */
mturner5 0:0d6b77c9ae01 4946 #define TPM1_BASE (0x40039000u)
mturner5 0:0d6b77c9ae01 4947 /** Peripheral TPM1 base pointer */
mturner5 0:0d6b77c9ae01 4948 #define TPM1 ((TPM_Type *)TPM1_BASE)
mturner5 0:0d6b77c9ae01 4949 /** Peripheral TPM2 base address */
mturner5 0:0d6b77c9ae01 4950 #define TPM2_BASE (0x4003A000u)
mturner5 0:0d6b77c9ae01 4951 /** Peripheral TPM2 base pointer */
mturner5 0:0d6b77c9ae01 4952 #define TPM2 ((TPM_Type *)TPM2_BASE)
mturner5 0:0d6b77c9ae01 4953 /** Array initializer of TPM peripheral base pointers */
mturner5 0:0d6b77c9ae01 4954 #define TPM_BASES { TPM0, TPM1, TPM2 }
mturner5 0:0d6b77c9ae01 4955
mturner5 0:0d6b77c9ae01 4956 /*!
mturner5 0:0d6b77c9ae01 4957 * @}
mturner5 0:0d6b77c9ae01 4958 */ /* end of group TPM_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 4959
mturner5 0:0d6b77c9ae01 4960
mturner5 0:0d6b77c9ae01 4961 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4962 -- TSI Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4963 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4964
mturner5 0:0d6b77c9ae01 4965 /*!
mturner5 0:0d6b77c9ae01 4966 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
mturner5 0:0d6b77c9ae01 4967 * @{
mturner5 0:0d6b77c9ae01 4968 */
mturner5 0:0d6b77c9ae01 4969
mturner5 0:0d6b77c9ae01 4970 /** TSI - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 4971 typedef struct {
mturner5 0:0d6b77c9ae01 4972 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 4973 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 4974 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 4975 } TSI_Type;
mturner5 0:0d6b77c9ae01 4976
mturner5 0:0d6b77c9ae01 4977 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 4978 -- TSI Register Masks
mturner5 0:0d6b77c9ae01 4979 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 4980
mturner5 0:0d6b77c9ae01 4981 /*!
mturner5 0:0d6b77c9ae01 4982 * @addtogroup TSI_Register_Masks TSI Register Masks
mturner5 0:0d6b77c9ae01 4983 * @{
mturner5 0:0d6b77c9ae01 4984 */
mturner5 0:0d6b77c9ae01 4985
mturner5 0:0d6b77c9ae01 4986 /* GENCS Bit Fields */
mturner5 0:0d6b77c9ae01 4987 #define TSI_GENCS_CURSW_MASK 0x2u
mturner5 0:0d6b77c9ae01 4988 #define TSI_GENCS_CURSW_SHIFT 1
mturner5 0:0d6b77c9ae01 4989 #define TSI_GENCS_EOSF_MASK 0x4u
mturner5 0:0d6b77c9ae01 4990 #define TSI_GENCS_EOSF_SHIFT 2
mturner5 0:0d6b77c9ae01 4991 #define TSI_GENCS_SCNIP_MASK 0x8u
mturner5 0:0d6b77c9ae01 4992 #define TSI_GENCS_SCNIP_SHIFT 3
mturner5 0:0d6b77c9ae01 4993 #define TSI_GENCS_STM_MASK 0x10u
mturner5 0:0d6b77c9ae01 4994 #define TSI_GENCS_STM_SHIFT 4
mturner5 0:0d6b77c9ae01 4995 #define TSI_GENCS_STPE_MASK 0x20u
mturner5 0:0d6b77c9ae01 4996 #define TSI_GENCS_STPE_SHIFT 5
mturner5 0:0d6b77c9ae01 4997 #define TSI_GENCS_TSIIEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 4998 #define TSI_GENCS_TSIIEN_SHIFT 6
mturner5 0:0d6b77c9ae01 4999 #define TSI_GENCS_TSIEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 5000 #define TSI_GENCS_TSIEN_SHIFT 7
mturner5 0:0d6b77c9ae01 5001 #define TSI_GENCS_NSCN_MASK 0x1F00u
mturner5 0:0d6b77c9ae01 5002 #define TSI_GENCS_NSCN_SHIFT 8
mturner5 0:0d6b77c9ae01 5003 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
mturner5 0:0d6b77c9ae01 5004 #define TSI_GENCS_PS_MASK 0xE000u
mturner5 0:0d6b77c9ae01 5005 #define TSI_GENCS_PS_SHIFT 13
mturner5 0:0d6b77c9ae01 5006 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
mturner5 0:0d6b77c9ae01 5007 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
mturner5 0:0d6b77c9ae01 5008 #define TSI_GENCS_EXTCHRG_SHIFT 16
mturner5 0:0d6b77c9ae01 5009 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
mturner5 0:0d6b77c9ae01 5010 #define TSI_GENCS_DVOLT_MASK 0x180000u
mturner5 0:0d6b77c9ae01 5011 #define TSI_GENCS_DVOLT_SHIFT 19
mturner5 0:0d6b77c9ae01 5012 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
mturner5 0:0d6b77c9ae01 5013 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
mturner5 0:0d6b77c9ae01 5014 #define TSI_GENCS_REFCHRG_SHIFT 21
mturner5 0:0d6b77c9ae01 5015 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
mturner5 0:0d6b77c9ae01 5016 #define TSI_GENCS_MODE_MASK 0xF000000u
mturner5 0:0d6b77c9ae01 5017 #define TSI_GENCS_MODE_SHIFT 24
mturner5 0:0d6b77c9ae01 5018 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
mturner5 0:0d6b77c9ae01 5019 #define TSI_GENCS_ESOR_MASK 0x10000000u
mturner5 0:0d6b77c9ae01 5020 #define TSI_GENCS_ESOR_SHIFT 28
mturner5 0:0d6b77c9ae01 5021 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
mturner5 0:0d6b77c9ae01 5022 #define TSI_GENCS_OUTRGF_SHIFT 31
mturner5 0:0d6b77c9ae01 5023 /* DATA Bit Fields */
mturner5 0:0d6b77c9ae01 5024 #define TSI_DATA_TSICNT_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 5025 #define TSI_DATA_TSICNT_SHIFT 0
mturner5 0:0d6b77c9ae01 5026 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
mturner5 0:0d6b77c9ae01 5027 #define TSI_DATA_SWTS_MASK 0x400000u
mturner5 0:0d6b77c9ae01 5028 #define TSI_DATA_SWTS_SHIFT 22
mturner5 0:0d6b77c9ae01 5029 #define TSI_DATA_DMAEN_MASK 0x800000u
mturner5 0:0d6b77c9ae01 5030 #define TSI_DATA_DMAEN_SHIFT 23
mturner5 0:0d6b77c9ae01 5031 #define TSI_DATA_TSICH_MASK 0xF0000000u
mturner5 0:0d6b77c9ae01 5032 #define TSI_DATA_TSICH_SHIFT 28
mturner5 0:0d6b77c9ae01 5033 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
mturner5 0:0d6b77c9ae01 5034 /* TSHD Bit Fields */
mturner5 0:0d6b77c9ae01 5035 #define TSI_TSHD_THRESL_MASK 0xFFFFu
mturner5 0:0d6b77c9ae01 5036 #define TSI_TSHD_THRESL_SHIFT 0
mturner5 0:0d6b77c9ae01 5037 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
mturner5 0:0d6b77c9ae01 5038 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
mturner5 0:0d6b77c9ae01 5039 #define TSI_TSHD_THRESH_SHIFT 16
mturner5 0:0d6b77c9ae01 5040 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
mturner5 0:0d6b77c9ae01 5041
mturner5 0:0d6b77c9ae01 5042 /*!
mturner5 0:0d6b77c9ae01 5043 * @}
mturner5 0:0d6b77c9ae01 5044 */ /* end of group TSI_Register_Masks */
mturner5 0:0d6b77c9ae01 5045
mturner5 0:0d6b77c9ae01 5046
mturner5 0:0d6b77c9ae01 5047 /* TSI - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 5048 /** Peripheral TSI0 base address */
mturner5 0:0d6b77c9ae01 5049 #define TSI0_BASE (0x40045000u)
mturner5 0:0d6b77c9ae01 5050 /** Peripheral TSI0 base pointer */
mturner5 0:0d6b77c9ae01 5051 #define TSI0 ((TSI_Type *)TSI0_BASE)
mturner5 0:0d6b77c9ae01 5052 /** Array initializer of TSI peripheral base pointers */
mturner5 0:0d6b77c9ae01 5053 #define TSI_BASES { TSI0 }
mturner5 0:0d6b77c9ae01 5054
mturner5 0:0d6b77c9ae01 5055 /*!
mturner5 0:0d6b77c9ae01 5056 * @}
mturner5 0:0d6b77c9ae01 5057 */ /* end of group TSI_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 5058
mturner5 0:0d6b77c9ae01 5059
mturner5 0:0d6b77c9ae01 5060 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5061 -- UART Peripheral Access Layer
mturner5 0:0d6b77c9ae01 5062 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5063
mturner5 0:0d6b77c9ae01 5064 /*!
mturner5 0:0d6b77c9ae01 5065 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mturner5 0:0d6b77c9ae01 5066 * @{
mturner5 0:0d6b77c9ae01 5067 */
mturner5 0:0d6b77c9ae01 5068
mturner5 0:0d6b77c9ae01 5069 /** UART - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 5070 typedef struct {
mturner5 0:0d6b77c9ae01 5071 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
mturner5 0:0d6b77c9ae01 5072 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
mturner5 0:0d6b77c9ae01 5073 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mturner5 0:0d6b77c9ae01 5074 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mturner5 0:0d6b77c9ae01 5075 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mturner5 0:0d6b77c9ae01 5076 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mturner5 0:0d6b77c9ae01 5077 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mturner5 0:0d6b77c9ae01 5078 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mturner5 0:0d6b77c9ae01 5079 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
mturner5 0:0d6b77c9ae01 5080 } UART_Type;
mturner5 0:0d6b77c9ae01 5081
mturner5 0:0d6b77c9ae01 5082 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5083 -- UART Register Masks
mturner5 0:0d6b77c9ae01 5084 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5085
mturner5 0:0d6b77c9ae01 5086 /*!
mturner5 0:0d6b77c9ae01 5087 * @addtogroup UART_Register_Masks UART Register Masks
mturner5 0:0d6b77c9ae01 5088 * @{
mturner5 0:0d6b77c9ae01 5089 */
mturner5 0:0d6b77c9ae01 5090
mturner5 0:0d6b77c9ae01 5091 /* BDH Bit Fields */
mturner5 0:0d6b77c9ae01 5092 #define UART_BDH_SBR_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 5093 #define UART_BDH_SBR_SHIFT 0
mturner5 0:0d6b77c9ae01 5094 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mturner5 0:0d6b77c9ae01 5095 #define UART_BDH_SBNS_MASK 0x20u
mturner5 0:0d6b77c9ae01 5096 #define UART_BDH_SBNS_SHIFT 5
mturner5 0:0d6b77c9ae01 5097 #define UART_BDH_RXEDGIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 5098 #define UART_BDH_RXEDGIE_SHIFT 6
mturner5 0:0d6b77c9ae01 5099 #define UART_BDH_LBKDIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5100 #define UART_BDH_LBKDIE_SHIFT 7
mturner5 0:0d6b77c9ae01 5101 /* BDL Bit Fields */
mturner5 0:0d6b77c9ae01 5102 #define UART_BDL_SBR_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5103 #define UART_BDL_SBR_SHIFT 0
mturner5 0:0d6b77c9ae01 5104 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mturner5 0:0d6b77c9ae01 5105 /* C1 Bit Fields */
mturner5 0:0d6b77c9ae01 5106 #define UART_C1_PT_MASK 0x1u
mturner5 0:0d6b77c9ae01 5107 #define UART_C1_PT_SHIFT 0
mturner5 0:0d6b77c9ae01 5108 #define UART_C1_PE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5109 #define UART_C1_PE_SHIFT 1
mturner5 0:0d6b77c9ae01 5110 #define UART_C1_ILT_MASK 0x4u
mturner5 0:0d6b77c9ae01 5111 #define UART_C1_ILT_SHIFT 2
mturner5 0:0d6b77c9ae01 5112 #define UART_C1_WAKE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5113 #define UART_C1_WAKE_SHIFT 3
mturner5 0:0d6b77c9ae01 5114 #define UART_C1_M_MASK 0x10u
mturner5 0:0d6b77c9ae01 5115 #define UART_C1_M_SHIFT 4
mturner5 0:0d6b77c9ae01 5116 #define UART_C1_RSRC_MASK 0x20u
mturner5 0:0d6b77c9ae01 5117 #define UART_C1_RSRC_SHIFT 5
mturner5 0:0d6b77c9ae01 5118 #define UART_C1_UARTSWAI_MASK 0x40u
mturner5 0:0d6b77c9ae01 5119 #define UART_C1_UARTSWAI_SHIFT 6
mturner5 0:0d6b77c9ae01 5120 #define UART_C1_LOOPS_MASK 0x80u
mturner5 0:0d6b77c9ae01 5121 #define UART_C1_LOOPS_SHIFT 7
mturner5 0:0d6b77c9ae01 5122 /* C2 Bit Fields */
mturner5 0:0d6b77c9ae01 5123 #define UART_C2_SBK_MASK 0x1u
mturner5 0:0d6b77c9ae01 5124 #define UART_C2_SBK_SHIFT 0
mturner5 0:0d6b77c9ae01 5125 #define UART_C2_RWU_MASK 0x2u
mturner5 0:0d6b77c9ae01 5126 #define UART_C2_RWU_SHIFT 1
mturner5 0:0d6b77c9ae01 5127 #define UART_C2_RE_MASK 0x4u
mturner5 0:0d6b77c9ae01 5128 #define UART_C2_RE_SHIFT 2
mturner5 0:0d6b77c9ae01 5129 #define UART_C2_TE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5130 #define UART_C2_TE_SHIFT 3
mturner5 0:0d6b77c9ae01 5131 #define UART_C2_ILIE_MASK 0x10u
mturner5 0:0d6b77c9ae01 5132 #define UART_C2_ILIE_SHIFT 4
mturner5 0:0d6b77c9ae01 5133 #define UART_C2_RIE_MASK 0x20u
mturner5 0:0d6b77c9ae01 5134 #define UART_C2_RIE_SHIFT 5
mturner5 0:0d6b77c9ae01 5135 #define UART_C2_TCIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 5136 #define UART_C2_TCIE_SHIFT 6
mturner5 0:0d6b77c9ae01 5137 #define UART_C2_TIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5138 #define UART_C2_TIE_SHIFT 7
mturner5 0:0d6b77c9ae01 5139 /* S1 Bit Fields */
mturner5 0:0d6b77c9ae01 5140 #define UART_S1_PF_MASK 0x1u
mturner5 0:0d6b77c9ae01 5141 #define UART_S1_PF_SHIFT 0
mturner5 0:0d6b77c9ae01 5142 #define UART_S1_FE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5143 #define UART_S1_FE_SHIFT 1
mturner5 0:0d6b77c9ae01 5144 #define UART_S1_NF_MASK 0x4u
mturner5 0:0d6b77c9ae01 5145 #define UART_S1_NF_SHIFT 2
mturner5 0:0d6b77c9ae01 5146 #define UART_S1_OR_MASK 0x8u
mturner5 0:0d6b77c9ae01 5147 #define UART_S1_OR_SHIFT 3
mturner5 0:0d6b77c9ae01 5148 #define UART_S1_IDLE_MASK 0x10u
mturner5 0:0d6b77c9ae01 5149 #define UART_S1_IDLE_SHIFT 4
mturner5 0:0d6b77c9ae01 5150 #define UART_S1_RDRF_MASK 0x20u
mturner5 0:0d6b77c9ae01 5151 #define UART_S1_RDRF_SHIFT 5
mturner5 0:0d6b77c9ae01 5152 #define UART_S1_TC_MASK 0x40u
mturner5 0:0d6b77c9ae01 5153 #define UART_S1_TC_SHIFT 6
mturner5 0:0d6b77c9ae01 5154 #define UART_S1_TDRE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5155 #define UART_S1_TDRE_SHIFT 7
mturner5 0:0d6b77c9ae01 5156 /* S2 Bit Fields */
mturner5 0:0d6b77c9ae01 5157 #define UART_S2_RAF_MASK 0x1u
mturner5 0:0d6b77c9ae01 5158 #define UART_S2_RAF_SHIFT 0
mturner5 0:0d6b77c9ae01 5159 #define UART_S2_LBKDE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5160 #define UART_S2_LBKDE_SHIFT 1
mturner5 0:0d6b77c9ae01 5161 #define UART_S2_BRK13_MASK 0x4u
mturner5 0:0d6b77c9ae01 5162 #define UART_S2_BRK13_SHIFT 2
mturner5 0:0d6b77c9ae01 5163 #define UART_S2_RWUID_MASK 0x8u
mturner5 0:0d6b77c9ae01 5164 #define UART_S2_RWUID_SHIFT 3
mturner5 0:0d6b77c9ae01 5165 #define UART_S2_RXINV_MASK 0x10u
mturner5 0:0d6b77c9ae01 5166 #define UART_S2_RXINV_SHIFT 4
mturner5 0:0d6b77c9ae01 5167 #define UART_S2_RXEDGIF_MASK 0x40u
mturner5 0:0d6b77c9ae01 5168 #define UART_S2_RXEDGIF_SHIFT 6
mturner5 0:0d6b77c9ae01 5169 #define UART_S2_LBKDIF_MASK 0x80u
mturner5 0:0d6b77c9ae01 5170 #define UART_S2_LBKDIF_SHIFT 7
mturner5 0:0d6b77c9ae01 5171 /* C3 Bit Fields */
mturner5 0:0d6b77c9ae01 5172 #define UART_C3_PEIE_MASK 0x1u
mturner5 0:0d6b77c9ae01 5173 #define UART_C3_PEIE_SHIFT 0
mturner5 0:0d6b77c9ae01 5174 #define UART_C3_FEIE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5175 #define UART_C3_FEIE_SHIFT 1
mturner5 0:0d6b77c9ae01 5176 #define UART_C3_NEIE_MASK 0x4u
mturner5 0:0d6b77c9ae01 5177 #define UART_C3_NEIE_SHIFT 2
mturner5 0:0d6b77c9ae01 5178 #define UART_C3_ORIE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5179 #define UART_C3_ORIE_SHIFT 3
mturner5 0:0d6b77c9ae01 5180 #define UART_C3_TXINV_MASK 0x10u
mturner5 0:0d6b77c9ae01 5181 #define UART_C3_TXINV_SHIFT 4
mturner5 0:0d6b77c9ae01 5182 #define UART_C3_TXDIR_MASK 0x20u
mturner5 0:0d6b77c9ae01 5183 #define UART_C3_TXDIR_SHIFT 5
mturner5 0:0d6b77c9ae01 5184 #define UART_C3_T8_MASK 0x40u
mturner5 0:0d6b77c9ae01 5185 #define UART_C3_T8_SHIFT 6
mturner5 0:0d6b77c9ae01 5186 #define UART_C3_R8_MASK 0x80u
mturner5 0:0d6b77c9ae01 5187 #define UART_C3_R8_SHIFT 7
mturner5 0:0d6b77c9ae01 5188 /* D Bit Fields */
mturner5 0:0d6b77c9ae01 5189 #define UART_D_R0T0_MASK 0x1u
mturner5 0:0d6b77c9ae01 5190 #define UART_D_R0T0_SHIFT 0
mturner5 0:0d6b77c9ae01 5191 #define UART_D_R1T1_MASK 0x2u
mturner5 0:0d6b77c9ae01 5192 #define UART_D_R1T1_SHIFT 1
mturner5 0:0d6b77c9ae01 5193 #define UART_D_R2T2_MASK 0x4u
mturner5 0:0d6b77c9ae01 5194 #define UART_D_R2T2_SHIFT 2
mturner5 0:0d6b77c9ae01 5195 #define UART_D_R3T3_MASK 0x8u
mturner5 0:0d6b77c9ae01 5196 #define UART_D_R3T3_SHIFT 3
mturner5 0:0d6b77c9ae01 5197 #define UART_D_R4T4_MASK 0x10u
mturner5 0:0d6b77c9ae01 5198 #define UART_D_R4T4_SHIFT 4
mturner5 0:0d6b77c9ae01 5199 #define UART_D_R5T5_MASK 0x20u
mturner5 0:0d6b77c9ae01 5200 #define UART_D_R5T5_SHIFT 5
mturner5 0:0d6b77c9ae01 5201 #define UART_D_R6T6_MASK 0x40u
mturner5 0:0d6b77c9ae01 5202 #define UART_D_R6T6_SHIFT 6
mturner5 0:0d6b77c9ae01 5203 #define UART_D_R7T7_MASK 0x80u
mturner5 0:0d6b77c9ae01 5204 #define UART_D_R7T7_SHIFT 7
mturner5 0:0d6b77c9ae01 5205 /* C4 Bit Fields */
mturner5 0:0d6b77c9ae01 5206 #define UART_C4_RDMAS_MASK 0x20u
mturner5 0:0d6b77c9ae01 5207 #define UART_C4_RDMAS_SHIFT 5
mturner5 0:0d6b77c9ae01 5208 #define UART_C4_TDMAS_MASK 0x80u
mturner5 0:0d6b77c9ae01 5209 #define UART_C4_TDMAS_SHIFT 7
mturner5 0:0d6b77c9ae01 5210
mturner5 0:0d6b77c9ae01 5211 /*!
mturner5 0:0d6b77c9ae01 5212 * @}
mturner5 0:0d6b77c9ae01 5213 */ /* end of group UART_Register_Masks */
mturner5 0:0d6b77c9ae01 5214
mturner5 0:0d6b77c9ae01 5215
mturner5 0:0d6b77c9ae01 5216 /* UART - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 5217 /** Peripheral UART1 base address */
mturner5 0:0d6b77c9ae01 5218 #define UART1_BASE (0x4006B000u)
mturner5 0:0d6b77c9ae01 5219 /** Peripheral UART1 base pointer */
mturner5 0:0d6b77c9ae01 5220 #define UART1 ((UART_Type *)UART1_BASE)
mturner5 0:0d6b77c9ae01 5221 /** Peripheral UART2 base address */
mturner5 0:0d6b77c9ae01 5222 #define UART2_BASE (0x4006C000u)
mturner5 0:0d6b77c9ae01 5223 /** Peripheral UART2 base pointer */
mturner5 0:0d6b77c9ae01 5224 #define UART2 ((UART_Type *)UART2_BASE)
mturner5 0:0d6b77c9ae01 5225 /** Array initializer of UART peripheral base pointers */
mturner5 0:0d6b77c9ae01 5226 #define UART_BASES { UART1, UART2 }
mturner5 0:0d6b77c9ae01 5227
mturner5 0:0d6b77c9ae01 5228 /*!
mturner5 0:0d6b77c9ae01 5229 * @}
mturner5 0:0d6b77c9ae01 5230 */ /* end of group UART_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 5231
mturner5 0:0d6b77c9ae01 5232
mturner5 0:0d6b77c9ae01 5233 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5234 -- UART0 Peripheral Access Layer
mturner5 0:0d6b77c9ae01 5235 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5236
mturner5 0:0d6b77c9ae01 5237 /*!
mturner5 0:0d6b77c9ae01 5238 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
mturner5 0:0d6b77c9ae01 5239 * @{
mturner5 0:0d6b77c9ae01 5240 */
mturner5 0:0d6b77c9ae01 5241
mturner5 0:0d6b77c9ae01 5242 /** UART0 - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 5243 typedef struct {
mturner5 0:0d6b77c9ae01 5244 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
mturner5 0:0d6b77c9ae01 5245 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
mturner5 0:0d6b77c9ae01 5246 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mturner5 0:0d6b77c9ae01 5247 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mturner5 0:0d6b77c9ae01 5248 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mturner5 0:0d6b77c9ae01 5249 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mturner5 0:0d6b77c9ae01 5250 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mturner5 0:0d6b77c9ae01 5251 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mturner5 0:0d6b77c9ae01 5252 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mturner5 0:0d6b77c9ae01 5253 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mturner5 0:0d6b77c9ae01 5254 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mturner5 0:0d6b77c9ae01 5255 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mturner5 0:0d6b77c9ae01 5256 } UART0_Type;
mturner5 0:0d6b77c9ae01 5257
mturner5 0:0d6b77c9ae01 5258 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5259 -- UART0 Register Masks
mturner5 0:0d6b77c9ae01 5260 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5261
mturner5 0:0d6b77c9ae01 5262 /*!
mturner5 0:0d6b77c9ae01 5263 * @addtogroup UART0_Register_Masks UART0 Register Masks
mturner5 0:0d6b77c9ae01 5264 * @{
mturner5 0:0d6b77c9ae01 5265 */
mturner5 0:0d6b77c9ae01 5266
mturner5 0:0d6b77c9ae01 5267 /* BDH Bit Fields */
mturner5 0:0d6b77c9ae01 5268 #define UART0_BDH_SBR_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 5269 #define UART0_BDH_SBR_SHIFT 0
mturner5 0:0d6b77c9ae01 5270 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
mturner5 0:0d6b77c9ae01 5271 #define UART0_BDH_SBNS_MASK 0x20u
mturner5 0:0d6b77c9ae01 5272 #define UART0_BDH_SBNS_SHIFT 5
mturner5 0:0d6b77c9ae01 5273 #define UART0_BDH_RXEDGIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 5274 #define UART0_BDH_RXEDGIE_SHIFT 6
mturner5 0:0d6b77c9ae01 5275 #define UART0_BDH_LBKDIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5276 #define UART0_BDH_LBKDIE_SHIFT 7
mturner5 0:0d6b77c9ae01 5277 /* BDL Bit Fields */
mturner5 0:0d6b77c9ae01 5278 #define UART0_BDL_SBR_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5279 #define UART0_BDL_SBR_SHIFT 0
mturner5 0:0d6b77c9ae01 5280 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
mturner5 0:0d6b77c9ae01 5281 /* C1 Bit Fields */
mturner5 0:0d6b77c9ae01 5282 #define UART0_C1_PT_MASK 0x1u
mturner5 0:0d6b77c9ae01 5283 #define UART0_C1_PT_SHIFT 0
mturner5 0:0d6b77c9ae01 5284 #define UART0_C1_PE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5285 #define UART0_C1_PE_SHIFT 1
mturner5 0:0d6b77c9ae01 5286 #define UART0_C1_ILT_MASK 0x4u
mturner5 0:0d6b77c9ae01 5287 #define UART0_C1_ILT_SHIFT 2
mturner5 0:0d6b77c9ae01 5288 #define UART0_C1_WAKE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5289 #define UART0_C1_WAKE_SHIFT 3
mturner5 0:0d6b77c9ae01 5290 #define UART0_C1_M_MASK 0x10u
mturner5 0:0d6b77c9ae01 5291 #define UART0_C1_M_SHIFT 4
mturner5 0:0d6b77c9ae01 5292 #define UART0_C1_RSRC_MASK 0x20u
mturner5 0:0d6b77c9ae01 5293 #define UART0_C1_RSRC_SHIFT 5
mturner5 0:0d6b77c9ae01 5294 #define UART0_C1_DOZEEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 5295 #define UART0_C1_DOZEEN_SHIFT 6
mturner5 0:0d6b77c9ae01 5296 #define UART0_C1_LOOPS_MASK 0x80u
mturner5 0:0d6b77c9ae01 5297 #define UART0_C1_LOOPS_SHIFT 7
mturner5 0:0d6b77c9ae01 5298 /* C2 Bit Fields */
mturner5 0:0d6b77c9ae01 5299 #define UART0_C2_SBK_MASK 0x1u
mturner5 0:0d6b77c9ae01 5300 #define UART0_C2_SBK_SHIFT 0
mturner5 0:0d6b77c9ae01 5301 #define UART0_C2_RWU_MASK 0x2u
mturner5 0:0d6b77c9ae01 5302 #define UART0_C2_RWU_SHIFT 1
mturner5 0:0d6b77c9ae01 5303 #define UART0_C2_RE_MASK 0x4u
mturner5 0:0d6b77c9ae01 5304 #define UART0_C2_RE_SHIFT 2
mturner5 0:0d6b77c9ae01 5305 #define UART0_C2_TE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5306 #define UART0_C2_TE_SHIFT 3
mturner5 0:0d6b77c9ae01 5307 #define UART0_C2_ILIE_MASK 0x10u
mturner5 0:0d6b77c9ae01 5308 #define UART0_C2_ILIE_SHIFT 4
mturner5 0:0d6b77c9ae01 5309 #define UART0_C2_RIE_MASK 0x20u
mturner5 0:0d6b77c9ae01 5310 #define UART0_C2_RIE_SHIFT 5
mturner5 0:0d6b77c9ae01 5311 #define UART0_C2_TCIE_MASK 0x40u
mturner5 0:0d6b77c9ae01 5312 #define UART0_C2_TCIE_SHIFT 6
mturner5 0:0d6b77c9ae01 5313 #define UART0_C2_TIE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5314 #define UART0_C2_TIE_SHIFT 7
mturner5 0:0d6b77c9ae01 5315 /* S1 Bit Fields */
mturner5 0:0d6b77c9ae01 5316 #define UART0_S1_PF_MASK 0x1u
mturner5 0:0d6b77c9ae01 5317 #define UART0_S1_PF_SHIFT 0
mturner5 0:0d6b77c9ae01 5318 #define UART0_S1_FE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5319 #define UART0_S1_FE_SHIFT 1
mturner5 0:0d6b77c9ae01 5320 #define UART0_S1_NF_MASK 0x4u
mturner5 0:0d6b77c9ae01 5321 #define UART0_S1_NF_SHIFT 2
mturner5 0:0d6b77c9ae01 5322 #define UART0_S1_OR_MASK 0x8u
mturner5 0:0d6b77c9ae01 5323 #define UART0_S1_OR_SHIFT 3
mturner5 0:0d6b77c9ae01 5324 #define UART0_S1_IDLE_MASK 0x10u
mturner5 0:0d6b77c9ae01 5325 #define UART0_S1_IDLE_SHIFT 4
mturner5 0:0d6b77c9ae01 5326 #define UART0_S1_RDRF_MASK 0x20u
mturner5 0:0d6b77c9ae01 5327 #define UART0_S1_RDRF_SHIFT 5
mturner5 0:0d6b77c9ae01 5328 #define UART0_S1_TC_MASK 0x40u
mturner5 0:0d6b77c9ae01 5329 #define UART0_S1_TC_SHIFT 6
mturner5 0:0d6b77c9ae01 5330 #define UART0_S1_TDRE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5331 #define UART0_S1_TDRE_SHIFT 7
mturner5 0:0d6b77c9ae01 5332 /* S2 Bit Fields */
mturner5 0:0d6b77c9ae01 5333 #define UART0_S2_RAF_MASK 0x1u
mturner5 0:0d6b77c9ae01 5334 #define UART0_S2_RAF_SHIFT 0
mturner5 0:0d6b77c9ae01 5335 #define UART0_S2_LBKDE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5336 #define UART0_S2_LBKDE_SHIFT 1
mturner5 0:0d6b77c9ae01 5337 #define UART0_S2_BRK13_MASK 0x4u
mturner5 0:0d6b77c9ae01 5338 #define UART0_S2_BRK13_SHIFT 2
mturner5 0:0d6b77c9ae01 5339 #define UART0_S2_RWUID_MASK 0x8u
mturner5 0:0d6b77c9ae01 5340 #define UART0_S2_RWUID_SHIFT 3
mturner5 0:0d6b77c9ae01 5341 #define UART0_S2_RXINV_MASK 0x10u
mturner5 0:0d6b77c9ae01 5342 #define UART0_S2_RXINV_SHIFT 4
mturner5 0:0d6b77c9ae01 5343 #define UART0_S2_MSBF_MASK 0x20u
mturner5 0:0d6b77c9ae01 5344 #define UART0_S2_MSBF_SHIFT 5
mturner5 0:0d6b77c9ae01 5345 #define UART0_S2_RXEDGIF_MASK 0x40u
mturner5 0:0d6b77c9ae01 5346 #define UART0_S2_RXEDGIF_SHIFT 6
mturner5 0:0d6b77c9ae01 5347 #define UART0_S2_LBKDIF_MASK 0x80u
mturner5 0:0d6b77c9ae01 5348 #define UART0_S2_LBKDIF_SHIFT 7
mturner5 0:0d6b77c9ae01 5349 /* C3 Bit Fields */
mturner5 0:0d6b77c9ae01 5350 #define UART0_C3_PEIE_MASK 0x1u
mturner5 0:0d6b77c9ae01 5351 #define UART0_C3_PEIE_SHIFT 0
mturner5 0:0d6b77c9ae01 5352 #define UART0_C3_FEIE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5353 #define UART0_C3_FEIE_SHIFT 1
mturner5 0:0d6b77c9ae01 5354 #define UART0_C3_NEIE_MASK 0x4u
mturner5 0:0d6b77c9ae01 5355 #define UART0_C3_NEIE_SHIFT 2
mturner5 0:0d6b77c9ae01 5356 #define UART0_C3_ORIE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5357 #define UART0_C3_ORIE_SHIFT 3
mturner5 0:0d6b77c9ae01 5358 #define UART0_C3_TXINV_MASK 0x10u
mturner5 0:0d6b77c9ae01 5359 #define UART0_C3_TXINV_SHIFT 4
mturner5 0:0d6b77c9ae01 5360 #define UART0_C3_TXDIR_MASK 0x20u
mturner5 0:0d6b77c9ae01 5361 #define UART0_C3_TXDIR_SHIFT 5
mturner5 0:0d6b77c9ae01 5362 #define UART0_C3_R9T8_MASK 0x40u
mturner5 0:0d6b77c9ae01 5363 #define UART0_C3_R9T8_SHIFT 6
mturner5 0:0d6b77c9ae01 5364 #define UART0_C3_R8T9_MASK 0x80u
mturner5 0:0d6b77c9ae01 5365 #define UART0_C3_R8T9_SHIFT 7
mturner5 0:0d6b77c9ae01 5366 /* D Bit Fields */
mturner5 0:0d6b77c9ae01 5367 #define UART0_D_R0T0_MASK 0x1u
mturner5 0:0d6b77c9ae01 5368 #define UART0_D_R0T0_SHIFT 0
mturner5 0:0d6b77c9ae01 5369 #define UART0_D_R1T1_MASK 0x2u
mturner5 0:0d6b77c9ae01 5370 #define UART0_D_R1T1_SHIFT 1
mturner5 0:0d6b77c9ae01 5371 #define UART0_D_R2T2_MASK 0x4u
mturner5 0:0d6b77c9ae01 5372 #define UART0_D_R2T2_SHIFT 2
mturner5 0:0d6b77c9ae01 5373 #define UART0_D_R3T3_MASK 0x8u
mturner5 0:0d6b77c9ae01 5374 #define UART0_D_R3T3_SHIFT 3
mturner5 0:0d6b77c9ae01 5375 #define UART0_D_R4T4_MASK 0x10u
mturner5 0:0d6b77c9ae01 5376 #define UART0_D_R4T4_SHIFT 4
mturner5 0:0d6b77c9ae01 5377 #define UART0_D_R5T5_MASK 0x20u
mturner5 0:0d6b77c9ae01 5378 #define UART0_D_R5T5_SHIFT 5
mturner5 0:0d6b77c9ae01 5379 #define UART0_D_R6T6_MASK 0x40u
mturner5 0:0d6b77c9ae01 5380 #define UART0_D_R6T6_SHIFT 6
mturner5 0:0d6b77c9ae01 5381 #define UART0_D_R7T7_MASK 0x80u
mturner5 0:0d6b77c9ae01 5382 #define UART0_D_R7T7_SHIFT 7
mturner5 0:0d6b77c9ae01 5383 /* MA1 Bit Fields */
mturner5 0:0d6b77c9ae01 5384 #define UART0_MA1_MA_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5385 #define UART0_MA1_MA_SHIFT 0
mturner5 0:0d6b77c9ae01 5386 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
mturner5 0:0d6b77c9ae01 5387 /* MA2 Bit Fields */
mturner5 0:0d6b77c9ae01 5388 #define UART0_MA2_MA_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5389 #define UART0_MA2_MA_SHIFT 0
mturner5 0:0d6b77c9ae01 5390 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
mturner5 0:0d6b77c9ae01 5391 /* C4 Bit Fields */
mturner5 0:0d6b77c9ae01 5392 #define UART0_C4_OSR_MASK 0x1Fu
mturner5 0:0d6b77c9ae01 5393 #define UART0_C4_OSR_SHIFT 0
mturner5 0:0d6b77c9ae01 5394 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
mturner5 0:0d6b77c9ae01 5395 #define UART0_C4_M10_MASK 0x20u
mturner5 0:0d6b77c9ae01 5396 #define UART0_C4_M10_SHIFT 5
mturner5 0:0d6b77c9ae01 5397 #define UART0_C4_MAEN2_MASK 0x40u
mturner5 0:0d6b77c9ae01 5398 #define UART0_C4_MAEN2_SHIFT 6
mturner5 0:0d6b77c9ae01 5399 #define UART0_C4_MAEN1_MASK 0x80u
mturner5 0:0d6b77c9ae01 5400 #define UART0_C4_MAEN1_SHIFT 7
mturner5 0:0d6b77c9ae01 5401 /* C5 Bit Fields */
mturner5 0:0d6b77c9ae01 5402 #define UART0_C5_RESYNCDIS_MASK 0x1u
mturner5 0:0d6b77c9ae01 5403 #define UART0_C5_RESYNCDIS_SHIFT 0
mturner5 0:0d6b77c9ae01 5404 #define UART0_C5_BOTHEDGE_MASK 0x2u
mturner5 0:0d6b77c9ae01 5405 #define UART0_C5_BOTHEDGE_SHIFT 1
mturner5 0:0d6b77c9ae01 5406 #define UART0_C5_RDMAE_MASK 0x20u
mturner5 0:0d6b77c9ae01 5407 #define UART0_C5_RDMAE_SHIFT 5
mturner5 0:0d6b77c9ae01 5408 #define UART0_C5_TDMAE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5409 #define UART0_C5_TDMAE_SHIFT 7
mturner5 0:0d6b77c9ae01 5410
mturner5 0:0d6b77c9ae01 5411 /*!
mturner5 0:0d6b77c9ae01 5412 * @}
mturner5 0:0d6b77c9ae01 5413 */ /* end of group UART0_Register_Masks */
mturner5 0:0d6b77c9ae01 5414
mturner5 0:0d6b77c9ae01 5415
mturner5 0:0d6b77c9ae01 5416 /* UART0 - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 5417 /** Peripheral UART0 base address */
mturner5 0:0d6b77c9ae01 5418 #define UART0_BASE (0x4006A000u)
mturner5 0:0d6b77c9ae01 5419 /** Peripheral UART0 base pointer */
mturner5 0:0d6b77c9ae01 5420 #define UART0 ((UART0_Type *)UART0_BASE)
mturner5 0:0d6b77c9ae01 5421 /** Array initializer of UART0 peripheral base pointers */
mturner5 0:0d6b77c9ae01 5422 #define UART0_BASES { UART0 }
mturner5 0:0d6b77c9ae01 5423
mturner5 0:0d6b77c9ae01 5424 /*!
mturner5 0:0d6b77c9ae01 5425 * @}
mturner5 0:0d6b77c9ae01 5426 */ /* end of group UART0_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 5427
mturner5 0:0d6b77c9ae01 5428
mturner5 0:0d6b77c9ae01 5429 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5430 -- USB Peripheral Access Layer
mturner5 0:0d6b77c9ae01 5431 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5432
mturner5 0:0d6b77c9ae01 5433 /*!
mturner5 0:0d6b77c9ae01 5434 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mturner5 0:0d6b77c9ae01 5435 * @{
mturner5 0:0d6b77c9ae01 5436 */
mturner5 0:0d6b77c9ae01 5437
mturner5 0:0d6b77c9ae01 5438 /** USB - Register Layout Typedef */
mturner5 0:0d6b77c9ae01 5439 typedef struct {
mturner5 0:0d6b77c9ae01 5440 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mturner5 0:0d6b77c9ae01 5441 uint8_t RESERVED_0[3];
mturner5 0:0d6b77c9ae01 5442 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mturner5 0:0d6b77c9ae01 5443 uint8_t RESERVED_1[3];
mturner5 0:0d6b77c9ae01 5444 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mturner5 0:0d6b77c9ae01 5445 uint8_t RESERVED_2[3];
mturner5 0:0d6b77c9ae01 5446 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mturner5 0:0d6b77c9ae01 5447 uint8_t RESERVED_3[3];
mturner5 0:0d6b77c9ae01 5448 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
mturner5 0:0d6b77c9ae01 5449 uint8_t RESERVED_4[3];
mturner5 0:0d6b77c9ae01 5450 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
mturner5 0:0d6b77c9ae01 5451 uint8_t RESERVED_5[3];
mturner5 0:0d6b77c9ae01 5452 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
mturner5 0:0d6b77c9ae01 5453 uint8_t RESERVED_6[3];
mturner5 0:0d6b77c9ae01 5454 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mturner5 0:0d6b77c9ae01 5455 uint8_t RESERVED_7[99];
mturner5 0:0d6b77c9ae01 5456 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mturner5 0:0d6b77c9ae01 5457 uint8_t RESERVED_8[3];
mturner5 0:0d6b77c9ae01 5458 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mturner5 0:0d6b77c9ae01 5459 uint8_t RESERVED_9[3];
mturner5 0:0d6b77c9ae01 5460 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mturner5 0:0d6b77c9ae01 5461 uint8_t RESERVED_10[3];
mturner5 0:0d6b77c9ae01 5462 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mturner5 0:0d6b77c9ae01 5463 uint8_t RESERVED_11[3];
mturner5 0:0d6b77c9ae01 5464 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mturner5 0:0d6b77c9ae01 5465 uint8_t RESERVED_12[3];
mturner5 0:0d6b77c9ae01 5466 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mturner5 0:0d6b77c9ae01 5467 uint8_t RESERVED_13[3];
mturner5 0:0d6b77c9ae01 5468 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mturner5 0:0d6b77c9ae01 5469 uint8_t RESERVED_14[3];
mturner5 0:0d6b77c9ae01 5470 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
mturner5 0:0d6b77c9ae01 5471 uint8_t RESERVED_15[3];
mturner5 0:0d6b77c9ae01 5472 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
mturner5 0:0d6b77c9ae01 5473 uint8_t RESERVED_16[3];
mturner5 0:0d6b77c9ae01 5474 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
mturner5 0:0d6b77c9ae01 5475 uint8_t RESERVED_17[3];
mturner5 0:0d6b77c9ae01 5476 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
mturner5 0:0d6b77c9ae01 5477 uint8_t RESERVED_18[3];
mturner5 0:0d6b77c9ae01 5478 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
mturner5 0:0d6b77c9ae01 5479 uint8_t RESERVED_19[3];
mturner5 0:0d6b77c9ae01 5480 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mturner5 0:0d6b77c9ae01 5481 uint8_t RESERVED_20[3];
mturner5 0:0d6b77c9ae01 5482 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mturner5 0:0d6b77c9ae01 5483 uint8_t RESERVED_21[11];
mturner5 0:0d6b77c9ae01 5484 struct { /* offset: 0xC0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 5485 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mturner5 0:0d6b77c9ae01 5486 uint8_t RESERVED_0[3];
mturner5 0:0d6b77c9ae01 5487 } ENDPOINT[16];
mturner5 0:0d6b77c9ae01 5488 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mturner5 0:0d6b77c9ae01 5489 uint8_t RESERVED_22[3];
mturner5 0:0d6b77c9ae01 5490 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mturner5 0:0d6b77c9ae01 5491 uint8_t RESERVED_23[3];
mturner5 0:0d6b77c9ae01 5492 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mturner5 0:0d6b77c9ae01 5493 uint8_t RESERVED_24[3];
mturner5 0:0d6b77c9ae01 5494 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
mturner5 0:0d6b77c9ae01 5495 uint8_t RESERVED_25[7];
mturner5 0:0d6b77c9ae01 5496 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mturner5 0:0d6b77c9ae01 5497 } USB_Type;
mturner5 0:0d6b77c9ae01 5498
mturner5 0:0d6b77c9ae01 5499 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5500 -- USB Register Masks
mturner5 0:0d6b77c9ae01 5501 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5502
mturner5 0:0d6b77c9ae01 5503 /*!
mturner5 0:0d6b77c9ae01 5504 * @addtogroup USB_Register_Masks USB Register Masks
mturner5 0:0d6b77c9ae01 5505 * @{
mturner5 0:0d6b77c9ae01 5506 */
mturner5 0:0d6b77c9ae01 5507
mturner5 0:0d6b77c9ae01 5508 /* PERID Bit Fields */
mturner5 0:0d6b77c9ae01 5509 #define USB_PERID_ID_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 5510 #define USB_PERID_ID_SHIFT 0
mturner5 0:0d6b77c9ae01 5511 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mturner5 0:0d6b77c9ae01 5512 /* IDCOMP Bit Fields */
mturner5 0:0d6b77c9ae01 5513 #define USB_IDCOMP_NID_MASK 0x3Fu
mturner5 0:0d6b77c9ae01 5514 #define USB_IDCOMP_NID_SHIFT 0
mturner5 0:0d6b77c9ae01 5515 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mturner5 0:0d6b77c9ae01 5516 /* REV Bit Fields */
mturner5 0:0d6b77c9ae01 5517 #define USB_REV_REV_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5518 #define USB_REV_REV_SHIFT 0
mturner5 0:0d6b77c9ae01 5519 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mturner5 0:0d6b77c9ae01 5520 /* ADDINFO Bit Fields */
mturner5 0:0d6b77c9ae01 5521 #define USB_ADDINFO_IEHOST_MASK 0x1u
mturner5 0:0d6b77c9ae01 5522 #define USB_ADDINFO_IEHOST_SHIFT 0
mturner5 0:0d6b77c9ae01 5523 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
mturner5 0:0d6b77c9ae01 5524 #define USB_ADDINFO_IRQNUM_SHIFT 3
mturner5 0:0d6b77c9ae01 5525 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
mturner5 0:0d6b77c9ae01 5526 /* OTGISTAT Bit Fields */
mturner5 0:0d6b77c9ae01 5527 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
mturner5 0:0d6b77c9ae01 5528 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
mturner5 0:0d6b77c9ae01 5529 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
mturner5 0:0d6b77c9ae01 5530 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
mturner5 0:0d6b77c9ae01 5531 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
mturner5 0:0d6b77c9ae01 5532 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
mturner5 0:0d6b77c9ae01 5533 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
mturner5 0:0d6b77c9ae01 5534 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
mturner5 0:0d6b77c9ae01 5535 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
mturner5 0:0d6b77c9ae01 5536 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
mturner5 0:0d6b77c9ae01 5537 #define USB_OTGISTAT_IDCHG_MASK 0x80u
mturner5 0:0d6b77c9ae01 5538 #define USB_OTGISTAT_IDCHG_SHIFT 7
mturner5 0:0d6b77c9ae01 5539 /* OTGICR Bit Fields */
mturner5 0:0d6b77c9ae01 5540 #define USB_OTGICR_AVBUSEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 5541 #define USB_OTGICR_AVBUSEN_SHIFT 0
mturner5 0:0d6b77c9ae01 5542 #define USB_OTGICR_BSESSEN_MASK 0x4u
mturner5 0:0d6b77c9ae01 5543 #define USB_OTGICR_BSESSEN_SHIFT 2
mturner5 0:0d6b77c9ae01 5544 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 5545 #define USB_OTGICR_SESSVLDEN_SHIFT 3
mturner5 0:0d6b77c9ae01 5546 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 5547 #define USB_OTGICR_LINESTATEEN_SHIFT 5
mturner5 0:0d6b77c9ae01 5548 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 5549 #define USB_OTGICR_ONEMSECEN_SHIFT 6
mturner5 0:0d6b77c9ae01 5550 #define USB_OTGICR_IDEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 5551 #define USB_OTGICR_IDEN_SHIFT 7
mturner5 0:0d6b77c9ae01 5552 /* OTGSTAT Bit Fields */
mturner5 0:0d6b77c9ae01 5553 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
mturner5 0:0d6b77c9ae01 5554 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
mturner5 0:0d6b77c9ae01 5555 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
mturner5 0:0d6b77c9ae01 5556 #define USB_OTGSTAT_BSESSEND_SHIFT 2
mturner5 0:0d6b77c9ae01 5557 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
mturner5 0:0d6b77c9ae01 5558 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
mturner5 0:0d6b77c9ae01 5559 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
mturner5 0:0d6b77c9ae01 5560 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
mturner5 0:0d6b77c9ae01 5561 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 5562 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
mturner5 0:0d6b77c9ae01 5563 #define USB_OTGSTAT_ID_MASK 0x80u
mturner5 0:0d6b77c9ae01 5564 #define USB_OTGSTAT_ID_SHIFT 7
mturner5 0:0d6b77c9ae01 5565 /* OTGCTL Bit Fields */
mturner5 0:0d6b77c9ae01 5566 #define USB_OTGCTL_OTGEN_MASK 0x4u
mturner5 0:0d6b77c9ae01 5567 #define USB_OTGCTL_OTGEN_SHIFT 2
mturner5 0:0d6b77c9ae01 5568 #define USB_OTGCTL_DMLOW_MASK 0x10u
mturner5 0:0d6b77c9ae01 5569 #define USB_OTGCTL_DMLOW_SHIFT 4
mturner5 0:0d6b77c9ae01 5570 #define USB_OTGCTL_DPLOW_MASK 0x20u
mturner5 0:0d6b77c9ae01 5571 #define USB_OTGCTL_DPLOW_SHIFT 5
mturner5 0:0d6b77c9ae01 5572 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mturner5 0:0d6b77c9ae01 5573 #define USB_OTGCTL_DPHIGH_SHIFT 7
mturner5 0:0d6b77c9ae01 5574 /* ISTAT Bit Fields */
mturner5 0:0d6b77c9ae01 5575 #define USB_ISTAT_USBRST_MASK 0x1u
mturner5 0:0d6b77c9ae01 5576 #define USB_ISTAT_USBRST_SHIFT 0
mturner5 0:0d6b77c9ae01 5577 #define USB_ISTAT_ERROR_MASK 0x2u
mturner5 0:0d6b77c9ae01 5578 #define USB_ISTAT_ERROR_SHIFT 1
mturner5 0:0d6b77c9ae01 5579 #define USB_ISTAT_SOFTOK_MASK 0x4u
mturner5 0:0d6b77c9ae01 5580 #define USB_ISTAT_SOFTOK_SHIFT 2
mturner5 0:0d6b77c9ae01 5581 #define USB_ISTAT_TOKDNE_MASK 0x8u
mturner5 0:0d6b77c9ae01 5582 #define USB_ISTAT_TOKDNE_SHIFT 3
mturner5 0:0d6b77c9ae01 5583 #define USB_ISTAT_SLEEP_MASK 0x10u
mturner5 0:0d6b77c9ae01 5584 #define USB_ISTAT_SLEEP_SHIFT 4
mturner5 0:0d6b77c9ae01 5585 #define USB_ISTAT_RESUME_MASK 0x20u
mturner5 0:0d6b77c9ae01 5586 #define USB_ISTAT_RESUME_SHIFT 5
mturner5 0:0d6b77c9ae01 5587 #define USB_ISTAT_ATTACH_MASK 0x40u
mturner5 0:0d6b77c9ae01 5588 #define USB_ISTAT_ATTACH_SHIFT 6
mturner5 0:0d6b77c9ae01 5589 #define USB_ISTAT_STALL_MASK 0x80u
mturner5 0:0d6b77c9ae01 5590 #define USB_ISTAT_STALL_SHIFT 7
mturner5 0:0d6b77c9ae01 5591 /* INTEN Bit Fields */
mturner5 0:0d6b77c9ae01 5592 #define USB_INTEN_USBRSTEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 5593 #define USB_INTEN_USBRSTEN_SHIFT 0
mturner5 0:0d6b77c9ae01 5594 #define USB_INTEN_ERROREN_MASK 0x2u
mturner5 0:0d6b77c9ae01 5595 #define USB_INTEN_ERROREN_SHIFT 1
mturner5 0:0d6b77c9ae01 5596 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mturner5 0:0d6b77c9ae01 5597 #define USB_INTEN_SOFTOKEN_SHIFT 2
mturner5 0:0d6b77c9ae01 5598 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 5599 #define USB_INTEN_TOKDNEEN_SHIFT 3
mturner5 0:0d6b77c9ae01 5600 #define USB_INTEN_SLEEPEN_MASK 0x10u
mturner5 0:0d6b77c9ae01 5601 #define USB_INTEN_SLEEPEN_SHIFT 4
mturner5 0:0d6b77c9ae01 5602 #define USB_INTEN_RESUMEEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 5603 #define USB_INTEN_RESUMEEN_SHIFT 5
mturner5 0:0d6b77c9ae01 5604 #define USB_INTEN_ATTACHEN_MASK 0x40u
mturner5 0:0d6b77c9ae01 5605 #define USB_INTEN_ATTACHEN_SHIFT 6
mturner5 0:0d6b77c9ae01 5606 #define USB_INTEN_STALLEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 5607 #define USB_INTEN_STALLEN_SHIFT 7
mturner5 0:0d6b77c9ae01 5608 /* ERRSTAT Bit Fields */
mturner5 0:0d6b77c9ae01 5609 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mturner5 0:0d6b77c9ae01 5610 #define USB_ERRSTAT_PIDERR_SHIFT 0
mturner5 0:0d6b77c9ae01 5611 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
mturner5 0:0d6b77c9ae01 5612 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
mturner5 0:0d6b77c9ae01 5613 #define USB_ERRSTAT_CRC16_MASK 0x4u
mturner5 0:0d6b77c9ae01 5614 #define USB_ERRSTAT_CRC16_SHIFT 2
mturner5 0:0d6b77c9ae01 5615 #define USB_ERRSTAT_DFN8_MASK 0x8u
mturner5 0:0d6b77c9ae01 5616 #define USB_ERRSTAT_DFN8_SHIFT 3
mturner5 0:0d6b77c9ae01 5617 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mturner5 0:0d6b77c9ae01 5618 #define USB_ERRSTAT_BTOERR_SHIFT 4
mturner5 0:0d6b77c9ae01 5619 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mturner5 0:0d6b77c9ae01 5620 #define USB_ERRSTAT_DMAERR_SHIFT 5
mturner5 0:0d6b77c9ae01 5621 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mturner5 0:0d6b77c9ae01 5622 #define USB_ERRSTAT_BTSERR_SHIFT 7
mturner5 0:0d6b77c9ae01 5623 /* ERREN Bit Fields */
mturner5 0:0d6b77c9ae01 5624 #define USB_ERREN_PIDERREN_MASK 0x1u
mturner5 0:0d6b77c9ae01 5625 #define USB_ERREN_PIDERREN_SHIFT 0
mturner5 0:0d6b77c9ae01 5626 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mturner5 0:0d6b77c9ae01 5627 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mturner5 0:0d6b77c9ae01 5628 #define USB_ERREN_CRC16EN_MASK 0x4u
mturner5 0:0d6b77c9ae01 5629 #define USB_ERREN_CRC16EN_SHIFT 2
mturner5 0:0d6b77c9ae01 5630 #define USB_ERREN_DFN8EN_MASK 0x8u
mturner5 0:0d6b77c9ae01 5631 #define USB_ERREN_DFN8EN_SHIFT 3
mturner5 0:0d6b77c9ae01 5632 #define USB_ERREN_BTOERREN_MASK 0x10u
mturner5 0:0d6b77c9ae01 5633 #define USB_ERREN_BTOERREN_SHIFT 4
mturner5 0:0d6b77c9ae01 5634 #define USB_ERREN_DMAERREN_MASK 0x20u
mturner5 0:0d6b77c9ae01 5635 #define USB_ERREN_DMAERREN_SHIFT 5
mturner5 0:0d6b77c9ae01 5636 #define USB_ERREN_BTSERREN_MASK 0x80u
mturner5 0:0d6b77c9ae01 5637 #define USB_ERREN_BTSERREN_SHIFT 7
mturner5 0:0d6b77c9ae01 5638 /* STAT Bit Fields */
mturner5 0:0d6b77c9ae01 5639 #define USB_STAT_ODD_MASK 0x4u
mturner5 0:0d6b77c9ae01 5640 #define USB_STAT_ODD_SHIFT 2
mturner5 0:0d6b77c9ae01 5641 #define USB_STAT_TX_MASK 0x8u
mturner5 0:0d6b77c9ae01 5642 #define USB_STAT_TX_SHIFT 3
mturner5 0:0d6b77c9ae01 5643 #define USB_STAT_ENDP_MASK 0xF0u
mturner5 0:0d6b77c9ae01 5644 #define USB_STAT_ENDP_SHIFT 4
mturner5 0:0d6b77c9ae01 5645 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mturner5 0:0d6b77c9ae01 5646 /* CTL Bit Fields */
mturner5 0:0d6b77c9ae01 5647 #define USB_CTL_USBENSOFEN_MASK 0x1u
mturner5 0:0d6b77c9ae01 5648 #define USB_CTL_USBENSOFEN_SHIFT 0
mturner5 0:0d6b77c9ae01 5649 #define USB_CTL_ODDRST_MASK 0x2u
mturner5 0:0d6b77c9ae01 5650 #define USB_CTL_ODDRST_SHIFT 1
mturner5 0:0d6b77c9ae01 5651 #define USB_CTL_RESUME_MASK 0x4u
mturner5 0:0d6b77c9ae01 5652 #define USB_CTL_RESUME_SHIFT 2
mturner5 0:0d6b77c9ae01 5653 #define USB_CTL_HOSTMODEEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 5654 #define USB_CTL_HOSTMODEEN_SHIFT 3
mturner5 0:0d6b77c9ae01 5655 #define USB_CTL_RESET_MASK 0x10u
mturner5 0:0d6b77c9ae01 5656 #define USB_CTL_RESET_SHIFT 4
mturner5 0:0d6b77c9ae01 5657 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mturner5 0:0d6b77c9ae01 5658 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mturner5 0:0d6b77c9ae01 5659 #define USB_CTL_SE0_MASK 0x40u
mturner5 0:0d6b77c9ae01 5660 #define USB_CTL_SE0_SHIFT 6
mturner5 0:0d6b77c9ae01 5661 #define USB_CTL_JSTATE_MASK 0x80u
mturner5 0:0d6b77c9ae01 5662 #define USB_CTL_JSTATE_SHIFT 7
mturner5 0:0d6b77c9ae01 5663 /* ADDR Bit Fields */
mturner5 0:0d6b77c9ae01 5664 #define USB_ADDR_ADDR_MASK 0x7Fu
mturner5 0:0d6b77c9ae01 5665 #define USB_ADDR_ADDR_SHIFT 0
mturner5 0:0d6b77c9ae01 5666 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mturner5 0:0d6b77c9ae01 5667 #define USB_ADDR_LSEN_MASK 0x80u
mturner5 0:0d6b77c9ae01 5668 #define USB_ADDR_LSEN_SHIFT 7
mturner5 0:0d6b77c9ae01 5669 /* BDTPAGE1 Bit Fields */
mturner5 0:0d6b77c9ae01 5670 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mturner5 0:0d6b77c9ae01 5671 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mturner5 0:0d6b77c9ae01 5672 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mturner5 0:0d6b77c9ae01 5673 /* FRMNUML Bit Fields */
mturner5 0:0d6b77c9ae01 5674 #define USB_FRMNUML_FRM_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5675 #define USB_FRMNUML_FRM_SHIFT 0
mturner5 0:0d6b77c9ae01 5676 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mturner5 0:0d6b77c9ae01 5677 /* FRMNUMH Bit Fields */
mturner5 0:0d6b77c9ae01 5678 #define USB_FRMNUMH_FRM_MASK 0x7u
mturner5 0:0d6b77c9ae01 5679 #define USB_FRMNUMH_FRM_SHIFT 0
mturner5 0:0d6b77c9ae01 5680 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mturner5 0:0d6b77c9ae01 5681 /* TOKEN Bit Fields */
mturner5 0:0d6b77c9ae01 5682 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
mturner5 0:0d6b77c9ae01 5683 #define USB_TOKEN_TOKENENDPT_SHIFT 0
mturner5 0:0d6b77c9ae01 5684 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
mturner5 0:0d6b77c9ae01 5685 #define USB_TOKEN_TOKENPID_MASK 0xF0u
mturner5 0:0d6b77c9ae01 5686 #define USB_TOKEN_TOKENPID_SHIFT 4
mturner5 0:0d6b77c9ae01 5687 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
mturner5 0:0d6b77c9ae01 5688 /* SOFTHLD Bit Fields */
mturner5 0:0d6b77c9ae01 5689 #define USB_SOFTHLD_CNT_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5690 #define USB_SOFTHLD_CNT_SHIFT 0
mturner5 0:0d6b77c9ae01 5691 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
mturner5 0:0d6b77c9ae01 5692 /* BDTPAGE2 Bit Fields */
mturner5 0:0d6b77c9ae01 5693 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5694 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mturner5 0:0d6b77c9ae01 5695 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mturner5 0:0d6b77c9ae01 5696 /* BDTPAGE3 Bit Fields */
mturner5 0:0d6b77c9ae01 5697 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5698 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mturner5 0:0d6b77c9ae01 5699 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mturner5 0:0d6b77c9ae01 5700 /* ENDPT Bit Fields */
mturner5 0:0d6b77c9ae01 5701 #define USB_ENDPT_EPHSHK_MASK 0x1u
mturner5 0:0d6b77c9ae01 5702 #define USB_ENDPT_EPHSHK_SHIFT 0
mturner5 0:0d6b77c9ae01 5703 #define USB_ENDPT_EPSTALL_MASK 0x2u
mturner5 0:0d6b77c9ae01 5704 #define USB_ENDPT_EPSTALL_SHIFT 1
mturner5 0:0d6b77c9ae01 5705 #define USB_ENDPT_EPTXEN_MASK 0x4u
mturner5 0:0d6b77c9ae01 5706 #define USB_ENDPT_EPTXEN_SHIFT 2
mturner5 0:0d6b77c9ae01 5707 #define USB_ENDPT_EPRXEN_MASK 0x8u
mturner5 0:0d6b77c9ae01 5708 #define USB_ENDPT_EPRXEN_SHIFT 3
mturner5 0:0d6b77c9ae01 5709 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mturner5 0:0d6b77c9ae01 5710 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mturner5 0:0d6b77c9ae01 5711 #define USB_ENDPT_RETRYDIS_MASK 0x40u
mturner5 0:0d6b77c9ae01 5712 #define USB_ENDPT_RETRYDIS_SHIFT 6
mturner5 0:0d6b77c9ae01 5713 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
mturner5 0:0d6b77c9ae01 5714 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
mturner5 0:0d6b77c9ae01 5715 /* USBCTRL Bit Fields */
mturner5 0:0d6b77c9ae01 5716 #define USB_USBCTRL_PDE_MASK 0x40u
mturner5 0:0d6b77c9ae01 5717 #define USB_USBCTRL_PDE_SHIFT 6
mturner5 0:0d6b77c9ae01 5718 #define USB_USBCTRL_SUSP_MASK 0x80u
mturner5 0:0d6b77c9ae01 5719 #define USB_USBCTRL_SUSP_SHIFT 7
mturner5 0:0d6b77c9ae01 5720 /* OBSERVE Bit Fields */
mturner5 0:0d6b77c9ae01 5721 #define USB_OBSERVE_DMPD_MASK 0x10u
mturner5 0:0d6b77c9ae01 5722 #define USB_OBSERVE_DMPD_SHIFT 4
mturner5 0:0d6b77c9ae01 5723 #define USB_OBSERVE_DPPD_MASK 0x40u
mturner5 0:0d6b77c9ae01 5724 #define USB_OBSERVE_DPPD_SHIFT 6
mturner5 0:0d6b77c9ae01 5725 #define USB_OBSERVE_DPPU_MASK 0x80u
mturner5 0:0d6b77c9ae01 5726 #define USB_OBSERVE_DPPU_SHIFT 7
mturner5 0:0d6b77c9ae01 5727 /* CONTROL Bit Fields */
mturner5 0:0d6b77c9ae01 5728 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mturner5 0:0d6b77c9ae01 5729 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mturner5 0:0d6b77c9ae01 5730 /* USBTRC0 Bit Fields */
mturner5 0:0d6b77c9ae01 5731 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mturner5 0:0d6b77c9ae01 5732 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mturner5 0:0d6b77c9ae01 5733 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mturner5 0:0d6b77c9ae01 5734 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mturner5 0:0d6b77c9ae01 5735 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mturner5 0:0d6b77c9ae01 5736 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mturner5 0:0d6b77c9ae01 5737 #define USB_USBTRC0_USBRESET_MASK 0x80u
mturner5 0:0d6b77c9ae01 5738 #define USB_USBTRC0_USBRESET_SHIFT 7
mturner5 0:0d6b77c9ae01 5739 /* USBFRMADJUST Bit Fields */
mturner5 0:0d6b77c9ae01 5740 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mturner5 0:0d6b77c9ae01 5741 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mturner5 0:0d6b77c9ae01 5742 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mturner5 0:0d6b77c9ae01 5743
mturner5 0:0d6b77c9ae01 5744 /*!
mturner5 0:0d6b77c9ae01 5745 * @}
mturner5 0:0d6b77c9ae01 5746 */ /* end of group USB_Register_Masks */
mturner5 0:0d6b77c9ae01 5747
mturner5 0:0d6b77c9ae01 5748
mturner5 0:0d6b77c9ae01 5749 /* USB - Peripheral instance base addresses */
mturner5 0:0d6b77c9ae01 5750 /** Peripheral USB0 base address */
mturner5 0:0d6b77c9ae01 5751 #define USB0_BASE (0x40072000u)
mturner5 0:0d6b77c9ae01 5752 /** Peripheral USB0 base pointer */
mturner5 0:0d6b77c9ae01 5753 #define USB0 ((USB_Type *)USB0_BASE)
mturner5 0:0d6b77c9ae01 5754 /** Array initializer of USB peripheral base pointers */
mturner5 0:0d6b77c9ae01 5755 #define USB_BASES { USB0 }
mturner5 0:0d6b77c9ae01 5756
mturner5 0:0d6b77c9ae01 5757 /*!
mturner5 0:0d6b77c9ae01 5758 * @}
mturner5 0:0d6b77c9ae01 5759 */ /* end of group USB_Peripheral_Access_Layer */
mturner5 0:0d6b77c9ae01 5760
mturner5 0:0d6b77c9ae01 5761
mturner5 0:0d6b77c9ae01 5762 /*
mturner5 0:0d6b77c9ae01 5763 ** End of section using anonymous unions
mturner5 0:0d6b77c9ae01 5764 */
mturner5 0:0d6b77c9ae01 5765
mturner5 0:0d6b77c9ae01 5766 #if defined(__ARMCC_VERSION)
mturner5 0:0d6b77c9ae01 5767 #pragma pop
mturner5 0:0d6b77c9ae01 5768 #elif defined(__CWCC__)
mturner5 0:0d6b77c9ae01 5769 #pragma pop
mturner5 0:0d6b77c9ae01 5770 #elif defined(__GNUC__)
mturner5 0:0d6b77c9ae01 5771 /* leave anonymous unions enabled */
mturner5 0:0d6b77c9ae01 5772 #elif defined(__IAR_SYSTEMS_ICC__)
mturner5 0:0d6b77c9ae01 5773 #pragma language=default
mturner5 0:0d6b77c9ae01 5774 #else
mturner5 0:0d6b77c9ae01 5775 #error Not supported compiler type
mturner5 0:0d6b77c9ae01 5776 #endif
mturner5 0:0d6b77c9ae01 5777
mturner5 0:0d6b77c9ae01 5778 /*!
mturner5 0:0d6b77c9ae01 5779 * @}
mturner5 0:0d6b77c9ae01 5780 */ /* end of group Peripheral_access_layer */
mturner5 0:0d6b77c9ae01 5781
mturner5 0:0d6b77c9ae01 5782
mturner5 0:0d6b77c9ae01 5783 /* ----------------------------------------------------------------------------
mturner5 0:0d6b77c9ae01 5784 -- Backward Compatibility
mturner5 0:0d6b77c9ae01 5785 ---------------------------------------------------------------------------- */
mturner5 0:0d6b77c9ae01 5786
mturner5 0:0d6b77c9ae01 5787 /*!
mturner5 0:0d6b77c9ae01 5788 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mturner5 0:0d6b77c9ae01 5789 * @{
mturner5 0:0d6b77c9ae01 5790 */
mturner5 0:0d6b77c9ae01 5791
mturner5 0:0d6b77c9ae01 5792 /* No backward compatibility issues. */
mturner5 0:0d6b77c9ae01 5793
mturner5 0:0d6b77c9ae01 5794 /*!
mturner5 0:0d6b77c9ae01 5795 * @}
mturner5 0:0d6b77c9ae01 5796 */ /* end of group Backward_Compatibility_Symbols */
mturner5 0:0d6b77c9ae01 5797
mturner5 0:0d6b77c9ae01 5798
mturner5 0:0d6b77c9ae01 5799 #endif /* #if !defined(MKL46Z4_H_) */
mturner5 0:0d6b77c9ae01 5800
mturner5 0:0d6b77c9ae01 5801 /* MKL46Z4.h, eof. */