Marcell Rausch / mbed-dev-no-serial

mbed library sources. Supersedes mbed-src. removed serial

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F1/pinmap.c@158:aa577577efe0, 2017-02-13 (annotated)

Committer:
mrcrsch
Date:
Mon Feb 13 14:26:36 2017 +0000
Revision:
158:aa577577efe0
Parent:
154:37f96f9d4de2 
removed stdio and serial to reduce size

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * Copyright (c) 2014, STMicroelectronics
<> 149:156823d33999 4 * All rights reserved.
<> 149:156823d33999 5 *
<> 149:156823d33999 6 * Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 7 * modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 10 * this list of conditions and the following disclaimer.
<> 149:156823d33999 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 12 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 13 * and/or other materials provided with the distribution.
<> 149:156823d33999 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 15 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 16 * without specific prior written permission.
<> 149:156823d33999 17 *
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 28 *******************************************************************************
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "pinmap.h"
<> 149:156823d33999 32 #include "PortNames.h"
<> 149:156823d33999 33 #include "mbed_error.h"
<> 149:156823d33999 34
<> 149:156823d33999 35 // GPIO mode look-up table
<> 149:156823d33999 36 // Warning: the elements order must be the same as the one defined in PinNames.h
<> 149:156823d33999 37 static const uint32_t gpio_mode[13] = {
<> 149:156823d33999 38 GPIO_MODE_INPUT, // 0 = STM_MODE_INPUT
<> 149:156823d33999 39 GPIO_MODE_OUTPUT_PP, // 1 = STM_MODE_OUTPUT_PP
<> 149:156823d33999 40 GPIO_MODE_OUTPUT_OD, // 2 = STM_MODE_OUTPUT_OD
<> 149:156823d33999 41 GPIO_MODE_AF_PP, // 3 = STM_MODE_AF_PP
<> 149:156823d33999 42 GPIO_MODE_AF_OD, // 4 = STM_MODE_AF_OD
<> 149:156823d33999 43 GPIO_MODE_ANALOG, // 5 = STM_MODE_ANALOG
<> 149:156823d33999 44 GPIO_MODE_IT_RISING, // 6 = STM_MODE_IT_RISING
<> 149:156823d33999 45 GPIO_MODE_IT_FALLING, // 7 = STM_MODE_IT_FALLING
<> 149:156823d33999 46 GPIO_MODE_IT_RISING_FALLING, // 8 = STM_MODE_IT_RISING_FALLING
<> 149:156823d33999 47 GPIO_MODE_EVT_RISING, // 9 = STM_MODE_EVT_RISING
<> 149:156823d33999 48 GPIO_MODE_EVT_FALLING, // 10 = STM_MODE_EVT_FALLING
<> 149:156823d33999 49 GPIO_MODE_EVT_RISING_FALLING, // 11 = STM_MODE_EVT_RISING_FALLING
<> 149:156823d33999 50 0x10000000 // 12 = STM_MODE_IT_EVT_RESET (not in STM32Cube HAL)
<> 149:156823d33999 51 };
<> 149:156823d33999 52
<> 149:156823d33999 53 // Enable GPIO clock and return GPIO base address
<> 149:156823d33999 54 uint32_t Set_GPIO_Clock(uint32_t port_idx)
<> 149:156823d33999 55 {
<> 149:156823d33999 56 uint32_t gpio_add = 0;
<> 149:156823d33999 57 switch (port_idx) {
<> 149:156823d33999 58 case PortA:
<> 149:156823d33999 59 gpio_add = GPIOA_BASE;
<> 149:156823d33999 60 __GPIOA_CLK_ENABLE();
<> 149:156823d33999 61 break;
<> 149:156823d33999 62 case PortB:
<> 149:156823d33999 63 gpio_add = GPIOB_BASE;
<> 149:156823d33999 64 __GPIOB_CLK_ENABLE();
<> 149:156823d33999 65 break;
<> 149:156823d33999 66 case PortC:
<> 149:156823d33999 67 gpio_add = GPIOC_BASE;
<> 149:156823d33999 68 __GPIOC_CLK_ENABLE();
<> 149:156823d33999 69 break;
<> 149:156823d33999 70 case PortD:
<> 149:156823d33999 71 gpio_add = GPIOD_BASE;
<> 149:156823d33999 72 __GPIOD_CLK_ENABLE();
<> 149:156823d33999 73 break;
<> 149:156823d33999 74 default:
<> 149:156823d33999 75 error("Pinmap error: wrong port number.");
<> 149:156823d33999 76 break;
<> 149:156823d33999 77 }
<> 149:156823d33999 78 return gpio_add;
<> 149:156823d33999 79 }
<> 149:156823d33999 80
<> 149:156823d33999 81 /**
<> 149:156823d33999 82 * Configure pin (input, output, alternate function or analog) + output speed + AF
<> 149:156823d33999 83 */
<> 149:156823d33999 84 void pin_function(PinName pin, int data)
<> 149:156823d33999 85 {
<> 149:156823d33999 86 MBED_ASSERT(pin != (PinName)NC);
<> 149:156823d33999 87 // Get the pin informations
<> 149:156823d33999 88 uint32_t mode = STM_PIN_MODE(data);
<> 149:156823d33999 89 uint32_t pupd = STM_PIN_PUPD(data);
<> 149:156823d33999 90 uint32_t afnum = STM_PIN_AFNUM(data);
<> 149:156823d33999 91
<> 149:156823d33999 92 uint32_t port_index = STM_PORT(pin);
<> 149:156823d33999 93 uint32_t pin_index = STM_PIN(pin);
<> 149:156823d33999 94
<> 149:156823d33999 95 // Enable GPIO clock
<> 149:156823d33999 96 uint32_t gpio_add = Set_GPIO_Clock(port_index);
<> 149:156823d33999 97 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
<> 149:156823d33999 98
<> 149:156823d33999 99 // Enable AFIO clock
<> 149:156823d33999 100 __HAL_RCC_AFIO_CLK_ENABLE();
<> 149:156823d33999 101
<> 149:156823d33999 102 // Configure Alternate Function
<> 149:156823d33999 103 // Warning: Must be done before the GPIO is initialized
<> 149:156823d33999 104 if (afnum > 0) {
<> 149:156823d33999 105 switch (afnum) {
<> 149:156823d33999 106 case 1: // Remap SPI1
<> 149:156823d33999 107 __HAL_AFIO_REMAP_SPI1_ENABLE();
<> 149:156823d33999 108 break;
<> 149:156823d33999 109 case 2: // Remap I2C1
<> 149:156823d33999 110 __HAL_AFIO_REMAP_I2C1_ENABLE();
<> 149:156823d33999 111 break;
<> 149:156823d33999 112 case 3: // Remap USART1
<> 149:156823d33999 113 __HAL_AFIO_REMAP_USART1_ENABLE();
<> 149:156823d33999 114 break;
<> 149:156823d33999 115 case 4: // Remap USART2
<> 149:156823d33999 116 __HAL_AFIO_REMAP_USART2_ENABLE();
<> 149:156823d33999 117 break;
<> 149:156823d33999 118 case 5: // Partial Remap USART3
<> 149:156823d33999 119 __HAL_AFIO_REMAP_USART3_PARTIAL();
<> 149:156823d33999 120 break;
<> 149:156823d33999 121 case 6: // Partial Remap TIM1
<> 149:156823d33999 122 __HAL_AFIO_REMAP_TIM1_PARTIAL();
<> 149:156823d33999 123 break;
<> 149:156823d33999 124 case 7: // Partial Remap TIM3
<> 149:156823d33999 125 __HAL_AFIO_REMAP_TIM3_PARTIAL();
<> 149:156823d33999 126 break;
<> 149:156823d33999 127 case 8: // Full Remap TIM2
<> 149:156823d33999 128 __HAL_AFIO_REMAP_TIM2_ENABLE();
<> 149:156823d33999 129 break;
<> 149:156823d33999 130 case 9: // Full Remap TIM3
<> 149:156823d33999 131 __HAL_AFIO_REMAP_TIM3_ENABLE();
<> 149:156823d33999 132 break;
<> 154:37f96f9d4de2 133 case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
<> 154:37f96f9d4de2 134 __HAL_AFIO_REMAP_CAN1_2();
<> 154:37f96f9d4de2 135 break;
<> 149:156823d33999 136 default:
<> 149:156823d33999 137 break;
<> 149:156823d33999 138 }
<> 149:156823d33999 139 }
<> 149:156823d33999 140
<> 149:156823d33999 141 // Configure GPIO
<> 149:156823d33999 142 GPIO_InitTypeDef GPIO_InitStructure;
<> 149:156823d33999 143 GPIO_InitStructure.Pin = (uint32_t)(1 << pin_index);
<> 149:156823d33999 144 GPIO_InitStructure.Mode = gpio_mode[mode];
<> 149:156823d33999 145 GPIO_InitStructure.Pull = pupd;
<> 149:156823d33999 146 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
<> 149:156823d33999 147 HAL_GPIO_Init(gpio, &GPIO_InitStructure);
<> 149:156823d33999 148
<> 149:156823d33999 149 // Disconnect JTAG-DP + SW-DP signals.
<> 149:156823d33999 150 // Warning: Need to reconnect under reset
<> 149:156823d33999 151 if ((pin == PA_13) || (pin == PA_14)) {
<> 149:156823d33999 152 __HAL_AFIO_REMAP_SWJ_DISABLE(); // JTAG-DP Disabled and SW-DP Disabled
<> 149:156823d33999 153 }
<> 149:156823d33999 154 if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
<> 149:156823d33999 155 __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled
<> 149:156823d33999 156 }
<> 149:156823d33999 157 }
<> 149:156823d33999 158
<> 149:156823d33999 159 /**
<> 149:156823d33999 160 * Configure pin pull-up/pull-down
<> 149:156823d33999 161 */
<> 149:156823d33999 162 void pin_mode(PinName pin, PinMode mode)
<> 149:156823d33999 163 {
<> 149:156823d33999 164 MBED_ASSERT(pin != (PinName)NC);
<> 149:156823d33999 165
<> 149:156823d33999 166 uint32_t port_index = STM_PORT(pin);
<> 149:156823d33999 167 uint32_t pin_index = STM_PIN(pin);
<> 149:156823d33999 168 // Enable GPIO clock
<> 149:156823d33999 169 uint32_t gpio_add = Set_GPIO_Clock(port_index);
<> 149:156823d33999 170 GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
<> 149:156823d33999 171 __IO uint32_t* gpio_reg_hl;//gpio register depends on bit index (high or low)
<> 149:156823d33999 172 uint32_t shift;
<> 149:156823d33999 173
<> 149:156823d33999 174 if (pin_index < 8) {
<> 149:156823d33999 175 shift = (pin_index * 4);
<> 149:156823d33999 176 gpio_reg_hl = &(gpio->CRL);
<> 149:156823d33999 177 } else {
<> 149:156823d33999 178 shift = (pin_index % 8) * 4;
<> 149:156823d33999 179 gpio_reg_hl = &(gpio->CRH);
<> 149:156823d33999 180 }
<> 149:156823d33999 181
<> 149:156823d33999 182 // Configure open-drain and pull-up/down
<> 149:156823d33999 183 switch (mode) {
<> 149:156823d33999 184 case PullNone:
<> 149:156823d33999 185 break;
<> 149:156823d33999 186 case PullUp:
<> 149:156823d33999 187 case PullDown:
<> 149:156823d33999 188 // Set pull-up / pull-down for Input mode
<> 149:156823d33999 189 if ((*gpio_reg_hl & (0x03 << shift)) == 0) { // MODE bits = Input mode
<> 149:156823d33999 190 *gpio_reg_hl |= (0x08 << shift); // Set pull-up / pull-down
<> 149:156823d33999 191 *gpio_reg_hl &= ~(0x04 << shift); // ENSURES GPIOx_CRL.CNFx.bit0 = 0
<> 149:156823d33999 192 }
<> 149:156823d33999 193 // Now it's time to setup properly if pullup or pulldown. This is done in ODR register:
<> 149:156823d33999 194 // set pull-up => bit=1, set pull-down => bit = 0
<> 149:156823d33999 195 if (mode == PullUp) {
<> 149:156823d33999 196 gpio->ODR |= (0x01 << (pin_index)); // Set pull-up
<> 154:37f96f9d4de2 197 } else {
<> 149:156823d33999 198 gpio->ODR &= ~(0x01 << (pin_index)); // Set pull-down
<> 149:156823d33999 199 }
<> 149:156823d33999 200 break;
<> 149:156823d33999 201 case OpenDrain:
<> 149:156823d33999 202 // Set open-drain for Output mode (General Purpose or Alternate Function)
<> 149:156823d33999 203 if ((*gpio_reg_hl & (0x03 << shift)) > 0) { // MODE bits = Output mode
<> 149:156823d33999 204 *gpio_reg_hl |= (0x04 << shift); // Set open-drain
<> 149:156823d33999 205 }
<> 149:156823d33999 206 break;
<> 149:156823d33999 207 default:
<> 149:156823d33999 208 break;
<> 149:156823d33999 209 }
<> 149:156823d33999 210 }
<> 149:156823d33999 211
<> 149:156823d33999 212 /* Internal function for setting the gpiomode/function
<> 149:156823d33999 213 * without changing Pull mode
<> 149:156823d33999 214 */
<> 154:37f96f9d4de2 215 void pin_function_gpiomode(PinName pin, uint32_t gpiomode)
<> 154:37f96f9d4de2 216 {
<> 149:156823d33999 217
<> 149:156823d33999 218 /* Read current pull state from HW to avoid over-write*/
<> 149:156823d33999 219 uint32_t port_index = STM_PORT(pin);
<> 149:156823d33999 220 uint32_t pin_index = STM_PIN(pin);
<> 149:156823d33999 221 GPIO_TypeDef *gpio = (GPIO_TypeDef *) Set_GPIO_Clock(port_index);
<> 149:156823d33999 222 uint32_t pull = PullNone;
<> 149:156823d33999 223 __IO uint32_t* gpio_reg_hl;//gpio register depends on bit index (high or low)
<> 149:156823d33999 224 uint32_t shift;
<> 149:156823d33999 225
<> 149:156823d33999 226 if (pin_index < 8) {
<> 149:156823d33999 227 shift = (pin_index * 4);
<> 149:156823d33999 228 gpio_reg_hl = &(gpio->CRL);
<> 149:156823d33999 229 } else {
<> 149:156823d33999 230 shift = (pin_index % 8) * 4;
<> 149:156823d33999 231 gpio_reg_hl = &(gpio->CRH);
<> 149:156823d33999 232 }
<> 149:156823d33999 233
<> 149:156823d33999 234 /* Check if pull/pull down is active */
<> 154:37f96f9d4de2 235 if (!(*gpio_reg_hl & (0x03 << shift))) {// input
<> 154:37f96f9d4de2 236 if((!!(*gpio_reg_hl & (0x08 << shift))) // pull-up / down
<> 154:37f96f9d4de2 237 && (!(*gpio_reg_hl & (0x04 << shift)))) { // GPIOx_CRL.CNFx.bit0 = 0
<> 154:37f96f9d4de2 238 if (!!(gpio->ODR & (0x01 << pin_index))) {
<> 154:37f96f9d4de2 239 pull = PullUp;
<> 154:37f96f9d4de2 240 } else {
<> 154:37f96f9d4de2 241 pull = PullDown;
<> 154:37f96f9d4de2 242 }
<> 149:156823d33999 243 }
<> 149:156823d33999 244 } else { //output
<> 149:156823d33999 245 if (!!(*gpio_reg_hl & (0x04 << shift))) { //open drain
<> 149:156823d33999 246 pull = OpenDrain;
<> 149:156823d33999 247 }
<> 149:156823d33999 248 }
<> 149:156823d33999 249
<> 149:156823d33999 250 /* Then re-use global function for updating the mode part*/
<> 149:156823d33999 251 pin_function(pin, STM_PIN_DATA(gpiomode, pull, 0));
<> 149:156823d33999 252 }