Marcell Rausch / mbed-dev-no-serial

mbed library sources. Supersedes mbed-src. removed serial

Fork of mbed-dev by mbed official

hal/spi_api.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1
<> 149:156823d33999 2 /** \addtogroup hal */
<> 149:156823d33999 3 /** @{*/
<> 144:ef7eb2e8f9f7 4 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 5 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 8 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 9 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 14 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 16 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 17 * limitations under the License.
<> 144:ef7eb2e8f9f7 18 */
<> 144:ef7eb2e8f9f7 19 #ifndef MBED_SPI_API_H
<> 144:ef7eb2e8f9f7 20 #define MBED_SPI_API_H
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #include "device.h"
<> 149:156823d33999 23 #include "hal/dma_api.h"
<> 149:156823d33999 24 #include "hal/buffer.h"
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #if DEVICE_SPI
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #define SPI_EVENT_ERROR (1 << 1)
<> 144:ef7eb2e8f9f7 29 #define SPI_EVENT_COMPLETE (1 << 2)
<> 144:ef7eb2e8f9f7 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
<> 144:ef7eb2e8f9f7 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #define SPI_FILL_WORD (0xFFFF)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 38 /** Asynch SPI HAL structure
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40 typedef struct {
<> 144:ef7eb2e8f9f7 41 struct spi_s spi; /**< Target specific SPI structure */
<> 144:ef7eb2e8f9f7 42 struct buffer_s tx_buff; /**< Tx buffer */
<> 144:ef7eb2e8f9f7 43 struct buffer_s rx_buff; /**< Rx buffer */
<> 144:ef7eb2e8f9f7 44 } spi_t;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #else
<> 144:ef7eb2e8f9f7 47 /** Non-asynch SPI HAL structure
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49 typedef struct spi_s spi_t;
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 #endif
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 54 extern "C" {
<> 144:ef7eb2e8f9f7 55 #endif
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /**
<> 144:ef7eb2e8f9f7 58 * \defgroup hal_GeneralSPI SPI Configuration Functions
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** Initialize the SPI peripheral
<> 144:ef7eb2e8f9f7 63 *
<> 144:ef7eb2e8f9f7 64 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
<> 144:ef7eb2e8f9f7 65 * @param[out] obj The SPI object to initialize
<> 144:ef7eb2e8f9f7 66 * @param[in] mosi The pin to use for MOSI
<> 144:ef7eb2e8f9f7 67 * @param[in] miso The pin to use for MISO
<> 144:ef7eb2e8f9f7 68 * @param[in] sclk The pin to use for SCLK
<> 144:ef7eb2e8f9f7 69 * @param[in] ssel The pin to use for SSEL
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /** Release a SPI object
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * TODO: spi_free is currently unimplemented
<> 144:ef7eb2e8f9f7 76 * This will require reference counting at the C++ level to be safe
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * Return the pins owned by the SPI object to their reset state
<> 144:ef7eb2e8f9f7 79 * Disable the SPI peripheral
<> 144:ef7eb2e8f9f7 80 * Disable the SPI clock
<> 144:ef7eb2e8f9f7 81 * @param[in] obj The SPI object to deinitialize
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 void spi_free(spi_t *obj);
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /** Configure the SPI format
<> 144:ef7eb2e8f9f7 86 *
<> 144:ef7eb2e8f9f7 87 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
<> 144:ef7eb2e8f9f7 88 * The default bit order is MSB.
<> 144:ef7eb2e8f9f7 89 * @param[in,out] obj The SPI object to configure
<> 144:ef7eb2e8f9f7 90 * @param[in] bits The number of bits per frame
<> 144:ef7eb2e8f9f7 91 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
<> 144:ef7eb2e8f9f7 92 * @param[in] slave Zero for master mode or non-zero for slave mode
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 void spi_format(spi_t *obj, int bits, int mode, int slave);
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** Set the SPI baud rate
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
<> 144:ef7eb2e8f9f7 99 * Configures the SPI peripheral's baud rate
<> 144:ef7eb2e8f9f7 100 * @param[in,out] obj The SPI object to configure
<> 144:ef7eb2e8f9f7 101 * @param[in] hz The baud rate in Hz
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 void spi_frequency(spi_t *obj, int hz);
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**@}*/
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** Write a byte out in master mode and receive a value
<> 144:ef7eb2e8f9f7 112 *
<> 144:ef7eb2e8f9f7 113 * @param[in] obj The SPI peripheral to use for sending
<> 144:ef7eb2e8f9f7 114 * @param[in] value The value to send
<> 144:ef7eb2e8f9f7 115 * @return Returns the value received during send
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 int spi_master_write(spi_t *obj, int value);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** Check if a value is available to read
<> 144:ef7eb2e8f9f7 120 *
<> 144:ef7eb2e8f9f7 121 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 122 * @return non-zero if a value is available
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 int spi_slave_receive(spi_t *obj);
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** Get a received value out of the SPI receive buffer in slave mode
<> 144:ef7eb2e8f9f7 127 *
<> 144:ef7eb2e8f9f7 128 * Blocks until a value is available
<> 144:ef7eb2e8f9f7 129 * @param[in] obj The SPI peripheral to read
<> 144:ef7eb2e8f9f7 130 * @return The value received
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 int spi_slave_read(spi_t *obj);
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** Write a value to the SPI peripheral in slave mode
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 * Blocks until the SPI peripheral can be written to
<> 144:ef7eb2e8f9f7 137 * @param[in] obj The SPI peripheral to write
<> 144:ef7eb2e8f9f7 138 * @param[in] value The value to write
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 void spi_slave_write(spi_t *obj, int value);
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** Checks if the specified SPI peripheral is in use
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 145 * @return non-zero if the peripheral is currently transmitting
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 int spi_busy(spi_t *obj);
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** Get the module number
<> 144:ef7eb2e8f9f7 150 *
<> 144:ef7eb2e8f9f7 151 * @param[in] obj The SPI peripheral to check
<> 144:ef7eb2e8f9f7 152 * @return The module number
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 uint8_t spi_get_module(spi_t *obj);
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**@}*/
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 #if DEVICE_SPI_ASYNCH
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
<> 144:ef7eb2e8f9f7 165 *
<> 144:ef7eb2e8f9f7 166 * @param[in] obj The SPI object that holds the transfer information
<> 144:ef7eb2e8f9f7 167 * @param[in] tx The transmit buffer
<> 144:ef7eb2e8f9f7 168 * @param[in] tx_length The number of bytes to transmit
<> 144:ef7eb2e8f9f7 169 * @param[in] rx The receive buffer
<> 144:ef7eb2e8f9f7 170 * @param[in] rx_length The number of bytes to receive
<> 144:ef7eb2e8f9f7 171 * @param[in] bit_width The bit width of buffer words
<> 144:ef7eb2e8f9f7 172 * @param[in] event The logical OR of events to be registered
<> 144:ef7eb2e8f9f7 173 * @param[in] handler SPI interrupt handler
<> 144:ef7eb2e8f9f7 174 * @param[in] hint A suggestion for how to use DMA with this transfer
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /** The asynchronous IRQ handler
<> 144:ef7eb2e8f9f7 179 *
<> 144:ef7eb2e8f9f7 180 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
<> 144:ef7eb2e8f9f7 181 * conditions, such as buffer overflows or transfer complete.
<> 144:ef7eb2e8f9f7 182 * @param[in] obj The SPI object that holds the transfer information
<> 144:ef7eb2e8f9f7 183 * @return Event flags if a transfer termination condition was met; otherwise 0.
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 uint32_t spi_irq_handler_asynch(spi_t *obj);
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /** Attempts to determine if the SPI peripheral is already in use
<> 144:ef7eb2e8f9f7 188 *
<> 144:ef7eb2e8f9f7 189 * If a temporary DMA channel has been allocated, peripheral is in use.
<> 144:ef7eb2e8f9f7 190 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
<> 144:ef7eb2e8f9f7 191 * channel were allocated.
<> 144:ef7eb2e8f9f7 192 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
<> 144:ef7eb2e8f9f7 193 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
<> 144:ef7eb2e8f9f7 194 * there are any bytes in the FIFOs.
<> 144:ef7eb2e8f9f7 195 * @param[in] obj The SPI object to check for activity
<> 144:ef7eb2e8f9f7 196 * @return Non-zero if the SPI port is active or zero if it is not.
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198 uint8_t spi_active(spi_t *obj);
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /** Abort an SPI transfer
<> 144:ef7eb2e8f9f7 201 *
<> 144:ef7eb2e8f9f7 202 * @param obj The SPI peripheral to stop
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 void spi_abort_asynch(spi_t *obj);
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #endif
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /**@}*/
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213 #endif // __cplusplus
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 #endif // SPI_DEVICE
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #endif // MBED_SPI_API_H
<> 149:156823d33999 218
<> 149:156823d33999 219 /** @}*/