Integrating the ublox LISA C200 modem
Fork of SprintUSBModemHTTPClientTest by
Core Debug Registers (CoreDebug)
[Defines and Type Definitions]
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. More...
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
Generated on Tue Jul 12 2022 13:16:12 by
1.7.2



