mohamed achour / vl53l0x_api

hh

Dependents:   VL53L0X-mbedOS-master VL53L0X-mbedOS-masterbb

vl53l0x_device.h@2:a1dffa1ff38a, 2019-04-23 (annotated)

Committer:
mohamedachour
Date:
Tue Apr 23 14:27:07 2019 +0000
Revision:
2:a1dffa1ff38a
Parent:
0:e6fcdb78a136 
xc

Who changed what in which revision?

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mjarvisal 0:e6fcdb78a136 1 /*******************************************************************************
mjarvisal 0:e6fcdb78a136 2 Copyright © 2016, STMicroelectronics International N.V.
mjarvisal 0:e6fcdb78a136 3 All rights reserved.
mjarvisal 0:e6fcdb78a136 4
mjarvisal 0:e6fcdb78a136 5 Redistribution and use in source and binary forms, with or without
mjarvisal 0:e6fcdb78a136 6 modification, are permitted provided that the following conditions are met:
mjarvisal 0:e6fcdb78a136 7 * Redistributions of source code must retain the above copyright
mjarvisal 0:e6fcdb78a136 8 notice, this list of conditions and the following disclaimer.
mjarvisal 0:e6fcdb78a136 9 * Redistributions in binary form must reproduce the above copyright
mjarvisal 0:e6fcdb78a136 10 notice, this list of conditions and the following disclaimer in the
mjarvisal 0:e6fcdb78a136 11 documentation and/or other materials provided with the distribution.
mjarvisal 0:e6fcdb78a136 12 * Neither the name of STMicroelectronics nor the
mjarvisal 0:e6fcdb78a136 13 names of its contributors may be used to endorse or promote products
mjarvisal 0:e6fcdb78a136 14 derived from this software without specific prior written permission.
mjarvisal 0:e6fcdb78a136 15
mjarvisal 0:e6fcdb78a136 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mjarvisal 0:e6fcdb78a136 17 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mjarvisal 0:e6fcdb78a136 18 WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
mjarvisal 0:e6fcdb78a136 19 NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
mjarvisal 0:e6fcdb78a136 20 IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
mjarvisal 0:e6fcdb78a136 21 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mjarvisal 0:e6fcdb78a136 22 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mjarvisal 0:e6fcdb78a136 23 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
mjarvisal 0:e6fcdb78a136 24 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mjarvisal 0:e6fcdb78a136 25 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mjarvisal 0:e6fcdb78a136 26 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mjarvisal 0:e6fcdb78a136 27 *******************************************************************************/
mjarvisal 0:e6fcdb78a136 28
mjarvisal 0:e6fcdb78a136 29 /**
mjarvisal 0:e6fcdb78a136 30 * Device specific defines. To be adapted by implementer for the targeted
mjarvisal 0:e6fcdb78a136 31 * device.
mjarvisal 0:e6fcdb78a136 32 */
mjarvisal 0:e6fcdb78a136 33
mjarvisal 0:e6fcdb78a136 34 #ifndef _VL53L0X_DEVICE_H_
mjarvisal 0:e6fcdb78a136 35 #define _VL53L0X_DEVICE_H_
mjarvisal 0:e6fcdb78a136 36
mjarvisal 0:e6fcdb78a136 37 #include "vl53l0x_types.h"
mjarvisal 0:e6fcdb78a136 38
mjarvisal 0:e6fcdb78a136 39
mjarvisal 0:e6fcdb78a136 40 /** @defgroup VL53L0X_DevSpecDefines_group VL53L0X cut1.1 Device Specific Defines
mjarvisal 0:e6fcdb78a136 41 * @brief VL53L0X cut1.1 Device Specific Defines
mjarvisal 0:e6fcdb78a136 42 * @{
mjarvisal 0:e6fcdb78a136 43 */
mjarvisal 0:e6fcdb78a136 44
mjarvisal 0:e6fcdb78a136 45
mjarvisal 0:e6fcdb78a136 46 /** @defgroup VL53L0X_DeviceError_group Device Error
mjarvisal 0:e6fcdb78a136 47 * @brief Device Error code
mjarvisal 0:e6fcdb78a136 48 *
mjarvisal 0:e6fcdb78a136 49 * This enum is Device specific it should be updated in the implementation
mjarvisal 0:e6fcdb78a136 50 * Use @a VL53L0X_GetStatusErrorString() to get the string.
mjarvisal 0:e6fcdb78a136 51 * It is related to Status Register of the Device.
mjarvisal 0:e6fcdb78a136 52 * @{
mjarvisal 0:e6fcdb78a136 53 */
mjarvisal 0:e6fcdb78a136 54 typedef uint8_t VL53L0X_DeviceError;
mjarvisal 0:e6fcdb78a136 55
mjarvisal 0:e6fcdb78a136 56 #define VL53L0X_DEVICEERROR_NONE ((VL53L0X_DeviceError) 0)
mjarvisal 0:e6fcdb78a136 57 /*!< 0 NoError */
mjarvisal 0:e6fcdb78a136 58 #define VL53L0X_DEVICEERROR_VCSELCONTINUITYTESTFAILURE ((VL53L0X_DeviceError) 1)
mjarvisal 0:e6fcdb78a136 59 #define VL53L0X_DEVICEERROR_VCSELWATCHDOGTESTFAILURE ((VL53L0X_DeviceError) 2)
mjarvisal 0:e6fcdb78a136 60 #define VL53L0X_DEVICEERROR_NOVHVVALUEFOUND ((VL53L0X_DeviceError) 3)
mjarvisal 0:e6fcdb78a136 61 #define VL53L0X_DEVICEERROR_MSRCNOTARGET ((VL53L0X_DeviceError) 4)
mjarvisal 0:e6fcdb78a136 62 #define VL53L0X_DEVICEERROR_SNRCHECK ((VL53L0X_DeviceError) 5)
mjarvisal 0:e6fcdb78a136 63 #define VL53L0X_DEVICEERROR_RANGEPHASECHECK ((VL53L0X_DeviceError) 6)
mjarvisal 0:e6fcdb78a136 64 #define VL53L0X_DEVICEERROR_SIGMATHRESHOLDCHECK ((VL53L0X_DeviceError) 7)
mjarvisal 0:e6fcdb78a136 65 #define VL53L0X_DEVICEERROR_TCC ((VL53L0X_DeviceError) 8)
mjarvisal 0:e6fcdb78a136 66 #define VL53L0X_DEVICEERROR_PHASECONSISTENCY ((VL53L0X_DeviceError) 9)
mjarvisal 0:e6fcdb78a136 67 #define VL53L0X_DEVICEERROR_MINCLIP ((VL53L0X_DeviceError) 10)
mjarvisal 0:e6fcdb78a136 68 #define VL53L0X_DEVICEERROR_RANGECOMPLETE ((VL53L0X_DeviceError) 11)
mjarvisal 0:e6fcdb78a136 69 #define VL53L0X_DEVICEERROR_ALGOUNDERFLOW ((VL53L0X_DeviceError) 12)
mjarvisal 0:e6fcdb78a136 70 #define VL53L0X_DEVICEERROR_ALGOOVERFLOW ((VL53L0X_DeviceError) 13)
mjarvisal 0:e6fcdb78a136 71 #define VL53L0X_DEVICEERROR_RANGEIGNORETHRESHOLD ((VL53L0X_DeviceError) 14)
mjarvisal 0:e6fcdb78a136 72
mjarvisal 0:e6fcdb78a136 73 /** @} end of VL53L0X_DeviceError_group */
mjarvisal 0:e6fcdb78a136 74
mjarvisal 0:e6fcdb78a136 75
mjarvisal 0:e6fcdb78a136 76 /** @defgroup VL53L0X_CheckEnable_group Check Enable list
mjarvisal 0:e6fcdb78a136 77 * @brief Check Enable code
mjarvisal 0:e6fcdb78a136 78 *
mjarvisal 0:e6fcdb78a136 79 * Define used to specify the LimitCheckId.
mjarvisal 0:e6fcdb78a136 80 * Use @a VL53L0X_GetLimitCheckInfo() to get the string.
mjarvisal 0:e6fcdb78a136 81 * @{
mjarvisal 0:e6fcdb78a136 82 */
mjarvisal 0:e6fcdb78a136 83
mjarvisal 0:e6fcdb78a136 84 #define VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE 0
mjarvisal 0:e6fcdb78a136 85 #define VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE 1
mjarvisal 0:e6fcdb78a136 86 #define VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP 2
mjarvisal 0:e6fcdb78a136 87 #define VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD 3
mjarvisal 0:e6fcdb78a136 88 #define VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC 4
mjarvisal 0:e6fcdb78a136 89 #define VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE 5
mjarvisal 0:e6fcdb78a136 90
mjarvisal 0:e6fcdb78a136 91 #define VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS 6
mjarvisal 0:e6fcdb78a136 92
mjarvisal 0:e6fcdb78a136 93 /** @} end of VL53L0X_CheckEnable_group */
mjarvisal 0:e6fcdb78a136 94
mjarvisal 0:e6fcdb78a136 95
mjarvisal 0:e6fcdb78a136 96 /** @defgroup VL53L0X_GpioFunctionality_group Gpio Functionality
mjarvisal 0:e6fcdb78a136 97 * @brief Defines the different functionalities for the device GPIO(s)
mjarvisal 0:e6fcdb78a136 98 * @{
mjarvisal 0:e6fcdb78a136 99 */
mjarvisal 0:e6fcdb78a136 100 typedef uint8_t VL53L0X_GpioFunctionality;
mjarvisal 0:e6fcdb78a136 101
mjarvisal 0:e6fcdb78a136 102 #define VL53L0X_GPIOFUNCTIONALITY_OFF \
mjarvisal 0:e6fcdb78a136 103 ((VL53L0X_GpioFunctionality) 0) /*!< NO Interrupt */
mjarvisal 0:e6fcdb78a136 104 #define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW \
mjarvisal 0:e6fcdb78a136 105 ((VL53L0X_GpioFunctionality) 1) /*!< Level Low (value < thresh_low) */
mjarvisal 0:e6fcdb78a136 106 #define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH \
mjarvisal 0:e6fcdb78a136 107 ((VL53L0X_GpioFunctionality) 2) /*!< Level High (value > thresh_high) */
mjarvisal 0:e6fcdb78a136 108 #define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT \
mjarvisal 0:e6fcdb78a136 109 ((VL53L0X_GpioFunctionality) 3)
mjarvisal 0:e6fcdb78a136 110 /*!< Out Of Window (value < thresh_low OR value > thresh_high) */
mjarvisal 0:e6fcdb78a136 111 #define VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY \
mjarvisal 0:e6fcdb78a136 112 ((VL53L0X_GpioFunctionality) 4) /*!< New Sample Ready */
mjarvisal 0:e6fcdb78a136 113
mjarvisal 0:e6fcdb78a136 114 /** @} end of VL53L0X_GpioFunctionality_group */
mjarvisal 0:e6fcdb78a136 115
mjarvisal 0:e6fcdb78a136 116
mjarvisal 0:e6fcdb78a136 117 /* Device register map */
mjarvisal 0:e6fcdb78a136 118
mjarvisal 0:e6fcdb78a136 119 /** @defgroup VL53L0X_DefineRegisters_group Define Registers
mjarvisal 0:e6fcdb78a136 120 * @brief List of all the defined registers
mjarvisal 0:e6fcdb78a136 121 * @{
mjarvisal 0:e6fcdb78a136 122 */
mjarvisal 0:e6fcdb78a136 123 #define VL53L0X_REG_SYSRANGE_START 0x000
mjarvisal 0:e6fcdb78a136 124 /** mask existing bit in #VL53L0X_REG_SYSRANGE_START*/
mjarvisal 0:e6fcdb78a136 125 #define VL53L0X_REG_SYSRANGE_MODE_MASK 0x0F
mjarvisal 0:e6fcdb78a136 126 /** bit 0 in #VL53L0X_REG_SYSRANGE_START write 1 toggle state in
mjarvisal 0:e6fcdb78a136 127 * continuous mode and arm next shot in single shot mode */
mjarvisal 0:e6fcdb78a136 128 #define VL53L0X_REG_SYSRANGE_MODE_START_STOP 0x01
mjarvisal 0:e6fcdb78a136 129 /** bit 1 write 0 in #VL53L0X_REG_SYSRANGE_START set single shot mode */
mjarvisal 0:e6fcdb78a136 130 #define VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT 0x00
mjarvisal 0:e6fcdb78a136 131 /** bit 1 write 1 in #VL53L0X_REG_SYSRANGE_START set back-to-back
mjarvisal 0:e6fcdb78a136 132 * operation mode */
mjarvisal 0:e6fcdb78a136 133 #define VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK 0x02
mjarvisal 0:e6fcdb78a136 134 /** bit 2 write 1 in #VL53L0X_REG_SYSRANGE_START set timed operation
mjarvisal 0:e6fcdb78a136 135 * mode */
mjarvisal 0:e6fcdb78a136 136 #define VL53L0X_REG_SYSRANGE_MODE_TIMED 0x04
mjarvisal 0:e6fcdb78a136 137 /** bit 3 write 1 in #VL53L0X_REG_SYSRANGE_START set histogram operation
mjarvisal 0:e6fcdb78a136 138 * mode */
mjarvisal 0:e6fcdb78a136 139 #define VL53L0X_REG_SYSRANGE_MODE_HISTOGRAM 0x08
mjarvisal 0:e6fcdb78a136 140
mjarvisal 0:e6fcdb78a136 141
mjarvisal 0:e6fcdb78a136 142 #define VL53L0X_REG_SYSTEM_THRESH_HIGH 0x000C
mjarvisal 0:e6fcdb78a136 143 #define VL53L0X_REG_SYSTEM_THRESH_LOW 0x000E
mjarvisal 0:e6fcdb78a136 144
mjarvisal 0:e6fcdb78a136 145
mjarvisal 0:e6fcdb78a136 146 #define VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG 0x0001
mjarvisal 0:e6fcdb78a136 147 #define VL53L0X_REG_SYSTEM_RANGE_CONFIG 0x0009
mjarvisal 0:e6fcdb78a136 148 #define VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD 0x0004
mjarvisal 0:e6fcdb78a136 149
mjarvisal 0:e6fcdb78a136 150
mjarvisal 0:e6fcdb78a136 151 #define VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO 0x000A
mjarvisal 0:e6fcdb78a136 152 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_DISABLED 0x00
mjarvisal 0:e6fcdb78a136 153 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_LOW 0x01
mjarvisal 0:e6fcdb78a136 154 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_HIGH 0x02
mjarvisal 0:e6fcdb78a136 155 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_OUT_OF_WINDOW 0x03
mjarvisal 0:e6fcdb78a136 156 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY 0x04
mjarvisal 0:e6fcdb78a136 157
mjarvisal 0:e6fcdb78a136 158 #define VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH 0x0084
mjarvisal 0:e6fcdb78a136 159
mjarvisal 0:e6fcdb78a136 160
mjarvisal 0:e6fcdb78a136 161 #define VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR 0x000B
mjarvisal 0:e6fcdb78a136 162
mjarvisal 0:e6fcdb78a136 163 /* Result registers */
mjarvisal 0:e6fcdb78a136 164 #define VL53L0X_REG_RESULT_INTERRUPT_STATUS 0x0013
mjarvisal 0:e6fcdb78a136 165 #define VL53L0X_REG_RESULT_RANGE_STATUS 0x0014
mjarvisal 0:e6fcdb78a136 166
mjarvisal 0:e6fcdb78a136 167 #define VL53L0X_REG_RESULT_CORE_PAGE 1
mjarvisal 0:e6fcdb78a136 168 #define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN 0x00BC
mjarvisal 0:e6fcdb78a136 169 #define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN 0x00C0
mjarvisal 0:e6fcdb78a136 170 #define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF 0x00D0
mjarvisal 0:e6fcdb78a136 171 #define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_REF 0x00D4
mjarvisal 0:e6fcdb78a136 172 #define VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF 0x00B6
mjarvisal 0:e6fcdb78a136 173
mjarvisal 0:e6fcdb78a136 174 /* Algo register */
mjarvisal 0:e6fcdb78a136 175
mjarvisal 0:e6fcdb78a136 176 #define VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM 0x0028
mjarvisal 0:e6fcdb78a136 177
mjarvisal 0:e6fcdb78a136 178 #define VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS 0x008a
mjarvisal 0:e6fcdb78a136 179
mjarvisal 0:e6fcdb78a136 180 /* Check Limit registers */
mjarvisal 0:e6fcdb78a136 181 #define VL53L0X_REG_MSRC_CONFIG_CONTROL 0x0060
mjarvisal 0:e6fcdb78a136 182
mjarvisal 0:e6fcdb78a136 183 #define VL53L0X_REG_PRE_RANGE_CONFIG_MIN_SNR 0X0027
mjarvisal 0:e6fcdb78a136 184 #define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW 0x0056
mjarvisal 0:e6fcdb78a136 185 #define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH 0x0057
mjarvisal 0:e6fcdb78a136 186 #define VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT 0x0064
mjarvisal 0:e6fcdb78a136 187
mjarvisal 0:e6fcdb78a136 188 #define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_SNR 0X0067
mjarvisal 0:e6fcdb78a136 189 #define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW 0x0047
mjarvisal 0:e6fcdb78a136 190 #define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH 0x0048
mjarvisal 0:e6fcdb78a136 191 #define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT 0x0044
mjarvisal 0:e6fcdb78a136 192
mjarvisal 0:e6fcdb78a136 193
mjarvisal 0:e6fcdb78a136 194 #define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_HI 0X0061
mjarvisal 0:e6fcdb78a136 195 #define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_LO 0X0062
mjarvisal 0:e6fcdb78a136 196
mjarvisal 0:e6fcdb78a136 197 /* PRE RANGE registers */
mjarvisal 0:e6fcdb78a136 198 #define VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD 0x0050
mjarvisal 0:e6fcdb78a136 199 #define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0051
mjarvisal 0:e6fcdb78a136 200 #define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0052
mjarvisal 0:e6fcdb78a136 201
mjarvisal 0:e6fcdb78a136 202 #define VL53L0X_REG_SYSTEM_HISTOGRAM_BIN 0x0081
mjarvisal 0:e6fcdb78a136 203 #define VL53L0X_REG_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT 0x0033
mjarvisal 0:e6fcdb78a136 204 #define VL53L0X_REG_HISTOGRAM_CONFIG_READOUT_CTRL 0x0055
mjarvisal 0:e6fcdb78a136 205
mjarvisal 0:e6fcdb78a136 206 #define VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD 0x0070
mjarvisal 0:e6fcdb78a136 207 #define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0071
mjarvisal 0:e6fcdb78a136 208 #define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0072
mjarvisal 0:e6fcdb78a136 209 #define VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS 0x0020
mjarvisal 0:e6fcdb78a136 210
mjarvisal 0:e6fcdb78a136 211 #define VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP 0x0046
mjarvisal 0:e6fcdb78a136 212
mjarvisal 0:e6fcdb78a136 213
mjarvisal 0:e6fcdb78a136 214 #define VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N 0x00bf
mjarvisal 0:e6fcdb78a136 215 #define VL53L0X_REG_IDENTIFICATION_MODEL_ID 0x00c0
mjarvisal 0:e6fcdb78a136 216 #define VL53L0X_REG_IDENTIFICATION_REVISION_ID 0x00c2
mjarvisal 0:e6fcdb78a136 217
mjarvisal 0:e6fcdb78a136 218 #define VL53L0X_REG_OSC_CALIBRATE_VAL 0x00f8
mjarvisal 0:e6fcdb78a136 219
mjarvisal 0:e6fcdb78a136 220
mjarvisal 0:e6fcdb78a136 221 #define VL53L0X_SIGMA_ESTIMATE_MAX_VALUE 65535
mjarvisal 0:e6fcdb78a136 222 /* equivalent to a range sigma of 655.35mm */
mjarvisal 0:e6fcdb78a136 223
mjarvisal 0:e6fcdb78a136 224 #define VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH 0x032
mjarvisal 0:e6fcdb78a136 225 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 0x0B0
mjarvisal 0:e6fcdb78a136 226 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 0x0B1
mjarvisal 0:e6fcdb78a136 227 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 0x0B2
mjarvisal 0:e6fcdb78a136 228 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 0x0B3
mjarvisal 0:e6fcdb78a136 229 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 0x0B4
mjarvisal 0:e6fcdb78a136 230 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 0x0B5
mjarvisal 0:e6fcdb78a136 231
mjarvisal 0:e6fcdb78a136 232 #define VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT 0xB6
mjarvisal 0:e6fcdb78a136 233 #define VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD 0x4E /* 0x14E */
mjarvisal 0:e6fcdb78a136 234 #define VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET 0x4F /* 0x14F */
mjarvisal 0:e6fcdb78a136 235 #define VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE 0x80
mjarvisal 0:e6fcdb78a136 236
mjarvisal 0:e6fcdb78a136 237 /*
mjarvisal 0:e6fcdb78a136 238 * Speed of light in um per 1E-10 Seconds
mjarvisal 0:e6fcdb78a136 239 */
mjarvisal 0:e6fcdb78a136 240
mjarvisal 0:e6fcdb78a136 241 #define VL53L0X_SPEED_OF_LIGHT_IN_AIR 2997
mjarvisal 0:e6fcdb78a136 242
mjarvisal 0:e6fcdb78a136 243 #define VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV 0x0089
mjarvisal 0:e6fcdb78a136 244
mjarvisal 0:e6fcdb78a136 245 #define VL53L0X_REG_ALGO_PHASECAL_LIM 0x0030 /* 0x130 */
mjarvisal 0:e6fcdb78a136 246 #define VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT 0x0030
mjarvisal 0:e6fcdb78a136 247
mjarvisal 0:e6fcdb78a136 248 /** @} VL53L0X_DefineRegisters_group */
mjarvisal 0:e6fcdb78a136 249
mjarvisal 0:e6fcdb78a136 250 /** @} VL53L0X_DevSpecDefines_group */
mjarvisal 0:e6fcdb78a136 251
mjarvisal 0:e6fcdb78a136 252
mjarvisal 0:e6fcdb78a136 253 #endif
mjarvisal 0:e6fcdb78a136 254
mjarvisal 0:e6fcdb78a136 255 /* _VL53L0X_DEVICE_H_ */
mjarvisal 0:e6fcdb78a136 256
mjarvisal 0:e6fcdb78a136 257