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core_sc000.h
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00001 /**************************************************************************//** 00002 * @file core_sc000.h 00003 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 00004 * @version V4.00 00005 * @date 22. August 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_SC000_H_GENERIC 00043 #define __CORE_SC000_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup SC000 00067 @{ 00068 */ 00069 00070 /* CMSIS SC000 definitions */ 00071 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ 00074 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_SC (000) /*!< Cortex secure core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 This core does not support an FPU at all 00113 */ 00114 #define __FPU_USED 0 00115 00116 #if defined ( __CC_ARM ) 00117 #if defined __TARGET_FPU_VFP 00118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00119 #endif 00120 00121 #elif defined ( __GNUC__ ) 00122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00124 #endif 00125 00126 #elif defined ( __ICCARM__ ) 00127 #if defined __ARMVFP__ 00128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00129 #endif 00130 00131 #elif defined ( __TMS470__ ) 00132 #if defined __TI__VFP_SUPPORT____ 00133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00139 #endif 00140 00141 #elif defined ( __CSMC__ ) /* Cosmic */ 00142 #if ( __CSMC__ & 0x400) // FPU present for parser 00143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #endif 00145 #endif 00146 00147 #include <stdint.h> /* standard types definitions */ 00148 #include <core_cmInstr.h> /* Core Instruction Access */ 00149 #include <core_cmFunc.h> /* Core Function Access */ 00150 00151 #ifdef __cplusplus 00152 } 00153 #endif 00154 00155 #endif /* __CORE_SC000_H_GENERIC */ 00156 00157 #ifndef __CMSIS_GENERIC 00158 00159 #ifndef __CORE_SC000_H_DEPENDANT 00160 #define __CORE_SC000_H_DEPENDANT 00161 00162 #ifdef __cplusplus 00163 extern "C" { 00164 #endif 00165 00166 /* check device defines and use defaults */ 00167 #if defined __CHECK_DEVICE_DEFINES 00168 #ifndef __SC000_REV 00169 #define __SC000_REV 0x0000 00170 #warning "__SC000_REV not defined in device header file; using default!" 00171 #endif 00172 00173 #ifndef __MPU_PRESENT 00174 #define __MPU_PRESENT 0 00175 #warning "__MPU_PRESENT not defined in device header file; using default!" 00176 #endif 00177 00178 #ifndef __NVIC_PRIO_BITS 00179 #define __NVIC_PRIO_BITS 2 00180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00181 #endif 00182 00183 #ifndef __Vendor_SysTickConfig 00184 #define __Vendor_SysTickConfig 0 00185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00186 #endif 00187 #endif 00188 00189 /* IO definitions (access restrictions to peripheral registers) */ 00190 /** 00191 \defgroup CMSIS_glob_defs CMSIS Global Defines 00192 00193 <strong>IO Type Qualifiers</strong> are used 00194 \li to specify the access to peripheral variables. 00195 \li for automatic generation of peripheral register debug information. 00196 */ 00197 #ifdef __cplusplus 00198 #define __I volatile /*!< Defines 'read only' permissions */ 00199 #else 00200 #define __I volatile const /*!< Defines 'read only' permissions */ 00201 #endif 00202 #define __O volatile /*!< Defines 'write only' permissions */ 00203 #define __IO volatile /*!< Defines 'read / write' permissions */ 00204 00205 /*@} end of group SC000 */ 00206 00207 00208 00209 /******************************************************************************* 00210 * Register Abstraction 00211 Core Register contain: 00212 - Core Register 00213 - Core NVIC Register 00214 - Core SCB Register 00215 - Core SysTick Register 00216 - Core MPU Register 00217 ******************************************************************************/ 00218 /** \defgroup CMSIS_core_register Defines and Type Definitions 00219 \brief Type definitions and defines for Cortex-M processor based devices. 00220 */ 00221 00222 /** \ingroup CMSIS_core_register 00223 \defgroup CMSIS_CORE Status and Control Registers 00224 \brief Core Register type definitions. 00225 @{ 00226 */ 00227 00228 /** \brief Union type to access the Application Program Status Register (APSR). 00229 */ 00230 typedef union 00231 { 00232 struct 00233 { 00234 #if (__CORTEX_M != 0x04) 00235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00236 #else 00237 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00238 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00239 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00240 #endif 00241 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00242 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00243 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00244 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00245 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00246 } b; /*!< Structure used for bit access */ 00247 uint32_t w; /*!< Type used for word access */ 00248 } APSR_Type; 00249 00250 00251 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00252 */ 00253 typedef union 00254 { 00255 struct 00256 { 00257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00259 } b; /*!< Structure used for bit access */ 00260 uint32_t w; /*!< Type used for word access */ 00261 } IPSR_Type; 00262 00263 00264 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00265 */ 00266 typedef union 00267 { 00268 struct 00269 { 00270 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00271 #if (__CORTEX_M != 0x04) 00272 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00273 #else 00274 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00275 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00276 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00277 #endif 00278 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00279 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00280 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00281 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00282 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00283 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00284 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00285 } b; /*!< Structure used for bit access */ 00286 uint32_t w; /*!< Type used for word access */ 00287 } xPSR_Type; 00288 00289 00290 /** \brief Union type to access the Control Registers (CONTROL). 00291 */ 00292 typedef union 00293 { 00294 struct 00295 { 00296 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00298 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00299 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00300 } b; /*!< Structure used for bit access */ 00301 uint32_t w; /*!< Type used for word access */ 00302 } CONTROL_Type; 00303 00304 /*@} end of group CMSIS_CORE */ 00305 00306 00307 /** \ingroup CMSIS_core_register 00308 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00309 \brief Type definitions for the NVIC Registers 00310 @{ 00311 */ 00312 00313 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00314 */ 00315 typedef struct 00316 { 00317 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00318 uint32_t RESERVED0[31]; 00319 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00320 uint32_t RSERVED1[31]; 00321 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00322 uint32_t RESERVED2[31]; 00323 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00324 uint32_t RESERVED3[31]; 00325 uint32_t RESERVED4[64]; 00326 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00327 } NVIC_Type; 00328 00329 /*@} end of group CMSIS_NVIC */ 00330 00331 00332 /** \ingroup CMSIS_core_register 00333 \defgroup CMSIS_SCB System Control Block (SCB) 00334 \brief Type definitions for the System Control Block Registers 00335 @{ 00336 */ 00337 00338 /** \brief Structure type to access the System Control Block (SCB). 00339 */ 00340 typedef struct 00341 { 00342 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00343 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00344 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00345 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00346 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00347 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00348 uint32_t RESERVED0[1]; 00349 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00350 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00351 uint32_t RESERVED1[154]; 00352 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ 00353 } SCB_Type; 00354 00355 /* SCB CPUID Register Definitions */ 00356 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00357 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00358 00359 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00360 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00361 00362 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00363 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00364 00365 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00366 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00367 00368 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00369 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00370 00371 /* SCB Interrupt Control State Register Definitions */ 00372 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00373 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00374 00375 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00376 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00377 00378 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00379 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00380 00381 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00382 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00383 00384 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00385 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00386 00387 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00388 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00389 00390 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00391 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00392 00393 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00394 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00395 00396 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00397 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00398 00399 /* SCB Interrupt Control State Register Definitions */ 00400 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00401 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00402 00403 /* SCB Application Interrupt and Reset Control Register Definitions */ 00404 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00406 00407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00409 00410 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00412 00413 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00415 00416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00418 00419 /* SCB System Control Register Definitions */ 00420 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00422 00423 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00425 00426 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00428 00429 /* SCB Configuration Control Register Definitions */ 00430 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00432 00433 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00435 00436 /* SCB System Handler Control and State Register Definitions */ 00437 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00439 00440 /* SCB Security Features Register Definitions */ 00441 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ 00442 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ 00443 00444 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ 00445 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ 00446 00447 /*@} end of group CMSIS_SCB */ 00448 00449 00450 /** \ingroup CMSIS_core_register 00451 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00452 \brief Type definitions for the System Control and ID Register not in the SCB 00453 @{ 00454 */ 00455 00456 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00457 */ 00458 typedef struct 00459 { 00460 uint32_t RESERVED0[2]; 00461 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00462 } SCnSCB_Type; 00463 00464 /* Auxiliary Control Register Definitions */ 00465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 00467 00468 /*@} end of group CMSIS_SCnotSCB */ 00469 00470 00471 /** \ingroup CMSIS_core_register 00472 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00473 \brief Type definitions for the System Timer Registers. 00474 @{ 00475 */ 00476 00477 /** \brief Structure type to access the System Timer (SysTick). 00478 */ 00479 typedef struct 00480 { 00481 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00482 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00483 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00484 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00485 } SysTick_Type; 00486 00487 /* SysTick Control / Status Register Definitions */ 00488 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00489 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00490 00491 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00492 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00493 00494 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00495 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00496 00497 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00498 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00499 00500 /* SysTick Reload Register Definitions */ 00501 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00502 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00503 00504 /* SysTick Current Register Definitions */ 00505 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00506 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00507 00508 /* SysTick Calibration Register Definitions */ 00509 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00510 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00511 00512 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00513 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00514 00515 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00516 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 00517 00518 /*@} end of group CMSIS_SysTick */ 00519 00520 #if (__MPU_PRESENT == 1) 00521 /** \ingroup CMSIS_core_register 00522 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00523 \brief Type definitions for the Memory Protection Unit (MPU) 00524 @{ 00525 */ 00526 00527 /** \brief Structure type to access the Memory Protection Unit (MPU). 00528 */ 00529 typedef struct 00530 { 00531 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00532 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00533 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00534 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00535 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00536 } MPU_Type; 00537 00538 /* MPU Type Register */ 00539 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00540 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00541 00542 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00543 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00544 00545 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00546 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 00547 00548 /* MPU Control Register */ 00549 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00550 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00551 00552 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00553 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00554 00555 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00556 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 00557 00558 /* MPU Region Number Register */ 00559 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00560 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 00561 00562 /* MPU Region Base Address Register */ 00563 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00564 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00565 00566 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00567 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00568 00569 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00570 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 00571 00572 /* MPU Region Attribute and Size Register */ 00573 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00574 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00575 00576 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00577 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00578 00579 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00580 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00581 00582 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00583 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00584 00585 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00586 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00587 00588 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00589 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00590 00591 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00592 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00593 00594 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00595 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00596 00597 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00598 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00599 00600 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00601 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 00602 00603 /*@} end of group CMSIS_MPU */ 00604 #endif 00605 00606 00607 /** \ingroup CMSIS_core_register 00608 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00609 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00610 are only accessible over DAP and not via processor. Therefore 00611 they are not covered by the Cortex-M0 header file. 00612 @{ 00613 */ 00614 /*@} end of group CMSIS_CoreDebug */ 00615 00616 00617 /** \ingroup CMSIS_core_register 00618 \defgroup CMSIS_core_base Core Definitions 00619 \brief Definitions for base addresses, unions, and structures. 00620 @{ 00621 */ 00622 00623 /* Memory mapping of SC000 Hardware */ 00624 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00625 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00626 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00627 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00628 00629 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 00630 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00631 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00632 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00633 00634 #if (__MPU_PRESENT == 1) 00635 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00636 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00637 #endif 00638 00639 /*@} */ 00640 00641 00642 00643 /******************************************************************************* 00644 * Hardware Abstraction Layer 00645 Core Function Interface contains: 00646 - Core NVIC Functions 00647 - Core SysTick Functions 00648 - Core Register Access Functions 00649 ******************************************************************************/ 00650 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00651 */ 00652 00653 00654 00655 /* ########################## NVIC functions #################################### */ 00656 /** \ingroup CMSIS_Core_FunctionInterface 00657 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00658 \brief Functions that manage interrupts and exceptions via the NVIC. 00659 @{ 00660 */ 00661 00662 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00663 /* The following MACROS handle generation of the register offset and byte masks */ 00664 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00665 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00666 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00667 00668 00669 /** \brief Enable External Interrupt 00670 00671 The function enables a device-specific interrupt in the NVIC interrupt controller. 00672 00673 \param [in] IRQn External interrupt number. Value cannot be negative. 00674 */ 00675 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00676 { 00677 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00678 } 00679 00680 00681 /** \brief Disable External Interrupt 00682 00683 The function disables a device-specific interrupt in the NVIC interrupt controller. 00684 00685 \param [in] IRQn External interrupt number. Value cannot be negative. 00686 */ 00687 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00688 { 00689 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00690 } 00691 00692 00693 /** \brief Get Pending Interrupt 00694 00695 The function reads the pending register in the NVIC and returns the pending bit 00696 for the specified interrupt. 00697 00698 \param [in] IRQn Interrupt number. 00699 00700 \return 0 Interrupt status is not pending. 00701 \return 1 Interrupt status is pending. 00702 */ 00703 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00704 { 00705 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00706 } 00707 00708 00709 /** \brief Set Pending Interrupt 00710 00711 The function sets the pending bit of an external interrupt. 00712 00713 \param [in] IRQn Interrupt number. Value cannot be negative. 00714 */ 00715 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00716 { 00717 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00718 } 00719 00720 00721 /** \brief Clear Pending Interrupt 00722 00723 The function clears the pending bit of an external interrupt. 00724 00725 \param [in] IRQn External interrupt number. Value cannot be negative. 00726 */ 00727 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00728 { 00729 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00730 } 00731 00732 00733 /** \brief Set Interrupt Priority 00734 00735 The function sets the priority of an interrupt. 00736 00737 \note The priority cannot be set for every core interrupt. 00738 00739 \param [in] IRQn Interrupt number. 00740 \param [in] priority Priority to set. 00741 */ 00742 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00743 { 00744 if(IRQn < 0) { 00745 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00746 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00747 else { 00748 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00749 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00750 } 00751 00752 00753 /** \brief Get Interrupt Priority 00754 00755 The function reads the priority of an interrupt. The interrupt 00756 number can be positive to specify an external (device specific) 00757 interrupt, or negative to specify an internal (core) interrupt. 00758 00759 00760 \param [in] IRQn Interrupt number. 00761 \return Interrupt Priority. Value is aligned automatically to the implemented 00762 priority bits of the microcontroller. 00763 */ 00764 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00765 { 00766 00767 if(IRQn < 0) { 00768 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00769 else { 00770 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00771 } 00772 00773 00774 /** \brief System Reset 00775 00776 The function initiates a system reset request to reset the MCU. 00777 */ 00778 __STATIC_INLINE void NVIC_SystemReset(void) 00779 { 00780 __DSB(); /* Ensure all outstanding memory accesses included 00781 buffered write are completed before reset */ 00782 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00783 SCB_AIRCR_SYSRESETREQ_Msk); 00784 __DSB(); /* Ensure completion of memory access */ 00785 while(1); /* wait until reset */ 00786 } 00787 00788 /*@} end of CMSIS_Core_NVICFunctions */ 00789 00790 00791 00792 /* ################################## SysTick function ############################################ */ 00793 /** \ingroup CMSIS_Core_FunctionInterface 00794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00795 \brief Functions that configure the System. 00796 @{ 00797 */ 00798 00799 #if (__Vendor_SysTickConfig == 0) 00800 00801 /** \brief System Tick Configuration 00802 00803 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00804 Counter is in free running mode to generate periodic interrupts. 00805 00806 \param [in] ticks Number of ticks between two interrupts. 00807 00808 \return 0 Function succeeded. 00809 \return 1 Function failed. 00810 00811 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00812 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00813 must contain a vendor-specific implementation of this function. 00814 00815 */ 00816 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00817 { 00818 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00819 00820 SysTick->LOAD = ticks - 1; /* set reload register */ 00821 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00822 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00823 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00824 SysTick_CTRL_TICKINT_Msk | 00825 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00826 return (0); /* Function successful */ 00827 } 00828 00829 #endif 00830 00831 /*@} end of CMSIS_Core_SysTickFunctions */ 00832 00833 00834 00835 00836 #ifdef __cplusplus 00837 } 00838 #endif 00839 00840 #endif /* __CORE_SC000_H_DEPENDANT */ 00841 00842 #endif /* __CMSIS_GENERIC */
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