core_cmInstr.h

00001 /**************************************************************************//**
00002  * @file     core_cmInstr.h
00003  * @brief    CMSIS Cortex-M Core Instruction Access Header File
00004  * @version  V4.00
00005  * @date     28. August 2014
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2014 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #ifndef __CORE_CMINSTR_H
00039 #define __CORE_CMINSTR_H
00040 
00041 
00042 /* ##########################  Core Instruction Access  ######################### */
00043 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
00044   Access to dedicated instructions
00045   @{
00046 */
00047 
00048 #if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
00049 /* ARM armcc specific functions */
00050 
00051 #if (__ARMCC_VERSION < 400677)
00052   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
00053 #endif
00054 
00055 
00056 /** \brief  No Operation
00057 
00058     No Operation does nothing. This instruction can be used for code alignment purposes.
00059  */
00060 #define __NOP                             __nop
00061 
00062 
00063 /** \brief  Wait For Interrupt
00064 
00065     Wait For Interrupt is a hint instruction that suspends execution
00066     until one of a number of events occurs.
00067  */
00068 #define __WFI                             __wfi
00069 
00070 
00071 /** \brief  Wait For Event
00072 
00073     Wait For Event is a hint instruction that permits the processor to enter
00074     a low-power state until one of a number of events occurs.
00075  */
00076 #define __WFE                             __wfe
00077 
00078 
00079 /** \brief  Send Event
00080 
00081     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
00082  */
00083 #define __SEV                             __sev
00084 
00085 
00086 /** \brief  Instruction Synchronization Barrier
00087 
00088     Instruction Synchronization Barrier flushes the pipeline in the processor,
00089     so that all instructions following the ISB are fetched from cache or
00090     memory, after the instruction has been completed.
00091  */
00092 #define __ISB()                           __isb(0xF)
00093 
00094 
00095 /** \brief  Data Synchronization Barrier
00096 
00097     This function acts as a special kind of Data Memory Barrier.
00098     It completes when all explicit memory accesses before this instruction complete.
00099  */
00100 #define __DSB()                           __dsb(0xF)
00101 
00102 
00103 /** \brief  Data Memory Barrier
00104 
00105     This function ensures the apparent order of the explicit memory operations before
00106     and after the instruction, without ensuring their completion.
00107  */
00108 #define __DMB()                           __dmb(0xF)
00109 
00110 
00111 /** \brief  Reverse byte order (32 bit)
00112 
00113     This function reverses the byte order in integer value.
00114 
00115     \param [in]    value  Value to reverse
00116     \return               Reversed value
00117  */
00118 #define __REV                             __rev
00119 
00120 
00121 /** \brief  Reverse byte order (16 bit)
00122 
00123     This function reverses the byte order in two unsigned short values.
00124 
00125     \param [in]    value  Value to reverse
00126     \return               Reversed value
00127  */
00128 #ifndef __NO_EMBEDDED_ASM
00129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
00130 {
00131   rev16 r0, r0
00132   bx lr
00133 }
00134 #endif
00135 
00136 /** \brief  Reverse byte order in signed short value
00137 
00138     This function reverses the byte order in a signed short value with sign extension to integer.
00139 
00140     \param [in]    value  Value to reverse
00141     \return               Reversed value
00142  */
00143 #ifndef __NO_EMBEDDED_ASM
00144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
00145 {
00146   revsh r0, r0
00147   bx lr
00148 }
00149 #endif
00150 
00151 
00152 /** \brief  Rotate Right in unsigned value (32 bit)
00153 
00154     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
00155 
00156     \param [in]    value  Value to rotate
00157     \param [in]    value  Number of Bits to rotate
00158     \return               Rotated value
00159  */
00160 #define __ROR                             __ror
00161 
00162 
00163 /** \brief  Breakpoint
00164 
00165     This function causes the processor to enter Debug state.
00166     Debug tools can use this to investigate system state when the instruction at a particular address is reached.
00167 
00168     \param [in]    value  is ignored by the processor.
00169                    If required, a debugger can use it to store additional information about the breakpoint.
00170  */
00171 #define __BKPT(value)                       __breakpoint(value)
00172 
00173 
00174 #if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
00175 
00176 /** \brief  Reverse bit order of value
00177 
00178     This function reverses the bit order of the given value.
00179 
00180     \param [in]    value  Value to reverse
00181     \return               Reversed value
00182  */
00183 #define __RBIT                            __rbit
00184 
00185 
00186 /** \brief  LDR Exclusive (8 bit)
00187 
00188     This function executes a exclusive LDR instruction for 8 bit value.
00189 
00190     \param [in]    ptr  Pointer to data
00191     \return             value of type uint8_t at (*ptr)
00192  */
00193 #define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
00194 
00195 
00196 /** \brief  LDR Exclusive (16 bit)
00197 
00198     This function executes a exclusive LDR instruction for 16 bit values.
00199 
00200     \param [in]    ptr  Pointer to data
00201     \return        value of type uint16_t at (*ptr)
00202  */
00203 #define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
00204 
00205 
00206 /** \brief  LDR Exclusive (32 bit)
00207 
00208     This function executes a exclusive LDR instruction for 32 bit values.
00209 
00210     \param [in]    ptr  Pointer to data
00211     \return        value of type uint32_t at (*ptr)
00212  */
00213 #define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
00214 
00215 
00216 /** \brief  STR Exclusive (8 bit)
00217 
00218     This function executes a exclusive STR instruction for 8 bit values.
00219 
00220     \param [in]  value  Value to store
00221     \param [in]    ptr  Pointer to location
00222     \return          0  Function succeeded
00223     \return          1  Function failed
00224  */
00225 #define __STREXB(value, ptr)              __strex(value, ptr)
00226 
00227 
00228 /** \brief  STR Exclusive (16 bit)
00229 
00230     This function executes a exclusive STR instruction for 16 bit values.
00231 
00232     \param [in]  value  Value to store
00233     \param [in]    ptr  Pointer to location
00234     \return          0  Function succeeded
00235     \return          1  Function failed
00236  */
00237 #define __STREXH(value, ptr)              __strex(value, ptr)
00238 
00239 
00240 /** \brief  STR Exclusive (32 bit)
00241 
00242     This function executes a exclusive STR instruction for 32 bit values.
00243 
00244     \param [in]  value  Value to store
00245     \param [in]    ptr  Pointer to location
00246     \return          0  Function succeeded
00247     \return          1  Function failed
00248  */
00249 #define __STREXW(value, ptr)              __strex(value, ptr)
00250 
00251 
00252 /** \brief  Remove the exclusive lock
00253 
00254     This function removes the exclusive lock which is created by LDREX.
00255 
00256  */
00257 #define __CLREX                           __clrex
00258 
00259 
00260 /** \brief  Signed Saturate
00261 
00262     This function saturates a signed value.
00263 
00264     \param [in]  value  Value to be saturated
00265     \param [in]    sat  Bit position to saturate to (1..32)
00266     \return             Saturated value
00267  */
00268 #define __SSAT                            __ssat
00269 
00270 
00271 /** \brief  Unsigned Saturate
00272 
00273     This function saturates an unsigned value.
00274 
00275     \param [in]  value  Value to be saturated
00276     \param [in]    sat  Bit position to saturate to (0..31)
00277     \return             Saturated value
00278  */
00279 #define __USAT                            __usat
00280 
00281 
00282 /** \brief  Count leading zeros
00283 
00284     This function counts the number of leading zeros of a data value.
00285 
00286     \param [in]  value  Value to count the leading zeros
00287     \return             number of leading zeros in value
00288  */
00289 #define __CLZ                             __clz
00290 
00291 
00292 /** \brief  Rotate Right with Extend (32 bit)
00293 
00294     This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
00295 
00296     \param [in]    value  Value to rotate
00297     \return               Rotated value
00298  */
00299 #ifndef __NO_EMBEDDED_ASM
00300 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
00301 {
00302   rrx r0, r0
00303   bx lr
00304 }
00305 #endif
00306 
00307 
00308 /** \brief  LDRT Unprivileged (8 bit)
00309 
00310     This function executes a Unprivileged LDRT instruction for 8 bit value.
00311 
00312     \param [in]    ptr  Pointer to data
00313     \return             value of type uint8_t at (*ptr)
00314  */
00315 #define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
00316 
00317 
00318 /** \brief  LDRT Unprivileged (16 bit)
00319 
00320     This function executes a Unprivileged LDRT instruction for 16 bit values.
00321 
00322     \param [in]    ptr  Pointer to data
00323     \return        value of type uint16_t at (*ptr)
00324  */
00325 #define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
00326 
00327 
00328 /** \brief  LDRT Unprivileged (32 bit)
00329 
00330     This function executes a Unprivileged LDRT instruction for 32 bit values.
00331 
00332     \param [in]    ptr  Pointer to data
00333     \return        value of type uint32_t at (*ptr)
00334  */
00335 #define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
00336 
00337 
00338 /** \brief  STRT Unprivileged (8 bit)
00339 
00340     This function executes a Unprivileged STRT instruction for 8 bit values.
00341 
00342     \param [in]  value  Value to store
00343     \param [in]    ptr  Pointer to location
00344  */
00345 #define __STRBT(value, ptr)               __strt(value, ptr)
00346 
00347 
00348 /** \brief  STRT Unprivileged (16 bit)
00349 
00350     This function executes a Unprivileged STRT instruction for 16 bit values.
00351 
00352     \param [in]  value  Value to store
00353     \param [in]    ptr  Pointer to location
00354  */
00355 #define __STRHT(value, ptr)               __strt(value, ptr)
00356 
00357 
00358 /** \brief  STRT Unprivileged (32 bit)
00359 
00360     This function executes a Unprivileged STRT instruction for 32 bit values.
00361 
00362     \param [in]  value  Value to store
00363     \param [in]    ptr  Pointer to location
00364  */
00365 #define __STRT(value, ptr)                __strt(value, ptr)
00366 
00367 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
00368 
00369 
00370 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
00371 /* GNU gcc specific functions */
00372 
00373 /* Define macros for porting to both thumb1 and thumb2.
00374  * For thumb1, use low register (r0-r7), specified by constrant "l"
00375  * Otherwise, use general registers, specified by constrant "r" */
00376 #if defined (__thumb__) && !defined (__thumb2__)
00377 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
00378 #define __CMSIS_GCC_USE_REG(r) "l" (r)
00379 #else
00380 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
00381 #define __CMSIS_GCC_USE_REG(r) "r" (r)
00382 #endif
00383 
00384 /** \brief  No Operation
00385 
00386     No Operation does nothing. This instruction can be used for code alignment purposes.
00387  */
00388 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
00389 {
00390   __ASM volatile ("nop");
00391 }
00392 
00393 
00394 /** \brief  Wait For Interrupt
00395 
00396     Wait For Interrupt is a hint instruction that suspends execution
00397     until one of a number of events occurs.
00398  */
00399 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
00400 {
00401   __ASM volatile ("wfi");
00402 }
00403 
00404 
00405 /** \brief  Wait For Event
00406 
00407     Wait For Event is a hint instruction that permits the processor to enter
00408     a low-power state until one of a number of events occurs.
00409  */
00410 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
00411 {
00412   __ASM volatile ("wfe");
00413 }
00414 
00415 
00416 /** \brief  Send Event
00417 
00418     Send Event is a hint instruction. It causes an event to be signaled to the CPU.
00419  */
00420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
00421 {
00422   __ASM volatile ("sev");
00423 }
00424 
00425 
00426 /** \brief  Instruction Synchronization Barrier
00427 
00428     Instruction Synchronization Barrier flushes the pipeline in the processor,
00429     so that all instructions following the ISB are fetched from cache or
00430     memory, after the instruction has been completed.
00431  */
00432 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
00433 {
00434   __ASM volatile ("isb");
00435 }
00436 
00437 
00438 /** \brief  Data Synchronization Barrier
00439 
00440     This function acts as a special kind of Data Memory Barrier.
00441     It completes when all explicit memory accesses before this instruction complete.
00442  */
00443 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
00444 {
00445   __ASM volatile ("dsb");
00446 }
00447 
00448 
00449 /** \brief  Data Memory Barrier
00450 
00451     This function ensures the apparent order of the explicit memory operations before
00452     and after the instruction, without ensuring their completion.
00453  */
00454 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
00455 {
00456   __ASM volatile ("dmb");
00457 }
00458 
00459 
00460 /** \brief  Reverse byte order (32 bit)
00461 
00462     This function reverses the byte order in integer value.
00463 
00464     \param [in]    value  Value to reverse
00465     \return               Reversed value
00466  */
00467 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
00468 {
00469 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
00470   return __builtin_bswap32(value);
00471 #else
00472   uint32_t result;
00473 
00474   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
00475   return(result);
00476 #endif
00477 }
00478 
00479 
00480 /** \brief  Reverse byte order (16 bit)
00481 
00482     This function reverses the byte order in two unsigned short values.
00483 
00484     \param [in]    value  Value to reverse
00485     \return               Reversed value
00486  */
00487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
00488 {
00489   uint32_t result;
00490 
00491   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
00492   return(result);
00493 }
00494 
00495 
00496 /** \brief  Reverse byte order in signed short value
00497 
00498     This function reverses the byte order in a signed short value with sign extension to integer.
00499 
00500     \param [in]    value  Value to reverse
00501     \return               Reversed value
00502  */
00503 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
00504 {
00505 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
00506   return (short)__builtin_bswap16(value);
00507 #else
00508   uint32_t result;
00509 
00510   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
00511   return(result);
00512 #endif
00513 }
00514 
00515 
00516 /** \brief  Rotate Right in unsigned value (32 bit)
00517 
00518     This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
00519 
00520     \param [in]    value  Value to rotate
00521     \param [in]    value  Number of Bits to rotate
00522     \return               Rotated value
00523  */
00524 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
00525 {
00526   return (op1 >> op2) | (op1 << (32 - op2)); 
00527 }
00528 
00529 
00530 /** \brief  Breakpoint
00531 
00532     This function causes the processor to enter Debug state.
00533     Debug tools can use this to investigate system state when the instruction at a particular address is reached.
00534 
00535     \param [in]    value  is ignored by the processor.
00536                    If required, a debugger can use it to store additional information about the breakpoint.
00537  */
00538 #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
00539 
00540 
00541 #if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
00542 
00543 /** \brief  Reverse bit order of value
00544 
00545     This function reverses the bit order of the given value.
00546 
00547     \param [in]    value  Value to reverse
00548     \return               Reversed value
00549  */
00550 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
00551 {
00552   uint32_t result;
00553 
00554    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
00555    return(result);
00556 }
00557 
00558 
00559 /** \brief  LDR Exclusive (8 bit)
00560 
00561     This function executes a exclusive LDR instruction for 8 bit value.
00562 
00563     \param [in]    ptr  Pointer to data
00564     \return             value of type uint8_t at (*ptr)
00565  */
00566 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
00567 {
00568     uint32_t result;
00569 
00570 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
00571    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
00572 #else
00573     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
00574        accepted by assembler. So has to use following less efficient pattern.
00575     */
00576    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
00577 #endif
00578    return ((uint8_t) result);    /* Add explicit type cast here */
00579 }
00580 
00581 
00582 /** \brief  LDR Exclusive (16 bit)
00583 
00584     This function executes a exclusive LDR instruction for 16 bit values.
00585 
00586     \param [in]    ptr  Pointer to data
00587     \return        value of type uint16_t at (*ptr)
00588  */
00589 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
00590 {
00591     uint32_t result;
00592 
00593 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
00594    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
00595 #else
00596     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
00597        accepted by assembler. So has to use following less efficient pattern.
00598     */
00599    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
00600 #endif
00601    return ((uint16_t) result);    /* Add explicit type cast here */
00602 }
00603 
00604 
00605 /** \brief  LDR Exclusive (32 bit)
00606 
00607     This function executes a exclusive LDR instruction for 32 bit values.
00608 
00609     \param [in]    ptr  Pointer to data
00610     \return        value of type uint32_t at (*ptr)
00611  */
00612 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
00613 {
00614     uint32_t result;
00615 
00616    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
00617    return(result);
00618 }
00619 
00620 
00621 /** \brief  STR Exclusive (8 bit)
00622 
00623     This function executes a exclusive STR instruction for 8 bit values.
00624 
00625     \param [in]  value  Value to store
00626     \param [in]    ptr  Pointer to location
00627     \return          0  Function succeeded
00628     \return          1  Function failed
00629  */
00630 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
00631 {
00632    uint32_t result;
00633 
00634    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
00635    return(result);
00636 }
00637 
00638 
00639 /** \brief  STR Exclusive (16 bit)
00640 
00641     This function executes a exclusive STR instruction for 16 bit values.
00642 
00643     \param [in]  value  Value to store
00644     \param [in]    ptr  Pointer to location
00645     \return          0  Function succeeded
00646     \return          1  Function failed
00647  */
00648 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
00649 {
00650    uint32_t result;
00651 
00652    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
00653    return(result);
00654 }
00655 
00656 
00657 /** \brief  STR Exclusive (32 bit)
00658 
00659     This function executes a exclusive STR instruction for 32 bit values.
00660 
00661     \param [in]  value  Value to store
00662     \param [in]    ptr  Pointer to location
00663     \return          0  Function succeeded
00664     \return          1  Function failed
00665  */
00666 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
00667 {
00668    uint32_t result;
00669 
00670    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
00671    return(result);
00672 }
00673 
00674 
00675 /** \brief  Remove the exclusive lock
00676 
00677     This function removes the exclusive lock which is created by LDREX.
00678 
00679  */
00680 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
00681 {
00682   __ASM volatile ("clrex" ::: "memory");
00683 }
00684 
00685 
00686 /** \brief  Signed Saturate
00687 
00688     This function saturates a signed value.
00689 
00690     \param [in]  value  Value to be saturated
00691     \param [in]    sat  Bit position to saturate to (1..32)
00692     \return             Saturated value
00693  */
00694 #define __SSAT(ARG1,ARG2) \
00695 ({                          \
00696   uint32_t __RES, __ARG1 = (ARG1); \
00697   __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
00698   __RES; \
00699  })
00700 
00701 
00702 /** \brief  Unsigned Saturate
00703 
00704     This function saturates an unsigned value.
00705 
00706     \param [in]  value  Value to be saturated
00707     \param [in]    sat  Bit position to saturate to (0..31)
00708     \return             Saturated value
00709  */
00710 #define __USAT(ARG1,ARG2) \
00711 ({                          \
00712   uint32_t __RES, __ARG1 = (ARG1); \
00713   __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
00714   __RES; \
00715  })
00716 
00717 
00718 /** \brief  Count leading zeros
00719 
00720     This function counts the number of leading zeros of a data value.
00721 
00722     \param [in]  value  Value to count the leading zeros
00723     \return             number of leading zeros in value
00724  */
00725 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
00726 {
00727   uint32_t result;
00728 
00729   __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
00730    return ((uint8_t) result);    /* Add explicit type cast here */
00731 }
00732 
00733 
00734 /** \brief  Rotate Right with Extend (32 bit)
00735 
00736     This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
00737 
00738     \param [in]    value  Value to rotate
00739     \return               Rotated value
00740  */
00741 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
00742 {
00743   uint32_t result;
00744 
00745   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
00746   return(result);
00747 }
00748 
00749 
00750 /** \brief  LDRT Unprivileged (8 bit)
00751 
00752     This function executes a Unprivileged LDRT instruction for 8 bit value.
00753 
00754     \param [in]    ptr  Pointer to data
00755     \return             value of type uint8_t at (*ptr)
00756  */
00757 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
00758 {
00759     uint32_t result;
00760 
00761 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
00762    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
00763 #else
00764     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
00765        accepted by assembler. So has to use following less efficient pattern.
00766     */
00767    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
00768 #endif
00769    return ((uint8_t) result);    /* Add explicit type cast here */
00770 }
00771 
00772 
00773 /** \brief  LDRT Unprivileged (16 bit)
00774 
00775     This function executes a Unprivileged LDRT instruction for 16 bit values.
00776 
00777     \param [in]    ptr  Pointer to data
00778     \return        value of type uint16_t at (*ptr)
00779  */
00780 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
00781 {
00782     uint32_t result;
00783 
00784 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
00785    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
00786 #else
00787     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
00788        accepted by assembler. So has to use following less efficient pattern.
00789     */
00790    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
00791 #endif
00792    return ((uint16_t) result);    /* Add explicit type cast here */
00793 }
00794 
00795 
00796 /** \brief  LDRT Unprivileged (32 bit)
00797 
00798     This function executes a Unprivileged LDRT instruction for 32 bit values.
00799 
00800     \param [in]    ptr  Pointer to data
00801     \return        value of type uint32_t at (*ptr)
00802  */
00803 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
00804 {
00805     uint32_t result;
00806 
00807    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
00808    return(result);
00809 }
00810 
00811 
00812 /** \brief  STRT Unprivileged (8 bit)
00813 
00814     This function executes a Unprivileged STRT instruction for 8 bit values.
00815 
00816     \param [in]  value  Value to store
00817     \param [in]    ptr  Pointer to location
00818  */
00819 __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
00820 {
00821    __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
00822 }
00823 
00824 
00825 /** \brief  STRT Unprivileged (16 bit)
00826 
00827     This function executes a Unprivileged STRT instruction for 16 bit values.
00828 
00829     \param [in]  value  Value to store
00830     \param [in]    ptr  Pointer to location
00831  */
00832 __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
00833 {
00834    __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
00835 }
00836 
00837 
00838 /** \brief  STRT Unprivileged (32 bit)
00839 
00840     This function executes a Unprivileged STRT instruction for 32 bit values.
00841 
00842     \param [in]  value  Value to store
00843     \param [in]    ptr  Pointer to location
00844  */
00845 __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
00846 {
00847    __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
00848 }
00849 
00850 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
00851 
00852 
00853 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
00854 /* IAR iccarm specific functions */
00855 #include <cmsis_iar.h>
00856 
00857 
00858 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
00859 /* TI CCS specific functions */
00860 #include <cmsis_ccs.h>
00861 
00862 
00863 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
00864 /* TASKING carm specific functions */
00865 /*
00866  * The CMSIS functions have been implemented as intrinsics in the compiler.
00867  * Please use "carm -?i" to get an up to date list of all intrinsics,
00868  * Including the CMSIS ones.
00869  */
00870 
00871 
00872 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
00873 /* Cosmic specific functions */
00874 #include <cmsis_csm.h>
00875 
00876 #endif
00877 
00878 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
00879 
00880 #endif /* __CORE_CMINSTR_H */