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core_cm7.h
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00001 /**************************************************************************//** 00002 * @file core_cm7.h 00003 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 00004 * @version V4.00 00005 * @date 01. September 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM7_H_GENERIC 00043 #define __CORE_CM7_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M7 00067 @{ 00068 */ 00069 00070 /* CMSIS CM7 definitions */ 00071 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x07) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00113 */ 00114 #if defined ( __CC_ARM ) 00115 #if defined __TARGET_FPU_VFP 00116 #if (__FPU_PRESENT == 1) 00117 #define __FPU_USED 1 00118 #else 00119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00120 #define __FPU_USED 0 00121 #endif 00122 #else 00123 #define __FPU_USED 0 00124 #endif 00125 00126 #elif defined ( __GNUC__ ) 00127 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00128 #if (__FPU_PRESENT == 1) 00129 #define __FPU_USED 1 00130 #else 00131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00132 #define __FPU_USED 0 00133 #endif 00134 #else 00135 #define __FPU_USED 0 00136 #endif 00137 00138 #elif defined ( __ICCARM__ ) 00139 #if defined __ARMVFP__ 00140 #if (__FPU_PRESENT == 1) 00141 #define __FPU_USED 1 00142 #else 00143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #define __FPU_USED 0 00145 #endif 00146 #else 00147 #define __FPU_USED 0 00148 #endif 00149 00150 #elif defined ( __TMS470__ ) 00151 #if defined __TI_VFP_SUPPORT__ 00152 #if (__FPU_PRESENT == 1) 00153 #define __FPU_USED 1 00154 #else 00155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00156 #define __FPU_USED 0 00157 #endif 00158 #else 00159 #define __FPU_USED 0 00160 #endif 00161 00162 #elif defined ( __TASKING__ ) 00163 #if defined __FPU_VFP__ 00164 #if (__FPU_PRESENT == 1) 00165 #define __FPU_USED 1 00166 #else 00167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00168 #define __FPU_USED 0 00169 #endif 00170 #else 00171 #define __FPU_USED 0 00172 #endif 00173 00174 #elif defined ( __CSMC__ ) /* Cosmic */ 00175 #if ( __CSMC__ & 0x400) // FPU present for parser 00176 #if (__FPU_PRESENT == 1) 00177 #define __FPU_USED 1 00178 #else 00179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00180 #define __FPU_USED 0 00181 #endif 00182 #else 00183 #define __FPU_USED 0 00184 #endif 00185 #endif 00186 00187 #include <stdint.h> /* standard types definitions */ 00188 #include <core_cmInstr.h> /* Core Instruction Access */ 00189 #include <core_cmFunc.h> /* Core Function Access */ 00190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ 00191 00192 #ifdef __cplusplus 00193 } 00194 #endif 00195 00196 #endif /* __CORE_CM7_H_GENERIC */ 00197 00198 #ifndef __CMSIS_GENERIC 00199 00200 #ifndef __CORE_CM7_H_DEPENDANT 00201 #define __CORE_CM7_H_DEPENDANT 00202 00203 #ifdef __cplusplus 00204 extern "C" { 00205 #endif 00206 00207 /* check device defines and use defaults */ 00208 #if defined __CHECK_DEVICE_DEFINES 00209 #ifndef __CM7_REV 00210 #define __CM7_REV 0x0000 00211 #warning "__CM7_REV not defined in device header file; using default!" 00212 #endif 00213 00214 #ifndef __FPU_PRESENT 00215 #define __FPU_PRESENT 0 00216 #warning "__FPU_PRESENT not defined in device header file; using default!" 00217 #endif 00218 00219 #ifndef __MPU_PRESENT 00220 #define __MPU_PRESENT 0 00221 #warning "__MPU_PRESENT not defined in device header file; using default!" 00222 #endif 00223 00224 #ifndef __ICACHE_PRESENT 00225 #define __ICACHE_PRESENT 0 00226 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 00227 #endif 00228 00229 #ifndef __DCACHE_PRESENT 00230 #define __DCACHE_PRESENT 0 00231 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 00232 #endif 00233 00234 #ifndef __DTCM_PRESENT 00235 #define __DTCM_PRESENT 0 00236 #warning "__DTCM_PRESENT not defined in device header file; using default!" 00237 #endif 00238 00239 #ifndef __NVIC_PRIO_BITS 00240 #define __NVIC_PRIO_BITS 3 00241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00242 #endif 00243 00244 #ifndef __Vendor_SysTickConfig 00245 #define __Vendor_SysTickConfig 0 00246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00247 #endif 00248 #endif 00249 00250 /* IO definitions (access restrictions to peripheral registers) */ 00251 /** 00252 \defgroup CMSIS_glob_defs CMSIS Global Defines 00253 00254 <strong>IO Type Qualifiers</strong> are used 00255 \li to specify the access to peripheral variables. 00256 \li for automatic generation of peripheral register debug information. 00257 */ 00258 #ifdef __cplusplus 00259 #define __I volatile /*!< Defines 'read only' permissions */ 00260 #else 00261 #define __I volatile const /*!< Defines 'read only' permissions */ 00262 #endif 00263 #define __O volatile /*!< Defines 'write only' permissions */ 00264 #define __IO volatile /*!< Defines 'read / write' permissions */ 00265 00266 /*@} end of group Cortex_M7 */ 00267 00268 00269 00270 /******************************************************************************* 00271 * Register Abstraction 00272 Core Register contain: 00273 - Core Register 00274 - Core NVIC Register 00275 - Core SCB Register 00276 - Core SysTick Register 00277 - Core Debug Register 00278 - Core MPU Register 00279 - Core FPU Register 00280 ******************************************************************************/ 00281 /** \defgroup CMSIS_core_register Defines and Type Definitions 00282 \brief Type definitions and defines for Cortex-M processor based devices. 00283 */ 00284 00285 /** \ingroup CMSIS_core_register 00286 \defgroup CMSIS_CORE Status and Control Registers 00287 \brief Core Register type definitions. 00288 @{ 00289 */ 00290 00291 /** \brief Union type to access the Application Program Status Register (APSR). 00292 */ 00293 typedef union 00294 { 00295 struct 00296 { 00297 #if (__CORTEX_M != 0x07) 00298 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00299 #else 00300 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00301 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00302 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00303 #endif 00304 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00305 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00306 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00307 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00308 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00309 } b; /*!< Structure used for bit access */ 00310 uint32_t w; /*!< Type used for word access */ 00311 } APSR_Type; 00312 00313 00314 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00315 */ 00316 typedef union 00317 { 00318 struct 00319 { 00320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00322 } b; /*!< Structure used for bit access */ 00323 uint32_t w; /*!< Type used for word access */ 00324 } IPSR_Type; 00325 00326 00327 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00328 */ 00329 typedef union 00330 { 00331 struct 00332 { 00333 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00334 #if (__CORTEX_M != 0x07) 00335 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00336 #else 00337 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00338 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00339 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00340 #endif 00341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00348 } b; /*!< Structure used for bit access */ 00349 uint32_t w; /*!< Type used for word access */ 00350 } xPSR_Type; 00351 00352 00353 /** \brief Union type to access the Control Registers (CONTROL). 00354 */ 00355 typedef union 00356 { 00357 struct 00358 { 00359 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00360 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00361 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00362 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00363 } b; /*!< Structure used for bit access */ 00364 uint32_t w; /*!< Type used for word access */ 00365 } CONTROL_Type; 00366 00367 /*@} end of group CMSIS_CORE */ 00368 00369 00370 /** \ingroup CMSIS_core_register 00371 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00372 \brief Type definitions for the NVIC Registers 00373 @{ 00374 */ 00375 00376 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00377 */ 00378 typedef struct 00379 { 00380 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00381 uint32_t RESERVED0[24]; 00382 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00383 uint32_t RSERVED1[24]; 00384 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00385 uint32_t RESERVED2[24]; 00386 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00387 uint32_t RESERVED3[24]; 00388 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00389 uint32_t RESERVED4[56]; 00390 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00391 uint32_t RESERVED5[644]; 00392 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00393 } NVIC_Type; 00394 00395 /* Software Triggered Interrupt Register Definitions */ 00396 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 00397 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ 00398 00399 /*@} end of group CMSIS_NVIC */ 00400 00401 00402 /** \ingroup CMSIS_core_register 00403 \defgroup CMSIS_SCB System Control Block (SCB) 00404 \brief Type definitions for the System Control Block Registers 00405 @{ 00406 */ 00407 00408 /** \brief Structure type to access the System Control Block (SCB). 00409 */ 00410 typedef struct 00411 { 00412 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00413 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00414 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00415 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00416 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00417 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00418 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00419 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00420 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00421 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00422 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00423 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00424 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00425 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00426 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00427 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00428 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00429 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00430 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00431 uint32_t RESERVED0[1]; 00432 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00433 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00434 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00435 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00436 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00437 uint32_t RESERVED3[93]; 00438 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00439 uint32_t RESERVED4[15]; 00440 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00441 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00442 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ 00443 uint32_t RESERVED5[1]; 00444 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00445 uint32_t RESERVED6[1]; 00446 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00447 __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00448 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00449 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00450 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00451 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00452 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00453 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00454 uint32_t RESERVED7[6]; 00455 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 00456 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 00457 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 00458 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 00459 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 00460 uint32_t RESERVED8[1]; 00461 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 00462 } SCB_Type; 00463 00464 /* SCB CPUID Register Definitions */ 00465 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00466 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00467 00468 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00469 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00470 00471 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00472 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00473 00474 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00475 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00476 00477 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00478 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00479 00480 /* SCB Interrupt Control State Register Definitions */ 00481 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00482 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00483 00484 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00485 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00486 00487 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00488 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00489 00490 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00491 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00492 00493 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00494 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00495 00496 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00497 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00498 00499 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00500 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00501 00502 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00503 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00504 00505 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 00506 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00507 00508 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00509 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00510 00511 /* SCB Vector Table Offset Register Definitions */ 00512 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00513 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00514 00515 /* SCB Application Interrupt and Reset Control Register Definitions */ 00516 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00517 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00518 00519 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00520 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00521 00522 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00523 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00524 00525 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 00526 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00527 00528 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00529 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00530 00531 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00532 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00533 00534 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 00535 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 00536 00537 /* SCB System Control Register Definitions */ 00538 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00539 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00540 00541 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00542 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00543 00544 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00545 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00546 00547 /* SCB Configuration Control Register Definitions */ 00548 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ 00549 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ 00550 00551 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ 00552 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ 00553 00554 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ 00555 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ 00556 00557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00559 00560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 00561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00562 00563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 00564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00565 00566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00568 00569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 00570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00571 00572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 00573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 00574 00575 /* SCB System Handler Control and State Register Definitions */ 00576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 00577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00578 00579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 00580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00581 00582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 00583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00584 00585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00587 00588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00590 00591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00593 00594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 00595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00596 00597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 00598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00599 00600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 00601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00602 00603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 00604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00605 00606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 00607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00608 00609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 00610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00611 00612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 00613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00614 00615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 00616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00617 00618 /* SCB Configurable Fault Status Registers Definitions */ 00619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 00620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00621 00622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 00623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00624 00625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00627 00628 /* SCB Hard Fault Status Registers Definitions */ 00629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 00630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00631 00632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 00633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00634 00635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 00636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00637 00638 /* SCB Debug Fault Status Register Definitions */ 00639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 00640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00641 00642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 00643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00644 00645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 00646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00647 00648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 00649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00650 00651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 00652 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 00653 00654 /* Cache Level ID register */ 00655 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ 00656 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00657 00658 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ 00659 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ 00660 00661 /* Cache Type register */ 00662 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ 00663 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00664 00665 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ 00666 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00667 00668 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ 00669 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00670 00671 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ 00672 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00673 00674 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ 00675 #define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ 00676 00677 /* Cache Size ID Register */ 00678 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ 00679 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00680 00681 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ 00682 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00683 00684 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ 00685 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00686 00687 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ 00688 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00689 00690 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ 00691 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00692 00693 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ 00694 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00695 00696 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ 00697 #define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ 00698 00699 /* Cache Size Selection Register */ 00700 #define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ 00701 #define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00702 00703 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ 00704 #define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ 00705 00706 /* SCB Software Triggered Interrupt Register */ 00707 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ 00708 #define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ 00709 00710 /* Instruction Tightly-Coupled Memory Control Register*/ 00711 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ 00712 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 00713 00714 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ 00715 #define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 00716 00717 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ 00718 #define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 00719 00720 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ 00721 #define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ 00722 00723 /* Data Tightly-Coupled Memory Control Registers */ 00724 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ 00725 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 00726 00727 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ 00728 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 00729 00730 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ 00731 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 00732 00733 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ 00734 #define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ 00735 00736 /* AHBP Control Register */ 00737 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ 00738 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 00739 00740 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ 00741 #define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ 00742 00743 /* L1 Cache Control Register */ 00744 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ 00745 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 00746 00747 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ 00748 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 00749 00750 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ 00751 #define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ 00752 00753 /* AHBS control register */ 00754 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ 00755 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 00756 00757 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ 00758 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 00759 00760 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ 00761 #define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ 00762 00763 /* Auxiliary Bus Fault Status Register */ 00764 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ 00765 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 00766 00767 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ 00768 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 00769 00770 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ 00771 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 00772 00773 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ 00774 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 00775 00776 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ 00777 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 00778 00779 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ 00780 #define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ 00781 00782 /*@} end of group CMSIS_SCB */ 00783 00784 00785 /** \ingroup CMSIS_core_register 00786 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00787 \brief Type definitions for the System Control and ID Register not in the SCB 00788 @{ 00789 */ 00790 00791 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00792 */ 00793 typedef struct 00794 { 00795 uint32_t RESERVED0[1]; 00796 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00797 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00798 } SCnSCB_Type; 00799 00800 /* Interrupt Controller Type Register Definitions */ 00801 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 00802 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ 00803 00804 /* Auxiliary Control Register Definitions */ 00805 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ 00806 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ 00807 00808 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ 00809 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ 00810 00811 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ 00812 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ 00813 00814 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 00815 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00816 00817 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00818 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 00819 00820 /*@} end of group CMSIS_SCnotSCB */ 00821 00822 00823 /** \ingroup CMSIS_core_register 00824 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00825 \brief Type definitions for the System Timer Registers. 00826 @{ 00827 */ 00828 00829 /** \brief Structure type to access the System Timer (SysTick). 00830 */ 00831 typedef struct 00832 { 00833 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00834 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00835 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00836 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00837 } SysTick_Type; 00838 00839 /* SysTick Control / Status Register Definitions */ 00840 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00841 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00842 00843 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00844 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00845 00846 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00847 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00848 00849 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00850 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00851 00852 /* SysTick Reload Register Definitions */ 00853 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00854 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00855 00856 /* SysTick Current Register Definitions */ 00857 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00858 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00859 00860 /* SysTick Calibration Register Definitions */ 00861 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00862 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00863 00864 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00865 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00866 00867 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00868 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 00869 00870 /*@} end of group CMSIS_SysTick */ 00871 00872 00873 /** \ingroup CMSIS_core_register 00874 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00875 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00876 @{ 00877 */ 00878 00879 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00880 */ 00881 typedef struct 00882 { 00883 __O union 00884 { 00885 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00886 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00887 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00888 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00889 uint32_t RESERVED0[864]; 00890 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00891 uint32_t RESERVED1[15]; 00892 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00893 uint32_t RESERVED2[15]; 00894 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00895 uint32_t RESERVED3[29]; 00896 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00897 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00898 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00899 uint32_t RESERVED4[43]; 00900 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00901 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00902 uint32_t RESERVED5[6]; 00903 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00904 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00905 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00906 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00907 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00908 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00909 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00910 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00911 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00912 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00913 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00914 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00915 } ITM_Type; 00916 00917 /* ITM Trace Privilege Register Definitions */ 00918 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 00919 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 00920 00921 /* ITM Trace Control Register Definitions */ 00922 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 00923 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00924 00925 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 00926 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00927 00928 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 00929 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00930 00931 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 00932 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00933 00934 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 00935 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00936 00937 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 00938 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00939 00940 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 00941 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00942 00943 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 00944 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00945 00946 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 00947 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 00948 00949 /* ITM Integration Write Register Definitions */ 00950 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 00951 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ 00952 00953 /* ITM Integration Read Register Definitions */ 00954 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 00955 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ 00956 00957 /* ITM Integration Mode Control Register Definitions */ 00958 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 00959 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ 00960 00961 /* ITM Lock Status Register Definitions */ 00962 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 00963 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00964 00965 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 00966 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00967 00968 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 00969 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ 00970 00971 /*@}*/ /* end of group CMSIS_ITM */ 00972 00973 00974 /** \ingroup CMSIS_core_register 00975 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00976 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00977 @{ 00978 */ 00979 00980 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00981 */ 00982 typedef struct 00983 { 00984 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00985 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00986 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00987 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00988 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00989 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00990 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00991 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00992 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00993 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00994 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00995 uint32_t RESERVED0[1]; 00996 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00997 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00998 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00999 uint32_t RESERVED1[1]; 01000 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01001 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 01002 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01003 uint32_t RESERVED2[1]; 01004 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01005 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 01006 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01007 uint32_t RESERVED3[981]; 01008 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 01009 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01010 } DWT_Type; 01011 01012 /* DWT Control Register Definitions */ 01013 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 01014 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01015 01016 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 01017 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01018 01019 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 01020 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01021 01022 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 01023 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01024 01025 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 01026 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01027 01028 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 01029 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01030 01031 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 01032 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01033 01034 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 01035 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01036 01037 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 01038 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01039 01040 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 01041 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01042 01043 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 01044 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01045 01046 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 01047 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01048 01049 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 01050 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01051 01052 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 01053 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01054 01055 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 01056 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01057 01058 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 01059 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01060 01061 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 01062 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01063 01064 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 01065 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ 01066 01067 /* DWT CPI Count Register Definitions */ 01068 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 01069 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ 01070 01071 /* DWT Exception Overhead Count Register Definitions */ 01072 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 01073 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ 01074 01075 /* DWT Sleep Count Register Definitions */ 01076 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01077 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01078 01079 /* DWT LSU Count Register Definitions */ 01080 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 01081 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ 01082 01083 /* DWT Folded-instruction Count Register Definitions */ 01084 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 01085 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01086 01087 /* DWT Comparator Mask Register Definitions */ 01088 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 01089 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ 01090 01091 /* DWT Comparator Function Register Definitions */ 01092 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 01093 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01094 01095 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 01096 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 01097 01098 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 01099 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 01100 01101 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 01102 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01103 01104 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 01105 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 01106 01107 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 01108 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 01109 01110 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 01111 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 01112 01113 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 01114 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 01115 01116 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 01117 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ 01118 01119 /*@}*/ /* end of group CMSIS_DWT */ 01120 01121 01122 /** \ingroup CMSIS_core_register 01123 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01124 \brief Type definitions for the Trace Port Interface (TPI) 01125 @{ 01126 */ 01127 01128 /** \brief Structure type to access the Trace Port Interface Register (TPI). 01129 */ 01130 typedef struct 01131 { 01132 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01133 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01134 uint32_t RESERVED0[2]; 01135 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01136 uint32_t RESERVED1[55]; 01137 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01138 uint32_t RESERVED2[131]; 01139 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01140 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01141 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01142 uint32_t RESERVED3[759]; 01143 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01144 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01145 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01146 uint32_t RESERVED4[1]; 01147 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01148 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01149 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01150 uint32_t RESERVED5[39]; 01151 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01152 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01153 uint32_t RESERVED7[8]; 01154 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01155 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01156 } TPI_Type; 01157 01158 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01159 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 01160 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ 01161 01162 /* TPI Selected Pin Protocol Register Definitions */ 01163 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 01164 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ 01165 01166 /* TPI Formatter and Flush Status Register Definitions */ 01167 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 01168 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01169 01170 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 01171 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01172 01173 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 01174 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01175 01176 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 01177 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ 01178 01179 /* TPI Formatter and Flush Control Register Definitions */ 01180 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 01181 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01182 01183 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 01184 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01185 01186 /* TPI TRIGGER Register Definitions */ 01187 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 01188 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ 01189 01190 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01191 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 01192 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01193 01194 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 01195 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01196 01197 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 01198 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01199 01200 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 01201 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01202 01203 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 01204 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01205 01206 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 01207 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01208 01209 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 01210 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ 01211 01212 /* TPI ITATBCTR2 Register Definitions */ 01213 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 01214 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ 01215 01216 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01217 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 01218 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01219 01220 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 01221 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01222 01223 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 01224 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01225 01226 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 01227 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01228 01229 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 01230 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01231 01232 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 01233 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01234 01235 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 01236 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ 01237 01238 /* TPI ITATBCTR0 Register Definitions */ 01239 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 01240 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ 01241 01242 /* TPI Integration Mode Control Register Definitions */ 01243 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 01244 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ 01245 01246 /* TPI DEVID Register Definitions */ 01247 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 01248 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01249 01250 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 01251 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01252 01253 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 01254 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01255 01256 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 01257 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01258 01259 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 01260 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01261 01262 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 01263 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ 01264 01265 /* TPI DEVTYPE Register Definitions */ 01266 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 01267 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ 01268 01269 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 01270 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01271 01272 /*@}*/ /* end of group CMSIS_TPI */ 01273 01274 01275 #if (__MPU_PRESENT == 1) 01276 /** \ingroup CMSIS_core_register 01277 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01278 \brief Type definitions for the Memory Protection Unit (MPU) 01279 @{ 01280 */ 01281 01282 /** \brief Structure type to access the Memory Protection Unit (MPU). 01283 */ 01284 typedef struct 01285 { 01286 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01287 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01288 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01289 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01290 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01291 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01292 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01293 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01294 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01295 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01296 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01297 } MPU_Type; 01298 01299 /* MPU Type Register */ 01300 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 01301 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01302 01303 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 01304 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01305 01306 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 01307 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 01308 01309 /* MPU Control Register */ 01310 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 01311 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01312 01313 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 01314 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01315 01316 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 01317 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 01318 01319 /* MPU Region Number Register */ 01320 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 01321 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 01322 01323 /* MPU Region Base Address Register */ 01324 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 01325 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01326 01327 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 01328 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01329 01330 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 01331 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 01332 01333 /* MPU Region Attribute and Size Register */ 01334 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 01335 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01336 01337 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 01338 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01339 01340 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 01341 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01342 01343 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 01344 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01345 01346 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 01347 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01348 01349 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 01350 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01351 01352 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 01353 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01354 01355 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 01356 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01357 01358 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 01359 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01360 01361 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 01362 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 01363 01364 /*@} end of group CMSIS_MPU */ 01365 #endif 01366 01367 01368 #if (__FPU_PRESENT == 1) 01369 /** \ingroup CMSIS_core_register 01370 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01371 \brief Type definitions for the Floating Point Unit (FPU) 01372 @{ 01373 */ 01374 01375 /** \brief Structure type to access the Floating Point Unit (FPU). 01376 */ 01377 typedef struct 01378 { 01379 uint32_t RESERVED0[1]; 01380 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01381 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01382 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01383 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01384 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01385 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 01386 } FPU_Type; 01387 01388 /* Floating-Point Context Control Register */ 01389 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ 01390 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01391 01392 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ 01393 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01394 01395 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ 01396 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01397 01398 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ 01399 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01400 01401 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ 01402 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01403 01404 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ 01405 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01406 01407 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ 01408 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01409 01410 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ 01411 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01412 01413 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ 01414 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ 01415 01416 /* Floating-Point Context Address Register */ 01417 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ 01418 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01419 01420 /* Floating-Point Default Status Control Register */ 01421 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ 01422 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01423 01424 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ 01425 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01426 01427 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ 01428 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01429 01430 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ 01431 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01432 01433 /* Media and FP Feature Register 0 */ 01434 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ 01435 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01436 01437 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ 01438 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01439 01440 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ 01441 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01442 01443 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ 01444 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01445 01446 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ 01447 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01448 01449 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ 01450 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01451 01452 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ 01453 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01454 01455 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ 01456 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ 01457 01458 /* Media and FP Feature Register 1 */ 01459 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ 01460 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01461 01462 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ 01463 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01464 01465 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ 01466 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01467 01468 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ 01469 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ 01470 01471 /* Media and FP Feature Register 2 */ 01472 01473 /*@} end of group CMSIS_FPU */ 01474 #endif 01475 01476 01477 /** \ingroup CMSIS_core_register 01478 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01479 \brief Type definitions for the Core Debug Registers 01480 @{ 01481 */ 01482 01483 /** \brief Structure type to access the Core Debug Register (CoreDebug). 01484 */ 01485 typedef struct 01486 { 01487 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01488 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01489 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01490 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01491 } CoreDebug_Type; 01492 01493 /* Debug Halting Control and Status Register */ 01494 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 01495 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01496 01497 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01498 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01499 01500 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01501 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01502 01503 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01504 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01505 01506 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 01507 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01508 01509 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 01510 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01511 01512 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 01513 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01514 01515 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01516 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01517 01518 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01519 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01520 01521 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 01522 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01523 01524 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 01525 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01526 01527 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01528 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01529 01530 /* Debug Core Register Selector Register */ 01531 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 01532 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01533 01534 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 01535 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 01536 01537 /* Debug Exception and Monitor Control Register */ 01538 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 01539 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01540 01541 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 01542 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01543 01544 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 01545 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01546 01547 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 01548 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01549 01550 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 01551 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01552 01553 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01554 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01555 01556 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 01557 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01558 01559 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01560 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01561 01562 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 01563 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01564 01565 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01566 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01567 01568 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01569 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01570 01571 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 01572 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01573 01574 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01575 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01576 01577 /*@} end of group CMSIS_CoreDebug */ 01578 01579 01580 /** \ingroup CMSIS_core_register 01581 \defgroup CMSIS_core_base Core Definitions 01582 \brief Definitions for base addresses, unions, and structures. 01583 @{ 01584 */ 01585 01586 /* Memory mapping of Cortex-M4 Hardware */ 01587 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01588 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01589 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01590 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01591 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01592 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01593 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01594 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01595 01596 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01597 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01598 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01599 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01600 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01601 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01602 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01603 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01604 01605 #if (__MPU_PRESENT == 1) 01606 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01607 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01608 #endif 01609 01610 #if (__FPU_PRESENT == 1) 01611 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01612 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01613 #endif 01614 01615 /*@} */ 01616 01617 01618 01619 /******************************************************************************* 01620 * Hardware Abstraction Layer 01621 Core Function Interface contains: 01622 - Core NVIC Functions 01623 - Core SysTick Functions 01624 - Core Debug Functions 01625 - Core Register Access Functions 01626 ******************************************************************************/ 01627 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01628 */ 01629 01630 01631 01632 /* ########################## NVIC functions #################################### */ 01633 /** \ingroup CMSIS_Core_FunctionInterface 01634 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01635 \brief Functions that manage interrupts and exceptions via the NVIC. 01636 @{ 01637 */ 01638 01639 /** \brief Set Priority Grouping 01640 01641 The function sets the priority grouping field using the required unlock sequence. 01642 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01643 Only values from 0..7 are used. 01644 In case of a conflict between priority grouping and available 01645 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01646 01647 \param [in] PriorityGroup Priority grouping field. 01648 */ 01649 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01650 { 01651 uint32_t reg_value; 01652 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 01653 01654 reg_value = SCB->AIRCR; /* read old register configuration */ 01655 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 01656 reg_value = (reg_value | 01657 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01658 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 01659 SCB->AIRCR = reg_value; 01660 } 01661 01662 01663 /** \brief Get Priority Grouping 01664 01665 The function reads the priority grouping field from the NVIC Interrupt Controller. 01666 01667 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01668 */ 01669 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 01670 { 01671 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 01672 } 01673 01674 01675 /** \brief Enable External Interrupt 01676 01677 The function enables a device-specific interrupt in the NVIC interrupt controller. 01678 01679 \param [in] IRQn External interrupt number. Value cannot be negative. 01680 */ 01681 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 01682 { 01683 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ 01684 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ 01685 } 01686 01687 01688 /** \brief Disable External Interrupt 01689 01690 The function disables a device-specific interrupt in the NVIC interrupt controller. 01691 01692 \param [in] IRQn External interrupt number. Value cannot be negative. 01693 */ 01694 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 01695 { 01696 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 01697 } 01698 01699 01700 /** \brief Get Pending Interrupt 01701 01702 The function reads the pending register in the NVIC and returns the pending bit 01703 for the specified interrupt. 01704 01705 \param [in] IRQn Interrupt number. 01706 01707 \return 0 Interrupt status is not pending. 01708 \return 1 Interrupt status is pending. 01709 */ 01710 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 01711 { 01712 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 01713 } 01714 01715 01716 /** \brief Set Pending Interrupt 01717 01718 The function sets the pending bit of an external interrupt. 01719 01720 \param [in] IRQn Interrupt number. Value cannot be negative. 01721 */ 01722 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 01723 { 01724 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 01725 } 01726 01727 01728 /** \brief Clear Pending Interrupt 01729 01730 The function clears the pending bit of an external interrupt. 01731 01732 \param [in] IRQn External interrupt number. Value cannot be negative. 01733 */ 01734 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01735 { 01736 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 01737 } 01738 01739 01740 /** \brief Get Active Interrupt 01741 01742 The function reads the active register in NVIC and returns the active bit. 01743 01744 \param [in] IRQn Interrupt number. 01745 01746 \return 0 Interrupt status is not active. 01747 \return 1 Interrupt status is active. 01748 */ 01749 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 01750 { 01751 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 01752 } 01753 01754 01755 /** \brief Set Interrupt Priority 01756 01757 The function sets the priority of an interrupt. 01758 01759 \note The priority cannot be set for every core interrupt. 01760 01761 \param [in] IRQn Interrupt number. 01762 \param [in] priority Priority to set. 01763 */ 01764 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01765 { 01766 if(IRQn < 0) { 01767 SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 01768 else { 01769 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 01770 } 01771 01772 01773 /** \brief Get Interrupt Priority 01774 01775 The function reads the priority of an interrupt. The interrupt 01776 number can be positive to specify an external (device specific) 01777 interrupt, or negative to specify an internal (core) interrupt. 01778 01779 01780 \param [in] IRQn Interrupt number. 01781 \return Interrupt Priority. Value is aligned automatically to the implemented 01782 priority bits of the microcontroller. 01783 */ 01784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 01785 { 01786 01787 if(IRQn < 0) { 01788 return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 01789 else { 01790 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 01791 } 01792 01793 01794 /** \brief Encode Priority 01795 01796 The function encodes the priority for an interrupt with the given priority group, 01797 preemptive priority value, and subpriority value. 01798 In case of a conflict between priority grouping and available 01799 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01800 01801 \param [in] PriorityGroup Used priority group. 01802 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01803 \param [in] SubPriority Subpriority value (starting from 0). 01804 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01805 */ 01806 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01807 { 01808 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01809 uint32_t PreemptPriorityBits; 01810 uint32_t SubPriorityBits; 01811 01812 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01813 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01814 01815 return ( 01816 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 01817 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 01818 ); 01819 } 01820 01821 01822 /** \brief Decode Priority 01823 01824 The function decodes an interrupt priority value with a given priority group to 01825 preemptive priority value and subpriority value. 01826 In case of a conflict between priority grouping and available 01827 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01828 01829 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01830 \param [in] PriorityGroup Used priority group. 01831 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01832 \param [out] pSubPriority Subpriority value (starting from 0). 01833 */ 01834 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01835 { 01836 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01837 uint32_t PreemptPriorityBits; 01838 uint32_t SubPriorityBits; 01839 01840 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01841 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01842 01843 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 01844 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 01845 } 01846 01847 01848 /** \brief System Reset 01849 01850 The function initiates a system reset request to reset the MCU. 01851 */ 01852 __STATIC_INLINE void NVIC_SystemReset(void) 01853 { 01854 __DSB(); /* Ensure all outstanding memory accesses included 01855 buffered write are completed before reset */ 01856 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01857 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01858 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 01859 __DSB(); /* Ensure completion of memory access */ 01860 while(1); /* wait until reset */ 01861 } 01862 01863 /*@} end of CMSIS_Core_NVICFunctions */ 01864 01865 01866 /* ########################## Cache functions #################################### */ 01867 /** \ingroup CMSIS_Core_FunctionInterface 01868 \defgroup CMSIS_Core_CacheFunctions Cache Functions 01869 \brief Functions that configure Instruction and Data cache. 01870 @{ 01871 */ 01872 01873 /* Cache Size ID Register Macros */ 01874 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 01875 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 01876 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) 01877 01878 01879 /** \brief Enable I-Cache 01880 01881 The function turns on I-Cache 01882 */ 01883 __STATIC_INLINE void SCB_EnableICache(void) 01884 { 01885 #if (__ICACHE_PRESENT == 1) 01886 __DSB(); 01887 __ISB(); 01888 SCB->ICIALLU = 0; // invalidate I-Cache 01889 SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache 01890 __DSB(); 01891 __ISB(); 01892 #endif 01893 } 01894 01895 01896 /** \brief Disable I-Cache 01897 01898 The function turns off I-Cache 01899 */ 01900 __STATIC_INLINE void SCB_DisableICache(void) 01901 { 01902 #if (__ICACHE_PRESENT == 1) 01903 __DSB(); 01904 __ISB(); 01905 SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache 01906 SCB->ICIALLU = 0; // invalidate I-Cache 01907 __DSB(); 01908 __ISB(); 01909 #endif 01910 } 01911 01912 01913 /** \brief Invalidate I-Cache 01914 01915 The function invalidates I-Cache 01916 */ 01917 __STATIC_INLINE void SCB_InvalidateICache(void) 01918 { 01919 #if (__ICACHE_PRESENT == 1) 01920 __DSB(); 01921 __ISB(); 01922 SCB->ICIALLU = 0; 01923 __DSB(); 01924 __ISB(); 01925 #endif 01926 } 01927 01928 01929 /** \brief Enable D-Cache 01930 01931 The function turns on D-Cache 01932 */ 01933 __STATIC_INLINE void SCB_EnableDCache(void) 01934 { 01935 #if (__DCACHE_PRESENT == 1) 01936 uint32_t ccsidr, sshift, wshift, sw; 01937 uint32_t sets, ways; 01938 01939 ccsidr = SCB->CCSIDR; 01940 sets = CCSIDR_SETS(ccsidr); 01941 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 01942 ways = CCSIDR_WAYS(ccsidr); 01943 wshift = __CLZ(ways) & 0x1f; 01944 01945 __DSB(); 01946 01947 do { // invalidate D-Cache 01948 int32_t tmpways = ways; 01949 do { 01950 sw = ((tmpways << wshift) | (sets << sshift)); 01951 SCB->DCISW = sw; 01952 } while(tmpways--); 01953 } while(sets--); 01954 __DSB(); 01955 01956 SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache 01957 01958 __DSB(); 01959 __ISB(); 01960 #endif 01961 } 01962 01963 01964 /** \brief Disable D-Cache 01965 01966 The function turns off D-Cache 01967 */ 01968 __STATIC_INLINE void SCB_DisableDCache(void) 01969 { 01970 #if (__DCACHE_PRESENT == 1) 01971 uint32_t ccsidr, sshift, wshift, sw; 01972 uint32_t sets, ways; 01973 01974 ccsidr = SCB->CCSIDR; 01975 sets = CCSIDR_SETS(ccsidr); 01976 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 01977 ways = CCSIDR_WAYS(ccsidr); 01978 wshift = __CLZ(ways) & 0x1f; 01979 01980 __DSB(); 01981 01982 SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache 01983 01984 do { // clean & invalidate D-Cache 01985 int32_t tmpways = ways; 01986 do { 01987 sw = ((tmpways << wshift) | (sets << sshift)); 01988 SCB->DCCISW = sw; 01989 } while(tmpways--); 01990 } while(sets--); 01991 01992 01993 __DSB(); 01994 __ISB(); 01995 #endif 01996 } 01997 01998 01999 /** \brief Invalidate D-Cache 02000 02001 The function invalidates D-Cache 02002 */ 02003 __STATIC_INLINE void SCB_InvalidateDCache(void) 02004 { 02005 #if (__DCACHE_PRESENT == 1) 02006 uint32_t ccsidr, sshift, wshift, sw; 02007 uint32_t sets, ways; 02008 02009 ccsidr = SCB->CCSIDR; 02010 sets = CCSIDR_SETS(ccsidr); 02011 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 02012 ways = CCSIDR_WAYS(ccsidr); 02013 wshift = __CLZ(ways) & 0x1f; 02014 02015 __DSB(); 02016 02017 do { // invalidate D-Cache 02018 int32_t tmpways = ways; 02019 do { 02020 sw = ((tmpways << wshift) | (sets << sshift)); 02021 SCB->DCISW = sw; 02022 } while(tmpways--); 02023 } while(sets--); 02024 02025 __DSB(); 02026 __ISB(); 02027 #endif 02028 } 02029 02030 02031 /** \brief Clean D-Cache 02032 02033 The function cleans D-Cache 02034 */ 02035 __STATIC_INLINE void SCB_CleanDCache(void) 02036 { 02037 #if (__DCACHE_PRESENT == 1) 02038 uint32_t ccsidr, sshift, wshift, sw; 02039 uint32_t sets, ways; 02040 02041 ccsidr = SCB->CCSIDR; 02042 sets = CCSIDR_SETS(ccsidr); 02043 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 02044 ways = CCSIDR_WAYS(ccsidr); 02045 wshift = __CLZ(ways) & 0x1f; 02046 02047 __DSB(); 02048 02049 do { // clean D-Cache 02050 int32_t tmpways = ways; 02051 do { 02052 sw = ((tmpways << wshift) | (sets << sshift)); 02053 SCB->DCCSW = sw; 02054 } while(tmpways--); 02055 } while(sets--); 02056 02057 __DSB(); 02058 __ISB(); 02059 #endif 02060 } 02061 02062 02063 /** \brief Clean & Invalidate D-Cache 02064 02065 The function cleans and Invalidates D-Cache 02066 */ 02067 __STATIC_INLINE void SCB_CleanInvalidateDCache(void) 02068 { 02069 #if (__DCACHE_PRESENT == 1) 02070 uint32_t ccsidr, sshift, wshift, sw; 02071 uint32_t sets, ways; 02072 02073 ccsidr = SCB->CCSIDR; 02074 sets = CCSIDR_SETS(ccsidr); 02075 sshift = CCSIDR_LSSHIFT(ccsidr) + 4; 02076 ways = CCSIDR_WAYS(ccsidr); 02077 wshift = __CLZ(ways) & 0x1f; 02078 02079 __DSB(); 02080 02081 do { // clean & invalidate D-Cache 02082 int32_t tmpways = ways; 02083 do { 02084 sw = ((tmpways << wshift) | (sets << sshift)); 02085 SCB->DCCISW = sw; 02086 } while(tmpways--); 02087 } while(sets--); 02088 02089 __DSB(); 02090 __ISB(); 02091 #endif 02092 } 02093 02094 02095 /*@} end of CMSIS_Core_CacheFunctions */ 02096 02097 02098 02099 /* ################################## SysTick function ############################################ */ 02100 /** \ingroup CMSIS_Core_FunctionInterface 02101 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02102 \brief Functions that configure the System. 02103 @{ 02104 */ 02105 02106 #if (__Vendor_SysTickConfig == 0) 02107 02108 /** \brief System Tick Configuration 02109 02110 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 02111 Counter is in free running mode to generate periodic interrupts. 02112 02113 \param [in] ticks Number of ticks between two interrupts. 02114 02115 \return 0 Function succeeded. 02116 \return 1 Function failed. 02117 02118 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02119 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02120 must contain a vendor-specific implementation of this function. 02121 02122 */ 02123 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02124 { 02125 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 02126 02127 SysTick->LOAD = ticks - 1; /* set reload register */ 02128 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 02129 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 02130 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02131 SysTick_CTRL_TICKINT_Msk | 02132 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02133 return (0); /* Function successful */ 02134 } 02135 02136 #endif 02137 02138 /*@} end of CMSIS_Core_SysTickFunctions */ 02139 02140 02141 02142 /* ##################################### Debug In/Output function ########################################### */ 02143 /** \ingroup CMSIS_Core_FunctionInterface 02144 \defgroup CMSIS_core_DebugFunctions ITM Functions 02145 \brief Functions that access the ITM debug interface. 02146 @{ 02147 */ 02148 02149 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02150 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02151 02152 02153 /** \brief ITM Send Character 02154 02155 The function transmits a character via the ITM channel 0, and 02156 \li Just returns when no debugger is connected that has booked the output. 02157 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02158 02159 \param [in] ch Character to transmit. 02160 02161 \returns Character to transmit. 02162 */ 02163 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02164 { 02165 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 02166 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 02167 { 02168 while (ITM->PORT[0].u32 == 0); 02169 ITM->PORT[0].u8 = (uint8_t) ch; 02170 } 02171 return (ch); 02172 } 02173 02174 02175 /** \brief ITM Receive Character 02176 02177 The function inputs a character via the external variable \ref ITM_RxBuffer. 02178 02179 \return Received character. 02180 \return -1 No character pending. 02181 */ 02182 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 02183 int32_t ch = -1; /* no character available */ 02184 02185 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 02186 ch = ITM_RxBuffer; 02187 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02188 } 02189 02190 return (ch); 02191 } 02192 02193 02194 /** \brief ITM Check Character 02195 02196 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02197 02198 \return 0 No character available. 02199 \return 1 Character available. 02200 */ 02201 __STATIC_INLINE int32_t ITM_CheckChar (void) { 02202 02203 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 02204 return (0); /* no character available */ 02205 } else { 02206 return (1); /* character available */ 02207 } 02208 } 02209 02210 /*@} end of CMSIS_core_DebugFunctions */ 02211 02212 02213 02214 02215 #ifdef __cplusplus 02216 } 02217 #endif 02218 02219 #endif /* __CORE_CM7_H_DEPENDANT */ 02220 02221 #endif /* __CMSIS_GENERIC */
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