core_cm3.h

00001 /**************************************************************************//**
00002  * @file     core_cm3.h
00003  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
00004  * @version  V4.00
00005  * @date     22. August 2014
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2014 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #if defined ( __ICCARM__ )
00039  #pragma system_include  /* treat file as system include file for MISRA check */
00040 #endif
00041 
00042 #ifndef __CORE_CM3_H_GENERIC
00043 #define __CORE_CM3_H_GENERIC
00044 
00045 #ifdef __cplusplus
00046  extern "C" {
00047 #endif
00048 
00049 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00050   CMSIS violates the following MISRA-C:2004 rules:
00051 
00052    \li Required Rule 8.5, object/function definition in header file.<br>
00053      Function definitions in header files are used to allow 'inlining'.
00054 
00055    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00056      Unions are used for effective representation of core registers.
00057 
00058    \li Advisory Rule 19.7, Function-like macro defined.<br>
00059      Function-like macros are used to allow more efficient code.
00060  */
00061 
00062 
00063 /*******************************************************************************
00064  *                 CMSIS definitions
00065  ******************************************************************************/
00066 /** \ingroup Cortex_M3
00067   @{
00068  */
00069 
00070 /*  CMSIS CM3 definitions */
00071 #define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
00072 #define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
00073 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
00074                                     __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00075 
00076 #define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
00077 
00078 
00079 #if   defined ( __CC_ARM )
00080   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00081   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00082   #define __STATIC_INLINE  static __inline
00083 
00084 #elif defined ( __GNUC__ )
00085   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00086   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00087   #define __STATIC_INLINE  static inline
00088 
00089 #elif defined ( __ICCARM__ )
00090   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00091   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00092   #define __STATIC_INLINE  static inline
00093 
00094 #elif defined ( __TMS470__ )
00095   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00096   #define __STATIC_INLINE  static inline
00097 
00098 #elif defined ( __TASKING__ )
00099   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00100   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00101   #define __STATIC_INLINE  static inline
00102 
00103 #elif defined ( __CSMC__ )
00104   #define __packed
00105   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
00106   #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
00107   #define __STATIC_INLINE  static inline
00108 
00109 #endif
00110 
00111 /** __FPU_USED indicates whether an FPU is used or not.
00112     This core does not support an FPU at all
00113 */
00114 #define __FPU_USED       0
00115 
00116 #if defined ( __CC_ARM )
00117   #if defined __TARGET_FPU_VFP
00118     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00119   #endif
00120 
00121 #elif defined ( __GNUC__ )
00122   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00123     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00124   #endif
00125 
00126 #elif defined ( __ICCARM__ )
00127   #if defined __ARMVFP__
00128     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00129   #endif
00130 
00131 #elif defined ( __TMS470__ )
00132   #if defined __TI__VFP_SUPPORT____
00133     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00134   #endif
00135 
00136 #elif defined ( __TASKING__ )
00137   #if defined __FPU_VFP__
00138     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00139   #endif
00140 
00141 #elif defined ( __CSMC__ )      /* Cosmic */
00142   #if ( __CSMC__ & 0x400)       // FPU present for parser
00143     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00144   #endif
00145 #endif
00146 
00147 #include <stdint.h>                      /* standard types definitions                      */
00148 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00149 #include <core_cmFunc.h>                 /* Core Function Access                            */
00150 
00151 #ifdef __cplusplus
00152 }
00153 #endif
00154 
00155 #endif /* __CORE_CM3_H_GENERIC */
00156 
00157 #ifndef __CMSIS_GENERIC
00158 
00159 #ifndef __CORE_CM3_H_DEPENDANT
00160 #define __CORE_CM3_H_DEPENDANT
00161 
00162 #ifdef __cplusplus
00163  extern "C" {
00164 #endif
00165 
00166 /* check device defines and use defaults */
00167 #if defined __CHECK_DEVICE_DEFINES
00168   #ifndef __CM3_REV
00169     #define __CM3_REV               0x0200
00170     #warning "__CM3_REV not defined in device header file; using default!"
00171   #endif
00172 
00173   #ifndef __MPU_PRESENT
00174     #define __MPU_PRESENT             0
00175     #warning "__MPU_PRESENT not defined in device header file; using default!"
00176   #endif
00177 
00178   #ifndef __NVIC_PRIO_BITS
00179     #define __NVIC_PRIO_BITS          4
00180     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00181   #endif
00182 
00183   #ifndef __Vendor_SysTickConfig
00184     #define __Vendor_SysTickConfig    0
00185     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00186   #endif
00187 #endif
00188 
00189 /* IO definitions (access restrictions to peripheral registers) */
00190 /**
00191     \defgroup CMSIS_glob_defs CMSIS Global Defines
00192 
00193     <strong>IO Type Qualifiers</strong> are used
00194     \li to specify the access to peripheral variables.
00195     \li for automatic generation of peripheral register debug information.
00196 */
00197 #ifdef __cplusplus
00198   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00199 #else
00200   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00201 #endif
00202 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00203 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00204 
00205 /*@} end of group Cortex_M3 */
00206 
00207 
00208 
00209 /*******************************************************************************
00210  *                 Register Abstraction
00211   Core Register contain:
00212   - Core Register
00213   - Core NVIC Register
00214   - Core SCB Register
00215   - Core SysTick Register
00216   - Core Debug Register
00217   - Core MPU Register
00218  ******************************************************************************/
00219 /** \defgroup CMSIS_core_register Defines and Type Definitions
00220     \brief Type definitions and defines for Cortex-M processor based devices.
00221 */
00222 
00223 /** \ingroup    CMSIS_core_register
00224     \defgroup   CMSIS_CORE  Status and Control Registers
00225     \brief  Core Register type definitions.
00226   @{
00227  */
00228 
00229 /** \brief  Union type to access the Application Program Status Register (APSR).
00230  */
00231 typedef union
00232 {
00233   struct
00234   {
00235 #if (__CORTEX_M != 0x04)
00236     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00237 #else
00238     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00239     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00240     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
00241 #endif
00242     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00243     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00244     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00245     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00246     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00247   } b;                                   /*!< Structure used for bit  access                  */
00248   uint32_t w;                            /*!< Type      used for word access                  */
00249 } APSR_Type;
00250 
00251 
00252 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00253  */
00254 typedef union
00255 {
00256   struct
00257   {
00258     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00259     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00260   } b;                                   /*!< Structure used for bit  access                  */
00261   uint32_t w;                            /*!< Type      used for word access                  */
00262 } IPSR_Type;
00263 
00264 
00265 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00266  */
00267 typedef union
00268 {
00269   struct
00270   {
00271     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00272 #if (__CORTEX_M != 0x04)
00273     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00274 #else
00275     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
00276     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00277     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
00278 #endif
00279     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00280     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00281     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00282     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00283     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00284     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00285     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00286   } b;                                   /*!< Structure used for bit  access                  */
00287   uint32_t w;                            /*!< Type      used for word access                  */
00288 } xPSR_Type;
00289 
00290 
00291 /** \brief  Union type to access the Control Registers (CONTROL).
00292  */
00293 typedef union
00294 {
00295   struct
00296   {
00297     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00298     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00299     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
00300     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
00301   } b;                                   /*!< Structure used for bit  access                  */
00302   uint32_t w;                            /*!< Type      used for word access                  */
00303 } CONTROL_Type;
00304 
00305 /*@} end of group CMSIS_CORE */
00306 
00307 
00308 /** \ingroup    CMSIS_core_register
00309     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00310     \brief      Type definitions for the NVIC Registers
00311   @{
00312  */
00313 
00314 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00315  */
00316 typedef struct
00317 {
00318   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00319        uint32_t RESERVED0[24];
00320   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
00321        uint32_t RSERVED1[24];
00322   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
00323        uint32_t RESERVED2[24];
00324   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
00325        uint32_t RESERVED3[24];
00326   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
00327        uint32_t RESERVED4[56];
00328   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00329        uint32_t RESERVED5[644];
00330   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
00331 }  NVIC_Type;
00332 
00333 /* Software Triggered Interrupt Register Definitions */
00334 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
00335 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
00336 
00337 /*@} end of group CMSIS_NVIC */
00338 
00339 
00340 /** \ingroup  CMSIS_core_register
00341     \defgroup CMSIS_SCB     System Control Block (SCB)
00342     \brief      Type definitions for the System Control Block Registers
00343   @{
00344  */
00345 
00346 /** \brief  Structure type to access the System Control Block (SCB).
00347  */
00348 typedef struct
00349 {
00350   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00351   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00352   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
00353   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00354   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00355   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00356   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00357   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00358   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
00359   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
00360   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
00361   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
00362   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
00363   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
00364   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
00365   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
00366   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
00367   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
00368   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
00369        uint32_t RESERVED0[5];
00370   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
00371 } SCB_Type;
00372 
00373 /* SCB CPUID Register Definitions */
00374 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00375 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00376 
00377 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00378 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00379 
00380 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00381 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00382 
00383 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00384 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00385 
00386 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00387 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
00388 
00389 /* SCB Interrupt Control State Register Definitions */
00390 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00391 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00392 
00393 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00394 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00395 
00396 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00397 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00398 
00399 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00400 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00401 
00402 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00403 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00404 
00405 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00406 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00407 
00408 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00409 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00410 
00411 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00412 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00413 
00414 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
00415 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00416 
00417 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00418 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
00419 
00420 /* SCB Vector Table Offset Register Definitions */
00421 #if (__CM3_REV < 0x0201)                   /* core r2p1 */
00422 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
00423 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
00424 
00425 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00426 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
00427 #else
00428 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00429 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00430 #endif
00431 
00432 /* SCB Application Interrupt and Reset Control Register Definitions */
00433 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00434 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00435 
00436 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00437 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00438 
00439 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00440 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00441 
00442 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
00443 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00444 
00445 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00446 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00447 
00448 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00449 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00450 
00451 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
00452 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
00453 
00454 /* SCB System Control Register Definitions */
00455 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00456 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00457 
00458 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00459 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00460 
00461 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00462 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00463 
00464 /* SCB Configuration Control Register Definitions */
00465 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00466 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00467 
00468 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
00469 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00470 
00471 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
00472 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00473 
00474 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00475 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00476 
00477 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
00478 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00479 
00480 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
00481 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
00482 
00483 /* SCB System Handler Control and State Register Definitions */
00484 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
00485 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00486 
00487 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
00488 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00489 
00490 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
00491 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00492 
00493 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00494 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00495 
00496 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
00497 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00498 
00499 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
00500 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00501 
00502 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
00503 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00504 
00505 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
00506 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00507 
00508 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
00509 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00510 
00511 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
00512 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00513 
00514 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
00515 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00516 
00517 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
00518 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00519 
00520 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
00521 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00522 
00523 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
00524 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
00525 
00526 /* SCB Configurable Fault Status Registers Definitions */
00527 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
00528 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00529 
00530 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
00531 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00532 
00533 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00534 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00535 
00536 /* SCB Hard Fault Status Registers Definitions */
00537 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
00538 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00539 
00540 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
00541 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00542 
00543 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
00544 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00545 
00546 /* SCB Debug Fault Status Register Definitions */
00547 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
00548 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00549 
00550 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
00551 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00552 
00553 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
00554 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00555 
00556 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
00557 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00558 
00559 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
00560 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
00561 
00562 /*@} end of group CMSIS_SCB */
00563 
00564 
00565 /** \ingroup  CMSIS_core_register
00566     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00567     \brief      Type definitions for the System Control and ID Register not in the SCB
00568   @{
00569  */
00570 
00571 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
00572  */
00573 typedef struct
00574 {
00575        uint32_t RESERVED0[1];
00576   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
00577 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
00578   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
00579 #else
00580        uint32_t RESERVED1[1];
00581 #endif
00582 } SCnSCB_Type;
00583 
00584 /* Interrupt Controller Type Register Definitions */
00585 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
00586 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
00587 
00588 /* Auxiliary Control Register Definitions */
00589 
00590 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
00591 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00592 
00593 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
00594 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00595 
00596 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
00597 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
00598 
00599 /*@} end of group CMSIS_SCnotSCB */
00600 
00601 
00602 /** \ingroup  CMSIS_core_register
00603     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00604     \brief      Type definitions for the System Timer Registers.
00605   @{
00606  */
00607 
00608 /** \brief  Structure type to access the System Timer (SysTick).
00609  */
00610 typedef struct
00611 {
00612   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00613   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00614   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00615   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00616 } SysTick_Type;
00617 
00618 /* SysTick Control / Status Register Definitions */
00619 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00620 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00621 
00622 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00623 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00624 
00625 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00626 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00627 
00628 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00629 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
00630 
00631 /* SysTick Reload Register Definitions */
00632 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00633 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
00634 
00635 /* SysTick Current Register Definitions */
00636 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00637 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
00638 
00639 /* SysTick Calibration Register Definitions */
00640 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00641 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00642 
00643 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00644 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00645 
00646 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00647 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
00648 
00649 /*@} end of group CMSIS_SysTick */
00650 
00651 
00652 /** \ingroup  CMSIS_core_register
00653     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00654     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
00655   @{
00656  */
00657 
00658 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00659  */
00660 typedef struct
00661 {
00662   __O  union
00663   {
00664     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
00665     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
00666     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
00667   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
00668        uint32_t RESERVED0[864];
00669   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
00670        uint32_t RESERVED1[15];
00671   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
00672        uint32_t RESERVED2[15];
00673   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
00674        uint32_t RESERVED3[29];
00675   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
00676   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
00677   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
00678        uint32_t RESERVED4[43];
00679   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
00680   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
00681        uint32_t RESERVED5[6];
00682   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00683   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00684   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00685   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00686   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00687   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00688   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00689   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00690   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00691   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00692   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00693   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00694 } ITM_Type;
00695 
00696 /* ITM Trace Privilege Register Definitions */
00697 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
00698 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
00699 
00700 /* ITM Trace Control Register Definitions */
00701 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
00702 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00703 
00704 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
00705 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00706 
00707 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
00708 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00709 
00710 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
00711 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00712 
00713 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
00714 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00715 
00716 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
00717 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00718 
00719 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
00720 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00721 
00722 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
00723 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00724 
00725 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
00726 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
00727 
00728 /* ITM Integration Write Register Definitions */
00729 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
00730 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
00731 
00732 /* ITM Integration Read Register Definitions */
00733 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
00734 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
00735 
00736 /* ITM Integration Mode Control Register Definitions */
00737 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
00738 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
00739 
00740 /* ITM Lock Status Register Definitions */
00741 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
00742 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00743 
00744 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
00745 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00746 
00747 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
00748 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
00749 
00750 /*@}*/ /* end of group CMSIS_ITM */
00751 
00752 
00753 /** \ingroup  CMSIS_core_register
00754     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00755     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
00756   @{
00757  */
00758 
00759 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00760  */
00761 typedef struct
00762 {
00763   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
00764   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
00765   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
00766   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
00767   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
00768   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
00769   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
00770   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
00771   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
00772   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
00773   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
00774        uint32_t RESERVED0[1];
00775   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
00776   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
00777   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
00778        uint32_t RESERVED1[1];
00779   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
00780   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
00781   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
00782        uint32_t RESERVED2[1];
00783   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
00784   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
00785   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
00786 } DWT_Type;
00787 
00788 /* DWT Control Register Definitions */
00789 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
00790 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00791 
00792 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
00793 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00794 
00795 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
00796 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00797 
00798 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
00799 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00800 
00801 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
00802 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00803 
00804 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
00805 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00806 
00807 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
00808 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00809 
00810 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
00811 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00812 
00813 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
00814 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00815 
00816 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
00817 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00818 
00819 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
00820 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00821 
00822 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
00823 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00824 
00825 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
00826 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00827 
00828 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
00829 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00830 
00831 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
00832 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00833 
00834 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
00835 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00836 
00837 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
00838 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00839 
00840 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
00841 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
00842 
00843 /* DWT CPI Count Register Definitions */
00844 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
00845 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
00846 
00847 /* DWT Exception Overhead Count Register Definitions */
00848 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
00849 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
00850 
00851 /* DWT Sleep Count Register Definitions */
00852 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
00853 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00854 
00855 /* DWT LSU Count Register Definitions */
00856 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
00857 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
00858 
00859 /* DWT Folded-instruction Count Register Definitions */
00860 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
00861 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
00862 
00863 /* DWT Comparator Mask Register Definitions */
00864 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
00865 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
00866 
00867 /* DWT Comparator Function Register Definitions */
00868 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
00869 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00870 
00871 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
00872 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00873 
00874 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
00875 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00876 
00877 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
00878 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00879 
00880 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
00881 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00882 
00883 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
00884 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00885 
00886 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
00887 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00888 
00889 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
00890 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00891 
00892 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
00893 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
00894 
00895 /*@}*/ /* end of group CMSIS_DWT */
00896 
00897 
00898 /** \ingroup  CMSIS_core_register
00899     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00900     \brief      Type definitions for the Trace Port Interface (TPI)
00901   @{
00902  */
00903 
00904 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
00905  */
00906 typedef struct
00907 {
00908   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
00909   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00910        uint32_t RESERVED0[2];
00911   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00912        uint32_t RESERVED1[55];
00913   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00914        uint32_t RESERVED2[131];
00915   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00916   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00917   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00918        uint32_t RESERVED3[759];
00919   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00920   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00921   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00922        uint32_t RESERVED4[1];
00923   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00924   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00925   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00926        uint32_t RESERVED5[39];
00927   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00928   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00929        uint32_t RESERVED7[8];
00930   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
00931   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
00932 } TPI_Type;
00933 
00934 /* TPI Asynchronous Clock Prescaler Register Definitions */
00935 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
00936 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
00937 
00938 /* TPI Selected Pin Protocol Register Definitions */
00939 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
00940 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
00941 
00942 /* TPI Formatter and Flush Status Register Definitions */
00943 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
00944 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
00945 
00946 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
00947 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
00948 
00949 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
00950 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
00951 
00952 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
00953 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
00954 
00955 /* TPI Formatter and Flush Control Register Definitions */
00956 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
00957 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
00958 
00959 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
00960 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
00961 
00962 /* TPI TRIGGER Register Definitions */
00963 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
00964 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
00965 
00966 /* TPI Integration ETM Data Register Definitions (FIFO0) */
00967 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
00968 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
00969 
00970 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
00971 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
00972 
00973 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
00974 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
00975 
00976 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
00977 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
00978 
00979 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
00980 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
00981 
00982 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
00983 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
00984 
00985 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
00986 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
00987 
00988 /* TPI ITATBCTR2 Register Definitions */
00989 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
00990 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
00991 
00992 /* TPI Integration ITM Data Register Definitions (FIFO1) */
00993 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
00994 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
00995 
00996 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
00997 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
00998 
00999 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
01000 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
01001 
01002 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
01003 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
01004 
01005 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
01006 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
01007 
01008 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
01009 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01010 
01011 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
01012 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
01013 
01014 /* TPI ITATBCTR0 Register Definitions */
01015 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
01016 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
01017 
01018 /* TPI Integration Mode Control Register Definitions */
01019 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
01020 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
01021 
01022 /* TPI DEVID Register Definitions */
01023 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
01024 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01025 
01026 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
01027 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01028 
01029 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
01030 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01031 
01032 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
01033 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01034 
01035 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
01036 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01037 
01038 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
01039 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
01040 
01041 /* TPI DEVTYPE Register Definitions */
01042 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
01043 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
01044 
01045 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
01046 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01047 
01048 /*@}*/ /* end of group CMSIS_TPI */
01049 
01050 
01051 #if (__MPU_PRESENT == 1)
01052 /** \ingroup  CMSIS_core_register
01053     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01054     \brief      Type definitions for the Memory Protection Unit (MPU)
01055   @{
01056  */
01057 
01058 /** \brief  Structure type to access the Memory Protection Unit (MPU).
01059  */
01060 typedef struct
01061 {
01062   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
01063   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
01064   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
01065   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
01066   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
01067   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
01068   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01069   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
01070   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01071   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
01072   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01073 } MPU_Type;
01074 
01075 /* MPU Type Register */
01076 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
01077 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01078 
01079 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
01080 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01081 
01082 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
01083 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
01084 
01085 /* MPU Control Register */
01086 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
01087 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01088 
01089 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
01090 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01091 
01092 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
01093 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
01094 
01095 /* MPU Region Number Register */
01096 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
01097 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
01098 
01099 /* MPU Region Base Address Register */
01100 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
01101 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01102 
01103 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
01104 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01105 
01106 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
01107 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
01108 
01109 /* MPU Region Attribute and Size Register */
01110 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
01111 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01112 
01113 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
01114 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01115 
01116 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
01117 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01118 
01119 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
01120 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01121 
01122 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
01123 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01124 
01125 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
01126 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01127 
01128 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
01129 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01130 
01131 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
01132 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01133 
01134 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
01135 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01136 
01137 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
01138 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
01139 
01140 /*@} end of group CMSIS_MPU */
01141 #endif
01142 
01143 
01144 /** \ingroup  CMSIS_core_register
01145     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01146     \brief      Type definitions for the Core Debug Registers
01147   @{
01148  */
01149 
01150 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
01151  */
01152 typedef struct
01153 {
01154   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
01155   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
01156   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
01157   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01158 } CoreDebug_Type;
01159 
01160 /* Debug Halting Control and Status Register */
01161 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
01162 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01163 
01164 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
01165 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01166 
01167 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01168 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01169 
01170 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
01171 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01172 
01173 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
01174 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01175 
01176 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
01177 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01178 
01179 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
01180 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01181 
01182 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01183 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01184 
01185 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
01186 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01187 
01188 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
01189 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01190 
01191 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
01192 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01193 
01194 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01195 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01196 
01197 /* Debug Core Register Selector Register */
01198 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
01199 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01200 
01201 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
01202 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
01203 
01204 /* Debug Exception and Monitor Control Register */
01205 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
01206 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01207 
01208 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
01209 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01210 
01211 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
01212 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01213 
01214 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
01215 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01216 
01217 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
01218 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01219 
01220 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
01221 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01222 
01223 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
01224 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01225 
01226 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
01227 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01228 
01229 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
01230 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01231 
01232 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
01233 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01234 
01235 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01236 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01237 
01238 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
01239 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01240 
01241 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
01242 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01243 
01244 /*@} end of group CMSIS_CoreDebug */
01245 
01246 
01247 /** \ingroup    CMSIS_core_register
01248     \defgroup   CMSIS_core_base     Core Definitions
01249     \brief      Definitions for base addresses, unions, and structures.
01250   @{
01251  */
01252 
01253 /* Memory mapping of Cortex-M3 Hardware */
01254 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
01255 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
01256 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
01257 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
01258 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
01259 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
01260 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
01261 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
01262 
01263 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01264 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
01265 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
01266 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
01267 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
01268 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
01269 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
01270 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
01271 
01272 #if (__MPU_PRESENT == 1)
01273   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
01274   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
01275 #endif
01276 
01277 /*@} */
01278 
01279 
01280 
01281 /*******************************************************************************
01282  *                Hardware Abstraction Layer
01283   Core Function Interface contains:
01284   - Core NVIC Functions
01285   - Core SysTick Functions
01286   - Core Debug Functions
01287   - Core Register Access Functions
01288  ******************************************************************************/
01289 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01290 */
01291 
01292 
01293 
01294 /* ##########################   NVIC functions  #################################### */
01295 /** \ingroup  CMSIS_Core_FunctionInterface
01296     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01297     \brief      Functions that manage interrupts and exceptions via the NVIC.
01298     @{
01299  */
01300 
01301 /** \brief  Set Priority Grouping
01302 
01303   The function sets the priority grouping field using the required unlock sequence.
01304   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01305   Only values from 0..7 are used.
01306   In case of a conflict between priority grouping and available
01307   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01308 
01309     \param [in]      PriorityGroup  Priority grouping field.
01310  */
01311 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01312 {
01313   uint32_t reg_value;
01314   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
01315 
01316   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01317   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
01318   reg_value  =  (reg_value                                 |
01319                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
01320                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
01321   SCB->AIRCR =  reg_value;
01322 }
01323 
01324 
01325 /** \brief  Get Priority Grouping
01326 
01327   The function reads the priority grouping field from the NVIC Interrupt Controller.
01328 
01329     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01330  */
01331 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
01332 {
01333   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
01334 }
01335 
01336 
01337 /** \brief  Enable External Interrupt
01338 
01339     The function enables a device-specific interrupt in the NVIC interrupt controller.
01340 
01341     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01342  */
01343 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
01344 {
01345   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
01346 }
01347 
01348 
01349 /** \brief  Disable External Interrupt
01350 
01351     The function disables a device-specific interrupt in the NVIC interrupt controller.
01352 
01353     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01354  */
01355 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
01356 {
01357   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
01358 }
01359 
01360 
01361 /** \brief  Get Pending Interrupt
01362 
01363     The function reads the pending register in the NVIC and returns the pending bit
01364     for the specified interrupt.
01365 
01366     \param [in]      IRQn  Interrupt number.
01367 
01368     \return             0  Interrupt status is not pending.
01369     \return             1  Interrupt status is pending.
01370  */
01371 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
01372 {
01373   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
01374 }
01375 
01376 
01377 /** \brief  Set Pending Interrupt
01378 
01379     The function sets the pending bit of an external interrupt.
01380 
01381     \param [in]      IRQn  Interrupt number. Value cannot be negative.
01382  */
01383 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
01384 {
01385   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
01386 }
01387 
01388 
01389 /** \brief  Clear Pending Interrupt
01390 
01391     The function clears the pending bit of an external interrupt.
01392 
01393     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01394  */
01395 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
01396 {
01397   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
01398 }
01399 
01400 
01401 /** \brief  Get Active Interrupt
01402 
01403     The function reads the active register in NVIC and returns the active bit.
01404 
01405     \param [in]      IRQn  Interrupt number.
01406 
01407     \return             0  Interrupt status is not active.
01408     \return             1  Interrupt status is active.
01409  */
01410 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
01411 {
01412   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
01413 }
01414 
01415 
01416 /** \brief  Set Interrupt Priority
01417 
01418     The function sets the priority of an interrupt.
01419 
01420     \note The priority cannot be set for every core interrupt.
01421 
01422     \param [in]      IRQn  Interrupt number.
01423     \param [in]  priority  Priority to set.
01424  */
01425 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
01426 {
01427   if(IRQn < 0) {
01428     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
01429   else {
01430     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
01431 }
01432 
01433 
01434 /** \brief  Get Interrupt Priority
01435 
01436     The function reads the priority of an interrupt. The interrupt
01437     number can be positive to specify an external (device specific)
01438     interrupt, or negative to specify an internal (core) interrupt.
01439 
01440 
01441     \param [in]   IRQn  Interrupt number.
01442     \return             Interrupt Priority. Value is aligned automatically to the implemented
01443                         priority bits of the microcontroller.
01444  */
01445 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
01446 {
01447 
01448   if(IRQn < 0) {
01449     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
01450   else {
01451     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
01452 }
01453 
01454 
01455 /** \brief  Encode Priority
01456 
01457     The function encodes the priority for an interrupt with the given priority group,
01458     preemptive priority value, and subpriority value.
01459     In case of a conflict between priority grouping and available
01460     priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01461 
01462     \param [in]     PriorityGroup  Used priority group.
01463     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01464     \param [in]       SubPriority  Subpriority value (starting from 0).
01465     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01466  */
01467 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01468 {
01469   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01470   uint32_t PreemptPriorityBits;
01471   uint32_t SubPriorityBits;
01472 
01473   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01474   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01475 
01476   return (
01477            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
01478            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
01479          );
01480 }
01481 
01482 
01483 /** \brief  Decode Priority
01484 
01485     The function decodes an interrupt priority value with a given priority group to
01486     preemptive priority value and subpriority value.
01487     In case of a conflict between priority grouping and available
01488     priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
01489 
01490     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01491     \param [in]     PriorityGroup  Used priority group.
01492     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01493     \param [out]     pSubPriority  Subpriority value (starting from 0).
01494  */
01495 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
01496 {
01497   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01498   uint32_t PreemptPriorityBits;
01499   uint32_t SubPriorityBits;
01500 
01501   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01502   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01503 
01504   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
01505   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
01506 }
01507 
01508 
01509 /** \brief  System Reset
01510 
01511     The function initiates a system reset request to reset the MCU.
01512  */
01513 __STATIC_INLINE void NVIC_SystemReset(void)
01514 {
01515   __DSB();                                                     /* Ensure all outstanding memory accesses included
01516                                                                   buffered write are completed before reset */
01517   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
01518                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01519                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
01520   __DSB();                                                     /* Ensure completion of memory access */
01521   while(1);                                                    /* wait until reset */
01522 }
01523 
01524 /*@} end of CMSIS_Core_NVICFunctions */
01525 
01526 
01527 
01528 /* ##################################    SysTick function  ############################################ */
01529 /** \ingroup  CMSIS_Core_FunctionInterface
01530     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01531     \brief      Functions that configure the System.
01532   @{
01533  */
01534 
01535 #if (__Vendor_SysTickConfig == 0)
01536 
01537 /** \brief  System Tick Configuration
01538 
01539     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
01540     Counter is in free running mode to generate periodic interrupts.
01541 
01542     \param [in]  ticks  Number of ticks between two interrupts.
01543 
01544     \return          0  Function succeeded.
01545     \return          1  Function failed.
01546 
01547     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01548     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01549     must contain a vendor-specific implementation of this function.
01550 
01551  */
01552 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01553 {
01554   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
01555 
01556   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
01557   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
01558   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
01559   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01560                    SysTick_CTRL_TICKINT_Msk   |
01561                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
01562   return (0);                                                  /* Function successful */
01563 }
01564 
01565 #endif
01566 
01567 /*@} end of CMSIS_Core_SysTickFunctions */
01568 
01569 
01570 
01571 /* ##################################### Debug In/Output function ########################################### */
01572 /** \ingroup  CMSIS_Core_FunctionInterface
01573     \defgroup CMSIS_core_DebugFunctions ITM Functions
01574     \brief   Functions that access the ITM debug interface.
01575   @{
01576  */
01577 
01578 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
01579 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01580 
01581 
01582 /** \brief  ITM Send Character
01583 
01584     The function transmits a character via the ITM channel 0, and
01585     \li Just returns when no debugger is connected that has booked the output.
01586     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01587 
01588     \param [in]     ch  Character to transmit.
01589 
01590     \returns            Character to transmit.
01591  */
01592 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01593 {
01594   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
01595       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
01596   {
01597     while (ITM->PORT[0].u32 == 0);
01598     ITM->PORT[0].u8 = (uint8_t) ch;
01599   }
01600   return (ch);
01601 }
01602 
01603 
01604 /** \brief  ITM Receive Character
01605 
01606     The function inputs a character via the external variable \ref ITM_RxBuffer.
01607 
01608     \return             Received character.
01609     \return         -1  No character pending.
01610  */
01611 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
01612   int32_t ch = -1;                           /* no character available */
01613 
01614   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
01615     ch = ITM_RxBuffer;
01616     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01617   }
01618 
01619   return (ch);
01620 }
01621 
01622 
01623 /** \brief  ITM Check Character
01624 
01625     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01626 
01627     \return          0  No character available.
01628     \return          1  Character available.
01629  */
01630 __STATIC_INLINE int32_t ITM_CheckChar (void) {
01631 
01632   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
01633     return (0);                                 /* no character available */
01634   } else {
01635     return (1);                                 /*    character available */
01636   }
01637 }
01638 
01639 /*@} end of CMSIS_core_DebugFunctions */
01640 
01641 
01642 
01643 
01644 #ifdef __cplusplus
01645 }
01646 #endif
01647 
01648 #endif /* __CORE_CM3_H_DEPENDANT */
01649 
01650 #endif /* __CMSIS_GENERIC */