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core_cm0.h
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00001 /**************************************************************************//** 00002 * @file core_cm0.h 00003 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 00004 * @version V4.00 00005 * @date 22. August 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_CM0_H_GENERIC 00043 #define __CORE_CM0_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M0 00067 @{ 00068 */ 00069 00070 /* CMSIS CM0 definitions */ 00071 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 This core does not support an FPU at all 00113 */ 00114 #define __FPU_USED 0 00115 00116 #if defined ( __CC_ARM ) 00117 #if defined __TARGET_FPU_VFP 00118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00119 #endif 00120 00121 #elif defined ( __GNUC__ ) 00122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00124 #endif 00125 00126 #elif defined ( __ICCARM__ ) 00127 #if defined __ARMVFP__ 00128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00129 #endif 00130 00131 #elif defined ( __TMS470__ ) 00132 #if defined __TI__VFP_SUPPORT____ 00133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00139 #endif 00140 00141 #elif defined ( __CSMC__ ) /* Cosmic */ 00142 #if ( __CSMC__ & 0x400) // FPU present for parser 00143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #endif 00145 #endif 00146 00147 #include <stdint.h> /* standard types definitions */ 00148 #include <core_cmInstr.h> /* Core Instruction Access */ 00149 #include <core_cmFunc.h> /* Core Function Access */ 00150 00151 #ifdef __cplusplus 00152 } 00153 #endif 00154 00155 #endif /* __CORE_CM0_H_GENERIC */ 00156 00157 #ifndef __CMSIS_GENERIC 00158 00159 #ifndef __CORE_CM0_H_DEPENDANT 00160 #define __CORE_CM0_H_DEPENDANT 00161 00162 #ifdef __cplusplus 00163 extern "C" { 00164 #endif 00165 00166 /* check device defines and use defaults */ 00167 #if defined __CHECK_DEVICE_DEFINES 00168 #ifndef __CM0_REV 00169 #define __CM0_REV 0x0000 00170 #warning "__CM0_REV not defined in device header file; using default!" 00171 #endif 00172 00173 #ifndef __NVIC_PRIO_BITS 00174 #define __NVIC_PRIO_BITS 2 00175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00176 #endif 00177 00178 #ifndef __Vendor_SysTickConfig 00179 #define __Vendor_SysTickConfig 0 00180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00181 #endif 00182 #endif 00183 00184 /* IO definitions (access restrictions to peripheral registers) */ 00185 /** 00186 \defgroup CMSIS_glob_defs CMSIS Global Defines 00187 00188 <strong>IO Type Qualifiers</strong> are used 00189 \li to specify the access to peripheral variables. 00190 \li for automatic generation of peripheral register debug information. 00191 */ 00192 #ifdef __cplusplus 00193 #define __I volatile /*!< Defines 'read only' permissions */ 00194 #else 00195 #define __I volatile const /*!< Defines 'read only' permissions */ 00196 #endif 00197 #define __O volatile /*!< Defines 'write only' permissions */ 00198 #define __IO volatile /*!< Defines 'read / write' permissions */ 00199 00200 /*@} end of group Cortex_M0 */ 00201 00202 00203 00204 /******************************************************************************* 00205 * Register Abstraction 00206 Core Register contain: 00207 - Core Register 00208 - Core NVIC Register 00209 - Core SCB Register 00210 - Core SysTick Register 00211 ******************************************************************************/ 00212 /** \defgroup CMSIS_core_register Defines and Type Definitions 00213 \brief Type definitions and defines for Cortex-M processor based devices. 00214 */ 00215 00216 /** \ingroup CMSIS_core_register 00217 \defgroup CMSIS_CORE Status and Control Registers 00218 \brief Core Register type definitions. 00219 @{ 00220 */ 00221 00222 /** \brief Union type to access the Application Program Status Register (APSR). 00223 */ 00224 typedef union 00225 { 00226 struct 00227 { 00228 #if (__CORTEX_M != 0x04) 00229 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00230 #else 00231 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00232 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00233 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00234 #endif 00235 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00240 } b; /*!< Structure used for bit access */ 00241 uint32_t w; /*!< Type used for word access */ 00242 } APSR_Type; 00243 00244 00245 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00246 */ 00247 typedef union 00248 { 00249 struct 00250 { 00251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00252 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00253 } b; /*!< Structure used for bit access */ 00254 uint32_t w; /*!< Type used for word access */ 00255 } IPSR_Type; 00256 00257 00258 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00259 */ 00260 typedef union 00261 { 00262 struct 00263 { 00264 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00265 #if (__CORTEX_M != 0x04) 00266 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00267 #else 00268 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00269 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00270 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00271 #endif 00272 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00273 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00274 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00275 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00276 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00277 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00278 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00279 } b; /*!< Structure used for bit access */ 00280 uint32_t w; /*!< Type used for word access */ 00281 } xPSR_Type; 00282 00283 00284 /** \brief Union type to access the Control Registers (CONTROL). 00285 */ 00286 typedef union 00287 { 00288 struct 00289 { 00290 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00291 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00292 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00293 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00294 } b; /*!< Structure used for bit access */ 00295 uint32_t w; /*!< Type used for word access */ 00296 } CONTROL_Type; 00297 00298 /*@} end of group CMSIS_CORE */ 00299 00300 00301 /** \ingroup CMSIS_core_register 00302 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00303 \brief Type definitions for the NVIC Registers 00304 @{ 00305 */ 00306 00307 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00308 */ 00309 typedef struct 00310 { 00311 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00312 uint32_t RESERVED0[31]; 00313 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00314 uint32_t RSERVED1[31]; 00315 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00316 uint32_t RESERVED2[31]; 00317 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00318 uint32_t RESERVED3[31]; 00319 uint32_t RESERVED4[64]; 00320 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00321 } NVIC_Type; 00322 00323 /*@} end of group CMSIS_NVIC */ 00324 00325 00326 /** \ingroup CMSIS_core_register 00327 \defgroup CMSIS_SCB System Control Block (SCB) 00328 \brief Type definitions for the System Control Block Registers 00329 @{ 00330 */ 00331 00332 /** \brief Structure type to access the System Control Block (SCB). 00333 */ 00334 typedef struct 00335 { 00336 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00337 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00338 uint32_t RESERVED0; 00339 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00340 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00341 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00342 uint32_t RESERVED1; 00343 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00344 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00345 } SCB_Type; 00346 00347 /* SCB CPUID Register Definitions */ 00348 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00349 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00350 00351 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00352 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00353 00354 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00355 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00356 00357 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00358 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00359 00360 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00361 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00362 00363 /* SCB Interrupt Control State Register Definitions */ 00364 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00365 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00366 00367 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00368 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00369 00370 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00371 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00372 00373 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00374 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00375 00376 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00377 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00378 00379 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00380 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00381 00382 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00383 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00384 00385 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00386 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00387 00388 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00389 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00390 00391 /* SCB Application Interrupt and Reset Control Register Definitions */ 00392 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00393 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00394 00395 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00396 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00397 00398 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00399 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00400 00401 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00402 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00403 00404 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00405 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00406 00407 /* SCB System Control Register Definitions */ 00408 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00409 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00410 00411 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00412 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00413 00414 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00415 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00416 00417 /* SCB Configuration Control Register Definitions */ 00418 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00419 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00420 00421 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00422 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00423 00424 /* SCB System Handler Control and State Register Definitions */ 00425 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00426 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00427 00428 /*@} end of group CMSIS_SCB */ 00429 00430 00431 /** \ingroup CMSIS_core_register 00432 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00433 \brief Type definitions for the System Timer Registers. 00434 @{ 00435 */ 00436 00437 /** \brief Structure type to access the System Timer (SysTick). 00438 */ 00439 typedef struct 00440 { 00441 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00442 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00443 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00444 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00445 } SysTick_Type; 00446 00447 /* SysTick Control / Status Register Definitions */ 00448 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00449 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00450 00451 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00452 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00453 00454 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00455 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00456 00457 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00458 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00459 00460 /* SysTick Reload Register Definitions */ 00461 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00462 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00463 00464 /* SysTick Current Register Definitions */ 00465 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00466 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00467 00468 /* SysTick Calibration Register Definitions */ 00469 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00470 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00471 00472 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00473 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00474 00475 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00476 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 00477 00478 /*@} end of group CMSIS_SysTick */ 00479 00480 00481 /** \ingroup CMSIS_core_register 00482 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00483 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00484 are only accessible over DAP and not via processor. Therefore 00485 they are not covered by the Cortex-M0 header file. 00486 @{ 00487 */ 00488 /*@} end of group CMSIS_CoreDebug */ 00489 00490 00491 /** \ingroup CMSIS_core_register 00492 \defgroup CMSIS_core_base Core Definitions 00493 \brief Definitions for base addresses, unions, and structures. 00494 @{ 00495 */ 00496 00497 /* Memory mapping of Cortex-M0 Hardware */ 00498 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00499 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00500 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00501 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00502 00503 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00504 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00505 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00506 00507 00508 /*@} */ 00509 00510 00511 00512 /******************************************************************************* 00513 * Hardware Abstraction Layer 00514 Core Function Interface contains: 00515 - Core NVIC Functions 00516 - Core SysTick Functions 00517 - Core Register Access Functions 00518 ******************************************************************************/ 00519 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00520 */ 00521 00522 00523 00524 /* ########################## NVIC functions #################################### */ 00525 /** \ingroup CMSIS_Core_FunctionInterface 00526 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00527 \brief Functions that manage interrupts and exceptions via the NVIC. 00528 @{ 00529 */ 00530 00531 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00532 /* The following MACROS handle generation of the register offset and byte masks */ 00533 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00534 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00535 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00536 00537 00538 /** \brief Enable External Interrupt 00539 00540 The function enables a device-specific interrupt in the NVIC interrupt controller. 00541 00542 \param [in] IRQn External interrupt number. Value cannot be negative. 00543 */ 00544 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00545 { 00546 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00547 } 00548 00549 00550 /** \brief Disable External Interrupt 00551 00552 The function disables a device-specific interrupt in the NVIC interrupt controller. 00553 00554 \param [in] IRQn External interrupt number. Value cannot be negative. 00555 */ 00556 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00557 { 00558 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00559 } 00560 00561 00562 /** \brief Get Pending Interrupt 00563 00564 The function reads the pending register in the NVIC and returns the pending bit 00565 for the specified interrupt. 00566 00567 \param [in] IRQn Interrupt number. 00568 00569 \return 0 Interrupt status is not pending. 00570 \return 1 Interrupt status is pending. 00571 */ 00572 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00573 { 00574 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00575 } 00576 00577 00578 /** \brief Set Pending Interrupt 00579 00580 The function sets the pending bit of an external interrupt. 00581 00582 \param [in] IRQn Interrupt number. Value cannot be negative. 00583 */ 00584 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00585 { 00586 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00587 } 00588 00589 00590 /** \brief Clear Pending Interrupt 00591 00592 The function clears the pending bit of an external interrupt. 00593 00594 \param [in] IRQn External interrupt number. Value cannot be negative. 00595 */ 00596 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00597 { 00598 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00599 } 00600 00601 00602 /** \brief Set Interrupt Priority 00603 00604 The function sets the priority of an interrupt. 00605 00606 \note The priority cannot be set for every core interrupt. 00607 00608 \param [in] IRQn Interrupt number. 00609 \param [in] priority Priority to set. 00610 */ 00611 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00612 { 00613 if(IRQn < 0) { 00614 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00615 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00616 else { 00617 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00618 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00619 } 00620 00621 00622 /** \brief Get Interrupt Priority 00623 00624 The function reads the priority of an interrupt. The interrupt 00625 number can be positive to specify an external (device specific) 00626 interrupt, or negative to specify an internal (core) interrupt. 00627 00628 00629 \param [in] IRQn Interrupt number. 00630 \return Interrupt Priority. Value is aligned automatically to the implemented 00631 priority bits of the microcontroller. 00632 */ 00633 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00634 { 00635 00636 if(IRQn < 0) { 00637 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00638 else { 00639 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00640 } 00641 00642 00643 /** \brief System Reset 00644 00645 The function initiates a system reset request to reset the MCU. 00646 */ 00647 __STATIC_INLINE void NVIC_SystemReset(void) 00648 { 00649 __DSB(); /* Ensure all outstanding memory accesses included 00650 buffered write are completed before reset */ 00651 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00652 SCB_AIRCR_SYSRESETREQ_Msk); 00653 __DSB(); /* Ensure completion of memory access */ 00654 while(1); /* wait until reset */ 00655 } 00656 00657 /*@} end of CMSIS_Core_NVICFunctions */ 00658 00659 00660 00661 /* ################################## SysTick function ############################################ */ 00662 /** \ingroup CMSIS_Core_FunctionInterface 00663 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00664 \brief Functions that configure the System. 00665 @{ 00666 */ 00667 00668 #if (__Vendor_SysTickConfig == 0) 00669 00670 /** \brief System Tick Configuration 00671 00672 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00673 Counter is in free running mode to generate periodic interrupts. 00674 00675 \param [in] ticks Number of ticks between two interrupts. 00676 00677 \return 0 Function succeeded. 00678 \return 1 Function failed. 00679 00680 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00681 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00682 must contain a vendor-specific implementation of this function. 00683 00684 */ 00685 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00686 { 00687 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00688 00689 SysTick->LOAD = ticks - 1; /* set reload register */ 00690 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00691 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00692 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00693 SysTick_CTRL_TICKINT_Msk | 00694 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00695 return (0); /* Function successful */ 00696 } 00697 00698 #endif 00699 00700 /*@} end of CMSIS_Core_SysTickFunctions */ 00701 00702 00703 00704 00705 #ifdef __cplusplus 00706 } 00707 #endif 00708 00709 #endif /* __CORE_CM0_H_DEPENDANT */ 00710 00711 #endif /* __CMSIS_GENERIC */
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