mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

spi_dma/spi_dma_stm32f4.c@38:7077795dbf81, 2017-01-22 (annotated)

Committer:
mimi3
Date:
Sun Jan 22 23:13:11 2017 +0900
Revision:
38:7077795dbf81
Parent:
35:4ecb46c4d9ad 
change: table.md

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dinau 35:4ecb46c4d9ad 1 #if defined(TARGET_STM32F4) || defined(TARGET_STM32L4)
mimi3 23:e3f06b3cc366 2 /* Mainly aim at
mimi3 23:e3f06b3cc366 3 NUCLEO-F401RE
mimi3 23:e3f06b3cc366 4 NUCLEO-F411RE
mimi3 23:e3f06b3cc366 5 NUCLEO-F410RB
mimi3 23:e3f06b3cc366 6 NUCLEO-F446RE
mimi3 23:e3f06b3cc366 7 */
mimi3 23:e3f06b3cc366 8
mimi3 2:0e871408d51b 9 /*
mimi3 2:0e871408d51b 10
mimi3 2:0e871408d51b 11 This file is licensed under Apache 2.0 license.
mimi3 2:0e871408d51b 12 (C) 2016 dinau
mimi3 2:0e871408d51b 13
mimi3 2:0e871408d51b 14 */
mimi3 2:0e871408d51b 15 #include "spi_dma.h"
mimi3 2:0e871408d51b 16
mimi3 23:e3f06b3cc366 17 /* For SPI1 */
mimi3 23:e3f06b3cc366 18 #define SPI1_DMAx_CLK_ENABLE() __DMA2_CLK_ENABLE()
mimi3 23:e3f06b3cc366 19 #define SPI1_DMAx_TX_STREAM DMA2_Stream3
mimi3 23:e3f06b3cc366 20 #define SPI1_DMAx_RX_STREAM DMA2_Stream2
mimi3 23:e3f06b3cc366 21 #define SPI1_DMAx_TX_CHANNEL DMA_CHANNEL_3
mimi3 23:e3f06b3cc366 22 #define SPI1_DMAx_RX_CHANNEL DMA_CHANNEL_3
mimi3 23:e3f06b3cc366 23 #define SPI1_DMAx_TX_IRQn DMA2_Stream3_IRQn
mimi3 23:e3f06b3cc366 24 #define SPI1_DMAx_RX_IRQn DMA2_Stream2_IRQn
mimi3 23:e3f06b3cc366 25 #define SPI1_DMAx_TX_IRQHandler DMA2_Stream3_IRQHandler
mimi3 23:e3f06b3cc366 26 #define SPI1_DMAx_RX_IRQHandler DMA2_Stream2_IRQHandler
mimi3 23:e3f06b3cc366 27 /* For SPI3 */
mimi3 23:e3f06b3cc366 28 #define SPI3_DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE()
mimi3 23:e3f06b3cc366 29 #define SPI3_DMAx_TX_STREAM DMA1_Stream5
mimi3 23:e3f06b3cc366 30 #define SPI3_DMAx_RX_STREAM DMA1_Stream2
mimi3 23:e3f06b3cc366 31 #define SPI3_DMAx_TX_CHANNEL DMA_CHANNEL_0
mimi3 23:e3f06b3cc366 32 #define SPI3_DMAx_RX_CHANNEL DMA_CHANNEL_0
mimi3 23:e3f06b3cc366 33 #define SPI3_DMAx_TX_IRQn DMA1_Stream5_IRQn
mimi3 23:e3f06b3cc366 34 #define SPI3_DMAx_RX_IRQn DMA1_Stream2_IRQn
mimi3 23:e3f06b3cc366 35 #define SPI3_DMAx_TX_IRQHandler DMA1_Stream5_IRQHandler
mimi3 23:e3f06b3cc366 36 #define SPI3_DMAx_RX_IRQHandler DMA1_Stream2_IRQHandler
mimi3 2:0e871408d51b 37
mimi3 2:0e871408d51b 38 #define readReg( reg, mask) ( (reg) & (mask) )
mimi3 2:0e871408d51b 39
mimi3 2:0e871408d51b 40 void spi_dma_get_info( SPI_TypeDef *spi )
mimi3 2:0e871408d51b 41 {
mimi3 21:41129109d6ab 42 SpiHandle.Instance = spi;
mimi3 21:41129109d6ab 43 SpiHandle.Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER);
mimi3 21:41129109d6ab 44 SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
mimi3 21:41129109d6ab 45 SpiHandle.Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE);
mimi3 21:41129109d6ab 46 SpiHandle.Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA);
mimi3 21:41129109d6ab 47 SpiHandle.Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL);
mimi3 21:41129109d6ab 48 SpiHandle.Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN);
mimi3 21:41129109d6ab 49 SpiHandle.Init.CRCPolynomial = spi->CRCPR & 0xFFFF;
mimi3 21:41129109d6ab 50 SpiHandle.Init.DataSize = readReg(spi->CR1, SPI_CR1_DFF);
mimi3 21:41129109d6ab 51 SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
mimi3 21:41129109d6ab 52 SpiHandle.Init.NSS = readReg(spi->CR1, SPI_CR1_SSM);
mimi3 21:41129109d6ab 53 SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
mimi3 21:41129109d6ab 54 SpiHandle.State = HAL_SPI_STATE_READY;
mimi3 2:0e871408d51b 55 }
mimi3 2:0e871408d51b 56
mimi3 18:1b1a0e68008a 57 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
mimi3 18:1b1a0e68008a 58 {
mimi3 21:41129109d6ab 59 static uint8_t dma_handle_inited = 0;
mimi3 21:41129109d6ab 60 /* Peripheral DMA init*/
mimi3 21:41129109d6ab 61 /* TX: */
mimi3 21:41129109d6ab 62 if( !dma_handle_inited ){
mimi3 23:e3f06b3cc366 63 if( spi == SPI1 ){
mimi3 23:e3f06b3cc366 64 hdma_spi_tx.Instance = SPI1_DMAx_TX_STREAM;
mimi3 23:e3f06b3cc366 65 hdma_spi_tx.Init.Channel = SPI1_DMAx_TX_CHANNEL;
mimi3 23:e3f06b3cc366 66 } else if( spi == SPI3 ) {
mimi3 23:e3f06b3cc366 67 hdma_spi_tx.Instance = SPI3_DMAx_TX_STREAM;
mimi3 23:e3f06b3cc366 68 hdma_spi_tx.Init.Channel = SPI3_DMAx_TX_CHANNEL;
mimi3 23:e3f06b3cc366 69 }
mimi3 21:41129109d6ab 70 hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
mimi3 21:41129109d6ab 71 hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 21:41129109d6ab 72 hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 21:41129109d6ab 73 hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 21:41129109d6ab 74 hdma_spi_tx.Init.Mode = DMA_NORMAL;
mimi3 21:41129109d6ab 75 hdma_spi_tx.Init.Priority = DMA_PRIORITY_HIGH;
mimi3 21:41129109d6ab 76 /**/
mimi3 21:41129109d6ab 77 hdma_spi_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
mimi3 21:41129109d6ab 78 hdma_spi_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
mimi3 21:41129109d6ab 79 hdma_spi_tx.Init.MemBurst = DMA_MBURST_SINGLE;
mimi3 21:41129109d6ab 80 hdma_spi_tx.Init.PeriphBurst = DMA_PBURST_SINGLE;
mimi3 21:41129109d6ab 81 /**/
mimi3 21:41129109d6ab 82 }
mimi3 21:41129109d6ab 83 hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
mimi3 21:41129109d6ab 84 HAL_DMA_Init(&hdma_spi_tx);
mimi3 21:41129109d6ab 85 __HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
mimi3 2:0e871408d51b 86
mimi3 21:41129109d6ab 87 /* RX: */
mimi3 21:41129109d6ab 88 if( !dma_handle_inited ){
mimi3 23:e3f06b3cc366 89 if( spi == SPI1 ){
mimi3 23:e3f06b3cc366 90 hdma_spi_rx.Instance = SPI1_DMAx_RX_STREAM;
mimi3 23:e3f06b3cc366 91 hdma_spi_rx.Init.Channel = SPI1_DMAx_RX_CHANNEL;
mimi3 23:e3f06b3cc366 92 } else if( spi == SPI3 ) {
mimi3 23:e3f06b3cc366 93 hdma_spi_rx.Instance = SPI3_DMAx_RX_STREAM;
mimi3 23:e3f06b3cc366 94 hdma_spi_rx.Init.Channel = SPI3_DMAx_RX_CHANNEL;
mimi3 23:e3f06b3cc366 95 }
mimi3 21:41129109d6ab 96 hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
mimi3 21:41129109d6ab 97 hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 21:41129109d6ab 98 hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 21:41129109d6ab 99 hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 21:41129109d6ab 100 hdma_spi_rx.Init.Mode = DMA_NORMAL;
mimi3 21:41129109d6ab 101 hdma_spi_rx.Init.Priority = DMA_PRIORITY_LOW;
mimi3 21:41129109d6ab 102 /**/
mimi3 21:41129109d6ab 103 hdma_spi_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
mimi3 21:41129109d6ab 104 hdma_spi_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
mimi3 21:41129109d6ab 105 hdma_spi_rx.Init.MemBurst = DMA_MBURST_SINGLE;
mimi3 21:41129109d6ab 106 hdma_spi_rx.Init.PeriphBurst = DMA_PBURST_SINGLE;
mimi3 21:41129109d6ab 107 /**/
mimi3 21:41129109d6ab 108 }
mimi3 21:41129109d6ab 109 hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
mimi3 21:41129109d6ab 110 HAL_DMA_Init(&hdma_spi_rx);
mimi3 21:41129109d6ab 111 __HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx);
mimi3 2:0e871408d51b 112
mimi3 21:41129109d6ab 113 dma_handle_inited = 1;
mimi3 2:0e871408d51b 114 }
mimi3 2:0e871408d51b 115
mimi3 2:0e871408d51b 116 void spi_dma_irq_setup( SPI_TypeDef *spi)
mimi3 2:0e871408d51b 117 {
mimi3 21:41129109d6ab 118 /* DMA controller clock enable */
mimi3 23:e3f06b3cc366 119 if( spi == SPI1 ){
mimi3 23:e3f06b3cc366 120 SPI1_DMAx_CLK_ENABLE();
mimi3 23:e3f06b3cc366 121 /* DMA interrupt init */
mimi3 23:e3f06b3cc366 122 HAL_NVIC_SetPriority(SPI1_DMAx_TX_IRQn, 0, 1);
mimi3 23:e3f06b3cc366 123 HAL_NVIC_EnableIRQ( SPI1_DMAx_TX_IRQn);
mimi3 23:e3f06b3cc366 124 HAL_NVIC_SetPriority(SPI1_DMAx_RX_IRQn, 0, 0);
mimi3 23:e3f06b3cc366 125 HAL_NVIC_EnableIRQ( SPI1_DMAx_RX_IRQn);
mimi3 23:e3f06b3cc366 126 } else if( spi == SPI3 ){
mimi3 23:e3f06b3cc366 127 SPI3_DMAx_CLK_ENABLE();
mimi3 23:e3f06b3cc366 128 /* DMA interrupt init */
mimi3 23:e3f06b3cc366 129 HAL_NVIC_SetPriority(SPI3_DMAx_TX_IRQn, 0, 1);
mimi3 23:e3f06b3cc366 130 HAL_NVIC_EnableIRQ( SPI3_DMAx_TX_IRQn);
mimi3 23:e3f06b3cc366 131 HAL_NVIC_SetPriority(SPI3_DMAx_RX_IRQn, 0, 0);
mimi3 23:e3f06b3cc366 132 HAL_NVIC_EnableIRQ( SPI3_DMAx_RX_IRQn);
mimi3 23:e3f06b3cc366 133 }
mimi3 2:0e871408d51b 134 }
mimi3 2:0e871408d51b 135
mimi3 23:e3f06b3cc366 136 /* For SPI1 */
mimi3 23:e3f06b3cc366 137 void SPI1_DMAx_TX_IRQHandler(void)
mimi3 18:1b1a0e68008a 138 {
mimi3 21:41129109d6ab 139 HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3 18:1b1a0e68008a 140 }
mimi3 2:0e871408d51b 141
mimi3 23:e3f06b3cc366 142 void SPI1_DMAx_RX_IRQHandler(void)
mimi3 2:0e871408d51b 143 {
mimi3 21:41129109d6ab 144 HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3 2:0e871408d51b 145 }
mimi3 2:0e871408d51b 146
mimi3 23:e3f06b3cc366 147 /* For SPI3 */
mimi3 23:e3f06b3cc366 148 void SPI3_DMAx_TX_IRQHandler(void)
mimi3 23:e3f06b3cc366 149 {
mimi3 23:e3f06b3cc366 150 HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3 23:e3f06b3cc366 151 }
mimi3 23:e3f06b3cc366 152
mimi3 23:e3f06b3cc366 153 void SPI3_DMAx_RX_IRQHandler(void)
mimi3 23:e3f06b3cc366 154 {
mimi3 23:e3f06b3cc366 155 HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3 23:e3f06b3cc366 156 }
mimi3 23:e3f06b3cc366 157
mimi3 23:e3f06b3cc366 158
mimi3 2:0e871408d51b 159 #endif /* TARGET_STM32F4 */
mimi3 2:0e871408d51b 160