mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

spi_dma/spi_dma_stm32f1.c@38:7077795dbf81, 2017-01-22 (annotated)

Committer:
mimi3
Date:
Sun Jan 22 23:13:11 2017 +0900
Revision:
38:7077795dbf81
Parent:
27:a9d19b780770 
change: table.md

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mimi3 2:0e871408d51b 1 #if defined(TARGET_STM32F1) || defined(TARGET_STM32L1)
mimi3 2:0e871408d51b 2 /*
mimi3 2:0e871408d51b 3
mimi3 2:0e871408d51b 4 This file is licensed under Apache 2.0 license.
mimi3 2:0e871408d51b 5 (C) 2016 dinau
mimi3 2:0e871408d51b 6
mimi3 2:0e871408d51b 7 */
mimi3 2:0e871408d51b 8 #include "spi_dma.h"
mimi3 2:0e871408d51b 9
mimi3 21:41129109d6ab 10 /* For SPI1 */
mimi3 25:f6aa2b6ff6c1 11 #define SPI1_DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE()
mimi3 25:f6aa2b6ff6c1 12 #define SPI1_DMAx_TX_CHANNEL DMA1_Channel3
mimi3 25:f6aa2b6ff6c1 13 #define SPI1_DMAx_RX_CHANNEL DMA1_Channel2
mimi3 25:f6aa2b6ff6c1 14 #define SPI1_DMAx_TX_IRQn DMA1_Channel3_IRQn
mimi3 25:f6aa2b6ff6c1 15 #define SPI1_DMAx_RX_IRQn DMA1_Channel2_IRQn
mimi3 25:f6aa2b6ff6c1 16 #define SPI1_DMAx_TX_IRQHandler DMA1_Channel3_IRQHandler
mimi3 25:f6aa2b6ff6c1 17 #define SPI1_DMAx_RX_IRQHandler DMA1_Channel2_IRQHandler
mimi3 25:f6aa2b6ff6c1 18 /* For SPI2 */
mimi3 25:f6aa2b6ff6c1 19 #define SPI2_DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE()
mimi3 25:f6aa2b6ff6c1 20 #define SPI2_DMAx_TX_CHANNEL DMA1_Channel5
mimi3 25:f6aa2b6ff6c1 21 #define SPI2_DMAx_RX_CHANNEL DMA1_Channel4
mimi3 25:f6aa2b6ff6c1 22 #define SPI2_DMAx_TX_IRQn DMA1_Channel5_IRQn
mimi3 25:f6aa2b6ff6c1 23 #define SPI2_DMAx_RX_IRQn DMA1_Channel4_IRQn
mimi3 25:f6aa2b6ff6c1 24 #define SPI2_DMAx_TX_IRQHandler DMA1_Channel5_IRQHandler
mimi3 25:f6aa2b6ff6c1 25 #define SPI2_DMAx_RX_IRQHandler DMA1_Channel4_IRQHandler
mimi3 21:41129109d6ab 26
mimi3 25:f6aa2b6ff6c1 27 #define readReg( reg, mask) ( (reg) & (mask) )
mimi3 2:0e871408d51b 28
mimi3 2:0e871408d51b 29
mimi3 2:0e871408d51b 30 void spi_dma_get_info( SPI_TypeDef *spi )
mimi3 2:0e871408d51b 31 {
mimi3 21:41129109d6ab 32 SpiHandle.Instance = spi;
mimi3 21:41129109d6ab 33 SpiHandle.Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER);
mimi3 21:41129109d6ab 34 SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
mimi3 21:41129109d6ab 35 SpiHandle.Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE);
mimi3 21:41129109d6ab 36 SpiHandle.Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA);
mimi3 21:41129109d6ab 37 SpiHandle.Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL);
mimi3 21:41129109d6ab 38 SpiHandle.Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN);
mimi3 21:41129109d6ab 39 SpiHandle.Init.CRCPolynomial = spi->CRCPR & 0xFFFF;
mimi3 21:41129109d6ab 40 SpiHandle.Init.DataSize = readReg(spi->CR1, SPI_CR1_DFF);
mimi3 21:41129109d6ab 41 SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
mimi3 21:41129109d6ab 42 SpiHandle.Init.NSS = readReg(spi->CR1, SPI_CR1_SSM);
mimi3 21:41129109d6ab 43 SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
mimi3 25:f6aa2b6ff6c1 44 SpiHandle.State = HAL_SPI_STATE_READY;
mimi3 2:0e871408d51b 45 }
mimi3 2:0e871408d51b 46
mimi3 21:41129109d6ab 47 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
mimi3 21:41129109d6ab 48 {
mimi3 21:41129109d6ab 49 static uint8_t dma_handle_inited = 0;
mimi3 25:f6aa2b6ff6c1 50 /* Peripheral DMA init*/
mimi3 25:f6aa2b6ff6c1 51 /* TX: */
mimi3 21:41129109d6ab 52 if( !dma_handle_inited ){
mimi3 25:f6aa2b6ff6c1 53 if( spi == SPI1 ){
mimi3 25:f6aa2b6ff6c1 54 hdma_spi_tx.Instance = SPI1_DMAx_TX_CHANNEL;
mimi3 25:f6aa2b6ff6c1 55 } else if( spi == SPI2 ) {
mimi3 25:f6aa2b6ff6c1 56 hdma_spi_tx.Instance = SPI2_DMAx_TX_CHANNEL;
mimi3 25:f6aa2b6ff6c1 57 }
mimi3 21:41129109d6ab 58 hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
mimi3 21:41129109d6ab 59 hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 21:41129109d6ab 60 hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 21:41129109d6ab 61 hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 21:41129109d6ab 62 hdma_spi_tx.Init.Mode = DMA_NORMAL;
mimi3 21:41129109d6ab 63 hdma_spi_tx.Init.Priority = DMA_PRIORITY_HIGH;
mimi3 21:41129109d6ab 64 }
mimi3 21:41129109d6ab 65 hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
mimi3 21:41129109d6ab 66 HAL_DMA_Init(&hdma_spi_tx);
mimi3 21:41129109d6ab 67 __HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
mimi3 25:f6aa2b6ff6c1 68 /* RX: */
mimi3 21:41129109d6ab 69 if( !dma_handle_inited ){
mimi3 25:f6aa2b6ff6c1 70 if( spi == SPI1 ){
mimi3 25:f6aa2b6ff6c1 71 hdma_spi_rx.Instance = SPI1_DMAx_RX_CHANNEL;
mimi3 25:f6aa2b6ff6c1 72 } else if( spi == SPI2 ) {
mimi3 25:f6aa2b6ff6c1 73 hdma_spi_rx.Instance = SPI2_DMAx_RX_CHANNEL;
mimi3 25:f6aa2b6ff6c1 74 }
mimi3 21:41129109d6ab 75 hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
mimi3 21:41129109d6ab 76 hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 21:41129109d6ab 77 hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 21:41129109d6ab 78 hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 21:41129109d6ab 79 hdma_spi_rx.Init.Mode = DMA_NORMAL;
mimi3 21:41129109d6ab 80 hdma_spi_rx.Init.Priority = DMA_PRIORITY_LOW;
mimi3 25:f6aa2b6ff6c1 81 }
mimi3 21:41129109d6ab 82 hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
mimi3 21:41129109d6ab 83 HAL_DMA_Init(&hdma_spi_rx);
mimi3 21:41129109d6ab 84 __HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx);
mimi3 2:0e871408d51b 85
mimi3 21:41129109d6ab 86 dma_handle_inited = 1;
mimi3 2:0e871408d51b 87 }
mimi3 2:0e871408d51b 88
mimi3 2:0e871408d51b 89 void spi_dma_irq_setup( SPI_TypeDef *spi)
mimi3 2:0e871408d51b 90 {
mimi3 27:a9d19b780770 91 if( spi == SPI1 ){
mimi3 25:f6aa2b6ff6c1 92 /* DMA controller clock enable */
mimi3 25:f6aa2b6ff6c1 93 SPI1_DMAx_CLK_ENABLE();
mimi3 25:f6aa2b6ff6c1 94 /* DMA interrupt init */
mimi3 25:f6aa2b6ff6c1 95 HAL_NVIC_SetPriority(SPI1_DMAx_TX_IRQn, 1, 0);
mimi3 25:f6aa2b6ff6c1 96 HAL_NVIC_EnableIRQ( SPI1_DMAx_TX_IRQn);
mimi3 25:f6aa2b6ff6c1 97 HAL_NVIC_SetPriority(SPI1_DMAx_RX_IRQn, 1, 0);
mimi3 25:f6aa2b6ff6c1 98 HAL_NVIC_EnableIRQ( SPI1_DMAx_RX_IRQn);
mimi3 25:f6aa2b6ff6c1 99 } else if( spi == SPI2 ){
mimi3 25:f6aa2b6ff6c1 100 /* DMA controller clock enable */
mimi3 25:f6aa2b6ff6c1 101 SPI2_DMAx_CLK_ENABLE();
mimi3 25:f6aa2b6ff6c1 102 /* DMA interrupt init */
mimi3 25:f6aa2b6ff6c1 103 HAL_NVIC_SetPriority(SPI2_DMAx_TX_IRQn, 1, 0);
mimi3 25:f6aa2b6ff6c1 104 HAL_NVIC_EnableIRQ( SPI2_DMAx_TX_IRQn);
mimi3 25:f6aa2b6ff6c1 105 HAL_NVIC_SetPriority(SPI2_DMAx_RX_IRQn, 1, 0);
mimi3 25:f6aa2b6ff6c1 106 HAL_NVIC_EnableIRQ( SPI2_DMAx_RX_IRQn);
mimi3 25:f6aa2b6ff6c1 107 }
mimi3 2:0e871408d51b 108 }
mimi3 2:0e871408d51b 109
mimi3 25:f6aa2b6ff6c1 110 /* SPI1 */
mimi3 25:f6aa2b6ff6c1 111 void SPI1_DMAx_RX_IRQHandler(void)
mimi3 2:0e871408d51b 112 {
mimi3 25:f6aa2b6ff6c1 113 HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3 25:f6aa2b6ff6c1 114 }
mimi3 25:f6aa2b6ff6c1 115 void SPI1_DMAx_TX_IRQHandler(void)
mimi3 25:f6aa2b6ff6c1 116 {
mimi3 25:f6aa2b6ff6c1 117 HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3 2:0e871408d51b 118 }
mimi3 2:0e871408d51b 119
mimi3 25:f6aa2b6ff6c1 120 /* SPI2 */
mimi3 25:f6aa2b6ff6c1 121 void SPI2_DMAx_RX_IRQHandler(void)
mimi3 2:0e871408d51b 122 {
mimi3 25:f6aa2b6ff6c1 123 HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3 25:f6aa2b6ff6c1 124 }
mimi3 25:f6aa2b6ff6c1 125 void SPI2_DMAx_TX_IRQHandler(void)
mimi3 25:f6aa2b6ff6c1 126 {
mimi3 25:f6aa2b6ff6c1 127 HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3 2:0e871408d51b 128 }
mimi3 2:0e871408d51b 129
mimi3 2:0e871408d51b 130 #endif /* TARGET_STM32F1 */
mimi3 2:0e871408d51b 131