mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

spi_dma/spi_dma_stm32f0.c@38:7077795dbf81, 2017-01-22 (annotated)

Committer:
mimi3
Date:
Sun Jan 22 23:13:11 2017 +0900
Revision:
38:7077795dbf81
Parent:
30:dde6a5f67add 
change: table.md

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dinau 30:dde6a5f67add 1 #if defined(TARGET_STM32F0) || defined(TARGET_STM32L0)
mimi3 2:0e871408d51b 2 /*
mimi3 2:0e871408d51b 3
mimi3 2:0e871408d51b 4 This file is licensed under Apache 2.0 license.
mimi3 2:0e871408d51b 5 (C) 2016 dinau
mimi3 2:0e871408d51b 6
mimi3 2:0e871408d51b 7 */
mimi3 2:0e871408d51b 8 #include "spi_dma.h"
mimi3 2:0e871408d51b 9
mimi3 21:41129109d6ab 10 /* For SPI1 */
mimi3 18:1b1a0e68008a 11 #define DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE()
mimi3 18:1b1a0e68008a 12 #define SPIx_TX_DMA_CHANNEL DMA1_Channel3
mimi3 18:1b1a0e68008a 13 #define SPIx_RX_DMA_CHANNEL DMA1_Channel2
dinau 30:dde6a5f67add 14
mimi3 21:41129109d6ab 15 #if defined(TARGET_STM32F091RC)
mimi3 21:41129109d6ab 16 #define SPIx_DMA_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn
mimi3 21:41129109d6ab 17 #define DMA_SPI_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
mimi3 21:41129109d6ab 18 #else
mimi3 21:41129109d6ab 19 #define SPIx_DMA_IRQn DMA1_Channel2_3_IRQn
mimi3 21:41129109d6ab 20 #define DMA_SPI_IRQHandler DMA1_Channel2_3_IRQHandler
mimi3 21:41129109d6ab 21 #endif
mimi3 21:41129109d6ab 22
mimi3 18:1b1a0e68008a 23
mimi3 18:1b1a0e68008a 24
mimi3 18:1b1a0e68008a 25 #define readReg( reg, mask) ( (reg) & (mask) )
mimi3 2:0e871408d51b 26
mimi3 2:0e871408d51b 27 void spi_dma_get_info( SPI_TypeDef *spi )
mimi3 2:0e871408d51b 28 {
mimi3 21:41129109d6ab 29 SpiHandle.Instance = spi;
mimi3 21:41129109d6ab 30 SpiHandle.Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER);
mimi3 21:41129109d6ab 31 SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
mimi3 21:41129109d6ab 32 SpiHandle.Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE);
mimi3 21:41129109d6ab 33 SpiHandle.Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA);
mimi3 21:41129109d6ab 34 SpiHandle.Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL);
mimi3 21:41129109d6ab 35 SpiHandle.Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN);
mimi3 21:41129109d6ab 36 SpiHandle.Init.CRCPolynomial = spi->CRCPR & 0xFFFF;
dinau 30:dde6a5f67add 37 #if defined(TARGET_STM32F0)
mimi3 21:41129109d6ab 38 SpiHandle.Init.DataSize = readReg(spi->CR2, SPI_CR2_DS);
dinau 30:dde6a5f67add 39 #endif
mimi3 21:41129109d6ab 40 SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
mimi3 21:41129109d6ab 41 SpiHandle.Init.NSS = readReg(spi->CR1, SPI_CR1_SSM);
mimi3 21:41129109d6ab 42 SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
mimi3 21:41129109d6ab 43 SpiHandle.State = HAL_SPI_STATE_READY;
mimi3 2:0e871408d51b 44 }
mimi3 2:0e871408d51b 45
mimi3 18:1b1a0e68008a 46 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
mimi3 18:1b1a0e68008a 47 {
mimi3 21:41129109d6ab 48 (void)spi;
mimi3 21:41129109d6ab 49 static uint8_t dma_handle_inited = 0;
mimi3 21:41129109d6ab 50 /* Peripheral DMA init*/
mimi3 21:41129109d6ab 51 /* TX: */
mimi3 21:41129109d6ab 52 if( !dma_handle_inited ){
mimi3 21:41129109d6ab 53 hdma_spi_tx.Instance = SPIx_TX_DMA_CHANNEL;
mimi3 21:41129109d6ab 54 hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
mimi3 21:41129109d6ab 55 hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 21:41129109d6ab 56 hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 21:41129109d6ab 57 hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 21:41129109d6ab 58 hdma_spi_tx.Init.Mode = DMA_NORMAL;
mimi3 21:41129109d6ab 59 hdma_spi_tx.Init.Priority = DMA_PRIORITY_HIGH;
mimi3 21:41129109d6ab 60 }
mimi3 21:41129109d6ab 61 hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
mimi3 21:41129109d6ab 62 HAL_DMA_Init(&hdma_spi_tx);
mimi3 21:41129109d6ab 63 __HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
mimi3 21:41129109d6ab 64 /* RX: */
mimi3 21:41129109d6ab 65 if( !dma_handle_inited ){
mimi3 21:41129109d6ab 66 hdma_spi_rx.Instance = SPIx_RX_DMA_CHANNEL;
mimi3 21:41129109d6ab 67 hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
mimi3 21:41129109d6ab 68 hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 21:41129109d6ab 69 hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 21:41129109d6ab 70 hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 21:41129109d6ab 71 hdma_spi_rx.Init.Mode = DMA_NORMAL;
mimi3 21:41129109d6ab 72 hdma_spi_rx.Init.Priority = DMA_PRIORITY_LOW;
mimi3 21:41129109d6ab 73 }
mimi3 21:41129109d6ab 74 hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
mimi3 21:41129109d6ab 75 HAL_DMA_Init(&hdma_spi_rx);
mimi3 21:41129109d6ab 76 __HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx);
mimi3 2:0e871408d51b 77
mimi3 21:41129109d6ab 78 dma_handle_inited = 1;
mimi3 2:0e871408d51b 79 }
mimi3 2:0e871408d51b 80
mimi3 2:0e871408d51b 81 void spi_dma_irq_setup( SPI_TypeDef *spi)
mimi3 2:0e871408d51b 82 {
mimi3 21:41129109d6ab 83 (void)spi;
mimi3 21:41129109d6ab 84 /* DMA controller clock enable */
mimi3 21:41129109d6ab 85 DMAx_CLK_ENABLE();
mimi3 2:0e871408d51b 86
mimi3 21:41129109d6ab 87 /* DMA interrupt init */
mimi3 21:41129109d6ab 88 HAL_NVIC_SetPriority(SPIx_DMA_IRQn, 1, 0);
mimi3 21:41129109d6ab 89 HAL_NVIC_EnableIRQ( SPIx_DMA_IRQn);
mimi3 2:0e871408d51b 90 }
mimi3 2:0e871408d51b 91
mimi3 18:1b1a0e68008a 92 void DMA_SPI_IRQHandler(void)
mimi3 2:0e871408d51b 93 {
mimi3 21:41129109d6ab 94 HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3 21:41129109d6ab 95 HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3 2:0e871408d51b 96 }
mimi3 2:0e871408d51b 97
mimi3 2:0e871408d51b 98
mimi3 18:1b1a0e68008a 99 #endif /* TARGET_STM32F0 */
mimi3 2:0e871408d51b 100