mi mi / Mbed 2 deprecated SDFileSystemDMA-test Featured

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Dependencies:   SDFileSystemDMA mbed

Refer to:
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA

Caution

If your board has SRAM less than or equal to 8KB, the 'buffer' size must be set to 512 Bytes.

NUCLEO-F411RE
About 2.5MBytes/sec
/media/uploads/mimi3/sdfilesystemdma-speed-test-teraterm-output-f411re.png
NUCLEO-L152RE
About 1MBytes/sec
/media/uploads/mimi3/sdfilesystemdma-l152re-cui.png

spi_device.h@27:a8f34ed4fac2, 2017-01-22 (annotated)

Committer:
mimi3
Date:
Sun Jan 22 23:26:05 2017 +0900
Revision:
27:a8f34ed4fac2
Parent:
21:6253a88675a5 
add: table.md

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mimi3 9:289de1b6d378 1
mimi3 9:289de1b6d378 2 /* SD card Interface connection
mimi3 9:289de1b6d378 3 * : aitendo : General
mimi3 9:289de1b6d378 4 * MCU sig. : IFB-254-SD : PIN name
mimi3 9:289de1b6d378 5 --- : 1 : 9 dat2
mimi3 9:289de1b6d378 6 CS : 2 : 1 cs/dat3
mimi3 9:289de1b6d378 7 MOSI : 3 : 2 di/cmd
mimi3 9:289de1b6d378 8 GND : 4 : 3 vss1
mimi3 9:289de1b6d378 9 VCC : 5 : 4 vdd
mimi3 9:289de1b6d378 10 CLK : 6 : 5 clk
mimi3 9:289de1b6d378 11 GND : 7 : 6 vss2
mimi3 9:289de1b6d378 12 MISO : 8 : 7 do/dat0
mimi3 9:289de1b6d378 13 --- : 9 : 8 dat1
mimi3 9:289de1b6d378 14 --- : 10 : 11 wp
mimi3 9:289de1b6d378 15 --- : 11 : 10 cd1
mimi3 9:289de1b6d378 16 --- : 12 : - case GND
mimi3 9:289de1b6d378 17 */
mimi3 9:289de1b6d378 18
mimi3 9:289de1b6d378 19 #define SPI_DEV 1
mimi3 9:289de1b6d378 20
dinau 15:b363001c7e40 21 #if defined(TARGET_STM32F4) || defined(TARGET_STM32L4)
dinau 15:b363001c7e40 22 #define CS D10 /* PB_6 or etc. */
mimi3 9:289de1b6d378 23 #if SPI_DEV==1
mimi3 9:289de1b6d378 24 /* SPI1 */
mimi3 9:289de1b6d378 25 #define MOSI D11 /* PA_7 */
mimi3 9:289de1b6d378 26 #define MISO D12 /* PA_6 */
mimi3 9:289de1b6d378 27 #define SCLK D13 /* PA_5 */
mimi3 9:289de1b6d378 28 #elif SPI_DEV==3
mimi3 9:289de1b6d378 29 /* SPI3 */
mimi3 9:289de1b6d378 30 #define MOSI D4 /* PB_5 */
mimi3 9:289de1b6d378 31 #define MISO D5 /* PB_4 */
mimi3 9:289de1b6d378 32 #define SCLK D3 /* PB_3 */
mimi3 9:289de1b6d378 33 #else
mimi3 9:289de1b6d378 34 #error
mimi3 9:289de1b6d378 35 #endif
mimi3 9:289de1b6d378 36 #endif
mimi3 9:289de1b6d378 37
dinau 16:54e179cc3063 38 #if defined(TARGET_DISCO_F303VC) \
dinau 16:54e179cc3063 39 || defined(TARGET_NUCLEO_F303RE) \
dinau 16:54e179cc3063 40 || defined(TARGET_NUCLEO_F302R8)
mimi3 9:289de1b6d378 41 #define CS PC_9
mimi3 9:289de1b6d378 42 /* SPI3 */
mimi3 9:289de1b6d378 43 #if SPI_DEV==3
mimi3 9:289de1b6d378 44 #define MOSI PC_12
mimi3 9:289de1b6d378 45 #define MISO PC_11
mimi3 9:289de1b6d378 46 #define SCLK PC_10
mimi3 9:289de1b6d378 47 #elif SPI_DEV==2
mimi3 9:289de1b6d378 48 /* SPI2 */
mimi3 9:289de1b6d378 49 #define MOSI PB_15
mimi3 9:289de1b6d378 50 #define MISO PB_14
mimi3 9:289de1b6d378 51 #define SCLK PB_13
mimi3 9:289de1b6d378 52 #else
mimi3 9:289de1b6d378 53 #error
mimi3 9:289de1b6d378 54 #endif
mimi3 9:289de1b6d378 55 #endif
mimi3 9:289de1b6d378 56
dinau 16:54e179cc3063 57 #if defined(TARGET_NUCLEO_F303K8) \
dinau 16:54e179cc3063 58 || defined(TARGET_NUCLEO_F334R8) \
dinau 16:54e179cc3063 59 || defined(TARGET_DISCO_F334C8)
dinau 16:54e179cc3063 60 #define CS PA_1
dinau 16:54e179cc3063 61 /* SPI1 */
dinau 16:54e179cc3063 62 #if SPI_DEV==1
dinau 16:54e179cc3063 63 #define MOSI PA_7
dinau 16:54e179cc3063 64 #define MISO PA_6
dinau 16:54e179cc3063 65 #define SCLK PA_5
dinau 16:54e179cc3063 66 #else
dinau 16:54e179cc3063 67 #error
dinau 16:54e179cc3063 68 #endif
dinau 16:54e179cc3063 69 #endif
dinau 16:54e179cc3063 70
mimi3 9:289de1b6d378 71 #if defined(TARGET_DISCO_F100RB)
mimi3 9:289de1b6d378 72 #define CS PB_12
mimi3 9:289de1b6d378 73 /* SPI1 */
mimi3 9:289de1b6d378 74 #if SPI_DEV==1
mimi3 9:289de1b6d378 75 #define MOSI PA_7
mimi3 9:289de1b6d378 76 #define MISO PA_6
mimi3 9:289de1b6d378 77 #define SCLK PA_5
mimi3 9:289de1b6d378 78 #elif SPI_DEV==2
mimi3 9:289de1b6d378 79 /* SPI2 */
mimi3 9:289de1b6d378 80 #define MOSI PB_15
mimi3 9:289de1b6d378 81 #define MISO PB_14
mimi3 9:289de1b6d378 82 #define SCLK PB_13
mimi3 9:289de1b6d378 83 #else
mimi3 9:289de1b6d378 84 #error
mimi3 9:289de1b6d378 85 #endif
mimi3 9:289de1b6d378 86 #endif
mimi3 9:289de1b6d378 87
mimi3 9:289de1b6d378 88 #if defined(TARGET_NUCLEO_F103RB)
mimi3 9:289de1b6d378 89 /* SPI1 */
mimi3 9:289de1b6d378 90 #if SPI_DEV==1
mimi3 9:289de1b6d378 91 #define CS PB_8
mimi3 9:289de1b6d378 92 #define MOSI PA_7
mimi3 9:289de1b6d378 93 #define MISO PA_6
mimi3 9:289de1b6d378 94 #define SCLK PA_5
mimi3 9:289de1b6d378 95 #elif SPI_DEV==2
mimi3 9:289de1b6d378 96 /* SPI2 */
mimi3 9:289de1b6d378 97 #define CS PD_2
mimi3 9:289de1b6d378 98 #define MOSI PB_15
mimi3 9:289de1b6d378 99 #define MISO PB_14
mimi3 9:289de1b6d378 100 #define SCLK PB_13
mimi3 9:289de1b6d378 101 #else
mimi3 9:289de1b6d378 102 #error
mimi3 9:289de1b6d378 103 #endif
mimi3 9:289de1b6d378 104 #endif
mimi3 9:289de1b6d378 105
mimi3 9:289de1b6d378 106
dinau 19:6519eb90d1ef 107 #if defined(TARGET_STM32F0) \
dinau 19:6519eb90d1ef 108 || defined(TARGET_STM32L1) \
dinau 19:6519eb90d1ef 109 || defined(TARGET_STM32L0)
dinau 21:6253a88675a5 110 #define CS D10 /* PB_6 */
dinau 21:6253a88675a5 111 #if 1
mimi3 11:d5fc11ac948a 112 #define MOSI D4 /* PB_5 */
mimi3 11:d5fc11ac948a 113 #define MISO D5 /* PB_4 */
mimi3 11:d5fc11ac948a 114 #define SCLK D3 /* PB_3 */
dinau 21:6253a88675a5 115 #else
dinau 21:6253a88675a5 116 #define MOSI D11 /* PA_7 */
dinau 21:6253a88675a5 117 #define MISO D12 /* PA_6 */
dinau 21:6253a88675a5 118 #define SCLK D13 /* PA_5 */
dinau 21:6253a88675a5 119 #endif
mimi3 9:289de1b6d378 120 #endif
mimi3 9:289de1b6d378 121
mimi3 9:289de1b6d378 122