Michael Koster / mbedEndpointNetworkMJK

observe fixes

Dependencies:   nsdl_lib Nanostack_lib

Fork of mbedEndpointNetwork by Michael Koster

mesh_nework/AtmelRFDriverLib/driverAtmelRFInterface.h@10:da76961ba3e9, 2015-04-23 (annotated)

Committer:
michaeljkoster
Date:
Thu Apr 23 02:57:56 2015 +0000
Revision:
10:da76961ba3e9
Parent:
0:2a5a48a8b4d4 
use prebuilt nsdl

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ansond 0:2a5a48a8b4d4 1 /*
ansond 0:2a5a48a8b4d4 2 * driverAtmelRFInterface.h
ansond 0:2a5a48a8b4d4 3 *
ansond 0:2a5a48a8b4d4 4 * Created on: 14 July 2014
ansond 0:2a5a48a8b4d4 5 * Author: mBed Team
ansond 0:2a5a48a8b4d4 6 */
ansond 0:2a5a48a8b4d4 7
ansond 0:2a5a48a8b4d4 8 #ifndef DRIVERRFINTERFACE_H_
ansond 0:2a5a48a8b4d4 9 #define DRIVERRFINTERFACE_H_
ansond 0:2a5a48a8b4d4 10
ansond 0:2a5a48a8b4d4 11
ansond 0:2a5a48a8b4d4 12 /*Delay between transfers(bytes) (32*DLYBCT)/MCK -> (32*6/120MHz=1.6us)*/
ansond 0:2a5a48a8b4d4 13 #define SPI_DLYBCT 6
ansond 0:2a5a48a8b4d4 14 /*Delay before SPCK DLYBS/MCK -> 140/120MHz=1.16us)*/
ansond 0:2a5a48a8b4d4 15 #define SPI_DLYBS 140
ansond 0:2a5a48a8b4d4 16 /*Serial clock baud rate MCK/SCBR -> 120MHz/18=6.7MHz)*/
ansond 0:2a5a48a8b4d4 17 #define SPI_SCBR 18
ansond 0:2a5a48a8b4d4 18
ansond 0:2a5a48a8b4d4 19 #define PHY_ACK_WAIT_TICK_VAL 185
ansond 0:2a5a48a8b4d4 20 #define PHY_CALIBRATION_TICK_VAL 185
ansond 0:2a5a48a8b4d4 21 #define PHY_ACK_WAIT_TIMER 1
ansond 0:2a5a48a8b4d4 22 #define PHY_CALIBRATION_TIMER 2
ansond 0:2a5a48a8b4d4 23
ansond 0:2a5a48a8b4d4 24 /*Supported transceivers*/
ansond 0:2a5a48a8b4d4 25 #define PART_AT86RF231 0x03
ansond 0:2a5a48a8b4d4 26 #define PART_AT86RF212 0x07
ansond 0:2a5a48a8b4d4 27 #define PART_AT86RF233 0x0B
ansond 0:2a5a48a8b4d4 28 #define VERSION_AT86RF212 0x01
ansond 0:2a5a48a8b4d4 29 #define VERSION_AT86RF212B 0x03
ansond 0:2a5a48a8b4d4 30
ansond 0:2a5a48a8b4d4 31 /*RF Configuration Registers*/
ansond 0:2a5a48a8b4d4 32 #define TRX_STATUS 0x01
ansond 0:2a5a48a8b4d4 33 #define TRX_STATE 0x02
ansond 0:2a5a48a8b4d4 34 #define TRX_CTRL_0 0x03
ansond 0:2a5a48a8b4d4 35 #define TRX_CTRL_1 0x04
ansond 0:2a5a48a8b4d4 36 #define PHY_TX_PWR 0x05
ansond 0:2a5a48a8b4d4 37 #define PHY_RSSI 0x06
ansond 0:2a5a48a8b4d4 38 #define PHY_ED_LEVEL 0x07
ansond 0:2a5a48a8b4d4 39 #define PHY_CC_CCA 0x08
ansond 0:2a5a48a8b4d4 40 #define RX_CTRL 0x0A
ansond 0:2a5a48a8b4d4 41 #define SFD_VALUE 0x0B
ansond 0:2a5a48a8b4d4 42 #define TRX_CTRL_2 0x0C
ansond 0:2a5a48a8b4d4 43 #define ANT_DIV 0x0D
ansond 0:2a5a48a8b4d4 44 #define IRQ_MASK 0x0E
ansond 0:2a5a48a8b4d4 45 #define IRQ_STATUS 0x0F
ansond 0:2a5a48a8b4d4 46 #define VREG_CTRL 0x10
ansond 0:2a5a48a8b4d4 47 #define BATMON 0x11
ansond 0:2a5a48a8b4d4 48 #define XOSC_CTRL 0x12
ansond 0:2a5a48a8b4d4 49 #define CC_CTRL_0 0x13
ansond 0:2a5a48a8b4d4 50 #define CC_CTRL_1 0x14
ansond 0:2a5a48a8b4d4 51 #define RX_SYN 0x15
ansond 0:2a5a48a8b4d4 52 #define TRX_RPC 0x16
ansond 0:2a5a48a8b4d4 53 #define RF_CTRL_0 0x16
ansond 0:2a5a48a8b4d4 54 #define XAH_CTRL_1 0x17
ansond 0:2a5a48a8b4d4 55 #define FTN_CTRL 0x18
ansond 0:2a5a48a8b4d4 56 #define PLL_CF 0x1A
ansond 0:2a5a48a8b4d4 57 #define PLL_DCU 0x1B
ansond 0:2a5a48a8b4d4 58 #define PART_NUM 0x1C
ansond 0:2a5a48a8b4d4 59 #define VERSION_NUM 0x1D
ansond 0:2a5a48a8b4d4 60 #define MAN_ID_0 0x1E
ansond 0:2a5a48a8b4d4 61 #define MAN_ID_1 0x1F
ansond 0:2a5a48a8b4d4 62 #define SHORT_ADDR_0 0x20
ansond 0:2a5a48a8b4d4 63 #define SHORT_ADDR_1 0x21
ansond 0:2a5a48a8b4d4 64 #define PAN_ID_0 0x22
ansond 0:2a5a48a8b4d4 65 #define PAN_ID_1 0x23
ansond 0:2a5a48a8b4d4 66 #define IEEE_ADDR_0 0x24
ansond 0:2a5a48a8b4d4 67 #define IEEE_ADDR_1 0x25
ansond 0:2a5a48a8b4d4 68 #define IEEE_ADDR_2 0x26
ansond 0:2a5a48a8b4d4 69 #define IEEE_ADDR_3 0x27
ansond 0:2a5a48a8b4d4 70 #define IEEE_ADDR_4 0x28
ansond 0:2a5a48a8b4d4 71 #define IEEE_ADDR_5 0x29
ansond 0:2a5a48a8b4d4 72 #define IEEE_ADDR_6 0x2A
ansond 0:2a5a48a8b4d4 73 #define IEEE_ADDR_7 0x2B
ansond 0:2a5a48a8b4d4 74 #define XAH_CTRL_0 0x2C
ansond 0:2a5a48a8b4d4 75 #define CSMA_SEED_0 0x2D
ansond 0:2a5a48a8b4d4 76 #define CSMA_SEED_1 0x2E
ansond 0:2a5a48a8b4d4 77 #define CSMA_BE 0x2F
ansond 0:2a5a48a8b4d4 78
ansond 0:2a5a48a8b4d4 79 /* CSMA_SEED_1*/
ansond 0:2a5a48a8b4d4 80 #define AACK_FVN_MODE1 7
ansond 0:2a5a48a8b4d4 81 #define AACK_FVN_MODE0 6
ansond 0:2a5a48a8b4d4 82 #define AACK_SET_PD 5
ansond 0:2a5a48a8b4d4 83 #define AACK_DIS_ACK 4
ansond 0:2a5a48a8b4d4 84 #define AACK_I_AM_COORD 3
ansond 0:2a5a48a8b4d4 85 #define CSMA_SEED_12 2
ansond 0:2a5a48a8b4d4 86 #define CSMA_SEED_11 1
ansond 0:2a5a48a8b4d4 87 #define CSMA_SEED_10 0
ansond 0:2a5a48a8b4d4 88
ansond 0:2a5a48a8b4d4 89 /*TRX_STATUS bits*/
ansond 0:2a5a48a8b4d4 90 #define CCA_STATUS 0x40
ansond 0:2a5a48a8b4d4 91 #define CCA_DONE 0x80
ansond 0:2a5a48a8b4d4 92
ansond 0:2a5a48a8b4d4 93 /*PHY_CC_CCA bits*/
ansond 0:2a5a48a8b4d4 94 #define CCA_REQUEST 0x80
ansond 0:2a5a48a8b4d4 95 #define CCA_MODE_1 0x20
ansond 0:2a5a48a8b4d4 96 #define CCA_MODE_3 0x60
ansond 0:2a5a48a8b4d4 97
ansond 0:2a5a48a8b4d4 98 /*IRQ_MASK bits*/
ansond 0:2a5a48a8b4d4 99 #define RX_START 0x04
ansond 0:2a5a48a8b4d4 100 #define TRX_END 0x08
ansond 0:2a5a48a8b4d4 101 #define CCA_ED_DONE 0x10
ansond 0:2a5a48a8b4d4 102 #define AMI 0x20
ansond 0:2a5a48a8b4d4 103 #define TRX_UR 0x40
ansond 0:2a5a48a8b4d4 104
ansond 0:2a5a48a8b4d4 105 /*ANT_DIV bits*/
ansond 0:2a5a48a8b4d4 106 #define ANT_DIV_EN 0x08
ansond 0:2a5a48a8b4d4 107 #define ANT_EXT_SW_EN 0x04
ansond 0:2a5a48a8b4d4 108 #define ANT_CTRL_DEFAULT 0x03
ansond 0:2a5a48a8b4d4 109
ansond 0:2a5a48a8b4d4 110 /*TRX_CTRL_1 bits*/
ansond 0:2a5a48a8b4d4 111 #define PA_EXT_EN 0x80
ansond 0:2a5a48a8b4d4 112
ansond 0:2a5a48a8b4d4 113 /*FTN_CTRL bits*/
ansond 0:2a5a48a8b4d4 114 #define FTN_START 0x80
ansond 0:2a5a48a8b4d4 115
ansond 0:2a5a48a8b4d4 116 /*PHY_RSSI bits*/
ansond 0:2a5a48a8b4d4 117 #define CRC_VALID 0x80
ansond 0:2a5a48a8b4d4 118
ansond 0:2a5a48a8b4d4 119 /*AT86RF212 PHY Modes*/
ansond 0:2a5a48a8b4d4 120 #define BPSK_20 0x00
ansond 0:2a5a48a8b4d4 121 #define BPSK_40 0x04
ansond 0:2a5a48a8b4d4 122 #define BPSK_40_ALT 0x14
ansond 0:2a5a48a8b4d4 123 #define OQPSK_SIN_RC_100 0x08
ansond 0:2a5a48a8b4d4 124 #define OQPSK_SIN_RC_200 0x09
ansond 0:2a5a48a8b4d4 125 #define OQPSK_RC_100 0x18
ansond 0:2a5a48a8b4d4 126 #define OQPSK_RC_200 0x19
ansond 0:2a5a48a8b4d4 127 #define OQPSK_SIN_250 0x0c
ansond 0:2a5a48a8b4d4 128 #define OQPSK_SIN_500 0x0d
ansond 0:2a5a48a8b4d4 129 #define OQPSK_SIN_500_ALT 0x0f
ansond 0:2a5a48a8b4d4 130 #define OQPSK_RC_250 0x1c
ansond 0:2a5a48a8b4d4 131 #define OQPSK_RC_500 0x1d
ansond 0:2a5a48a8b4d4 132 #define OQPSK_RC_500_ALT 0x1f
ansond 0:2a5a48a8b4d4 133 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
ansond 0:2a5a48a8b4d4 134 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
ansond 0:2a5a48a8b4d4 135 #define OQPSK_RC_400_SCR_ON 0x3A
ansond 0:2a5a48a8b4d4 136 #define OQPSK_RC_400_SCR_OFF 0x1A
ansond 0:2a5a48a8b4d4 137 #define OQPSK_SIN_1000_SCR_ON 0x2E
ansond 0:2a5a48a8b4d4 138 #define OQPSK_SIN_1000_SCR_OFF 0x0E
ansond 0:2a5a48a8b4d4 139 #define OQPSK_RC_1000_SCR_ON 0x3E
ansond 0:2a5a48a8b4d4 140 #define OQPSK_RC_1000_SCR_OFF 0x1E
ansond 0:2a5a48a8b4d4 141
ansond 0:2a5a48a8b4d4 142 extern void rf_if_delay_function(uint16_t ticks);
ansond 0:2a5a48a8b4d4 143 extern uint8_t rf_if_read_rnd(void);
ansond 0:2a5a48a8b4d4 144 extern void rf_if_calibration_timer_start(uint32_t slots);
ansond 0:2a5a48a8b4d4 145 extern void rf_if_interrupt_handler(void);
ansond 0:2a5a48a8b4d4 146 extern void (*rf_if_get_rf_interrupt_function(void))(void);
ansond 0:2a5a48a8b4d4 147 extern void rf_if_calibration_timer_interrupt(void);
ansond 0:2a5a48a8b4d4 148 extern void rf_if_timer_init(void);
ansond 0:2a5a48a8b4d4 149 extern void rf_if_ack_wait_timer_start(uint16_t slots);
ansond 0:2a5a48a8b4d4 150 extern void rf_if_ack_wait_timer_stop(void);
ansond 0:2a5a48a8b4d4 151 extern void rf_if_ack_wait_timer_interrupt(void);
ansond 0:2a5a48a8b4d4 152 extern int8_t rf_if_set_rf_irq_pin(uint8_t port, uint8_t pin);
ansond 0:2a5a48a8b4d4 153 extern int8_t rf_if_set_slp_tr_pin(uint8_t port, uint8_t pin);
ansond 0:2a5a48a8b4d4 154 extern int8_t rf_if_set_reset_pin(uint8_t port, uint8_t pin);
ansond 0:2a5a48a8b4d4 155 extern int8_t rf_if_set_spi_interface(uint8_t spi_interface, uint8_t cs_device);
ansond 0:2a5a48a8b4d4 156 extern uint8_t rf_if_spi_exchange(uint8_t spi_if, uint8_t out);
ansond 0:2a5a48a8b4d4 157 extern void rf_if_ack_pending_ctrl(uint8_t state);
ansond 0:2a5a48a8b4d4 158 extern void rf_if_calibration(void);
ansond 0:2a5a48a8b4d4 159 extern uint8_t rf_if_read_register(uint8_t addr);
ansond 0:2a5a48a8b4d4 160 extern void rf_if_set_bit(uint8_t addr, uint8_t bit, uint8_t bit_mask);
ansond 0:2a5a48a8b4d4 161 extern void rf_if_clear_bit(uint8_t addr, uint8_t bit);
ansond 0:2a5a48a8b4d4 162 extern void rf_if_write_register(uint8_t addr, uint8_t data);
ansond 0:2a5a48a8b4d4 163 extern void rf_if_reset_radio(void);
ansond 0:2a5a48a8b4d4 164 extern void rf_if_enable_pa_ext(void);
ansond 0:2a5a48a8b4d4 165 extern void rf_if_disable_pa_ext(void);
ansond 0:2a5a48a8b4d4 166 extern void rf_if_enable_ant_div(void);
ansond 0:2a5a48a8b4d4 167 extern void rf_if_disable_ant_div(void);
ansond 0:2a5a48a8b4d4 168 extern void rf_if_enable_slptr(void);
ansond 0:2a5a48a8b4d4 169 extern void rf_if_disable_slptr(void);
ansond 0:2a5a48a8b4d4 170 extern void rf_if_write_antenna_diversity_settings(void);
ansond 0:2a5a48a8b4d4 171 extern void rf_if_write_set_tx_power_register(uint8_t value);
ansond 0:2a5a48a8b4d4 172 extern void rf_if_write_set_trx_rpc_register(uint8_t value);
ansond 0:2a5a48a8b4d4 173 extern void rf_if_write_rf_settings(void);
ansond 0:2a5a48a8b4d4 174 extern uint8_t rf_if_check_cca(void);
ansond 0:2a5a48a8b4d4 175 extern uint8_t rf_if_check_crc(void);
ansond 0:2a5a48a8b4d4 176 extern uint8_t rf_if_read_trx_state(void);
ansond 0:2a5a48a8b4d4 177 extern void rf_if_read_packet(uint8_t *ptr, uint8_t len);
ansond 0:2a5a48a8b4d4 178 extern void rf_if_write_short_addr_registers(uint8_t *short_address);
ansond 0:2a5a48a8b4d4 179 extern uint8_t rf_if_last_acked_pending(void);
ansond 0:2a5a48a8b4d4 180 extern void rf_if_write_pan_id_registers(uint8_t *pan_id);
ansond 0:2a5a48a8b4d4 181 extern void rf_if_write_ieee_addr_registers(uint8_t *address);
ansond 0:2a5a48a8b4d4 182 extern void rf_if_write_frame_buffer(uint8_t *ptr, uint8_t length);
ansond 0:2a5a48a8b4d4 183 extern void rf_if_change_trx_state(rf_trx_states_t trx_state);
ansond 0:2a5a48a8b4d4 184 extern void rf_if_enable_tx_end_interrupt(void);
ansond 0:2a5a48a8b4d4 185 extern void rf_if_enable_rx_end_interrupt(void);
ansond 0:2a5a48a8b4d4 186 extern void rf_if_enable_rx_start_interrupt(void);
ansond 0:2a5a48a8b4d4 187 extern void rf_if_enable_cca_ed_done_interrupt(void);
ansond 0:2a5a48a8b4d4 188 extern void rf_if_start_cca_process(void);
ansond 0:2a5a48a8b4d4 189 extern uint8_t rf_if_read_received_frame_length(void);
ansond 0:2a5a48a8b4d4 190 extern uint8_t rf_if_read_lqi(void);
ansond 0:2a5a48a8b4d4 191 extern int8_t rf_if_read_rssi(void);
ansond 0:2a5a48a8b4d4 192 extern void rf_if_set_channel_register(uint8_t channel);
ansond 0:2a5a48a8b4d4 193
ansond 0:2a5a48a8b4d4 194 #endif /* DRIVERRFINTERFACE_H_ */